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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * James Liao <jamesjj.liao@mediatek.com>5 * Copyright (c) 2023 Collabora, Ltd.6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>7 */8 9#include <dt-bindings/clock/mt8135-clk.h>10#include <linux/clk.h>11#include <linux/of.h>12#include <linux/platform_device.h>13 14#include "clk-mtk.h"15#include "clk-pll.h"16 17#define MT8135_PLL_FMAX (2000 * MHZ)18#define CON0_MT8135_RST_BAR BIT(27)19 20#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \21 .id = _id, \22 .name = _name, \23 .reg = _reg, \24 .pwr_reg = _pwr_reg, \25 .en_mask = _en_mask, \26 .flags = _flags, \27 .rst_bar_mask = CON0_MT8135_RST_BAR, \28 .fmax = MT8135_PLL_FMAX, \29 .pcwbits = _pcwbits, \30 .pd_reg = _pd_reg, \31 .pd_shift = _pd_shift, \32 .tuner_reg = _tuner_reg, \33 .pcw_reg = _pcw_reg, \34 .pcw_shift = _pcw_shift, \35 }36 37static const struct mtk_pll_data plls[] = {38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),40 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),41 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),42 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),48};49 50static int clk_mt8135_apmixed_probe(struct platform_device *pdev)51{52 struct clk_hw_onecell_data *clk_data;53 struct device_node *node = pdev->dev.of_node;54 int ret;55 56 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);57 if (!clk_data)58 return -ENOMEM;59 60 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);61 if (ret)62 goto free_clk_data;63 64 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);65 if (ret)66 goto unregister_plls;67 68 return 0;69 70unregister_plls:71 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);72free_clk_data:73 mtk_free_clk_data(clk_data);74 75 return ret;76}77 78static void clk_mt8135_apmixed_remove(struct platform_device *pdev)79{80 struct device_node *node = pdev->dev.of_node;81 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);82 83 of_clk_del_provider(node);84 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);85 mtk_free_clk_data(clk_data);86}87 88static const struct of_device_id of_match_clk_mt8135_apmixed[] = {89 { .compatible = "mediatek,mt8135-apmixedsys" },90 { /* sentinel */ }91};92MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed);93 94static struct platform_driver clk_mt8135_apmixed_drv = {95 .probe = clk_mt8135_apmixed_probe,96 .remove = clk_mt8135_apmixed_remove,97 .driver = {98 .name = "clk-mt8135-apmixed",99 .of_match_table = of_match_clk_mt8135_apmixed,100 },101};102module_platform_driver(clk_mt8135_apmixed_drv)103 104MODULE_DESCRIPTION("MediaTek MT8135 apmixedsys clocks driver");105MODULE_LICENSE("GPL");106