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brintos / linux-shallow public Read only

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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2020 MediaTek Inc.4 * Copyright (c) 2020 BayLibre, SAS5 * Author: James Liao <jamesjj.liao@mediatek.com>6 *         Fabien Parent <fparent@baylibre.com>7 */8 9#include <linux/clk-provider.h>10#include <linux/mod_devicetable.h>11#include <linux/platform_device.h>12 13#include "clk-mtk.h"14#include "clk-gate.h"15 16#include <dt-bindings/clock/mt8167-clk.h>17 18static const struct mtk_gate_regs aud_cg_regs = {19	.set_ofs = 0x0,20	.clr_ofs = 0x0,21	.sta_ofs = 0x0,22};23 24#define GATE_AUD(_id, _name, _parent, _shift)			\25	GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)26 27 28static const struct mtk_gate aud_clks[] = {29	GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),30	GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),31	GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),32	GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),33	GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),34	GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),35	GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),36	GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),37	GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),38	GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),39	GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),40	GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),41	GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),42};43 44static const struct mtk_clk_desc aud_desc = {45	.clks = aud_clks,46	.num_clks = ARRAY_SIZE(aud_clks),47};48 49static const struct of_device_id of_match_clk_mt8167_audsys[] = {50	{ .compatible = "mediatek,mt8167-audsys", .data = &aud_desc },51	{ /* sentinel */ }52};53MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_audsys);54 55static struct platform_driver clk_mt8167_audsys_drv = {56	.probe = mtk_clk_simple_probe,57	.remove = mtk_clk_simple_remove,58	.driver = {59		.name = "clk-mt8167-audsys",60		.of_match_table = of_match_clk_mt8167_audsys,61	},62};63module_platform_driver(clk_mt8167_audsys_drv);64 65MODULE_DESCRIPTION("MediaTek MT8167 audio clocks driver");66MODULE_LICENSE("GPL");67