655 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Copyright (c) 2022 Collabora Ltd.5 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>6 */7 8#include <dt-bindings/clock/mt8173-clk.h>9#include <linux/module.h>10#include <linux/platform_device.h>11#include "clk-gate.h"12#include "clk-mtk.h"13#include "clk-mux.h"14 15/*16 * For some clocks, we don't care what their actual rates are. And these17 * clocks may change their rate on different products or different scenarios.18 * So we model these clocks' rate as 0, to denote it's not an actual rate.19 */20#define DUMMY_RATE 021 22#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \23 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \25 _gate, 0, -1, _flags)26 27#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \29 _gate, CLK_SET_RATE_PARENT | _flags)30 31static DEFINE_SPINLOCK(mt8173_top_clk_lock);32 33static const char * const axi_parents[] = {34 "clk26m",35 "syspll1_d2",36 "syspll_d5",37 "syspll1_d4",38 "univpll_d5",39 "univpll2_d2",40 "dmpll_d2",41 "dmpll_d4"42};43 44static const char * const mem_parents[] = {45 "clk26m",46 "dmpll_ck"47};48 49static const char * const ddrphycfg_parents[] = {50 "clk26m",51 "syspll1_d8"52};53 54static const char * const mm_parents[] = {55 "clk26m",56 "vencpll_d2",57 "main_h364m",58 "syspll1_d2",59 "syspll_d5",60 "syspll1_d4",61 "univpll1_d2",62 "univpll2_d2",63 "dmpll_d2"64};65 66static const char * const pwm_parents[] = {67 "clk26m",68 "univpll2_d4",69 "univpll3_d2",70 "univpll1_d4"71};72 73static const char * const vdec_parents[] = {74 "clk26m",75 "vcodecpll_ck",76 "tvdpll_445p5m",77 "univpll_d3",78 "vencpll_d2",79 "syspll_d3",80 "univpll1_d2",81 "mmpll_d2",82 "dmpll_d2",83 "dmpll_d4"84};85 86static const char * const venc_parents[] = {87 "clk26m",88 "vcodecpll_ck",89 "tvdpll_445p5m",90 "univpll_d3",91 "vencpll_d2",92 "syspll_d3",93 "univpll1_d2",94 "univpll2_d2",95 "dmpll_d2",96 "dmpll_d4"97};98 99static const char * const mfg_parents[] = {100 "clk26m",101 "mmpll_ck",102 "dmpll_ck",103 "clk26m",104 "clk26m",105 "clk26m",106 "clk26m",107 "clk26m",108 "clk26m",109 "syspll_d3",110 "syspll1_d2",111 "syspll_d5",112 "univpll_d3",113 "univpll1_d2",114 "univpll_d5",115 "univpll2_d2"116};117 118static const char * const camtg_parents[] = {119 "clk26m",120 "univpll_d26",121 "univpll2_d2",122 "syspll3_d2",123 "syspll3_d4",124 "univpll1_d4"125};126 127static const char * const uart_parents[] = {128 "clk26m",129 "univpll2_d8"130};131 132static const char * const spi_parents[] = {133 "clk26m",134 "syspll3_d2",135 "syspll1_d4",136 "syspll4_d2",137 "univpll3_d2",138 "univpll2_d4",139 "univpll1_d8"140};141 142static const char * const usb20_parents[] = {143 "clk26m",144 "univpll1_d8",145 "univpll3_d4"146};147 148static const char * const usb30_parents[] = {149 "clk26m",150 "univpll3_d2",151 "usb_syspll_125m",152 "univpll2_d4"153};154 155static const char * const msdc50_0_h_parents[] = {156 "clk26m",157 "syspll1_d2",158 "syspll2_d2",159 "syspll4_d2",160 "univpll_d5",161 "univpll1_d4"162};163 164static const char * const msdc50_0_parents[] = {165 "clk26m",166 "msdcpll_ck",167 "msdcpll_d2",168 "univpll1_d4",169 "syspll2_d2",170 "syspll_d7",171 "msdcpll_d4",172 "vencpll_d4",173 "tvdpll_ck",174 "univpll_d2",175 "univpll1_d2",176 "mmpll_ck",177 "msdcpll2_ck",178 "msdcpll2_d2",179 "msdcpll2_d4"180};181 182static const char * const msdc30_1_parents[] = {183 "clk26m",184 "univpll2_d2",185 "msdcpll_d4",186 "univpll1_d4",187 "syspll2_d2",188 "syspll_d7",189 "univpll_d7",190 "vencpll_d4"191};192 193static const char * const msdc30_2_parents[] = {194 "clk26m",195 "univpll2_d2",196 "msdcpll_d4",197 "univpll1_d4",198 "syspll2_d2",199 "syspll_d7",200 "univpll_d7",201 "vencpll_d2"202};203 204static const char * const msdc30_3_parents[] = {205 "clk26m",206 "msdcpll2_ck",207 "msdcpll2_d2",208 "univpll2_d2",209 "msdcpll2_d4",210 "msdcpll_d4",211 "univpll1_d4",212 "syspll2_d2",213 "syspll_d7",214 "univpll_d7",215 "vencpll_d4",216 "msdcpll_ck",217 "msdcpll_d2",218 "msdcpll_d4"219};220 221static const char * const audio_parents[] = {222 "clk26m",223 "syspll3_d4",224 "syspll4_d4",225 "syspll1_d16"226};227 228static const char * const aud_intbus_parents[] = {229 "clk26m",230 "syspll1_d4",231 "syspll4_d2",232 "univpll3_d2",233 "univpll2_d8",234 "dmpll_d4",235 "dmpll_d8"236};237 238static const char * const pmicspi_parents[] = {239 "clk26m",240 "syspll1_d8",241 "syspll3_d4",242 "syspll1_d16",243 "univpll3_d4",244 "univpll_d26",245 "dmpll_d8",246 "dmpll_d16"247};248 249static const char * const scp_parents[] = {250 "clk26m",251 "syspll1_d2",252 "univpll_d5",253 "syspll_d5",254 "dmpll_d2",255 "dmpll_d4"256};257 258static const char * const atb_parents[] = {259 "clk26m",260 "syspll1_d2",261 "univpll_d5",262 "dmpll_d2"263};264 265static const char * const venc_lt_parents[] = {266 "clk26m",267 "univpll_d3",268 "vcodecpll_ck",269 "tvdpll_445p5m",270 "vencpll_d2",271 "syspll_d3",272 "univpll1_d2",273 "univpll2_d2",274 "syspll1_d2",275 "univpll_d5",276 "vcodecpll_370p5",277 "dmpll_ck"278};279 280static const char * const dpi0_parents[] = {281 "clk26m",282 "tvdpll_d2",283 "tvdpll_d4",284 "clk26m",285 "clk26m",286 "tvdpll_d8",287 "tvdpll_d16"288};289 290static const char * const irda_parents[] = {291 "clk26m",292 "univpll2_d4",293 "syspll2_d4"294};295 296static const char * const cci400_parents[] = {297 "clk26m",298 "vencpll_ck",299 "armca7pll_754m",300 "armca7pll_502m",301 "univpll_d2",302 "syspll_d2",303 "msdcpll_ck",304 "dmpll_ck"305};306 307static const char * const aud_1_parents[] = {308 "clk26m",309 "apll1_ck",310 "univpll2_d4",311 "univpll2_d8"312};313 314static const char * const aud_2_parents[] = {315 "clk26m",316 "apll2_ck",317 "univpll2_d4",318 "univpll2_d8"319};320 321static const char * const mem_mfg_in_parents[] = {322 "clk26m",323 "mmpll_ck",324 "dmpll_ck",325 "clk26m"326};327 328static const char * const axi_mfg_in_parents[] = {329 "clk26m",330 "axi_sel",331 "dmpll_d2"332};333 334static const char * const scam_parents[] = {335 "clk26m",336 "syspll3_d2",337 "univpll2_d4",338 "dmpll_d4"339};340 341static const char * const spinfi_ifr_parents[] = {342 "clk26m",343 "univpll2_d8",344 "univpll3_d4",345 "syspll4_d2",346 "univpll2_d4",347 "univpll3_d2",348 "syspll1_d4",349 "univpll1_d4"350};351 352static const char * const hdmi_parents[] = {353 "clk26m",354 "hdmitx_dig_cts",355 "hdmitxpll_d2",356 "hdmitxpll_d3"357};358 359static const char * const dpilvds_parents[] = {360 "clk26m",361 "lvdspll",362 "lvdspll_d2",363 "lvdspll_d4",364 "lvdspll_d8",365 "fpc_ck"366};367 368static const char * const msdc50_2_h_parents[] = {369 "clk26m",370 "syspll1_d2",371 "syspll2_d2",372 "syspll4_d2",373 "univpll_d5",374 "univpll1_d4"375};376 377static const char * const hdcp_parents[] = {378 "clk26m",379 "syspll4_d2",380 "syspll3_d4",381 "univpll2_d4"382};383 384static const char * const hdcp_24m_parents[] = {385 "clk26m",386 "univpll_d26",387 "univpll_d52",388 "univpll2_d8"389};390 391static const char * const rtc_parents[] = {392 "clkrtc_int",393 "clkrtc_ext",394 "clk26m",395 "univpll3_d8"396};397 398static const char * const i2s0_m_ck_parents[] = {399 "apll1_div1",400 "apll2_div1"401};402 403static const char * const i2s1_m_ck_parents[] = {404 "apll1_div2",405 "apll2_div2"406};407 408static const char * const i2s2_m_ck_parents[] = {409 "apll1_div3",410 "apll2_div3"411};412 413static const char * const i2s3_m_ck_parents[] = {414 "apll1_div4",415 "apll2_div4"416};417 418static const char * const i2s3_b_ck_parents[] = {419 "apll1_div5",420 "apll2_div5"421};422 423static const struct mtk_fixed_clk fixed_clks[] = {424 FIXED_CLK(CLK_DUMMY, "topck_dummy", "clk26m", DUMMY_RATE),425 FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),426 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),427 FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),428 FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),429 FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),430 FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),431};432 433static const struct mtk_fixed_factor top_divs[] = {434 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),435 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),436 437 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),438 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),439 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),440 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),441 442 FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),443 FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),444 445 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),446 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),447 FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),448 FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),449 FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),450 451 FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),452 FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),453 FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),454 455 FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),456 FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),457 458 FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),459 FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),460 461 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),462 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),463 464 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),465 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),466 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),467 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),468 FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),469 470 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),471 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),472 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),473 474 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),475 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),476 477 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),478 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),479 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),480 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),481 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),482 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),483 484 FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),485 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),486 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),487 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),488 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),489 FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),490 FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),491 FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),492 FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),493 FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),494 FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),495 FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),496 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),497 FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),498 499 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),500 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),501 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),502 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),503 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),504 505 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),506 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),507 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),508 FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),509 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),510 FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),511 FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),512 FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),513 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),514 FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),515 FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),516 FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),517 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),518 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),519 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),520 521 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),522 FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),523 524 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),525 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),526 FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),527};528 529static const struct mtk_composite top_muxes[] = {530 /* CLK_CFG_0 */531 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),532 MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,533 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),534 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",535 ddrphycfg_parents, 0x0040, 16, 1, 23,536 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),538 /* CLK_CFG_1 */539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),540 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),541 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),542 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),543 /* CLK_CFG_2 */544 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),545 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),546 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),547 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),548 /* CLK_CFG_3 */549 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),550 MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,551 0x0070, 8, 3, 15, 0),552 MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents,553 0x0070, 16, 4, 23, 0),554 MUX_GATE_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,555 0x0070, 24, 3, 31, 0),556 /* CLK_CFG_4 */557 MUX_GATE_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents,558 0x0080, 0, 3, 7, 0),559 MUX_GATE_FLAGS(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents,560 0x0080, 8, 4, 15, 0),561 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,562 0x0080, 16, 2, 23),563 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,564 0x0080, 24, 3, 31),565 /* CLK_CFG_5 */566 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,567 0x0090, 0, 3, 7 /* 7:5 */),568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),569 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),570 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents,571 0x0090, 24, 4, 31),572 /* CLK_CFG_6 */573 /*574 * The dpi0_sel clock should not propagate rate changes to its parent575 * clock so the dpi driver can have full control over PLL and divider.576 */577 MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,578 0x00a0, 0, 3, 7, 0),579 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),580 MUX_GATE_FLAGS(CLK_TOP_CCI400_SEL, "cci400_sel",581 cci400_parents, 0x00a0, 16, 3, 23,582 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),583 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),584 /* CLK_CFG_7 */585 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),586 MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents,587 0x00b0, 8, 2, 15),588 MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,589 0x00b0, 16, 2, 23),590 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),591 /* CLK_CFG_12 */592 MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents,593 0x00c0, 0, 3, 7),594 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),595 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents,596 0x00c0, 24, 3, 31),597 /* CLK_CFG_13 */598 MUX_GATE_FLAGS(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents,599 0x00d0, 0, 3, 7, 0),600 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),601 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents,602 0x00d0, 16, 2, 23),603 MUX_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2,604 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),605 606 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),607 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),608 DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),609 DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),610 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),611 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),612 613 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),614 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),615 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),616 DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),617 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),618 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),619 620 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),621 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),622 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),623 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),624 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),625};626 627static const struct mtk_clk_desc topck_desc = {628 .fixed_clks = fixed_clks,629 .num_fixed_clks = ARRAY_SIZE(fixed_clks),630 .factor_clks = top_divs,631 .num_factor_clks = ARRAY_SIZE(top_divs),632 .composite_clks = top_muxes,633 .num_composite_clks = ARRAY_SIZE(top_muxes),634 .clk_lock = &mt8173_top_clk_lock,635};636 637static const struct of_device_id of_match_clk_mt8173_topckgen[] = {638 { .compatible = "mediatek,mt8173-topckgen", .data = &topck_desc },639 { /* sentinel */ }640};641MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_topckgen);642 643static struct platform_driver clk_mt8173_topckgen_drv = {644 .driver = {645 .name = "clk-mt8173-topckgen",646 .of_match_table = of_match_clk_mt8173_topckgen,647 },648 .probe = mtk_clk_simple_probe,649 .remove = mtk_clk_simple_remove,650};651module_platform_driver(clk_mt8173_topckgen_drv);652 653MODULE_DESCRIPTION("MediaTek MT8173 topckgen clocks driver");654MODULE_LICENSE("GPL");655