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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Copyright (c) 2022 Collabora Ltd.5 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>6 */7 8#include <dt-bindings/clock/mt8173-clk.h>9#include <linux/module.h>10#include <linux/platform_device.h>11#include "clk-gate.h"12#include "clk-mtk.h"13 14static const struct mtk_gate_regs venc_cg_regs = {15 .set_ofs = 0x4,16 .clr_ofs = 0x8,17 .sta_ofs = 0x0,18};19 20#define GATE_VENC(_id, _name, _parent, _shift) \21 GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)22 23static const struct mtk_gate venc_clks[] = {24 GATE_DUMMY(CLK_DUMMY, "venc_dummy"),25 GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),26 GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),27 GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),28 GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),29};30 31static const struct mtk_gate venclt_clks[] = {32 GATE_DUMMY(CLK_DUMMY, "venclt_dummy"),33 GATE_VENC(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),34 GATE_VENC(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),35};36 37static const struct mtk_clk_desc venc_desc = {38 .clks = venc_clks,39 .num_clks = ARRAY_SIZE(venc_clks),40};41 42static const struct mtk_clk_desc venc_lt_desc = {43 .clks = venclt_clks,44 .num_clks = ARRAY_SIZE(venclt_clks),45};46 47static const struct of_device_id of_match_clk_mt8173_vencsys[] = {48 { .compatible = "mediatek,mt8173-vencsys", .data = &venc_desc },49 { .compatible = "mediatek,mt8173-vencltsys", .data = &venc_lt_desc },50 { /* sentinel */ }51};52MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vencsys);53 54static struct platform_driver clk_mt8173_vencsys_drv = {55 .driver = {56 .name = "clk-mt8173-vencsys",57 .of_match_table = of_match_clk_mt8173_vencsys,58 },59 .probe = mtk_clk_simple_probe,60 .remove = mtk_clk_simple_remove,61};62module_platform_driver(clk_mt8173_vencsys_drv);63 64MODULE_DESCRIPTION("MediaTek MT8173 vencsys clocks driver");65MODULE_LICENSE("GPL");66