95 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Garmin Chang <garmin.chang@mediatek.com>5 */6 7#include <dt-bindings/clock/mediatek,mt8188-clk.h>8#include <linux/clk-provider.h>9#include <linux/platform_device.h>10 11#include "clk-gate.h"12#include "clk-mtk.h"13 14static const struct mtk_gate_regs vdec0_cg_regs = {15 .set_ofs = 0x0,16 .clr_ofs = 0x4,17 .sta_ofs = 0x0,18};19 20static const struct mtk_gate_regs vdec1_cg_regs = {21 .set_ofs = 0x200,22 .clr_ofs = 0x204,23 .sta_ofs = 0x200,24};25 26static const struct mtk_gate_regs vdec2_cg_regs = {27 .set_ofs = 0x8,28 .clr_ofs = 0xc,29 .sta_ofs = 0x8,30};31 32#define GATE_VDEC0(_id, _name, _parent, _shift) \33 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)34 35#define GATE_VDEC1(_id, _name, _parent, _shift) \36 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)37 38#define GATE_VDEC2(_id, _name, _parent, _shift) \39 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)40 41static const struct mtk_gate vdec1_clks[] = {42 /* VDEC1_0 */43 GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0),44 GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4),45 GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8),46 /* VDEC1_1 */47 GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0),48 GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4),49 GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8),50 /* VDEC1_2 */51 GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0),52};53 54static const struct mtk_gate vdec2_clks[] = {55 /* VDEC2_0 */56 GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0),57 GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4),58 GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8),59 /* VDEC2_1 */60 GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0),61 /* VDEC2_2 */62 GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0),63};64 65static const struct mtk_clk_desc vdec1_desc = {66 .clks = vdec1_clks,67 .num_clks = ARRAY_SIZE(vdec1_clks),68};69 70static const struct mtk_clk_desc vdec2_desc = {71 .clks = vdec2_clks,72 .num_clks = ARRAY_SIZE(vdec2_clks),73};74 75static const struct of_device_id of_match_clk_mt8188_vdec[] = {76 { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc },77 { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc },78 { /* sentinel */ }79};80MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec);81 82static struct platform_driver clk_mt8188_vdec_drv = {83 .probe = mtk_clk_simple_probe,84 .remove = mtk_clk_simple_remove,85 .driver = {86 .name = "clk-mt8188-vdec",87 .of_match_table = of_match_clk_mt8188_vdec,88 },89};90 91module_platform_driver(clk_mt8188_vdec_drv);92 93MODULE_DESCRIPTION("MediaTek MT8188 Video Decoders clocks driver");94MODULE_LICENSE("GPL");95