124 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2//3// Copyright (c) 2021 MediaTek Inc.4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/platform_device.h>9 10#include "clk-mtk.h"11#include "clk-gate.h"12 13#include <dt-bindings/clock/mt8192-clk.h>14 15static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {16 .set_ofs = 0xe08,17 .clr_ofs = 0xe04,18 .sta_ofs = 0xe00,19};20 21#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \22 GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \23 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)24 25static const struct mtk_gate imp_iic_wrap_c_clks[] = {26 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),27 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1),28 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2),29 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3),30};31 32static const struct mtk_gate imp_iic_wrap_e_clks[] = {33 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0),34};35 36static const struct mtk_gate imp_iic_wrap_n_clks[] = {37 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0),38 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1),39};40 41static const struct mtk_gate imp_iic_wrap_s_clks[] = {42 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0),43 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1),44 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2),45};46 47static const struct mtk_gate imp_iic_wrap_w_clks[] = {48 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),49};50 51static const struct mtk_gate imp_iic_wrap_ws_clks[] = {52 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0),53 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1),54 GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2),55};56 57static const struct mtk_clk_desc imp_iic_wrap_c_desc = {58 .clks = imp_iic_wrap_c_clks,59 .num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),60};61 62static const struct mtk_clk_desc imp_iic_wrap_e_desc = {63 .clks = imp_iic_wrap_e_clks,64 .num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),65};66 67static const struct mtk_clk_desc imp_iic_wrap_n_desc = {68 .clks = imp_iic_wrap_n_clks,69 .num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),70};71 72static const struct mtk_clk_desc imp_iic_wrap_s_desc = {73 .clks = imp_iic_wrap_s_clks,74 .num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),75};76 77static const struct mtk_clk_desc imp_iic_wrap_w_desc = {78 .clks = imp_iic_wrap_w_clks,79 .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),80};81 82static const struct mtk_clk_desc imp_iic_wrap_ws_desc = {83 .clks = imp_iic_wrap_ws_clks,84 .num_clks = ARRAY_SIZE(imp_iic_wrap_ws_clks),85};86 87static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = {88 {89 .compatible = "mediatek,mt8192-imp_iic_wrap_c",90 .data = &imp_iic_wrap_c_desc,91 }, {92 .compatible = "mediatek,mt8192-imp_iic_wrap_e",93 .data = &imp_iic_wrap_e_desc,94 }, {95 .compatible = "mediatek,mt8192-imp_iic_wrap_n",96 .data = &imp_iic_wrap_n_desc,97 }, {98 .compatible = "mediatek,mt8192-imp_iic_wrap_s",99 .data = &imp_iic_wrap_s_desc,100 }, {101 .compatible = "mediatek,mt8192-imp_iic_wrap_w",102 .data = &imp_iic_wrap_w_desc,103 }, {104 .compatible = "mediatek,mt8192-imp_iic_wrap_ws",105 .data = &imp_iic_wrap_ws_desc,106 }, {107 /* sentinel */108 }109};110MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_imp_iic_wrap);111 112static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {113 .probe = mtk_clk_simple_probe,114 .remove = mtk_clk_simple_remove,115 .driver = {116 .name = "clk-mt8192-imp_iic_wrap",117 .of_match_table = of_match_clk_mt8192_imp_iic_wrap,118 },119};120module_platform_driver(clk_mt8192_imp_iic_wrap_drv);121 122MODULE_DESCRIPTION("MediaTek MT8192 I2C Wrapper clocks driver");123MODULE_LICENSE("GPL");124