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1// SPDX-License-Identifier: GPL-2.0-only2//3// Copyright (c) 2021 MediaTek Inc.4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/platform_device.h>9 10#include "clk-mtk.h"11#include "clk-gate.h"12 13#include <dt-bindings/clock/mt8192-clk.h>14 15static const struct mtk_gate_regs ipe_cg_regs = {16 .set_ofs = 0x4,17 .clr_ofs = 0x8,18 .sta_ofs = 0x0,19};20 21#define GATE_IPE(_id, _name, _parent, _shift) \22 GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)23 24static const struct mtk_gate ipe_clks[] = {25 GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),26 GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),27 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),28 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),29 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),30 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),31 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),32 GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),33};34 35static const struct mtk_clk_desc ipe_desc = {36 .clks = ipe_clks,37 .num_clks = ARRAY_SIZE(ipe_clks),38};39 40static const struct of_device_id of_match_clk_mt8192_ipe[] = {41 {42 .compatible = "mediatek,mt8192-ipesys",43 .data = &ipe_desc,44 }, {45 /* sentinel */46 }47};48MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_ipe);49 50static struct platform_driver clk_mt8192_ipe_drv = {51 .probe = mtk_clk_simple_probe,52 .remove = mtk_clk_simple_remove,53 .driver = {54 .name = "clk-mt8192-ipe",55 .of_match_table = of_match_clk_mt8192_ipe,56 },57};58module_platform_driver(clk_mt8192_ipe_drv);59 60MODULE_DESCRIPTION("MediaTek MT8192 Image Processing Engine clocks driver");61MODULE_LICENSE("GPL");62