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1// SPDX-License-Identifier: GPL-2.0-only2//3// Copyright (c) 2021 MediaTek Inc.4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 6#include "clk-gate.h"7#include "clk-mtk.h"8 9#include <dt-bindings/clock/mt8195-clk.h>10#include <linux/clk-provider.h>11#include <linux/platform_device.h>12 13static const struct mtk_gate_regs vdec0_cg_regs = {14 .set_ofs = 0x0,15 .clr_ofs = 0x4,16 .sta_ofs = 0x0,17};18 19static const struct mtk_gate_regs vdec1_cg_regs = {20 .set_ofs = 0x200,21 .clr_ofs = 0x204,22 .sta_ofs = 0x200,23};24 25static const struct mtk_gate_regs vdec2_cg_regs = {26 .set_ofs = 0x8,27 .clr_ofs = 0xc,28 .sta_ofs = 0x8,29};30 31#define GATE_VDEC0(_id, _name, _parent, _shift) \32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)33 34#define GATE_VDEC1(_id, _name, _parent, _shift) \35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)36 37#define GATE_VDEC2(_id, _name, _parent, _shift) \38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)39 40static const struct mtk_gate vdec_clks[] = {41 /* VDEC0 */42 GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "top_vdec", 0),43 /* VDEC1 */44 GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "top_vdec", 0),45 /* VDEC2 */46 GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "top_vdec", 0),47};48 49static const struct mtk_gate vdec_core1_clks[] = {50 /* VDEC0 */51 GATE_VDEC0(CLK_VDEC_CORE1_VDEC, "vdec_core1_vdec", "top_vdec", 0),52 /* VDEC1 */53 GATE_VDEC1(CLK_VDEC_CORE1_LAT, "vdec_core1_lat", "top_vdec", 0),54 /* VDEC2 */55 GATE_VDEC2(CLK_VDEC_CORE1_LARB1, "vdec_core1_larb1", "top_vdec", 0),56};57 58static const struct mtk_gate vdec_soc_clks[] = {59 /* VDEC0 */60 GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "top_vdec", 0),61 /* VDEC1 */62 GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "top_vdec", 0),63 /* VDEC2 */64 GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "top_vdec", 0),65};66 67static const struct mtk_clk_desc vdec_desc = {68 .clks = vdec_clks,69 .num_clks = ARRAY_SIZE(vdec_clks),70};71 72static const struct mtk_clk_desc vdec_core1_desc = {73 .clks = vdec_core1_clks,74 .num_clks = ARRAY_SIZE(vdec_core1_clks),75};76 77static const struct mtk_clk_desc vdec_soc_desc = {78 .clks = vdec_soc_clks,79 .num_clks = ARRAY_SIZE(vdec_soc_clks),80};81 82static const struct of_device_id of_match_clk_mt8195_vdec[] = {83 {84 .compatible = "mediatek,mt8195-vdecsys",85 .data = &vdec_desc,86 }, {87 .compatible = "mediatek,mt8195-vdecsys_core1",88 .data = &vdec_core1_desc,89 }, {90 .compatible = "mediatek,mt8195-vdecsys_soc",91 .data = &vdec_soc_desc,92 }, {93 /* sentinel */94 }95};96MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_vdec);97 98static struct platform_driver clk_mt8195_vdec_drv = {99 .probe = mtk_clk_simple_probe,100 .remove = mtk_clk_simple_remove,101 .driver = {102 .name = "clk-mt8195-vdec",103 .of_match_table = of_match_clk_mt8195_vdec,104 },105};106module_platform_driver(clk_mt8195_vdec_drv);107 108MODULE_DESCRIPTION("MediaTek MT8195 Video Decoders clocks driver");109MODULE_LICENSE("GPL");110