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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (C) 2022 MediaTek Inc.4 */5 6#include <dt-bindings/clock/mediatek,mt8365-clk.h>7#include <linux/clk-provider.h>8#include <linux/platform_device.h>9 10#include "clk-gate.h"11#include "clk-mtk.h"12 13static const struct mtk_gate_regs mfg0_cg_regs = {14 .set_ofs = 0x4,15 .clr_ofs = 0x8,16 .sta_ofs = 0x0,17};18 19static const struct mtk_gate_regs mfg1_cg_regs = {20 .set_ofs = 0x280,21 .clr_ofs = 0x280,22 .sta_ofs = 0x280,23};24 25#define GATE_MFG0(_id, _name, _parent, _shift) \26 GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \27 &mtk_clk_gate_ops_setclr)28 29#define GATE_MFG1(_id, _name, _parent, _shift) \30 GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \31 &mtk_clk_gate_ops_no_setclr)32 33static const struct mtk_gate mfg_clks[] = {34 /* MFG0 */35 GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),36 /* MFG1 */37 GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24),38};39 40static const struct mtk_clk_desc mfg_desc = {41 .clks = mfg_clks,42 .num_clks = ARRAY_SIZE(mfg_clks),43};44 45static const struct of_device_id of_match_clk_mt8365_mfg[] = {46 {47 .compatible = "mediatek,mt8365-mfgcfg",48 .data = &mfg_desc,49 }, {50 /* sentinel */51 }52};53MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_mfg);54 55static struct platform_driver clk_mt8365_mfg_drv = {56 .probe = mtk_clk_simple_probe,57 .remove = mtk_clk_simple_remove,58 .driver = {59 .name = "clk-mt8365-mfg",60 .of_match_table = of_match_clk_mt8365_mfg,61 },62};63module_platform_driver(clk_mt8365_mfg_drv);64 65MODULE_DESCRIPTION("MediaTek MT8365 GPU mfg clocks driver");66MODULE_LICENSE("GPL");67