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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (C) 2022 MediaTek Inc.4 */5 6#include <dt-bindings/clock/mediatek,mt8365-clk.h>7#include <linux/clk-provider.h>8#include <linux/platform_device.h>9 10#include "clk-gate.h"11#include "clk-mtk.h"12 13static const struct mtk_gate_regs vdec0_cg_regs = {14 .set_ofs = 0x0,15 .clr_ofs = 0x4,16 .sta_ofs = 0x0,17};18 19static const struct mtk_gate_regs vdec1_cg_regs = {20 .set_ofs = 0x8,21 .clr_ofs = 0xc,22 .sta_ofs = 0x8,23};24 25#define GATE_VDEC0(_id, _name, _parent, _shift) \26 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \27 &mtk_clk_gate_ops_setclr_inv)28 29#define GATE_VDEC1(_id, _name, _parent, _shift) \30 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \31 &mtk_clk_gate_ops_setclr_inv)32 33static const struct mtk_gate vdec_clks[] = {34 /* VDEC0 */35 GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0),36 /* VDEC1 */37 GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0),38};39 40static const struct mtk_clk_desc vdec_desc = {41 .clks = vdec_clks,42 .num_clks = ARRAY_SIZE(vdec_clks),43};44 45static const struct of_device_id of_match_clk_mt8365_vdec[] = {46 {47 .compatible = "mediatek,mt8365-vdecsys",48 .data = &vdec_desc,49 }, {50 /* sentinel */51 }52};53MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec);54 55static struct platform_driver clk_mt8365_vdec_drv = {56 .probe = mtk_clk_simple_probe,57 .remove = mtk_clk_simple_remove,58 .driver = {59 .name = "clk-mt8365-vdec",60 .of_match_table = of_match_clk_mt8365_vdec,61 },62};63module_platform_driver(clk_mt8365_vdec_drv);64 65MODULE_DESCRIPTION("MediaTek MT8365 Video Decoders clocks driver");66MODULE_LICENSE("GPL");67