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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: James Liao <jamesjj.liao@mediatek.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/container_of.h>9#include <linux/delay.h>10#include <linux/err.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of_address.h>14#include <linux/slab.h>15 16#include "clk-pll.h"17 18#define MHZ (1000 * 1000)19 20#define REG_CON0 021#define REG_CON1 422 23#define CON0_BASE_EN BIT(0)24#define CON0_PWR_ON BIT(0)25#define CON0_ISO_EN BIT(1)26#define PCW_CHG_BIT 3127 28#define AUDPLL_TUNER_EN BIT(31)29 30/* default 7 bits integer, can be overridden with pcwibits. */31#define INTEGER_BITS 732 33int mtk_pll_is_prepared(struct clk_hw *hw)34{35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);36 37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;38}39 40static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,41 u32 pcw, int postdiv)42{43 int pcwbits = pll->data->pcwbits;44 int pcwfbits = 0;45 int ibits;46 u64 vco;47 u8 c = 0;48 49 /* The fractional part of the PLL divider. */50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;51 if (pcwbits > ibits)52 pcwfbits = pcwbits - ibits;53 54 vco = (u64)fin * pcw;55 56 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))57 c = 1;58 59 vco >>= pcwfbits;60 61 if (c)62 vco++;63 64 return ((unsigned long)vco + postdiv - 1) / postdiv;65}66 67static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)68{69 u32 r;70 71 if (pll->tuner_en_addr) {72 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);73 writel(r, pll->tuner_en_addr);74 } else if (pll->tuner_addr) {75 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;76 writel(r, pll->tuner_addr);77 }78}79 80static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)81{82 u32 r;83 84 if (pll->tuner_en_addr) {85 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);86 writel(r, pll->tuner_en_addr);87 } else if (pll->tuner_addr) {88 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;89 writel(r, pll->tuner_addr);90 }91}92 93static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,94 int postdiv)95{96 u32 chg, val;97 98 /* disable tuner */99 __mtk_pll_tuner_disable(pll);100 101 /* set postdiv */102 val = readl(pll->pd_addr);103 val &= ~(POSTDIV_MASK << pll->data->pd_shift);104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;105 106 /* postdiv and pcw need to set at the same time if on same register */107 if (pll->pd_addr != pll->pcw_addr) {108 writel(val, pll->pd_addr);109 val = readl(pll->pcw_addr);110 }111 112 /* set pcw */113 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,114 pll->data->pcw_shift);115 val |= pcw << pll->data->pcw_shift;116 writel(val, pll->pcw_addr);117 chg = readl(pll->pcw_chg_addr) |118 BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);119 writel(chg, pll->pcw_chg_addr);120 if (pll->tuner_addr)121 writel(val + 1, pll->tuner_addr);122 123 /* restore tuner_en */124 __mtk_pll_tuner_enable(pll);125 126 udelay(20);127}128 129/*130 * mtk_pll_calc_values - calculate good values for a given input frequency.131 * @pll: The pll132 * @pcw: The pcw value (output)133 * @postdiv: The post divider (output)134 * @freq: The desired target frequency135 * @fin: The input frequency136 *137 */138void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,139 u32 freq, u32 fin)140{141 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);142 const struct mtk_pll_div_table *div_table = pll->data->div_table;143 u64 _pcw;144 int ibits;145 u32 val;146 147 if (freq > pll->data->fmax)148 freq = pll->data->fmax;149 150 if (div_table) {151 if (freq > div_table[0].freq)152 freq = div_table[0].freq;153 154 for (val = 0; div_table[val + 1].freq != 0; val++) {155 if (freq > div_table[val + 1].freq)156 break;157 }158 *postdiv = 1 << val;159 } else {160 for (val = 0; val < 5; val++) {161 *postdiv = 1 << val;162 if ((u64)freq * *postdiv >= fmin)163 break;164 }165 }166 167 /* _pcw = freq * postdiv / fin * 2^pcwfbits */168 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;169 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);170 do_div(_pcw, fin);171 172 *pcw = (u32)_pcw;173}174 175int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,176 unsigned long parent_rate)177{178 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);179 u32 pcw = 0;180 u32 postdiv;181 182 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);183 mtk_pll_set_rate_regs(pll, pcw, postdiv);184 185 return 0;186}187 188unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)189{190 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);191 u32 postdiv;192 u32 pcw;193 194 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;195 postdiv = 1 << postdiv;196 197 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;198 pcw &= GENMASK(pll->data->pcwbits - 1, 0);199 200 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);201}202 203long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,204 unsigned long *prate)205{206 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);207 u32 pcw = 0;208 int postdiv;209 210 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);211 212 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);213}214 215int mtk_pll_prepare(struct clk_hw *hw)216{217 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);218 u32 r;219 220 r = readl(pll->pwr_addr) | CON0_PWR_ON;221 writel(r, pll->pwr_addr);222 udelay(1);223 224 r = readl(pll->pwr_addr) & ~CON0_ISO_EN;225 writel(r, pll->pwr_addr);226 udelay(1);227 228 r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);229 writel(r, pll->en_addr);230 231 if (pll->data->en_mask) {232 r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;233 writel(r, pll->base_addr + REG_CON0);234 }235 236 __mtk_pll_tuner_enable(pll);237 238 udelay(20);239 240 if (pll->data->flags & HAVE_RST_BAR) {241 r = readl(pll->base_addr + REG_CON0);242 r |= pll->data->rst_bar_mask;243 writel(r, pll->base_addr + REG_CON0);244 }245 246 return 0;247}248 249void mtk_pll_unprepare(struct clk_hw *hw)250{251 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);252 u32 r;253 254 if (pll->data->flags & HAVE_RST_BAR) {255 r = readl(pll->base_addr + REG_CON0);256 r &= ~pll->data->rst_bar_mask;257 writel(r, pll->base_addr + REG_CON0);258 }259 260 __mtk_pll_tuner_disable(pll);261 262 if (pll->data->en_mask) {263 r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;264 writel(r, pll->base_addr + REG_CON0);265 }266 267 r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);268 writel(r, pll->en_addr);269 270 r = readl(pll->pwr_addr) | CON0_ISO_EN;271 writel(r, pll->pwr_addr);272 273 r = readl(pll->pwr_addr) & ~CON0_PWR_ON;274 writel(r, pll->pwr_addr);275}276 277const struct clk_ops mtk_pll_ops = {278 .is_prepared = mtk_pll_is_prepared,279 .prepare = mtk_pll_prepare,280 .unprepare = mtk_pll_unprepare,281 .recalc_rate = mtk_pll_recalc_rate,282 .round_rate = mtk_pll_round_rate,283 .set_rate = mtk_pll_set_rate,284};285 286struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,287 const struct mtk_pll_data *data,288 void __iomem *base,289 const struct clk_ops *pll_ops)290{291 struct clk_init_data init = {};292 int ret;293 const char *parent_name = "clk26m";294 295 pll->base_addr = base + data->reg;296 pll->pwr_addr = base + data->pwr_reg;297 pll->pd_addr = base + data->pd_reg;298 pll->pcw_addr = base + data->pcw_reg;299 if (data->pcw_chg_reg)300 pll->pcw_chg_addr = base + data->pcw_chg_reg;301 else302 pll->pcw_chg_addr = pll->base_addr + REG_CON1;303 if (data->tuner_reg)304 pll->tuner_addr = base + data->tuner_reg;305 if (data->tuner_en_reg || data->tuner_en_bit)306 pll->tuner_en_addr = base + data->tuner_en_reg;307 if (data->en_reg)308 pll->en_addr = base + data->en_reg;309 else310 pll->en_addr = pll->base_addr + REG_CON0;311 pll->hw.init = &init;312 pll->data = data;313 314 init.name = data->name;315 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;316 init.ops = pll_ops;317 if (data->parent_name)318 init.parent_names = &data->parent_name;319 else320 init.parent_names = &parent_name;321 init.num_parents = 1;322 323 ret = clk_hw_register(NULL, &pll->hw);324 325 if (ret)326 return ERR_PTR(ret);327 328 return &pll->hw;329}330 331struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,332 void __iomem *base)333{334 struct mtk_clk_pll *pll;335 struct clk_hw *hw;336 337 pll = kzalloc(sizeof(*pll), GFP_KERNEL);338 if (!pll)339 return ERR_PTR(-ENOMEM);340 341 hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);342 if (IS_ERR(hw))343 kfree(pll);344 345 return hw;346}347 348void mtk_clk_unregister_pll(struct clk_hw *hw)349{350 struct mtk_clk_pll *pll;351 352 if (!hw)353 return;354 355 pll = to_mtk_clk_pll(hw);356 357 clk_hw_unregister(hw);358 kfree(pll);359}360 361int mtk_clk_register_plls(struct device_node *node,362 const struct mtk_pll_data *plls, int num_plls,363 struct clk_hw_onecell_data *clk_data)364{365 void __iomem *base;366 int i;367 struct clk_hw *hw;368 369 base = of_iomap(node, 0);370 if (!base) {371 pr_err("%s(): ioremap failed\n", __func__);372 return -EINVAL;373 }374 375 for (i = 0; i < num_plls; i++) {376 const struct mtk_pll_data *pll = &plls[i];377 378 if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {379 pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",380 node, pll->id);381 continue;382 }383 384 hw = mtk_clk_register_pll(pll, base);385 386 if (IS_ERR(hw)) {387 pr_err("Failed to register clk %s: %pe\n", pll->name,388 hw);389 goto err;390 }391 392 clk_data->hws[pll->id] = hw;393 }394 395 return 0;396 397err:398 while (--i >= 0) {399 const struct mtk_pll_data *pll = &plls[i];400 401 mtk_clk_unregister_pll(clk_data->hws[pll->id]);402 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);403 }404 405 iounmap(base);406 407 return PTR_ERR(hw);408}409EXPORT_SYMBOL_GPL(mtk_clk_register_plls);410 411__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,412 const struct mtk_pll_data *data)413{414 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);415 416 return pll->base_addr - data->reg;417}418 419void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,420 struct clk_hw_onecell_data *clk_data)421{422 __iomem void *base = NULL;423 int i;424 425 if (!clk_data)426 return;427 428 for (i = num_plls; i > 0; i--) {429 const struct mtk_pll_data *pll = &plls[i - 1];430 431 if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))432 continue;433 434 /*435 * This is quite ugly but unfortunately the clks don't have436 * any device tied to them, so there's no place to store the437 * pointer to the I/O region base address. We have to fetch438 * it from one of the registered clks.439 */440 base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);441 442 mtk_clk_unregister_pll(clk_data->hws[pll->id]);443 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);444 }445 446 iounmap(base);447}448EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls);449 450MODULE_LICENSE("GPL");451