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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>5 */6 7#include <linux/of.h>8#include <linux/of_address.h>9#include <linux/io.h>10#include <linux/slab.h>11#include <linux/clkdev.h>12#include <linux/delay.h>13 14#include "clk-mtk.h"15#include "clk-pllfh.h"16#include "clk-fhctl.h"17 18static DEFINE_SPINLOCK(pllfh_lock);19 20inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw)21{22 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);23 24 return container_of(pll, struct mtk_fh, clk_pll);25}26 27static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate,28 unsigned long parent_rate)29{30 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);31 struct mtk_fh *fh = to_mtk_fh(hw);32 u32 pcw = 0;33 u32 postdiv;34 35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);36 37 return fh->ops->hopping(fh, pcw, postdiv);38}39 40static const struct clk_ops mtk_pllfh_ops = {41 .is_prepared = mtk_pll_is_prepared,42 .prepare = mtk_pll_prepare,43 .unprepare = mtk_pll_unprepare,44 .recalc_rate = mtk_pll_recalc_rate,45 .round_rate = mtk_pll_round_rate,46 .set_rate = mtk_fhctl_set_rate,47};48 49static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,50 int num_fhs, int pll_id)51{52 int i;53 54 for (i = 0; i < num_fhs; i++)55 if (pllfhs[i].data.pll_id == pll_id)56 return &pllfhs[i];57 58 return NULL;59}60 61void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,62 int num_fhs)63{64 void __iomem *base;65 struct device_node *node;66 u32 num_clocks, pll_id, ssc_rate;67 int offset, i;68 69 node = of_find_compatible_node(NULL, NULL, compatible_node);70 if (!node) {71 pr_warn("cannot find \"%s\"\n", compatible_node);72 return;73 }74 75 base = of_iomap(node, 0);76 if (!base) {77 pr_err("%s(): ioremap failed\n", __func__);78 goto out_node_put;79 }80 81 num_clocks = of_clk_get_parent_count(node);82 if (!num_clocks) {83 pr_err("%s(): failed to get clocks property\n", __func__);84 goto err;85 }86 87 for (i = 0; i < num_clocks; i++) {88 struct mtk_pllfh_data *pllfh;89 90 offset = i * 2;91 92 of_property_read_u32_index(node, "clocks", offset + 1, &pll_id);93 of_property_read_u32_index(node,94 "mediatek,hopping-ssc-percent",95 i, &ssc_rate);96 97 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id);98 if (!pllfh)99 continue;100 101 pllfh->state.fh_enable = 1;102 pllfh->state.ssc_rate = ssc_rate;103 pllfh->state.base = base;104 }105 106out_node_put:107 of_node_put(node);108 return;109err:110 iounmap(base);111 goto out_node_put;112}113EXPORT_SYMBOL_GPL(fhctl_parse_dt);114 115static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)116{117 struct fh_pll_regs *regs = &fh->regs;118 const struct fhctl_offset *offset;119 void __iomem *base = pllfh_data->state.base;120 void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;121 122 offset = fhctl_get_offset_table(pllfh_data->data.fh_ver);123 if (IS_ERR(offset))124 return PTR_ERR(offset);125 126 regs->reg_hp_en = base + offset->offset_hp_en;127 regs->reg_clk_con = base + offset->offset_clk_con;128 regs->reg_rst_con = base + offset->offset_rst_con;129 regs->reg_slope0 = base + offset->offset_slope0;130 regs->reg_slope1 = base + offset->offset_slope1;131 132 regs->reg_cfg = fhx_base + offset->offset_cfg;133 regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;134 regs->reg_dds = fhx_base + offset->offset_dds;135 regs->reg_dvfs = fhx_base + offset->offset_dvfs;136 regs->reg_mon = fhx_base + offset->offset_mon;137 138 fh->pllfh_data = pllfh_data;139 fh->lock = &pllfh_lock;140 141 fh->ops = fhctl_get_ops();142 143 return 0;144}145 146static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)147{148 return pllfh && (pllfh->state.fh_enable == 1);149}150 151static struct clk_hw *152mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,153 struct mtk_pllfh_data *pllfh_data, void __iomem *base)154{155 struct clk_hw *hw;156 struct mtk_fh *fh;157 int ret;158 159 fh = kzalloc(sizeof(*fh), GFP_KERNEL);160 if (!fh)161 return ERR_PTR(-ENOMEM);162 163 ret = pllfh_init(fh, pllfh_data);164 if (ret) {165 hw = ERR_PTR(ret);166 goto out;167 }168 169 hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,170 &mtk_pllfh_ops);171 172 if (IS_ERR(hw))173 goto out;174 175 fhctl_hw_init(fh);176 177out:178 if (IS_ERR(hw))179 kfree(fh);180 181 return hw;182}183 184static void mtk_clk_unregister_pllfh(struct clk_hw *hw)185{186 struct mtk_fh *fh;187 188 if (!hw)189 return;190 191 fh = to_mtk_fh(hw);192 193 clk_hw_unregister(hw);194 kfree(fh);195}196 197int mtk_clk_register_pllfhs(struct device_node *node,198 const struct mtk_pll_data *plls, int num_plls,199 struct mtk_pllfh_data *pllfhs, int num_fhs,200 struct clk_hw_onecell_data *clk_data)201{202 void __iomem *base;203 int i;204 struct clk_hw *hw;205 206 base = of_iomap(node, 0);207 if (!base) {208 pr_err("%s(): ioremap failed\n", __func__);209 return -EINVAL;210 }211 212 for (i = 0; i < num_plls; i++) {213 const struct mtk_pll_data *pll = &plls[i];214 struct mtk_pllfh_data *pllfh;215 bool use_fhctl;216 217 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);218 use_fhctl = fhctl_is_supported_and_enabled(pllfh);219 220 if (use_fhctl)221 hw = mtk_clk_register_pllfh(pll, pllfh, base);222 else223 hw = mtk_clk_register_pll(pll, base);224 225 if (IS_ERR(hw)) {226 pr_err("Failed to register %s clk %s: %ld\n",227 use_fhctl ? "fhpll" : "pll", pll->name,228 PTR_ERR(hw));229 goto err;230 }231 232 clk_data->hws[pll->id] = hw;233 }234 235 return 0;236 237err:238 while (--i >= 0) {239 const struct mtk_pll_data *pll = &plls[i];240 struct mtk_pllfh_data *pllfh;241 bool use_fhctl;242 243 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);244 use_fhctl = fhctl_is_supported_and_enabled(pllfh);245 246 if (use_fhctl)247 mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);248 else249 mtk_clk_unregister_pll(clk_data->hws[pll->id]);250 251 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);252 }253 254 iounmap(base);255 256 return PTR_ERR(hw);257}258EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs);259 260void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,261 struct mtk_pllfh_data *pllfhs, int num_fhs,262 struct clk_hw_onecell_data *clk_data)263{264 void __iomem *base = NULL, *fhctl_base = NULL;265 int i;266 267 if (!clk_data)268 return;269 270 for (i = num_plls; i > 0; i--) {271 const struct mtk_pll_data *pll = &plls[i - 1];272 struct mtk_pllfh_data *pllfh;273 bool use_fhctl;274 275 if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))276 continue;277 278 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);279 use_fhctl = fhctl_is_supported_and_enabled(pllfh);280 281 if (use_fhctl) {282 fhctl_base = pllfh->state.base;283 mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);284 } else {285 base = mtk_clk_pll_get_base(clk_data->hws[pll->id],286 pll);287 mtk_clk_unregister_pll(clk_data->hws[pll->id]);288 }289 290 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);291 }292 293 if (fhctl_base)294 iounmap(fhctl_base);295 296 iounmap(base);297}298EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs);299