30 lines · plain
1# SPDX-License-Identifier: GPL-2.0-only2# Amlogic clock drivers3 4obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o5obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o6obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o7obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o8obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o9obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o10obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o11obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o12obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o13obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o14obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o15obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o16 17# Amlogic Clock controllers18 19obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o20obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o21obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o22obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o23obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o24obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o25obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o26obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o27obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o28obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o29obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o30