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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Amlogic A1 Peripherals Clock Controller internals4 *5 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.6 * Author: Jian Hu <jian.hu@amlogic.com>7 *8 * Copyright (c) 2023, SberDevices. All Rights Reserved.9 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>10 */11 12#ifndef __A1_PERIPHERALS_H13#define __A1_PERIPHERALS_H14 15/* peripherals clock controller register offset */16#define SYS_OSCIN_CTRL 0x017#define RTC_BY_OSCIN_CTRL0 0x418#define RTC_BY_OSCIN_CTRL1 0x819#define RTC_CTRL 0xc20#define SYS_CLK_CTRL0 0x1021#define SYS_CLK_EN0 0x1c22#define SYS_CLK_EN1 0x2023#define AXI_CLK_EN 0x2424#define DSPA_CLK_EN 0x2825#define DSPB_CLK_EN 0x2c26#define DSPA_CLK_CTRL0 0x3027#define DSPB_CLK_CTRL0 0x3428#define CLK12_24_CTRL 0x3829#define GEN_CLK_CTRL 0x3c30#define SAR_ADC_CLK_CTRL 0xc031#define PWM_CLK_AB_CTRL 0xc432#define PWM_CLK_CD_CTRL 0xc833#define PWM_CLK_EF_CTRL 0xcc34#define SPICC_CLK_CTRL 0xd035#define TS_CLK_CTRL 0xd436#define SPIFC_CLK_CTRL 0xd837#define USB_BUSCLK_CTRL 0xdc38#define SD_EMMC_CLK_CTRL 0xe039#define CECA_CLK_CTRL0 0xe440#define CECA_CLK_CTRL1 0xe841#define CECB_CLK_CTRL0 0xec42#define CECB_CLK_CTRL1 0xf043#define PSRAM_CLK_CTRL 0xf444#define DMC_CLK_CTRL 0xf845 46#endif /* __A1_PERIPHERALS_H */47