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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2018 BayLibre, SAS.4 * Author: Jerome Brunet <jbrunet@baylibre.com>5 */6 7#ifndef __AXG_AUDIO_CLKC_H8#define __AXG_AUDIO_CLKC_H9 10/*11 * Audio Clock register offsets12 *13 * Register offsets from the datasheet must be multiplied by 4 before14 * to get the right offset15 */16#define AUDIO_CLK_GATE_EN 0x00017#define AUDIO_MCLK_A_CTRL 0x00418#define AUDIO_MCLK_B_CTRL 0x00819#define AUDIO_MCLK_C_CTRL 0x00C20#define AUDIO_MCLK_D_CTRL 0x01021#define AUDIO_MCLK_E_CTRL 0x01422#define AUDIO_MCLK_F_CTRL 0x01823#define AUDIO_MST_PAD_CTRL0 0x01c24#define AUDIO_MST_PAD_CTRL1 0x02025#define AUDIO_SW_RESET 0x02426#define AUDIO_MST_A_SCLK_CTRL0 0x04027#define AUDIO_MST_A_SCLK_CTRL1 0x04428#define AUDIO_MST_B_SCLK_CTRL0 0x04829#define AUDIO_MST_B_SCLK_CTRL1 0x04C30#define AUDIO_MST_C_SCLK_CTRL0 0x05031#define AUDIO_MST_C_SCLK_CTRL1 0x05432#define AUDIO_MST_D_SCLK_CTRL0 0x05833#define AUDIO_MST_D_SCLK_CTRL1 0x05C34#define AUDIO_MST_E_SCLK_CTRL0 0x06035#define AUDIO_MST_E_SCLK_CTRL1 0x06436#define AUDIO_MST_F_SCLK_CTRL0 0x06837#define AUDIO_MST_F_SCLK_CTRL1 0x06C38#define AUDIO_CLK_TDMIN_A_CTRL 0x08039#define AUDIO_CLK_TDMIN_B_CTRL 0x08440#define AUDIO_CLK_TDMIN_C_CTRL 0x08841#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C42#define AUDIO_CLK_TDMOUT_A_CTRL 0x09043#define AUDIO_CLK_TDMOUT_B_CTRL 0x09444#define AUDIO_CLK_TDMOUT_C_CTRL 0x09845#define AUDIO_CLK_SPDIFIN_CTRL 0x09C46#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A047#define AUDIO_CLK_RESAMPLE_CTRL 0x0A448#define AUDIO_CLK_LOCKER_CTRL 0x0A849#define AUDIO_CLK_PDMIN_CTRL0 0x0AC50#define AUDIO_CLK_PDMIN_CTRL1 0x0B051#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B452 53/* SM1 introduce new register and some shifts :( */54#define AUDIO_CLK_GATE_EN1 0x00455#define AUDIO_SM1_MCLK_A_CTRL 0x00856#define AUDIO_SM1_MCLK_B_CTRL 0x00C57#define AUDIO_SM1_MCLK_C_CTRL 0x01058#define AUDIO_SM1_MCLK_D_CTRL 0x01459#define AUDIO_SM1_MCLK_E_CTRL 0x01860#define AUDIO_SM1_MCLK_F_CTRL 0x01C61#define AUDIO_SM1_MST_PAD_CTRL0 0x02062#define AUDIO_SM1_MST_PAD_CTRL1 0x02463#define AUDIO_SM1_SW_RESET0 0x02864#define AUDIO_SM1_SW_RESET1 0x02C65#define AUDIO_CLK81_CTRL 0x03066#define AUDIO_CLK81_EN 0x03467#define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D068#define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D469 70#endif /*__AXG_AUDIO_CLKC_H */71