106 lines · c
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright (c) 2016 AmLogic, Inc.4 * Author: Michael Turquette <mturquette@baylibre.com>5 *6 * Copyright (c) 2017 Amlogic, inc.7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>8 *9 */10#ifndef __AXG_H11#define __AXG_H12 13/*14 * Clock controller register offsets15 *16 * Register offsets from the data sheet must be multiplied by 4 before17 * adding them to the base address to get the right value.18 */19#define HHI_GP0_PLL_CNTL 0x4020#define HHI_GP0_PLL_CNTL2 0x4421#define HHI_GP0_PLL_CNTL3 0x4822#define HHI_GP0_PLL_CNTL4 0x4c23#define HHI_GP0_PLL_CNTL5 0x5024#define HHI_GP0_PLL_STS 0x5425#define HHI_GP0_PLL_CNTL1 0x5826#define HHI_HIFI_PLL_CNTL 0x8027#define HHI_HIFI_PLL_CNTL2 0x8428#define HHI_HIFI_PLL_CNTL3 0x8829#define HHI_HIFI_PLL_CNTL4 0x8C30#define HHI_HIFI_PLL_CNTL5 0x9031#define HHI_HIFI_PLL_STS 0x9432#define HHI_HIFI_PLL_CNTL1 0x9833 34#define HHI_XTAL_DIVN_CNTL 0xbc35#define HHI_GCLK2_MPEG0 0xc036#define HHI_GCLK2_MPEG1 0xc437#define HHI_GCLK2_MPEG2 0xc838#define HHI_GCLK2_OTHER 0xd039#define HHI_GCLK2_AO 0xd440#define HHI_PCIE_PLL_CNTL 0xd841#define HHI_PCIE_PLL_CNTL1 0xdC42#define HHI_PCIE_PLL_CNTL2 0xe043#define HHI_PCIE_PLL_CNTL3 0xe444#define HHI_PCIE_PLL_CNTL4 0xe845#define HHI_PCIE_PLL_CNTL5 0xec46#define HHI_PCIE_PLL_CNTL6 0xf047#define HHI_PCIE_PLL_STS 0xf448 49#define HHI_MEM_PD_REG0 0x10050#define HHI_VPU_MEM_PD_REG0 0x10451#define HHI_VIID_CLK_DIV 0x12852#define HHI_VIID_CLK_CNTL 0x12c53 54#define HHI_GCLK_MPEG0 0x14055#define HHI_GCLK_MPEG1 0x14456#define HHI_GCLK_MPEG2 0x14857#define HHI_GCLK_OTHER 0x15058#define HHI_GCLK_AO 0x15459#define HHI_SYS_CPU_CLK_CNTL1 0x15c60#define HHI_SYS_CPU_RESET_CNTL 0x16061#define HHI_VID_CLK_DIV 0x16462#define HHI_SPICC_HCLK_CNTL 0x16863 64#define HHI_MPEG_CLK_CNTL 0x17465#define HHI_VID_CLK_CNTL 0x17c66#define HHI_TS_CLK_CNTL 0x19067#define HHI_VID_CLK_CNTL2 0x19468#define HHI_SYS_CPU_CLK_CNTL0 0x19c69#define HHI_VID_PLL_CLK_DIV 0x1a070#define HHI_VPU_CLK_CNTL 0x1bC71 72#define HHI_VAPBCLK_CNTL 0x1F473 74#define HHI_GEN_CLK_CNTL 0x22875 76#define HHI_VDIN_MEAS_CLK_CNTL 0x25077#define HHI_NAND_CLK_CNTL 0x25C78#define HHI_SD_EMMC_CLK_CNTL 0x26479 80#define HHI_MPLL_CNTL 0x28081#define HHI_MPLL_CNTL2 0x28482#define HHI_MPLL_CNTL3 0x28883#define HHI_MPLL_CNTL4 0x28C84#define HHI_MPLL_CNTL5 0x29085#define HHI_MPLL_CNTL6 0x29486#define HHI_MPLL_CNTL7 0x29887#define HHI_MPLL_CNTL8 0x29C88#define HHI_MPLL_CNTL9 0x2A089#define HHI_MPLL_CNTL10 0x2A490 91#define HHI_MPLL3_CNTL0 0x2E092#define HHI_MPLL3_CNTL1 0x2E493#define HHI_PLL_TOP_MISC 0x2E894 95#define HHI_SYS_PLL_CNTL1 0x2FC96#define HHI_SYS_PLL_CNTL 0x30097#define HHI_SYS_PLL_CNTL2 0x30498#define HHI_SYS_PLL_CNTL3 0x30899#define HHI_SYS_PLL_CNTL4 0x30c100#define HHI_SYS_PLL_CNTL5 0x310101#define HHI_SYS_PLL_STS 0x314102#define HHI_DPLL_TOP_I 0x318103#define HHI_DPLL_TOP2_I 0x31C104 105#endif /* __AXG_H */106