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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Amlogic Meson-G12A Clock Controller Driver4 *5 * Copyright (c) 2016 Baylibre SAS.6 * Author: Michael Turquette <mturquette@baylibre.com>7 *8 * Copyright (c) 2018 Amlogic, inc.9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>10 * Author: Jian Hu <jian.hu@amlogic.com>11 */12 13#include <linux/clk-provider.h>14#include <linux/init.h>15#include <linux/of.h>16#include <linux/platform_device.h>17#include <linux/clk.h>18#include <linux/module.h>19 20#include "clk-mpll.h"21#include "clk-pll.h"22#include "clk-regmap.h"23#include "clk-cpu-dyndiv.h"24#include "vid-pll-div.h"25#include "vclk.h"26#include "meson-eeclk.h"27#include "g12a.h"28 29#include <dt-bindings/clock/g12a-clkc.h>30 31static DEFINE_SPINLOCK(meson_clk_lock);32 33static struct clk_regmap g12a_fixed_pll_dco = {34 .data = &(struct meson_clk_pll_data){35 .en = {36 .reg_off = HHI_FIX_PLL_CNTL0,37 .shift = 28,38 .width = 1,39 },40 .m = {41 .reg_off = HHI_FIX_PLL_CNTL0,42 .shift = 0,43 .width = 8,44 },45 .n = {46 .reg_off = HHI_FIX_PLL_CNTL0,47 .shift = 10,48 .width = 5,49 },50 .frac = {51 .reg_off = HHI_FIX_PLL_CNTL1,52 .shift = 0,53 .width = 17,54 },55 .l = {56 .reg_off = HHI_FIX_PLL_CNTL0,57 .shift = 31,58 .width = 1,59 },60 .rst = {61 .reg_off = HHI_FIX_PLL_CNTL0,62 .shift = 29,63 .width = 1,64 },65 },66 .hw.init = &(struct clk_init_data){67 .name = "fixed_pll_dco",68 .ops = &meson_clk_pll_ro_ops,69 .parent_data = &(const struct clk_parent_data) {70 .fw_name = "xtal",71 },72 .num_parents = 1,73 },74};75 76static struct clk_regmap g12a_fixed_pll = {77 .data = &(struct clk_regmap_div_data){78 .offset = HHI_FIX_PLL_CNTL0,79 .shift = 16,80 .width = 2,81 .flags = CLK_DIVIDER_POWER_OF_TWO,82 },83 .hw.init = &(struct clk_init_data){84 .name = "fixed_pll",85 .ops = &clk_regmap_divider_ro_ops,86 .parent_hws = (const struct clk_hw *[]) {87 &g12a_fixed_pll_dco.hw88 },89 .num_parents = 1,90 /*91 * This clock won't ever change at runtime so92 * CLK_SET_RATE_PARENT is not required93 */94 },95};96 97static const struct pll_mult_range g12a_sys_pll_mult_range = {98 .min = 128,99 .max = 250,100};101 102static struct clk_regmap g12a_sys_pll_dco = {103 .data = &(struct meson_clk_pll_data){104 .en = {105 .reg_off = HHI_SYS_PLL_CNTL0,106 .shift = 28,107 .width = 1,108 },109 .m = {110 .reg_off = HHI_SYS_PLL_CNTL0,111 .shift = 0,112 .width = 8,113 },114 .n = {115 .reg_off = HHI_SYS_PLL_CNTL0,116 .shift = 10,117 .width = 5,118 },119 .l = {120 .reg_off = HHI_SYS_PLL_CNTL0,121 .shift = 31,122 .width = 1,123 },124 .rst = {125 .reg_off = HHI_SYS_PLL_CNTL0,126 .shift = 29,127 .width = 1,128 },129 .range = &g12a_sys_pll_mult_range,130 },131 .hw.init = &(struct clk_init_data){132 .name = "sys_pll_dco",133 .ops = &meson_clk_pll_ops,134 .parent_data = &(const struct clk_parent_data) {135 .fw_name = "xtal",136 },137 .num_parents = 1,138 /* This clock feeds the CPU, avoid disabling it */139 .flags = CLK_IS_CRITICAL,140 },141};142 143static struct clk_regmap g12a_sys_pll = {144 .data = &(struct clk_regmap_div_data){145 .offset = HHI_SYS_PLL_CNTL0,146 .shift = 16,147 .width = 3,148 .flags = CLK_DIVIDER_POWER_OF_TWO,149 },150 .hw.init = &(struct clk_init_data){151 .name = "sys_pll",152 .ops = &clk_regmap_divider_ops,153 .parent_hws = (const struct clk_hw *[]) {154 &g12a_sys_pll_dco.hw155 },156 .num_parents = 1,157 .flags = CLK_SET_RATE_PARENT,158 },159};160 161static struct clk_regmap g12b_sys1_pll_dco = {162 .data = &(struct meson_clk_pll_data){163 .en = {164 .reg_off = HHI_SYS1_PLL_CNTL0,165 .shift = 28,166 .width = 1,167 },168 .m = {169 .reg_off = HHI_SYS1_PLL_CNTL0,170 .shift = 0,171 .width = 8,172 },173 .n = {174 .reg_off = HHI_SYS1_PLL_CNTL0,175 .shift = 10,176 .width = 5,177 },178 .l = {179 .reg_off = HHI_SYS1_PLL_CNTL0,180 .shift = 31,181 .width = 1,182 },183 .rst = {184 .reg_off = HHI_SYS1_PLL_CNTL0,185 .shift = 29,186 .width = 1,187 },188 .range = &g12a_sys_pll_mult_range,189 },190 .hw.init = &(struct clk_init_data){191 .name = "sys1_pll_dco",192 .ops = &meson_clk_pll_ops,193 .parent_data = &(const struct clk_parent_data) {194 .fw_name = "xtal",195 },196 .num_parents = 1,197 /* This clock feeds the CPU, avoid disabling it */198 .flags = CLK_IS_CRITICAL,199 },200};201 202static struct clk_regmap g12b_sys1_pll = {203 .data = &(struct clk_regmap_div_data){204 .offset = HHI_SYS1_PLL_CNTL0,205 .shift = 16,206 .width = 3,207 .flags = CLK_DIVIDER_POWER_OF_TWO,208 },209 .hw.init = &(struct clk_init_data){210 .name = "sys1_pll",211 .ops = &clk_regmap_divider_ops,212 .parent_hws = (const struct clk_hw *[]) {213 &g12b_sys1_pll_dco.hw214 },215 .num_parents = 1,216 .flags = CLK_SET_RATE_PARENT,217 },218};219 220static struct clk_regmap g12a_sys_pll_div16_en = {221 .data = &(struct clk_regmap_gate_data){222 .offset = HHI_SYS_CPU_CLK_CNTL1,223 .bit_idx = 24,224 },225 .hw.init = &(struct clk_init_data) {226 .name = "sys_pll_div16_en",227 .ops = &clk_regmap_gate_ro_ops,228 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },229 .num_parents = 1,230 /*231 * This clock is used to debug the sys_pll range232 * Linux should not change it at runtime233 */234 },235};236 237static struct clk_regmap g12b_sys1_pll_div16_en = {238 .data = &(struct clk_regmap_gate_data){239 .offset = HHI_SYS_CPUB_CLK_CNTL1,240 .bit_idx = 24,241 },242 .hw.init = &(struct clk_init_data) {243 .name = "sys1_pll_div16_en",244 .ops = &clk_regmap_gate_ro_ops,245 .parent_hws = (const struct clk_hw *[]) {246 &g12b_sys1_pll.hw247 },248 .num_parents = 1,249 /*250 * This clock is used to debug the sys_pll range251 * Linux should not change it at runtime252 */253 },254};255 256static struct clk_fixed_factor g12a_sys_pll_div16 = {257 .mult = 1,258 .div = 16,259 .hw.init = &(struct clk_init_data){260 .name = "sys_pll_div16",261 .ops = &clk_fixed_factor_ops,262 .parent_hws = (const struct clk_hw *[]) {263 &g12a_sys_pll_div16_en.hw264 },265 .num_parents = 1,266 },267};268 269static struct clk_fixed_factor g12b_sys1_pll_div16 = {270 .mult = 1,271 .div = 16,272 .hw.init = &(struct clk_init_data){273 .name = "sys1_pll_div16",274 .ops = &clk_fixed_factor_ops,275 .parent_hws = (const struct clk_hw *[]) {276 &g12b_sys1_pll_div16_en.hw277 },278 .num_parents = 1,279 },280};281 282static struct clk_fixed_factor g12a_fclk_div2_div = {283 .mult = 1,284 .div = 2,285 .hw.init = &(struct clk_init_data){286 .name = "fclk_div2_div",287 .ops = &clk_fixed_factor_ops,288 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },289 .num_parents = 1,290 },291};292 293static struct clk_regmap g12a_fclk_div2 = {294 .data = &(struct clk_regmap_gate_data){295 .offset = HHI_FIX_PLL_CNTL1,296 .bit_idx = 24,297 },298 .hw.init = &(struct clk_init_data){299 .name = "fclk_div2",300 .ops = &clk_regmap_gate_ops,301 .parent_hws = (const struct clk_hw *[]) {302 &g12a_fclk_div2_div.hw303 },304 .num_parents = 1,305 /*306 * Similar to fclk_div3, it seems that this clock is used by307 * the resident firmware and is required by the platform to308 * operate correctly.309 * Until the following condition are met, we need this clock to310 * be marked as critical:311 * a) Mark the clock used by a firmware resource, if possible312 * b) CCF has a clock hand-off mechanism to make the sure the313 * clock stays on until the proper driver comes along314 */315 .flags = CLK_IS_CRITICAL,316 },317};318 319static struct clk_fixed_factor g12a_fclk_div3_div = {320 .mult = 1,321 .div = 3,322 .hw.init = &(struct clk_init_data){323 .name = "fclk_div3_div",324 .ops = &clk_fixed_factor_ops,325 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },326 .num_parents = 1,327 },328};329 330static struct clk_regmap g12a_fclk_div3 = {331 .data = &(struct clk_regmap_gate_data){332 .offset = HHI_FIX_PLL_CNTL1,333 .bit_idx = 20,334 },335 .hw.init = &(struct clk_init_data){336 .name = "fclk_div3",337 .ops = &clk_regmap_gate_ops,338 .parent_hws = (const struct clk_hw *[]) {339 &g12a_fclk_div3_div.hw340 },341 .num_parents = 1,342 /*343 * This clock is used by the resident firmware and is required344 * by the platform to operate correctly.345 * Until the following condition are met, we need this clock to346 * be marked as critical:347 * a) Mark the clock used by a firmware resource, if possible348 * b) CCF has a clock hand-off mechanism to make the sure the349 * clock stays on until the proper driver comes along350 */351 .flags = CLK_IS_CRITICAL,352 },353};354 355/* Datasheet names this field as "premux0" */356static struct clk_regmap g12a_cpu_clk_premux0 = {357 .data = &(struct clk_regmap_mux_data){358 .offset = HHI_SYS_CPU_CLK_CNTL0,359 .mask = 0x3,360 .shift = 0,361 .flags = CLK_MUX_ROUND_CLOSEST,362 },363 .hw.init = &(struct clk_init_data){364 .name = "cpu_clk_dyn0_sel",365 .ops = &clk_regmap_mux_ops,366 .parent_data = (const struct clk_parent_data []) {367 { .fw_name = "xtal", },368 { .hw = &g12a_fclk_div2.hw },369 { .hw = &g12a_fclk_div3.hw },370 },371 .num_parents = 3,372 .flags = CLK_SET_RATE_PARENT,373 },374};375 376/* Datasheet names this field as "premux1" */377static struct clk_regmap g12a_cpu_clk_premux1 = {378 .data = &(struct clk_regmap_mux_data){379 .offset = HHI_SYS_CPU_CLK_CNTL0,380 .mask = 0x3,381 .shift = 16,382 },383 .hw.init = &(struct clk_init_data){384 .name = "cpu_clk_dyn1_sel",385 .ops = &clk_regmap_mux_ops,386 .parent_data = (const struct clk_parent_data []) {387 { .fw_name = "xtal", },388 { .hw = &g12a_fclk_div2.hw },389 { .hw = &g12a_fclk_div3.hw },390 },391 .num_parents = 3,392 /* This sub-tree is used a parking clock */393 .flags = CLK_SET_RATE_NO_REPARENT394 },395};396 397/* Datasheet names this field as "mux0_divn_tcnt" */398static struct clk_regmap g12a_cpu_clk_mux0_div = {399 .data = &(struct meson_clk_cpu_dyndiv_data){400 .div = {401 .reg_off = HHI_SYS_CPU_CLK_CNTL0,402 .shift = 4,403 .width = 6,404 },405 .dyn = {406 .reg_off = HHI_SYS_CPU_CLK_CNTL0,407 .shift = 26,408 .width = 1,409 },410 },411 .hw.init = &(struct clk_init_data){412 .name = "cpu_clk_dyn0_div",413 .ops = &meson_clk_cpu_dyndiv_ops,414 .parent_hws = (const struct clk_hw *[]) {415 &g12a_cpu_clk_premux0.hw416 },417 .num_parents = 1,418 .flags = CLK_SET_RATE_PARENT,419 },420};421 422/* Datasheet names this field as "postmux0" */423static struct clk_regmap g12a_cpu_clk_postmux0 = {424 .data = &(struct clk_regmap_mux_data){425 .offset = HHI_SYS_CPU_CLK_CNTL0,426 .mask = 0x1,427 .shift = 2,428 .flags = CLK_MUX_ROUND_CLOSEST,429 },430 .hw.init = &(struct clk_init_data){431 .name = "cpu_clk_dyn0",432 .ops = &clk_regmap_mux_ops,433 .parent_hws = (const struct clk_hw *[]) {434 &g12a_cpu_clk_premux0.hw,435 &g12a_cpu_clk_mux0_div.hw,436 },437 .num_parents = 2,438 .flags = CLK_SET_RATE_PARENT,439 },440};441 442/* Datasheet names this field as "Mux1_divn_tcnt" */443static struct clk_regmap g12a_cpu_clk_mux1_div = {444 .data = &(struct clk_regmap_div_data){445 .offset = HHI_SYS_CPU_CLK_CNTL0,446 .shift = 20,447 .width = 6,448 },449 .hw.init = &(struct clk_init_data){450 .name = "cpu_clk_dyn1_div",451 .ops = &clk_regmap_divider_ro_ops,452 .parent_hws = (const struct clk_hw *[]) {453 &g12a_cpu_clk_premux1.hw454 },455 .num_parents = 1,456 },457};458 459/* Datasheet names this field as "postmux1" */460static struct clk_regmap g12a_cpu_clk_postmux1 = {461 .data = &(struct clk_regmap_mux_data){462 .offset = HHI_SYS_CPU_CLK_CNTL0,463 .mask = 0x1,464 .shift = 18,465 },466 .hw.init = &(struct clk_init_data){467 .name = "cpu_clk_dyn1",468 .ops = &clk_regmap_mux_ops,469 .parent_hws = (const struct clk_hw *[]) {470 &g12a_cpu_clk_premux1.hw,471 &g12a_cpu_clk_mux1_div.hw,472 },473 .num_parents = 2,474 /* This sub-tree is used a parking clock */475 .flags = CLK_SET_RATE_NO_REPARENT,476 },477};478 479/* Datasheet names this field as "Final_dyn_mux_sel" */480static struct clk_regmap g12a_cpu_clk_dyn = {481 .data = &(struct clk_regmap_mux_data){482 .offset = HHI_SYS_CPU_CLK_CNTL0,483 .mask = 0x1,484 .shift = 10,485 .flags = CLK_MUX_ROUND_CLOSEST,486 },487 .hw.init = &(struct clk_init_data){488 .name = "cpu_clk_dyn",489 .ops = &clk_regmap_mux_ops,490 .parent_hws = (const struct clk_hw *[]) {491 &g12a_cpu_clk_postmux0.hw,492 &g12a_cpu_clk_postmux1.hw,493 },494 .num_parents = 2,495 .flags = CLK_SET_RATE_PARENT,496 },497};498 499/* Datasheet names this field as "Final_mux_sel" */500static struct clk_regmap g12a_cpu_clk = {501 .data = &(struct clk_regmap_mux_data){502 .offset = HHI_SYS_CPU_CLK_CNTL0,503 .mask = 0x1,504 .shift = 11,505 .flags = CLK_MUX_ROUND_CLOSEST,506 },507 .hw.init = &(struct clk_init_data){508 .name = "cpu_clk",509 .ops = &clk_regmap_mux_ops,510 .parent_hws = (const struct clk_hw *[]) {511 &g12a_cpu_clk_dyn.hw,512 &g12a_sys_pll.hw,513 },514 .num_parents = 2,515 .flags = CLK_SET_RATE_PARENT,516 },517};518 519/* Datasheet names this field as "Final_mux_sel" */520static struct clk_regmap g12b_cpu_clk = {521 .data = &(struct clk_regmap_mux_data){522 .offset = HHI_SYS_CPU_CLK_CNTL0,523 .mask = 0x1,524 .shift = 11,525 .flags = CLK_MUX_ROUND_CLOSEST,526 },527 .hw.init = &(struct clk_init_data){528 .name = "cpu_clk",529 .ops = &clk_regmap_mux_ops,530 .parent_hws = (const struct clk_hw *[]) {531 &g12a_cpu_clk_dyn.hw,532 &g12b_sys1_pll.hw533 },534 .num_parents = 2,535 .flags = CLK_SET_RATE_PARENT,536 },537};538 539/* Datasheet names this field as "premux0" */540static struct clk_regmap g12b_cpub_clk_premux0 = {541 .data = &(struct clk_regmap_mux_data){542 .offset = HHI_SYS_CPUB_CLK_CNTL,543 .mask = 0x3,544 .shift = 0,545 .flags = CLK_MUX_ROUND_CLOSEST,546 },547 .hw.init = &(struct clk_init_data){548 .name = "cpub_clk_dyn0_sel",549 .ops = &clk_regmap_mux_ops,550 .parent_data = (const struct clk_parent_data []) {551 { .fw_name = "xtal", },552 { .hw = &g12a_fclk_div2.hw },553 { .hw = &g12a_fclk_div3.hw },554 },555 .num_parents = 3,556 .flags = CLK_SET_RATE_PARENT,557 },558};559 560/* Datasheet names this field as "mux0_divn_tcnt" */561static struct clk_regmap g12b_cpub_clk_mux0_div = {562 .data = &(struct meson_clk_cpu_dyndiv_data){563 .div = {564 .reg_off = HHI_SYS_CPUB_CLK_CNTL,565 .shift = 4,566 .width = 6,567 },568 .dyn = {569 .reg_off = HHI_SYS_CPUB_CLK_CNTL,570 .shift = 26,571 .width = 1,572 },573 },574 .hw.init = &(struct clk_init_data){575 .name = "cpub_clk_dyn0_div",576 .ops = &meson_clk_cpu_dyndiv_ops,577 .parent_hws = (const struct clk_hw *[]) {578 &g12b_cpub_clk_premux0.hw579 },580 .num_parents = 1,581 .flags = CLK_SET_RATE_PARENT,582 },583};584 585/* Datasheet names this field as "postmux0" */586static struct clk_regmap g12b_cpub_clk_postmux0 = {587 .data = &(struct clk_regmap_mux_data){588 .offset = HHI_SYS_CPUB_CLK_CNTL,589 .mask = 0x1,590 .shift = 2,591 .flags = CLK_MUX_ROUND_CLOSEST,592 },593 .hw.init = &(struct clk_init_data){594 .name = "cpub_clk_dyn0",595 .ops = &clk_regmap_mux_ops,596 .parent_hws = (const struct clk_hw *[]) {597 &g12b_cpub_clk_premux0.hw,598 &g12b_cpub_clk_mux0_div.hw599 },600 .num_parents = 2,601 .flags = CLK_SET_RATE_PARENT,602 },603};604 605/* Datasheet names this field as "premux1" */606static struct clk_regmap g12b_cpub_clk_premux1 = {607 .data = &(struct clk_regmap_mux_data){608 .offset = HHI_SYS_CPUB_CLK_CNTL,609 .mask = 0x3,610 .shift = 16,611 },612 .hw.init = &(struct clk_init_data){613 .name = "cpub_clk_dyn1_sel",614 .ops = &clk_regmap_mux_ops,615 .parent_data = (const struct clk_parent_data []) {616 { .fw_name = "xtal", },617 { .hw = &g12a_fclk_div2.hw },618 { .hw = &g12a_fclk_div3.hw },619 },620 .num_parents = 3,621 /* This sub-tree is used a parking clock */622 .flags = CLK_SET_RATE_NO_REPARENT,623 },624};625 626/* Datasheet names this field as "Mux1_divn_tcnt" */627static struct clk_regmap g12b_cpub_clk_mux1_div = {628 .data = &(struct clk_regmap_div_data){629 .offset = HHI_SYS_CPUB_CLK_CNTL,630 .shift = 20,631 .width = 6,632 },633 .hw.init = &(struct clk_init_data){634 .name = "cpub_clk_dyn1_div",635 .ops = &clk_regmap_divider_ro_ops,636 .parent_hws = (const struct clk_hw *[]) {637 &g12b_cpub_clk_premux1.hw638 },639 .num_parents = 1,640 },641};642 643/* Datasheet names this field as "postmux1" */644static struct clk_regmap g12b_cpub_clk_postmux1 = {645 .data = &(struct clk_regmap_mux_data){646 .offset = HHI_SYS_CPUB_CLK_CNTL,647 .mask = 0x1,648 .shift = 18,649 },650 .hw.init = &(struct clk_init_data){651 .name = "cpub_clk_dyn1",652 .ops = &clk_regmap_mux_ops,653 .parent_hws = (const struct clk_hw *[]) {654 &g12b_cpub_clk_premux1.hw,655 &g12b_cpub_clk_mux1_div.hw656 },657 .num_parents = 2,658 /* This sub-tree is used a parking clock */659 .flags = CLK_SET_RATE_NO_REPARENT,660 },661};662 663/* Datasheet names this field as "Final_dyn_mux_sel" */664static struct clk_regmap g12b_cpub_clk_dyn = {665 .data = &(struct clk_regmap_mux_data){666 .offset = HHI_SYS_CPUB_CLK_CNTL,667 .mask = 0x1,668 .shift = 10,669 .flags = CLK_MUX_ROUND_CLOSEST,670 },671 .hw.init = &(struct clk_init_data){672 .name = "cpub_clk_dyn",673 .ops = &clk_regmap_mux_ops,674 .parent_hws = (const struct clk_hw *[]) {675 &g12b_cpub_clk_postmux0.hw,676 &g12b_cpub_clk_postmux1.hw677 },678 .num_parents = 2,679 .flags = CLK_SET_RATE_PARENT,680 },681};682 683/* Datasheet names this field as "Final_mux_sel" */684static struct clk_regmap g12b_cpub_clk = {685 .data = &(struct clk_regmap_mux_data){686 .offset = HHI_SYS_CPUB_CLK_CNTL,687 .mask = 0x1,688 .shift = 11,689 .flags = CLK_MUX_ROUND_CLOSEST,690 },691 .hw.init = &(struct clk_init_data){692 .name = "cpub_clk",693 .ops = &clk_regmap_mux_ops,694 .parent_hws = (const struct clk_hw *[]) {695 &g12b_cpub_clk_dyn.hw,696 &g12a_sys_pll.hw697 },698 .num_parents = 2,699 .flags = CLK_SET_RATE_PARENT,700 },701};702 703static struct clk_regmap sm1_gp1_pll;704 705/* Datasheet names this field as "premux0" */706static struct clk_regmap sm1_dsu_clk_premux0 = {707 .data = &(struct clk_regmap_mux_data){708 .offset = HHI_SYS_CPU_CLK_CNTL5,709 .mask = 0x3,710 .shift = 0,711 },712 .hw.init = &(struct clk_init_data){713 .name = "dsu_clk_dyn0_sel",714 .ops = &clk_regmap_mux_ro_ops,715 .parent_data = (const struct clk_parent_data []) {716 { .fw_name = "xtal", },717 { .hw = &g12a_fclk_div2.hw },718 { .hw = &g12a_fclk_div3.hw },719 { .hw = &sm1_gp1_pll.hw },720 },721 .num_parents = 4,722 },723};724 725/* Datasheet names this field as "premux1" */726static struct clk_regmap sm1_dsu_clk_premux1 = {727 .data = &(struct clk_regmap_mux_data){728 .offset = HHI_SYS_CPU_CLK_CNTL5,729 .mask = 0x3,730 .shift = 16,731 },732 .hw.init = &(struct clk_init_data){733 .name = "dsu_clk_dyn1_sel",734 .ops = &clk_regmap_mux_ro_ops,735 .parent_data = (const struct clk_parent_data []) {736 { .fw_name = "xtal", },737 { .hw = &g12a_fclk_div2.hw },738 { .hw = &g12a_fclk_div3.hw },739 { .hw = &sm1_gp1_pll.hw },740 },741 .num_parents = 4,742 },743};744 745/* Datasheet names this field as "Mux0_divn_tcnt" */746static struct clk_regmap sm1_dsu_clk_mux0_div = {747 .data = &(struct clk_regmap_div_data){748 .offset = HHI_SYS_CPU_CLK_CNTL5,749 .shift = 4,750 .width = 6,751 },752 .hw.init = &(struct clk_init_data){753 .name = "dsu_clk_dyn0_div",754 .ops = &clk_regmap_divider_ro_ops,755 .parent_hws = (const struct clk_hw *[]) {756 &sm1_dsu_clk_premux0.hw757 },758 .num_parents = 1,759 },760};761 762/* Datasheet names this field as "postmux0" */763static struct clk_regmap sm1_dsu_clk_postmux0 = {764 .data = &(struct clk_regmap_mux_data){765 .offset = HHI_SYS_CPU_CLK_CNTL5,766 .mask = 0x1,767 .shift = 2,768 },769 .hw.init = &(struct clk_init_data){770 .name = "dsu_clk_dyn0",771 .ops = &clk_regmap_mux_ro_ops,772 .parent_hws = (const struct clk_hw *[]) {773 &sm1_dsu_clk_premux0.hw,774 &sm1_dsu_clk_mux0_div.hw,775 },776 .num_parents = 2,777 },778};779 780/* Datasheet names this field as "Mux1_divn_tcnt" */781static struct clk_regmap sm1_dsu_clk_mux1_div = {782 .data = &(struct clk_regmap_div_data){783 .offset = HHI_SYS_CPU_CLK_CNTL5,784 .shift = 20,785 .width = 6,786 },787 .hw.init = &(struct clk_init_data){788 .name = "dsu_clk_dyn1_div",789 .ops = &clk_regmap_divider_ro_ops,790 .parent_hws = (const struct clk_hw *[]) {791 &sm1_dsu_clk_premux1.hw792 },793 .num_parents = 1,794 },795};796 797/* Datasheet names this field as "postmux1" */798static struct clk_regmap sm1_dsu_clk_postmux1 = {799 .data = &(struct clk_regmap_mux_data){800 .offset = HHI_SYS_CPU_CLK_CNTL5,801 .mask = 0x1,802 .shift = 18,803 },804 .hw.init = &(struct clk_init_data){805 .name = "dsu_clk_dyn1",806 .ops = &clk_regmap_mux_ro_ops,807 .parent_hws = (const struct clk_hw *[]) {808 &sm1_dsu_clk_premux1.hw,809 &sm1_dsu_clk_mux1_div.hw,810 },811 .num_parents = 2,812 },813};814 815/* Datasheet names this field as "Final_dyn_mux_sel" */816static struct clk_regmap sm1_dsu_clk_dyn = {817 .data = &(struct clk_regmap_mux_data){818 .offset = HHI_SYS_CPU_CLK_CNTL5,819 .mask = 0x1,820 .shift = 10,821 },822 .hw.init = &(struct clk_init_data){823 .name = "dsu_clk_dyn",824 .ops = &clk_regmap_mux_ro_ops,825 .parent_hws = (const struct clk_hw *[]) {826 &sm1_dsu_clk_postmux0.hw,827 &sm1_dsu_clk_postmux1.hw,828 },829 .num_parents = 2,830 },831};832 833/* Datasheet names this field as "Final_mux_sel" */834static struct clk_regmap sm1_dsu_final_clk = {835 .data = &(struct clk_regmap_mux_data){836 .offset = HHI_SYS_CPU_CLK_CNTL5,837 .mask = 0x1,838 .shift = 11,839 },840 .hw.init = &(struct clk_init_data){841 .name = "dsu_clk_final",842 .ops = &clk_regmap_mux_ro_ops,843 .parent_hws = (const struct clk_hw *[]) {844 &sm1_dsu_clk_dyn.hw,845 &g12a_sys_pll.hw,846 },847 .num_parents = 2,848 },849};850 851/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */852static struct clk_regmap sm1_cpu1_clk = {853 .data = &(struct clk_regmap_mux_data){854 .offset = HHI_SYS_CPU_CLK_CNTL6,855 .mask = 0x1,856 .shift = 24,857 },858 .hw.init = &(struct clk_init_data){859 .name = "cpu1_clk",860 .ops = &clk_regmap_mux_ro_ops,861 .parent_hws = (const struct clk_hw *[]) {862 &g12a_cpu_clk.hw,863 /* This CPU also have a dedicated clock tree */864 },865 .num_parents = 1,866 },867};868 869/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */870static struct clk_regmap sm1_cpu2_clk = {871 .data = &(struct clk_regmap_mux_data){872 .offset = HHI_SYS_CPU_CLK_CNTL6,873 .mask = 0x1,874 .shift = 25,875 },876 .hw.init = &(struct clk_init_data){877 .name = "cpu2_clk",878 .ops = &clk_regmap_mux_ro_ops,879 .parent_hws = (const struct clk_hw *[]) {880 &g12a_cpu_clk.hw,881 /* This CPU also have a dedicated clock tree */882 },883 .num_parents = 1,884 },885};886 887/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */888static struct clk_regmap sm1_cpu3_clk = {889 .data = &(struct clk_regmap_mux_data){890 .offset = HHI_SYS_CPU_CLK_CNTL6,891 .mask = 0x1,892 .shift = 26,893 },894 .hw.init = &(struct clk_init_data){895 .name = "cpu3_clk",896 .ops = &clk_regmap_mux_ro_ops,897 .parent_hws = (const struct clk_hw *[]) {898 &g12a_cpu_clk.hw,899 /* This CPU also have a dedicated clock tree */900 },901 .num_parents = 1,902 },903};904 905/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */906static struct clk_regmap sm1_dsu_clk = {907 .data = &(struct clk_regmap_mux_data){908 .offset = HHI_SYS_CPU_CLK_CNTL6,909 .mask = 0x1,910 .shift = 27,911 },912 .hw.init = &(struct clk_init_data){913 .name = "dsu_clk",914 .ops = &clk_regmap_mux_ro_ops,915 .parent_hws = (const struct clk_hw *[]) {916 &g12a_cpu_clk.hw,917 &sm1_dsu_final_clk.hw,918 },919 .num_parents = 2,920 },921};922 923static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,924 unsigned long event, void *data)925{926 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {927 /* Wait for clock propagation before/after changing the mux */928 udelay(100);929 return NOTIFY_OK;930 }931 932 return NOTIFY_DONE;933}934 935static struct notifier_block g12a_cpu_clk_mux_nb = {936 .notifier_call = g12a_cpu_clk_mux_notifier_cb,937};938 939struct g12a_cpu_clk_postmux_nb_data {940 struct notifier_block nb;941 struct clk_hw *xtal;942 struct clk_hw *cpu_clk_dyn;943 struct clk_hw *cpu_clk_postmux0;944 struct clk_hw *cpu_clk_postmux1;945 struct clk_hw *cpu_clk_premux1;946};947 948static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,949 unsigned long event, void *data)950{951 struct g12a_cpu_clk_postmux_nb_data *nb_data =952 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);953 954 switch (event) {955 case PRE_RATE_CHANGE:956 /*957 * This notifier means cpu_clk_postmux0 clock will be changed958 * to feed cpu_clk, this is the current path :959 * cpu_clk960 * \- cpu_clk_dyn961 * \- cpu_clk_postmux0962 * \- cpu_clk_muxX_div963 * \- cpu_clk_premux0964 * \- fclk_div3 or fclk_div2965 * OR966 * \- cpu_clk_premux0967 * \- fclk_div3 or fclk_div2968 */969 970 /* Setup cpu_clk_premux1 to xtal */971 clk_hw_set_parent(nb_data->cpu_clk_premux1,972 nb_data->xtal);973 974 /* Setup cpu_clk_postmux1 to bypass divider */975 clk_hw_set_parent(nb_data->cpu_clk_postmux1,976 nb_data->cpu_clk_premux1);977 978 /* Switch to parking clk on cpu_clk_postmux1 */979 clk_hw_set_parent(nb_data->cpu_clk_dyn,980 nb_data->cpu_clk_postmux1);981 982 /*983 * Now, cpu_clk is 24MHz in the current path :984 * cpu_clk985 * \- cpu_clk_dyn986 * \- cpu_clk_postmux1987 * \- cpu_clk_premux1988 * \- xtal989 */990 991 udelay(100);992 993 return NOTIFY_OK;994 995 case POST_RATE_CHANGE:996 /*997 * The cpu_clk_postmux0 has ben updated, now switch back998 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes999 * in account.1000 */1001 1002 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */1003 clk_hw_set_parent(nb_data->cpu_clk_dyn,1004 nb_data->cpu_clk_postmux0);1005 1006 /*1007 * new path :1008 * cpu_clk1009 * \- cpu_clk_dyn1010 * \- cpu_clk_postmux01011 * \- cpu_clk_muxX_div1012 * \- cpu_clk_premux01013 * \- fclk_div3 or fclk_div21014 * OR1015 * \- cpu_clk_premux01016 * \- fclk_div3 or fclk_div21017 */1018 1019 udelay(100);1020 1021 return NOTIFY_OK;1022 1023 default:1024 return NOTIFY_DONE;1025 }1026}1027 1028static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {1029 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,1030 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,1031 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,1032 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,1033 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,1034};1035 1036static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {1037 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,1038 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,1039 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,1040 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,1041 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,1042};1043 1044struct g12a_sys_pll_nb_data {1045 struct notifier_block nb;1046 struct clk_hw *sys_pll;1047 struct clk_hw *cpu_clk;1048 struct clk_hw *cpu_clk_dyn;1049};1050 1051static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,1052 unsigned long event, void *data)1053{1054 struct g12a_sys_pll_nb_data *nb_data =1055 container_of(nb, struct g12a_sys_pll_nb_data, nb);1056 1057 switch (event) {1058 case PRE_RATE_CHANGE:1059 /*1060 * This notifier means sys_pll clock will be changed1061 * to feed cpu_clk, this the current path :1062 * cpu_clk1063 * \- sys_pll1064 * \- sys_pll_dco1065 */1066 1067 /* Configure cpu_clk to use cpu_clk_dyn */1068 clk_hw_set_parent(nb_data->cpu_clk,1069 nb_data->cpu_clk_dyn);1070 1071 /*1072 * Now, cpu_clk uses the dyn path1073 * cpu_clk1074 * \- cpu_clk_dyn1075 * \- cpu_clk_dynX1076 * \- cpu_clk_dynX_sel1077 * \- cpu_clk_dynX_div1078 * \- xtal/fclk_div2/fclk_div31079 * \- xtal/fclk_div2/fclk_div31080 */1081 1082 udelay(100);1083 1084 return NOTIFY_OK;1085 1086 case POST_RATE_CHANGE:1087 /*1088 * The sys_pll has ben updated, now switch back cpu_clk to1089 * sys_pll1090 */1091 1092 /* Configure cpu_clk to use sys_pll */1093 clk_hw_set_parent(nb_data->cpu_clk,1094 nb_data->sys_pll);1095 1096 udelay(100);1097 1098 /* new path :1099 * cpu_clk1100 * \- sys_pll1101 * \- sys_pll_dco1102 */1103 1104 return NOTIFY_OK;1105 1106 default:1107 return NOTIFY_DONE;1108 }1109}1110 1111static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {1112 .sys_pll = &g12a_sys_pll.hw,1113 .cpu_clk = &g12a_cpu_clk.hw,1114 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,1115 .nb.notifier_call = g12a_sys_pll_notifier_cb,1116};1117 1118/* G12B first CPU cluster uses sys1_pll */1119static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {1120 .sys_pll = &g12b_sys1_pll.hw,1121 .cpu_clk = &g12b_cpu_clk.hw,1122 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,1123 .nb.notifier_call = g12a_sys_pll_notifier_cb,1124};1125 1126/* G12B second CPU cluster uses sys_pll */1127static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {1128 .sys_pll = &g12a_sys_pll.hw,1129 .cpu_clk = &g12b_cpub_clk.hw,1130 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,1131 .nb.notifier_call = g12a_sys_pll_notifier_cb,1132};1133 1134static struct clk_regmap g12a_cpu_clk_div16_en = {1135 .data = &(struct clk_regmap_gate_data){1136 .offset = HHI_SYS_CPU_CLK_CNTL1,1137 .bit_idx = 1,1138 },1139 .hw.init = &(struct clk_init_data) {1140 .name = "cpu_clk_div16_en",1141 .ops = &clk_regmap_gate_ro_ops,1142 .parent_hws = (const struct clk_hw *[]) {1143 &g12a_cpu_clk.hw1144 },1145 .num_parents = 1,1146 /*1147 * This clock is used to debug the cpu_clk range1148 * Linux should not change it at runtime1149 */1150 },1151};1152 1153static struct clk_regmap g12b_cpub_clk_div16_en = {1154 .data = &(struct clk_regmap_gate_data){1155 .offset = HHI_SYS_CPUB_CLK_CNTL1,1156 .bit_idx = 1,1157 },1158 .hw.init = &(struct clk_init_data) {1159 .name = "cpub_clk_div16_en",1160 .ops = &clk_regmap_gate_ro_ops,1161 .parent_hws = (const struct clk_hw *[]) {1162 &g12b_cpub_clk.hw1163 },1164 .num_parents = 1,1165 /*1166 * This clock is used to debug the cpu_clk range1167 * Linux should not change it at runtime1168 */1169 },1170};1171 1172static struct clk_fixed_factor g12a_cpu_clk_div16 = {1173 .mult = 1,1174 .div = 16,1175 .hw.init = &(struct clk_init_data){1176 .name = "cpu_clk_div16",1177 .ops = &clk_fixed_factor_ops,1178 .parent_hws = (const struct clk_hw *[]) {1179 &g12a_cpu_clk_div16_en.hw1180 },1181 .num_parents = 1,1182 },1183};1184 1185static struct clk_fixed_factor g12b_cpub_clk_div16 = {1186 .mult = 1,1187 .div = 16,1188 .hw.init = &(struct clk_init_data){1189 .name = "cpub_clk_div16",1190 .ops = &clk_fixed_factor_ops,1191 .parent_hws = (const struct clk_hw *[]) {1192 &g12b_cpub_clk_div16_en.hw1193 },1194 .num_parents = 1,1195 },1196};1197 1198static struct clk_regmap g12a_cpu_clk_apb_div = {1199 .data = &(struct clk_regmap_div_data){1200 .offset = HHI_SYS_CPU_CLK_CNTL1,1201 .shift = 3,1202 .width = 3,1203 .flags = CLK_DIVIDER_POWER_OF_TWO,1204 },1205 .hw.init = &(struct clk_init_data){1206 .name = "cpu_clk_apb_div",1207 .ops = &clk_regmap_divider_ro_ops,1208 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },1209 .num_parents = 1,1210 },1211};1212 1213static struct clk_regmap g12a_cpu_clk_apb = {1214 .data = &(struct clk_regmap_gate_data){1215 .offset = HHI_SYS_CPU_CLK_CNTL1,1216 .bit_idx = 1,1217 },1218 .hw.init = &(struct clk_init_data) {1219 .name = "cpu_clk_apb",1220 .ops = &clk_regmap_gate_ro_ops,1221 .parent_hws = (const struct clk_hw *[]) {1222 &g12a_cpu_clk_apb_div.hw1223 },1224 .num_parents = 1,1225 /*1226 * This clock is set by the ROM monitor code,1227 * Linux should not change it at runtime1228 */1229 },1230};1231 1232static struct clk_regmap g12a_cpu_clk_atb_div = {1233 .data = &(struct clk_regmap_div_data){1234 .offset = HHI_SYS_CPU_CLK_CNTL1,1235 .shift = 6,1236 .width = 3,1237 .flags = CLK_DIVIDER_POWER_OF_TWO,1238 },1239 .hw.init = &(struct clk_init_data){1240 .name = "cpu_clk_atb_div",1241 .ops = &clk_regmap_divider_ro_ops,1242 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },1243 .num_parents = 1,1244 },1245};1246 1247static struct clk_regmap g12a_cpu_clk_atb = {1248 .data = &(struct clk_regmap_gate_data){1249 .offset = HHI_SYS_CPU_CLK_CNTL1,1250 .bit_idx = 17,1251 },1252 .hw.init = &(struct clk_init_data) {1253 .name = "cpu_clk_atb",1254 .ops = &clk_regmap_gate_ro_ops,1255 .parent_hws = (const struct clk_hw *[]) {1256 &g12a_cpu_clk_atb_div.hw1257 },1258 .num_parents = 1,1259 /*1260 * This clock is set by the ROM monitor code,1261 * Linux should not change it at runtime1262 */1263 },1264};1265 1266static struct clk_regmap g12a_cpu_clk_axi_div = {1267 .data = &(struct clk_regmap_div_data){1268 .offset = HHI_SYS_CPU_CLK_CNTL1,1269 .shift = 9,1270 .width = 3,1271 .flags = CLK_DIVIDER_POWER_OF_TWO,1272 },1273 .hw.init = &(struct clk_init_data){1274 .name = "cpu_clk_axi_div",1275 .ops = &clk_regmap_divider_ro_ops,1276 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },1277 .num_parents = 1,1278 },1279};1280 1281static struct clk_regmap g12a_cpu_clk_axi = {1282 .data = &(struct clk_regmap_gate_data){1283 .offset = HHI_SYS_CPU_CLK_CNTL1,1284 .bit_idx = 18,1285 },1286 .hw.init = &(struct clk_init_data) {1287 .name = "cpu_clk_axi",1288 .ops = &clk_regmap_gate_ro_ops,1289 .parent_hws = (const struct clk_hw *[]) {1290 &g12a_cpu_clk_axi_div.hw1291 },1292 .num_parents = 1,1293 /*1294 * This clock is set by the ROM monitor code,1295 * Linux should not change it at runtime1296 */1297 },1298};1299 1300static struct clk_regmap g12a_cpu_clk_trace_div = {1301 .data = &(struct clk_regmap_div_data){1302 .offset = HHI_SYS_CPU_CLK_CNTL1,1303 .shift = 20,1304 .width = 3,1305 .flags = CLK_DIVIDER_POWER_OF_TWO,1306 },1307 .hw.init = &(struct clk_init_data){1308 .name = "cpu_clk_trace_div",1309 .ops = &clk_regmap_divider_ro_ops,1310 .parent_data = &(const struct clk_parent_data) {1311 /*1312 * Note:1313 * G12A and G12B have different cpu_clks (with1314 * different struct clk_hw). We fallback to the global1315 * naming string mechanism so cpu_clk_trace_div picks1316 * up the appropriate one.1317 */1318 .name = "cpu_clk",1319 .index = -1,1320 },1321 .num_parents = 1,1322 },1323};1324 1325static struct clk_regmap g12a_cpu_clk_trace = {1326 .data = &(struct clk_regmap_gate_data){1327 .offset = HHI_SYS_CPU_CLK_CNTL1,1328 .bit_idx = 23,1329 },1330 .hw.init = &(struct clk_init_data) {1331 .name = "cpu_clk_trace",1332 .ops = &clk_regmap_gate_ro_ops,1333 .parent_hws = (const struct clk_hw *[]) {1334 &g12a_cpu_clk_trace_div.hw1335 },1336 .num_parents = 1,1337 /*1338 * This clock is set by the ROM monitor code,1339 * Linux should not change it at runtime1340 */1341 },1342};1343 1344static struct clk_fixed_factor g12b_cpub_clk_div2 = {1345 .mult = 1,1346 .div = 2,1347 .hw.init = &(struct clk_init_data){1348 .name = "cpub_clk_div2",1349 .ops = &clk_fixed_factor_ops,1350 .parent_hws = (const struct clk_hw *[]) {1351 &g12b_cpub_clk.hw1352 },1353 .num_parents = 1,1354 },1355};1356 1357static struct clk_fixed_factor g12b_cpub_clk_div3 = {1358 .mult = 1,1359 .div = 3,1360 .hw.init = &(struct clk_init_data){1361 .name = "cpub_clk_div3",1362 .ops = &clk_fixed_factor_ops,1363 .parent_hws = (const struct clk_hw *[]) {1364 &g12b_cpub_clk.hw1365 },1366 .num_parents = 1,1367 },1368};1369 1370static struct clk_fixed_factor g12b_cpub_clk_div4 = {1371 .mult = 1,1372 .div = 4,1373 .hw.init = &(struct clk_init_data){1374 .name = "cpub_clk_div4",1375 .ops = &clk_fixed_factor_ops,1376 .parent_hws = (const struct clk_hw *[]) {1377 &g12b_cpub_clk.hw1378 },1379 .num_parents = 1,1380 },1381};1382 1383static struct clk_fixed_factor g12b_cpub_clk_div5 = {1384 .mult = 1,1385 .div = 5,1386 .hw.init = &(struct clk_init_data){1387 .name = "cpub_clk_div5",1388 .ops = &clk_fixed_factor_ops,1389 .parent_hws = (const struct clk_hw *[]) {1390 &g12b_cpub_clk.hw1391 },1392 .num_parents = 1,1393 },1394};1395 1396static struct clk_fixed_factor g12b_cpub_clk_div6 = {1397 .mult = 1,1398 .div = 6,1399 .hw.init = &(struct clk_init_data){1400 .name = "cpub_clk_div6",1401 .ops = &clk_fixed_factor_ops,1402 .parent_hws = (const struct clk_hw *[]) {1403 &g12b_cpub_clk.hw1404 },1405 .num_parents = 1,1406 },1407};1408 1409static struct clk_fixed_factor g12b_cpub_clk_div7 = {1410 .mult = 1,1411 .div = 7,1412 .hw.init = &(struct clk_init_data){1413 .name = "cpub_clk_div7",1414 .ops = &clk_fixed_factor_ops,1415 .parent_hws = (const struct clk_hw *[]) {1416 &g12b_cpub_clk.hw1417 },1418 .num_parents = 1,1419 },1420};1421 1422static struct clk_fixed_factor g12b_cpub_clk_div8 = {1423 .mult = 1,1424 .div = 8,1425 .hw.init = &(struct clk_init_data){1426 .name = "cpub_clk_div8",1427 .ops = &clk_fixed_factor_ops,1428 .parent_hws = (const struct clk_hw *[]) {1429 &g12b_cpub_clk.hw1430 },1431 .num_parents = 1,1432 },1433};1434 1435static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };1436static struct clk_regmap g12b_cpub_clk_apb_sel = {1437 .data = &(struct clk_regmap_mux_data){1438 .offset = HHI_SYS_CPUB_CLK_CNTL1,1439 .mask = 7,1440 .shift = 3,1441 .table = mux_table_cpub,1442 },1443 .hw.init = &(struct clk_init_data){1444 .name = "cpub_clk_apb_sel",1445 .ops = &clk_regmap_mux_ro_ops,1446 .parent_hws = (const struct clk_hw *[]) {1447 &g12b_cpub_clk_div2.hw,1448 &g12b_cpub_clk_div3.hw,1449 &g12b_cpub_clk_div4.hw,1450 &g12b_cpub_clk_div5.hw,1451 &g12b_cpub_clk_div6.hw,1452 &g12b_cpub_clk_div7.hw,1453 &g12b_cpub_clk_div8.hw1454 },1455 .num_parents = 7,1456 },1457};1458 1459static struct clk_regmap g12b_cpub_clk_apb = {1460 .data = &(struct clk_regmap_gate_data){1461 .offset = HHI_SYS_CPUB_CLK_CNTL1,1462 .bit_idx = 16,1463 .flags = CLK_GATE_SET_TO_DISABLE,1464 },1465 .hw.init = &(struct clk_init_data) {1466 .name = "cpub_clk_apb",1467 .ops = &clk_regmap_gate_ro_ops,1468 .parent_hws = (const struct clk_hw *[]) {1469 &g12b_cpub_clk_apb_sel.hw1470 },1471 .num_parents = 1,1472 /*1473 * This clock is set by the ROM monitor code,1474 * Linux should not change it at runtime1475 */1476 },1477};1478 1479static struct clk_regmap g12b_cpub_clk_atb_sel = {1480 .data = &(struct clk_regmap_mux_data){1481 .offset = HHI_SYS_CPUB_CLK_CNTL1,1482 .mask = 7,1483 .shift = 6,1484 .table = mux_table_cpub,1485 },1486 .hw.init = &(struct clk_init_data){1487 .name = "cpub_clk_atb_sel",1488 .ops = &clk_regmap_mux_ro_ops,1489 .parent_hws = (const struct clk_hw *[]) {1490 &g12b_cpub_clk_div2.hw,1491 &g12b_cpub_clk_div3.hw,1492 &g12b_cpub_clk_div4.hw,1493 &g12b_cpub_clk_div5.hw,1494 &g12b_cpub_clk_div6.hw,1495 &g12b_cpub_clk_div7.hw,1496 &g12b_cpub_clk_div8.hw1497 },1498 .num_parents = 7,1499 },1500};1501 1502static struct clk_regmap g12b_cpub_clk_atb = {1503 .data = &(struct clk_regmap_gate_data){1504 .offset = HHI_SYS_CPUB_CLK_CNTL1,1505 .bit_idx = 17,1506 .flags = CLK_GATE_SET_TO_DISABLE,1507 },1508 .hw.init = &(struct clk_init_data) {1509 .name = "cpub_clk_atb",1510 .ops = &clk_regmap_gate_ro_ops,1511 .parent_hws = (const struct clk_hw *[]) {1512 &g12b_cpub_clk_atb_sel.hw1513 },1514 .num_parents = 1,1515 /*1516 * This clock is set by the ROM monitor code,1517 * Linux should not change it at runtime1518 */1519 },1520};1521 1522static struct clk_regmap g12b_cpub_clk_axi_sel = {1523 .data = &(struct clk_regmap_mux_data){1524 .offset = HHI_SYS_CPUB_CLK_CNTL1,1525 .mask = 7,1526 .shift = 9,1527 .table = mux_table_cpub,1528 },1529 .hw.init = &(struct clk_init_data){1530 .name = "cpub_clk_axi_sel",1531 .ops = &clk_regmap_mux_ro_ops,1532 .parent_hws = (const struct clk_hw *[]) {1533 &g12b_cpub_clk_div2.hw,1534 &g12b_cpub_clk_div3.hw,1535 &g12b_cpub_clk_div4.hw,1536 &g12b_cpub_clk_div5.hw,1537 &g12b_cpub_clk_div6.hw,1538 &g12b_cpub_clk_div7.hw,1539 &g12b_cpub_clk_div8.hw1540 },1541 .num_parents = 7,1542 },1543};1544 1545static struct clk_regmap g12b_cpub_clk_axi = {1546 .data = &(struct clk_regmap_gate_data){1547 .offset = HHI_SYS_CPUB_CLK_CNTL1,1548 .bit_idx = 18,1549 .flags = CLK_GATE_SET_TO_DISABLE,1550 },1551 .hw.init = &(struct clk_init_data) {1552 .name = "cpub_clk_axi",1553 .ops = &clk_regmap_gate_ro_ops,1554 .parent_hws = (const struct clk_hw *[]) {1555 &g12b_cpub_clk_axi_sel.hw1556 },1557 .num_parents = 1,1558 /*1559 * This clock is set by the ROM monitor code,1560 * Linux should not change it at runtime1561 */1562 },1563};1564 1565static struct clk_regmap g12b_cpub_clk_trace_sel = {1566 .data = &(struct clk_regmap_mux_data){1567 .offset = HHI_SYS_CPUB_CLK_CNTL1,1568 .mask = 7,1569 .shift = 20,1570 .table = mux_table_cpub,1571 },1572 .hw.init = &(struct clk_init_data){1573 .name = "cpub_clk_trace_sel",1574 .ops = &clk_regmap_mux_ro_ops,1575 .parent_hws = (const struct clk_hw *[]) {1576 &g12b_cpub_clk_div2.hw,1577 &g12b_cpub_clk_div3.hw,1578 &g12b_cpub_clk_div4.hw,1579 &g12b_cpub_clk_div5.hw,1580 &g12b_cpub_clk_div6.hw,1581 &g12b_cpub_clk_div7.hw,1582 &g12b_cpub_clk_div8.hw1583 },1584 .num_parents = 7,1585 },1586};1587 1588static struct clk_regmap g12b_cpub_clk_trace = {1589 .data = &(struct clk_regmap_gate_data){1590 .offset = HHI_SYS_CPUB_CLK_CNTL1,1591 .bit_idx = 23,1592 .flags = CLK_GATE_SET_TO_DISABLE,1593 },1594 .hw.init = &(struct clk_init_data) {1595 .name = "cpub_clk_trace",1596 .ops = &clk_regmap_gate_ro_ops,1597 .parent_hws = (const struct clk_hw *[]) {1598 &g12b_cpub_clk_trace_sel.hw1599 },1600 .num_parents = 1,1601 /*1602 * This clock is set by the ROM monitor code,1603 * Linux should not change it at runtime1604 */1605 },1606};1607 1608static const struct pll_mult_range g12a_gp0_pll_mult_range = {1609 .min = 125,1610 .max = 255,1611};1612 1613/*1614 * Internal gp0 pll emulation configuration parameters1615 */1616static const struct reg_sequence g12a_gp0_init_regs[] = {1617 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },1618 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },1619 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },1620 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },1621 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },1622 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },1623};1624 1625static struct clk_regmap g12a_gp0_pll_dco = {1626 .data = &(struct meson_clk_pll_data){1627 .en = {1628 .reg_off = HHI_GP0_PLL_CNTL0,1629 .shift = 28,1630 .width = 1,1631 },1632 .m = {1633 .reg_off = HHI_GP0_PLL_CNTL0,1634 .shift = 0,1635 .width = 8,1636 },1637 .n = {1638 .reg_off = HHI_GP0_PLL_CNTL0,1639 .shift = 10,1640 .width = 5,1641 },1642 .frac = {1643 .reg_off = HHI_GP0_PLL_CNTL1,1644 .shift = 0,1645 .width = 17,1646 },1647 .l = {1648 .reg_off = HHI_GP0_PLL_CNTL0,1649 .shift = 31,1650 .width = 1,1651 },1652 .rst = {1653 .reg_off = HHI_GP0_PLL_CNTL0,1654 .shift = 29,1655 .width = 1,1656 },1657 .range = &g12a_gp0_pll_mult_range,1658 .init_regs = g12a_gp0_init_regs,1659 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),1660 },1661 .hw.init = &(struct clk_init_data){1662 .name = "gp0_pll_dco",1663 .ops = &meson_clk_pll_ops,1664 .parent_data = &(const struct clk_parent_data) {1665 .fw_name = "xtal",1666 },1667 .num_parents = 1,1668 },1669};1670 1671static struct clk_regmap g12a_gp0_pll = {1672 .data = &(struct clk_regmap_div_data){1673 .offset = HHI_GP0_PLL_CNTL0,1674 .shift = 16,1675 .width = 3,1676 .flags = (CLK_DIVIDER_POWER_OF_TWO |1677 CLK_DIVIDER_ROUND_CLOSEST),1678 },1679 .hw.init = &(struct clk_init_data){1680 .name = "gp0_pll",1681 .ops = &clk_regmap_divider_ops,1682 .parent_hws = (const struct clk_hw *[]) {1683 &g12a_gp0_pll_dco.hw1684 },1685 .num_parents = 1,1686 .flags = CLK_SET_RATE_PARENT,1687 },1688};1689 1690static struct clk_regmap sm1_gp1_pll_dco = {1691 .data = &(struct meson_clk_pll_data){1692 .en = {1693 .reg_off = HHI_GP1_PLL_CNTL0,1694 .shift = 28,1695 .width = 1,1696 },1697 .m = {1698 .reg_off = HHI_GP1_PLL_CNTL0,1699 .shift = 0,1700 .width = 8,1701 },1702 .n = {1703 .reg_off = HHI_GP1_PLL_CNTL0,1704 .shift = 10,1705 .width = 5,1706 },1707 .frac = {1708 .reg_off = HHI_GP1_PLL_CNTL1,1709 .shift = 0,1710 .width = 17,1711 },1712 .l = {1713 .reg_off = HHI_GP1_PLL_CNTL0,1714 .shift = 31,1715 .width = 1,1716 },1717 .rst = {1718 .reg_off = HHI_GP1_PLL_CNTL0,1719 .shift = 29,1720 .width = 1,1721 },1722 },1723 .hw.init = &(struct clk_init_data){1724 .name = "gp1_pll_dco",1725 .ops = &meson_clk_pll_ro_ops,1726 .parent_data = &(const struct clk_parent_data) {1727 .fw_name = "xtal",1728 },1729 .num_parents = 1,1730 /* This clock feeds the DSU, avoid disabling it */1731 .flags = CLK_IS_CRITICAL,1732 },1733};1734 1735static struct clk_regmap sm1_gp1_pll = {1736 .data = &(struct clk_regmap_div_data){1737 .offset = HHI_GP1_PLL_CNTL0,1738 .shift = 16,1739 .width = 3,1740 .flags = (CLK_DIVIDER_POWER_OF_TWO |1741 CLK_DIVIDER_ROUND_CLOSEST),1742 },1743 .hw.init = &(struct clk_init_data){1744 .name = "gp1_pll",1745 .ops = &clk_regmap_divider_ro_ops,1746 .parent_hws = (const struct clk_hw *[]) {1747 &sm1_gp1_pll_dco.hw1748 },1749 .num_parents = 1,1750 },1751};1752 1753/*1754 * Internal hifi pll emulation configuration parameters1755 */1756static const struct reg_sequence g12a_hifi_init_regs[] = {1757 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },1758 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },1759 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },1760 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },1761 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },1762 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },1763};1764 1765static struct clk_regmap g12a_hifi_pll_dco = {1766 .data = &(struct meson_clk_pll_data){1767 .en = {1768 .reg_off = HHI_HIFI_PLL_CNTL0,1769 .shift = 28,1770 .width = 1,1771 },1772 .m = {1773 .reg_off = HHI_HIFI_PLL_CNTL0,1774 .shift = 0,1775 .width = 8,1776 },1777 .n = {1778 .reg_off = HHI_HIFI_PLL_CNTL0,1779 .shift = 10,1780 .width = 5,1781 },1782 .frac = {1783 .reg_off = HHI_HIFI_PLL_CNTL1,1784 .shift = 0,1785 .width = 17,1786 },1787 .l = {1788 .reg_off = HHI_HIFI_PLL_CNTL0,1789 .shift = 31,1790 .width = 1,1791 },1792 .rst = {1793 .reg_off = HHI_HIFI_PLL_CNTL0,1794 .shift = 29,1795 .width = 1,1796 },1797 .range = &g12a_gp0_pll_mult_range,1798 .init_regs = g12a_hifi_init_regs,1799 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),1800 .flags = CLK_MESON_PLL_ROUND_CLOSEST,1801 },1802 .hw.init = &(struct clk_init_data){1803 .name = "hifi_pll_dco",1804 .ops = &meson_clk_pll_ops,1805 .parent_data = &(const struct clk_parent_data) {1806 .fw_name = "xtal",1807 },1808 .num_parents = 1,1809 },1810};1811 1812static struct clk_regmap g12a_hifi_pll = {1813 .data = &(struct clk_regmap_div_data){1814 .offset = HHI_HIFI_PLL_CNTL0,1815 .shift = 16,1816 .width = 2,1817 .flags = (CLK_DIVIDER_POWER_OF_TWO |1818 CLK_DIVIDER_ROUND_CLOSEST),1819 },1820 .hw.init = &(struct clk_init_data){1821 .name = "hifi_pll",1822 .ops = &clk_regmap_divider_ops,1823 .parent_hws = (const struct clk_hw *[]) {1824 &g12a_hifi_pll_dco.hw1825 },1826 .num_parents = 1,1827 .flags = CLK_SET_RATE_PARENT,1828 },1829};1830 1831/*1832 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise1833 * 100MHz reference clock for the PCIe Analog PHY, and thus requires1834 * a strict register sequence to enable the PLL.1835 */1836static const struct reg_sequence g12a_pcie_pll_init_regs[] = {1837 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },1838 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },1839 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },1840 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },1841 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },1842 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },1843 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },1844 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },1845 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },1846 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },1847 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },1848 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },1849};1850 1851/* Keep a single entry table for recalc/round_rate() ops */1852static const struct pll_params_table g12a_pcie_pll_table[] = {1853 PLL_PARAMS(150, 1),1854 {0, 0},1855};1856 1857static struct clk_regmap g12a_pcie_pll_dco = {1858 .data = &(struct meson_clk_pll_data){1859 .en = {1860 .reg_off = HHI_PCIE_PLL_CNTL0,1861 .shift = 28,1862 .width = 1,1863 },1864 .m = {1865 .reg_off = HHI_PCIE_PLL_CNTL0,1866 .shift = 0,1867 .width = 8,1868 },1869 .n = {1870 .reg_off = HHI_PCIE_PLL_CNTL0,1871 .shift = 10,1872 .width = 5,1873 },1874 .frac = {1875 .reg_off = HHI_PCIE_PLL_CNTL1,1876 .shift = 0,1877 .width = 12,1878 },1879 .l = {1880 .reg_off = HHI_PCIE_PLL_CNTL0,1881 .shift = 31,1882 .width = 1,1883 },1884 .rst = {1885 .reg_off = HHI_PCIE_PLL_CNTL0,1886 .shift = 29,1887 .width = 1,1888 },1889 .table = g12a_pcie_pll_table,1890 .init_regs = g12a_pcie_pll_init_regs,1891 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),1892 },1893 .hw.init = &(struct clk_init_data){1894 .name = "pcie_pll_dco",1895 .ops = &meson_clk_pcie_pll_ops,1896 .parent_data = &(const struct clk_parent_data) {1897 .fw_name = "xtal",1898 },1899 .num_parents = 1,1900 },1901};1902 1903static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {1904 .mult = 1,1905 .div = 2,1906 .hw.init = &(struct clk_init_data){1907 .name = "pcie_pll_dco_div2",1908 .ops = &clk_fixed_factor_ops,1909 .parent_hws = (const struct clk_hw *[]) {1910 &g12a_pcie_pll_dco.hw1911 },1912 .num_parents = 1,1913 .flags = CLK_SET_RATE_PARENT,1914 },1915};1916 1917static struct clk_regmap g12a_pcie_pll_od = {1918 .data = &(struct clk_regmap_div_data){1919 .offset = HHI_PCIE_PLL_CNTL0,1920 .shift = 16,1921 .width = 5,1922 .flags = CLK_DIVIDER_ROUND_CLOSEST |1923 CLK_DIVIDER_ONE_BASED |1924 CLK_DIVIDER_ALLOW_ZERO,1925 },1926 .hw.init = &(struct clk_init_data){1927 .name = "pcie_pll_od",1928 .ops = &clk_regmap_divider_ops,1929 .parent_hws = (const struct clk_hw *[]) {1930 &g12a_pcie_pll_dco_div2.hw1931 },1932 .num_parents = 1,1933 .flags = CLK_SET_RATE_PARENT,1934 },1935};1936 1937static struct clk_fixed_factor g12a_pcie_pll = {1938 .mult = 1,1939 .div = 2,1940 .hw.init = &(struct clk_init_data){1941 .name = "pcie_pll_pll",1942 .ops = &clk_fixed_factor_ops,1943 .parent_hws = (const struct clk_hw *[]) {1944 &g12a_pcie_pll_od.hw1945 },1946 .num_parents = 1,1947 .flags = CLK_SET_RATE_PARENT,1948 },1949};1950 1951static struct clk_regmap g12a_hdmi_pll_dco = {1952 .data = &(struct meson_clk_pll_data){1953 .en = {1954 .reg_off = HHI_HDMI_PLL_CNTL0,1955 .shift = 28,1956 .width = 1,1957 },1958 .m = {1959 .reg_off = HHI_HDMI_PLL_CNTL0,1960 .shift = 0,1961 .width = 8,1962 },1963 .n = {1964 .reg_off = HHI_HDMI_PLL_CNTL0,1965 .shift = 10,1966 .width = 5,1967 },1968 .frac = {1969 .reg_off = HHI_HDMI_PLL_CNTL1,1970 .shift = 0,1971 .width = 16,1972 },1973 .l = {1974 .reg_off = HHI_HDMI_PLL_CNTL0,1975 .shift = 30,1976 .width = 1,1977 },1978 .rst = {1979 .reg_off = HHI_HDMI_PLL_CNTL0,1980 .shift = 29,1981 .width = 1,1982 },1983 },1984 .hw.init = &(struct clk_init_data){1985 .name = "hdmi_pll_dco",1986 .ops = &meson_clk_pll_ro_ops,1987 .parent_data = &(const struct clk_parent_data) {1988 .fw_name = "xtal",1989 },1990 .num_parents = 1,1991 /*1992 * Display directly handle hdmi pll registers ATM, we need1993 * NOCACHE to keep our view of the clock as accurate as possible1994 */1995 .flags = CLK_GET_RATE_NOCACHE,1996 },1997};1998 1999static struct clk_regmap g12a_hdmi_pll_od = {2000 .data = &(struct clk_regmap_div_data){2001 .offset = HHI_HDMI_PLL_CNTL0,2002 .shift = 16,2003 .width = 2,2004 .flags = CLK_DIVIDER_POWER_OF_TWO,2005 },2006 .hw.init = &(struct clk_init_data){2007 .name = "hdmi_pll_od",2008 .ops = &clk_regmap_divider_ro_ops,2009 .parent_hws = (const struct clk_hw *[]) {2010 &g12a_hdmi_pll_dco.hw2011 },2012 .num_parents = 1,2013 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,2014 },2015};2016 2017static struct clk_regmap g12a_hdmi_pll_od2 = {2018 .data = &(struct clk_regmap_div_data){2019 .offset = HHI_HDMI_PLL_CNTL0,2020 .shift = 18,2021 .width = 2,2022 .flags = CLK_DIVIDER_POWER_OF_TWO,2023 },2024 .hw.init = &(struct clk_init_data){2025 .name = "hdmi_pll_od2",2026 .ops = &clk_regmap_divider_ro_ops,2027 .parent_hws = (const struct clk_hw *[]) {2028 &g12a_hdmi_pll_od.hw2029 },2030 .num_parents = 1,2031 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,2032 },2033};2034 2035static struct clk_regmap g12a_hdmi_pll = {2036 .data = &(struct clk_regmap_div_data){2037 .offset = HHI_HDMI_PLL_CNTL0,2038 .shift = 20,2039 .width = 2,2040 .flags = CLK_DIVIDER_POWER_OF_TWO,2041 },2042 .hw.init = &(struct clk_init_data){2043 .name = "hdmi_pll",2044 .ops = &clk_regmap_divider_ro_ops,2045 .parent_hws = (const struct clk_hw *[]) {2046 &g12a_hdmi_pll_od2.hw2047 },2048 .num_parents = 1,2049 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,2050 },2051};2052 2053static struct clk_fixed_factor g12a_fclk_div4_div = {2054 .mult = 1,2055 .div = 4,2056 .hw.init = &(struct clk_init_data){2057 .name = "fclk_div4_div",2058 .ops = &clk_fixed_factor_ops,2059 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },2060 .num_parents = 1,2061 },2062};2063 2064static struct clk_regmap g12a_fclk_div4 = {2065 .data = &(struct clk_regmap_gate_data){2066 .offset = HHI_FIX_PLL_CNTL1,2067 .bit_idx = 21,2068 },2069 .hw.init = &(struct clk_init_data){2070 .name = "fclk_div4",2071 .ops = &clk_regmap_gate_ops,2072 .parent_hws = (const struct clk_hw *[]) {2073 &g12a_fclk_div4_div.hw2074 },2075 .num_parents = 1,2076 },2077};2078 2079static struct clk_fixed_factor g12a_fclk_div5_div = {2080 .mult = 1,2081 .div = 5,2082 .hw.init = &(struct clk_init_data){2083 .name = "fclk_div5_div",2084 .ops = &clk_fixed_factor_ops,2085 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },2086 .num_parents = 1,2087 },2088};2089 2090static struct clk_regmap g12a_fclk_div5 = {2091 .data = &(struct clk_regmap_gate_data){2092 .offset = HHI_FIX_PLL_CNTL1,2093 .bit_idx = 22,2094 },2095 .hw.init = &(struct clk_init_data){2096 .name = "fclk_div5",2097 .ops = &clk_regmap_gate_ops,2098 .parent_hws = (const struct clk_hw *[]) {2099 &g12a_fclk_div5_div.hw2100 },2101 .num_parents = 1,2102 },2103};2104 2105static struct clk_fixed_factor g12a_fclk_div7_div = {2106 .mult = 1,2107 .div = 7,2108 .hw.init = &(struct clk_init_data){2109 .name = "fclk_div7_div",2110 .ops = &clk_fixed_factor_ops,2111 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },2112 .num_parents = 1,2113 },2114};2115 2116static struct clk_regmap g12a_fclk_div7 = {2117 .data = &(struct clk_regmap_gate_data){2118 .offset = HHI_FIX_PLL_CNTL1,2119 .bit_idx = 23,2120 },2121 .hw.init = &(struct clk_init_data){2122 .name = "fclk_div7",2123 .ops = &clk_regmap_gate_ops,2124 .parent_hws = (const struct clk_hw *[]) {2125 &g12a_fclk_div7_div.hw2126 },2127 .num_parents = 1,2128 },2129};2130 2131static struct clk_fixed_factor g12a_fclk_div2p5_div = {2132 .mult = 1,2133 .div = 5,2134 .hw.init = &(struct clk_init_data){2135 .name = "fclk_div2p5_div",2136 .ops = &clk_fixed_factor_ops,2137 .parent_hws = (const struct clk_hw *[]) {2138 &g12a_fixed_pll_dco.hw2139 },2140 .num_parents = 1,2141 },2142};2143 2144static struct clk_regmap g12a_fclk_div2p5 = {2145 .data = &(struct clk_regmap_gate_data){2146 .offset = HHI_FIX_PLL_CNTL1,2147 .bit_idx = 25,2148 },2149 .hw.init = &(struct clk_init_data){2150 .name = "fclk_div2p5",2151 .ops = &clk_regmap_gate_ops,2152 .parent_hws = (const struct clk_hw *[]) {2153 &g12a_fclk_div2p5_div.hw2154 },2155 .num_parents = 1,2156 },2157};2158 2159static struct clk_fixed_factor g12a_mpll_50m_div = {2160 .mult = 1,2161 .div = 80,2162 .hw.init = &(struct clk_init_data){2163 .name = "mpll_50m_div",2164 .ops = &clk_fixed_factor_ops,2165 .parent_hws = (const struct clk_hw *[]) {2166 &g12a_fixed_pll_dco.hw2167 },2168 .num_parents = 1,2169 },2170};2171 2172static struct clk_regmap g12a_mpll_50m = {2173 .data = &(struct clk_regmap_mux_data){2174 .offset = HHI_FIX_PLL_CNTL3,2175 .mask = 0x1,2176 .shift = 5,2177 },2178 .hw.init = &(struct clk_init_data){2179 .name = "mpll_50m",2180 .ops = &clk_regmap_mux_ro_ops,2181 .parent_data = (const struct clk_parent_data []) {2182 { .fw_name = "xtal", },2183 { .hw = &g12a_mpll_50m_div.hw },2184 },2185 .num_parents = 2,2186 },2187};2188 2189static struct clk_fixed_factor g12a_mpll_prediv = {2190 .mult = 1,2191 .div = 2,2192 .hw.init = &(struct clk_init_data){2193 .name = "mpll_prediv",2194 .ops = &clk_fixed_factor_ops,2195 .parent_hws = (const struct clk_hw *[]) {2196 &g12a_fixed_pll_dco.hw2197 },2198 .num_parents = 1,2199 },2200};2201 2202static const struct reg_sequence g12a_mpll0_init_regs[] = {2203 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },2204};2205 2206static struct clk_regmap g12a_mpll0_div = {2207 .data = &(struct meson_clk_mpll_data){2208 .sdm = {2209 .reg_off = HHI_MPLL_CNTL1,2210 .shift = 0,2211 .width = 14,2212 },2213 .sdm_en = {2214 .reg_off = HHI_MPLL_CNTL1,2215 .shift = 30,2216 .width = 1,2217 },2218 .n2 = {2219 .reg_off = HHI_MPLL_CNTL1,2220 .shift = 20,2221 .width = 9,2222 },2223 .ssen = {2224 .reg_off = HHI_MPLL_CNTL1,2225 .shift = 29,2226 .width = 1,2227 },2228 .lock = &meson_clk_lock,2229 .init_regs = g12a_mpll0_init_regs,2230 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),2231 },2232 .hw.init = &(struct clk_init_data){2233 .name = "mpll0_div",2234 .ops = &meson_clk_mpll_ops,2235 .parent_hws = (const struct clk_hw *[]) {2236 &g12a_mpll_prediv.hw2237 },2238 .num_parents = 1,2239 },2240};2241 2242static struct clk_regmap g12a_mpll0 = {2243 .data = &(struct clk_regmap_gate_data){2244 .offset = HHI_MPLL_CNTL1,2245 .bit_idx = 31,2246 },2247 .hw.init = &(struct clk_init_data){2248 .name = "mpll0",2249 .ops = &clk_regmap_gate_ops,2250 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },2251 .num_parents = 1,2252 .flags = CLK_SET_RATE_PARENT,2253 },2254};2255 2256static const struct reg_sequence g12a_mpll1_init_regs[] = {2257 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },2258};2259 2260static struct clk_regmap g12a_mpll1_div = {2261 .data = &(struct meson_clk_mpll_data){2262 .sdm = {2263 .reg_off = HHI_MPLL_CNTL3,2264 .shift = 0,2265 .width = 14,2266 },2267 .sdm_en = {2268 .reg_off = HHI_MPLL_CNTL3,2269 .shift = 30,2270 .width = 1,2271 },2272 .n2 = {2273 .reg_off = HHI_MPLL_CNTL3,2274 .shift = 20,2275 .width = 9,2276 },2277 .ssen = {2278 .reg_off = HHI_MPLL_CNTL3,2279 .shift = 29,2280 .width = 1,2281 },2282 .lock = &meson_clk_lock,2283 .init_regs = g12a_mpll1_init_regs,2284 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),2285 },2286 .hw.init = &(struct clk_init_data){2287 .name = "mpll1_div",2288 .ops = &meson_clk_mpll_ops,2289 .parent_hws = (const struct clk_hw *[]) {2290 &g12a_mpll_prediv.hw2291 },2292 .num_parents = 1,2293 },2294};2295 2296static struct clk_regmap g12a_mpll1 = {2297 .data = &(struct clk_regmap_gate_data){2298 .offset = HHI_MPLL_CNTL3,2299 .bit_idx = 31,2300 },2301 .hw.init = &(struct clk_init_data){2302 .name = "mpll1",2303 .ops = &clk_regmap_gate_ops,2304 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },2305 .num_parents = 1,2306 .flags = CLK_SET_RATE_PARENT,2307 },2308};2309 2310static const struct reg_sequence g12a_mpll2_init_regs[] = {2311 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },2312};2313 2314static struct clk_regmap g12a_mpll2_div = {2315 .data = &(struct meson_clk_mpll_data){2316 .sdm = {2317 .reg_off = HHI_MPLL_CNTL5,2318 .shift = 0,2319 .width = 14,2320 },2321 .sdm_en = {2322 .reg_off = HHI_MPLL_CNTL5,2323 .shift = 30,2324 .width = 1,2325 },2326 .n2 = {2327 .reg_off = HHI_MPLL_CNTL5,2328 .shift = 20,2329 .width = 9,2330 },2331 .ssen = {2332 .reg_off = HHI_MPLL_CNTL5,2333 .shift = 29,2334 .width = 1,2335 },2336 .lock = &meson_clk_lock,2337 .init_regs = g12a_mpll2_init_regs,2338 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),2339 },2340 .hw.init = &(struct clk_init_data){2341 .name = "mpll2_div",2342 .ops = &meson_clk_mpll_ops,2343 .parent_hws = (const struct clk_hw *[]) {2344 &g12a_mpll_prediv.hw2345 },2346 .num_parents = 1,2347 },2348};2349 2350static struct clk_regmap g12a_mpll2 = {2351 .data = &(struct clk_regmap_gate_data){2352 .offset = HHI_MPLL_CNTL5,2353 .bit_idx = 31,2354 },2355 .hw.init = &(struct clk_init_data){2356 .name = "mpll2",2357 .ops = &clk_regmap_gate_ops,2358 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },2359 .num_parents = 1,2360 .flags = CLK_SET_RATE_PARENT,2361 },2362};2363 2364static const struct reg_sequence g12a_mpll3_init_regs[] = {2365 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },2366};2367 2368static struct clk_regmap g12a_mpll3_div = {2369 .data = &(struct meson_clk_mpll_data){2370 .sdm = {2371 .reg_off = HHI_MPLL_CNTL7,2372 .shift = 0,2373 .width = 14,2374 },2375 .sdm_en = {2376 .reg_off = HHI_MPLL_CNTL7,2377 .shift = 30,2378 .width = 1,2379 },2380 .n2 = {2381 .reg_off = HHI_MPLL_CNTL7,2382 .shift = 20,2383 .width = 9,2384 },2385 .ssen = {2386 .reg_off = HHI_MPLL_CNTL7,2387 .shift = 29,2388 .width = 1,2389 },2390 .lock = &meson_clk_lock,2391 .init_regs = g12a_mpll3_init_regs,2392 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),2393 },2394 .hw.init = &(struct clk_init_data){2395 .name = "mpll3_div",2396 .ops = &meson_clk_mpll_ops,2397 .parent_hws = (const struct clk_hw *[]) {2398 &g12a_mpll_prediv.hw2399 },2400 .num_parents = 1,2401 },2402};2403 2404static struct clk_regmap g12a_mpll3 = {2405 .data = &(struct clk_regmap_gate_data){2406 .offset = HHI_MPLL_CNTL7,2407 .bit_idx = 31,2408 },2409 .hw.init = &(struct clk_init_data){2410 .name = "mpll3",2411 .ops = &clk_regmap_gate_ops,2412 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },2413 .num_parents = 1,2414 .flags = CLK_SET_RATE_PARENT,2415 },2416};2417 2418static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };2419static const struct clk_parent_data clk81_parent_data[] = {2420 { .fw_name = "xtal", },2421 { .hw = &g12a_fclk_div7.hw },2422 { .hw = &g12a_mpll1.hw },2423 { .hw = &g12a_mpll2.hw },2424 { .hw = &g12a_fclk_div4.hw },2425 { .hw = &g12a_fclk_div3.hw },2426 { .hw = &g12a_fclk_div5.hw },2427};2428 2429static struct clk_regmap g12a_mpeg_clk_sel = {2430 .data = &(struct clk_regmap_mux_data){2431 .offset = HHI_MPEG_CLK_CNTL,2432 .mask = 0x7,2433 .shift = 12,2434 .table = mux_table_clk81,2435 },2436 .hw.init = &(struct clk_init_data){2437 .name = "mpeg_clk_sel",2438 .ops = &clk_regmap_mux_ro_ops,2439 .parent_data = clk81_parent_data,2440 .num_parents = ARRAY_SIZE(clk81_parent_data),2441 },2442};2443 2444static struct clk_regmap g12a_mpeg_clk_div = {2445 .data = &(struct clk_regmap_div_data){2446 .offset = HHI_MPEG_CLK_CNTL,2447 .shift = 0,2448 .width = 7,2449 },2450 .hw.init = &(struct clk_init_data){2451 .name = "mpeg_clk_div",2452 .ops = &clk_regmap_divider_ops,2453 .parent_hws = (const struct clk_hw *[]) {2454 &g12a_mpeg_clk_sel.hw2455 },2456 .num_parents = 1,2457 .flags = CLK_SET_RATE_PARENT,2458 },2459};2460 2461static struct clk_regmap g12a_clk81 = {2462 .data = &(struct clk_regmap_gate_data){2463 .offset = HHI_MPEG_CLK_CNTL,2464 .bit_idx = 7,2465 },2466 .hw.init = &(struct clk_init_data){2467 .name = "clk81",2468 .ops = &clk_regmap_gate_ops,2469 .parent_hws = (const struct clk_hw *[]) {2470 &g12a_mpeg_clk_div.hw2471 },2472 .num_parents = 1,2473 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),2474 },2475};2476 2477static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {2478 { .fw_name = "xtal", },2479 { .hw = &g12a_fclk_div2.hw },2480 { .hw = &g12a_fclk_div3.hw },2481 { .hw = &g12a_fclk_div5.hw },2482 { .hw = &g12a_fclk_div7.hw },2483 /*2484 * Following these parent clocks, we should also have had mpll2, mpll32485 * and gp0_pll but these clocks are too precious to be used here. All2486 * the necessary rates for MMC and NAND operation can be acheived using2487 * g12a_ee_core or fclk_div clocks2488 */2489};2490 2491/* SDIO clock */2492static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {2493 .data = &(struct clk_regmap_mux_data){2494 .offset = HHI_SD_EMMC_CLK_CNTL,2495 .mask = 0x7,2496 .shift = 9,2497 },2498 .hw.init = &(struct clk_init_data) {2499 .name = "sd_emmc_a_clk0_sel",2500 .ops = &clk_regmap_mux_ops,2501 .parent_data = g12a_sd_emmc_clk0_parent_data,2502 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),2503 .flags = CLK_SET_RATE_PARENT,2504 },2505};2506 2507static struct clk_regmap g12a_sd_emmc_a_clk0_div = {2508 .data = &(struct clk_regmap_div_data){2509 .offset = HHI_SD_EMMC_CLK_CNTL,2510 .shift = 0,2511 .width = 7,2512 },2513 .hw.init = &(struct clk_init_data) {2514 .name = "sd_emmc_a_clk0_div",2515 .ops = &clk_regmap_divider_ops,2516 .parent_hws = (const struct clk_hw *[]) {2517 &g12a_sd_emmc_a_clk0_sel.hw2518 },2519 .num_parents = 1,2520 .flags = CLK_SET_RATE_PARENT,2521 },2522};2523 2524static struct clk_regmap g12a_sd_emmc_a_clk0 = {2525 .data = &(struct clk_regmap_gate_data){2526 .offset = HHI_SD_EMMC_CLK_CNTL,2527 .bit_idx = 7,2528 },2529 .hw.init = &(struct clk_init_data){2530 .name = "sd_emmc_a_clk0",2531 .ops = &clk_regmap_gate_ops,2532 .parent_hws = (const struct clk_hw *[]) {2533 &g12a_sd_emmc_a_clk0_div.hw2534 },2535 .num_parents = 1,2536 .flags = CLK_SET_RATE_PARENT,2537 },2538};2539 2540/* SDcard clock */2541static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {2542 .data = &(struct clk_regmap_mux_data){2543 .offset = HHI_SD_EMMC_CLK_CNTL,2544 .mask = 0x7,2545 .shift = 25,2546 },2547 .hw.init = &(struct clk_init_data) {2548 .name = "sd_emmc_b_clk0_sel",2549 .ops = &clk_regmap_mux_ops,2550 .parent_data = g12a_sd_emmc_clk0_parent_data,2551 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),2552 .flags = CLK_SET_RATE_PARENT,2553 },2554};2555 2556static struct clk_regmap g12a_sd_emmc_b_clk0_div = {2557 .data = &(struct clk_regmap_div_data){2558 .offset = HHI_SD_EMMC_CLK_CNTL,2559 .shift = 16,2560 .width = 7,2561 },2562 .hw.init = &(struct clk_init_data) {2563 .name = "sd_emmc_b_clk0_div",2564 .ops = &clk_regmap_divider_ops,2565 .parent_hws = (const struct clk_hw *[]) {2566 &g12a_sd_emmc_b_clk0_sel.hw2567 },2568 .num_parents = 1,2569 .flags = CLK_SET_RATE_PARENT,2570 },2571};2572 2573static struct clk_regmap g12a_sd_emmc_b_clk0 = {2574 .data = &(struct clk_regmap_gate_data){2575 .offset = HHI_SD_EMMC_CLK_CNTL,2576 .bit_idx = 23,2577 },2578 .hw.init = &(struct clk_init_data){2579 .name = "sd_emmc_b_clk0",2580 .ops = &clk_regmap_gate_ops,2581 .parent_hws = (const struct clk_hw *[]) {2582 &g12a_sd_emmc_b_clk0_div.hw2583 },2584 .num_parents = 1,2585 .flags = CLK_SET_RATE_PARENT,2586 },2587};2588 2589/* EMMC/NAND clock */2590static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {2591 .data = &(struct clk_regmap_mux_data){2592 .offset = HHI_NAND_CLK_CNTL,2593 .mask = 0x7,2594 .shift = 9,2595 },2596 .hw.init = &(struct clk_init_data) {2597 .name = "sd_emmc_c_clk0_sel",2598 .ops = &clk_regmap_mux_ops,2599 .parent_data = g12a_sd_emmc_clk0_parent_data,2600 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),2601 .flags = CLK_SET_RATE_PARENT,2602 },2603};2604 2605static struct clk_regmap g12a_sd_emmc_c_clk0_div = {2606 .data = &(struct clk_regmap_div_data){2607 .offset = HHI_NAND_CLK_CNTL,2608 .shift = 0,2609 .width = 7,2610 },2611 .hw.init = &(struct clk_init_data) {2612 .name = "sd_emmc_c_clk0_div",2613 .ops = &clk_regmap_divider_ops,2614 .parent_hws = (const struct clk_hw *[]) {2615 &g12a_sd_emmc_c_clk0_sel.hw2616 },2617 .num_parents = 1,2618 .flags = CLK_SET_RATE_PARENT,2619 },2620};2621 2622static struct clk_regmap g12a_sd_emmc_c_clk0 = {2623 .data = &(struct clk_regmap_gate_data){2624 .offset = HHI_NAND_CLK_CNTL,2625 .bit_idx = 7,2626 },2627 .hw.init = &(struct clk_init_data){2628 .name = "sd_emmc_c_clk0",2629 .ops = &clk_regmap_gate_ops,2630 .parent_hws = (const struct clk_hw *[]) {2631 &g12a_sd_emmc_c_clk0_div.hw2632 },2633 .num_parents = 1,2634 .flags = CLK_SET_RATE_PARENT,2635 },2636};2637 2638/* Video Clocks */2639 2640static struct clk_regmap g12a_vid_pll_div = {2641 .data = &(struct meson_vid_pll_div_data){2642 .val = {2643 .reg_off = HHI_VID_PLL_CLK_DIV,2644 .shift = 0,2645 .width = 15,2646 },2647 .sel = {2648 .reg_off = HHI_VID_PLL_CLK_DIV,2649 .shift = 16,2650 .width = 2,2651 },2652 },2653 .hw.init = &(struct clk_init_data) {2654 .name = "vid_pll_div",2655 .ops = &meson_vid_pll_div_ro_ops,2656 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },2657 .num_parents = 1,2658 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,2659 },2660};2661 2662static const struct clk_hw *g12a_vid_pll_parent_hws[] = {2663 &g12a_vid_pll_div.hw,2664 &g12a_hdmi_pll.hw,2665};2666 2667static struct clk_regmap g12a_vid_pll_sel = {2668 .data = &(struct clk_regmap_mux_data){2669 .offset = HHI_VID_PLL_CLK_DIV,2670 .mask = 0x1,2671 .shift = 18,2672 },2673 .hw.init = &(struct clk_init_data){2674 .name = "vid_pll_sel",2675 .ops = &clk_regmap_mux_ops,2676 /*2677 * bit 18 selects from 2 possible parents:2678 * vid_pll_div or hdmi_pll2679 */2680 .parent_hws = g12a_vid_pll_parent_hws,2681 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),2682 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2683 },2684};2685 2686static struct clk_regmap g12a_vid_pll = {2687 .data = &(struct clk_regmap_gate_data){2688 .offset = HHI_VID_PLL_CLK_DIV,2689 .bit_idx = 19,2690 },2691 .hw.init = &(struct clk_init_data) {2692 .name = "vid_pll",2693 .ops = &clk_regmap_gate_ops,2694 .parent_hws = (const struct clk_hw *[]) {2695 &g12a_vid_pll_sel.hw2696 },2697 .num_parents = 1,2698 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2699 },2700};2701 2702/* VPU Clock */2703 2704static const struct clk_hw *g12a_vpu_parent_hws[] = {2705 &g12a_fclk_div3.hw,2706 &g12a_fclk_div4.hw,2707 &g12a_fclk_div5.hw,2708 &g12a_fclk_div7.hw,2709 &g12a_mpll1.hw,2710 &g12a_vid_pll.hw,2711 &g12a_hifi_pll.hw,2712 &g12a_gp0_pll.hw,2713};2714 2715static struct clk_regmap g12a_vpu_0_sel = {2716 .data = &(struct clk_regmap_mux_data){2717 .offset = HHI_VPU_CLK_CNTL,2718 .mask = 0x7,2719 .shift = 9,2720 },2721 .hw.init = &(struct clk_init_data){2722 .name = "vpu_0_sel",2723 .ops = &clk_regmap_mux_ops,2724 .parent_hws = g12a_vpu_parent_hws,2725 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),2726 .flags = CLK_SET_RATE_NO_REPARENT,2727 },2728};2729 2730static struct clk_regmap g12a_vpu_0_div = {2731 .data = &(struct clk_regmap_div_data){2732 .offset = HHI_VPU_CLK_CNTL,2733 .shift = 0,2734 .width = 7,2735 },2736 .hw.init = &(struct clk_init_data){2737 .name = "vpu_0_div",2738 .ops = &clk_regmap_divider_ops,2739 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },2740 .num_parents = 1,2741 .flags = CLK_SET_RATE_PARENT,2742 },2743};2744 2745static struct clk_regmap g12a_vpu_0 = {2746 .data = &(struct clk_regmap_gate_data){2747 .offset = HHI_VPU_CLK_CNTL,2748 .bit_idx = 8,2749 },2750 .hw.init = &(struct clk_init_data) {2751 .name = "vpu_0",2752 .ops = &clk_regmap_gate_ops,2753 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },2754 .num_parents = 1,2755 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2756 },2757};2758 2759static struct clk_regmap g12a_vpu_1_sel = {2760 .data = &(struct clk_regmap_mux_data){2761 .offset = HHI_VPU_CLK_CNTL,2762 .mask = 0x7,2763 .shift = 25,2764 },2765 .hw.init = &(struct clk_init_data){2766 .name = "vpu_1_sel",2767 .ops = &clk_regmap_mux_ops,2768 .parent_hws = g12a_vpu_parent_hws,2769 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),2770 .flags = CLK_SET_RATE_NO_REPARENT,2771 },2772};2773 2774static struct clk_regmap g12a_vpu_1_div = {2775 .data = &(struct clk_regmap_div_data){2776 .offset = HHI_VPU_CLK_CNTL,2777 .shift = 16,2778 .width = 7,2779 },2780 .hw.init = &(struct clk_init_data){2781 .name = "vpu_1_div",2782 .ops = &clk_regmap_divider_ops,2783 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },2784 .num_parents = 1,2785 .flags = CLK_SET_RATE_PARENT,2786 },2787};2788 2789static struct clk_regmap g12a_vpu_1 = {2790 .data = &(struct clk_regmap_gate_data){2791 .offset = HHI_VPU_CLK_CNTL,2792 .bit_idx = 24,2793 },2794 .hw.init = &(struct clk_init_data) {2795 .name = "vpu_1",2796 .ops = &clk_regmap_gate_ops,2797 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },2798 .num_parents = 1,2799 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2800 },2801};2802 2803static struct clk_regmap g12a_vpu = {2804 .data = &(struct clk_regmap_mux_data){2805 .offset = HHI_VPU_CLK_CNTL,2806 .mask = 1,2807 .shift = 31,2808 },2809 .hw.init = &(struct clk_init_data){2810 .name = "vpu",2811 .ops = &clk_regmap_mux_ops,2812 /*2813 * bit 31 selects from 2 possible parents:2814 * vpu_0 or vpu_12815 */2816 .parent_hws = (const struct clk_hw *[]) {2817 &g12a_vpu_0.hw,2818 &g12a_vpu_1.hw,2819 },2820 .num_parents = 2,2821 .flags = CLK_SET_RATE_NO_REPARENT,2822 },2823};2824 2825/* VDEC clocks */2826 2827static const struct clk_hw *g12a_vdec_parent_hws[] = {2828 &g12a_fclk_div2p5.hw,2829 &g12a_fclk_div3.hw,2830 &g12a_fclk_div4.hw,2831 &g12a_fclk_div5.hw,2832 &g12a_fclk_div7.hw,2833 &g12a_hifi_pll.hw,2834 &g12a_gp0_pll.hw,2835};2836 2837static struct clk_regmap g12a_vdec_1_sel = {2838 .data = &(struct clk_regmap_mux_data){2839 .offset = HHI_VDEC_CLK_CNTL,2840 .mask = 0x7,2841 .shift = 9,2842 .flags = CLK_MUX_ROUND_CLOSEST,2843 },2844 .hw.init = &(struct clk_init_data){2845 .name = "vdec_1_sel",2846 .ops = &clk_regmap_mux_ops,2847 .parent_hws = g12a_vdec_parent_hws,2848 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),2849 .flags = CLK_SET_RATE_PARENT,2850 },2851};2852 2853static struct clk_regmap g12a_vdec_1_div = {2854 .data = &(struct clk_regmap_div_data){2855 .offset = HHI_VDEC_CLK_CNTL,2856 .shift = 0,2857 .width = 7,2858 .flags = CLK_DIVIDER_ROUND_CLOSEST,2859 },2860 .hw.init = &(struct clk_init_data){2861 .name = "vdec_1_div",2862 .ops = &clk_regmap_divider_ops,2863 .parent_hws = (const struct clk_hw *[]) {2864 &g12a_vdec_1_sel.hw2865 },2866 .num_parents = 1,2867 .flags = CLK_SET_RATE_PARENT,2868 },2869};2870 2871static struct clk_regmap g12a_vdec_1 = {2872 .data = &(struct clk_regmap_gate_data){2873 .offset = HHI_VDEC_CLK_CNTL,2874 .bit_idx = 8,2875 },2876 .hw.init = &(struct clk_init_data) {2877 .name = "vdec_1",2878 .ops = &clk_regmap_gate_ops,2879 .parent_hws = (const struct clk_hw *[]) {2880 &g12a_vdec_1_div.hw2881 },2882 .num_parents = 1,2883 .flags = CLK_SET_RATE_PARENT,2884 },2885};2886 2887static struct clk_regmap g12a_vdec_hevcf_sel = {2888 .data = &(struct clk_regmap_mux_data){2889 .offset = HHI_VDEC2_CLK_CNTL,2890 .mask = 0x7,2891 .shift = 9,2892 .flags = CLK_MUX_ROUND_CLOSEST,2893 },2894 .hw.init = &(struct clk_init_data){2895 .name = "vdec_hevcf_sel",2896 .ops = &clk_regmap_mux_ops,2897 .parent_hws = g12a_vdec_parent_hws,2898 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),2899 .flags = CLK_SET_RATE_PARENT,2900 },2901};2902 2903static struct clk_regmap g12a_vdec_hevcf_div = {2904 .data = &(struct clk_regmap_div_data){2905 .offset = HHI_VDEC2_CLK_CNTL,2906 .shift = 0,2907 .width = 7,2908 .flags = CLK_DIVIDER_ROUND_CLOSEST,2909 },2910 .hw.init = &(struct clk_init_data){2911 .name = "vdec_hevcf_div",2912 .ops = &clk_regmap_divider_ops,2913 .parent_hws = (const struct clk_hw *[]) {2914 &g12a_vdec_hevcf_sel.hw2915 },2916 .num_parents = 1,2917 .flags = CLK_SET_RATE_PARENT,2918 },2919};2920 2921static struct clk_regmap g12a_vdec_hevcf = {2922 .data = &(struct clk_regmap_gate_data){2923 .offset = HHI_VDEC2_CLK_CNTL,2924 .bit_idx = 8,2925 },2926 .hw.init = &(struct clk_init_data) {2927 .name = "vdec_hevcf",2928 .ops = &clk_regmap_gate_ops,2929 .parent_hws = (const struct clk_hw *[]) {2930 &g12a_vdec_hevcf_div.hw2931 },2932 .num_parents = 1,2933 .flags = CLK_SET_RATE_PARENT,2934 },2935};2936 2937static struct clk_regmap g12a_vdec_hevc_sel = {2938 .data = &(struct clk_regmap_mux_data){2939 .offset = HHI_VDEC2_CLK_CNTL,2940 .mask = 0x7,2941 .shift = 25,2942 .flags = CLK_MUX_ROUND_CLOSEST,2943 },2944 .hw.init = &(struct clk_init_data){2945 .name = "vdec_hevc_sel",2946 .ops = &clk_regmap_mux_ops,2947 .parent_hws = g12a_vdec_parent_hws,2948 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),2949 .flags = CLK_SET_RATE_PARENT,2950 },2951};2952 2953static struct clk_regmap g12a_vdec_hevc_div = {2954 .data = &(struct clk_regmap_div_data){2955 .offset = HHI_VDEC2_CLK_CNTL,2956 .shift = 16,2957 .width = 7,2958 .flags = CLK_DIVIDER_ROUND_CLOSEST,2959 },2960 .hw.init = &(struct clk_init_data){2961 .name = "vdec_hevc_div",2962 .ops = &clk_regmap_divider_ops,2963 .parent_hws = (const struct clk_hw *[]) {2964 &g12a_vdec_hevc_sel.hw2965 },2966 .num_parents = 1,2967 .flags = CLK_SET_RATE_PARENT,2968 },2969};2970 2971static struct clk_regmap g12a_vdec_hevc = {2972 .data = &(struct clk_regmap_gate_data){2973 .offset = HHI_VDEC2_CLK_CNTL,2974 .bit_idx = 24,2975 },2976 .hw.init = &(struct clk_init_data) {2977 .name = "vdec_hevc",2978 .ops = &clk_regmap_gate_ops,2979 .parent_hws = (const struct clk_hw *[]) {2980 &g12a_vdec_hevc_div.hw2981 },2982 .num_parents = 1,2983 .flags = CLK_SET_RATE_PARENT,2984 },2985};2986 2987/* VAPB Clock */2988 2989static const struct clk_hw *g12a_vapb_parent_hws[] = {2990 &g12a_fclk_div4.hw,2991 &g12a_fclk_div3.hw,2992 &g12a_fclk_div5.hw,2993 &g12a_fclk_div7.hw,2994 &g12a_mpll1.hw,2995 &g12a_vid_pll.hw,2996 &g12a_mpll2.hw,2997 &g12a_fclk_div2p5.hw,2998};2999 3000static struct clk_regmap g12a_vapb_0_sel = {3001 .data = &(struct clk_regmap_mux_data){3002 .offset = HHI_VAPBCLK_CNTL,3003 .mask = 0x3,3004 .shift = 9,3005 },3006 .hw.init = &(struct clk_init_data){3007 .name = "vapb_0_sel",3008 .ops = &clk_regmap_mux_ops,3009 .parent_hws = g12a_vapb_parent_hws,3010 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),3011 .flags = CLK_SET_RATE_NO_REPARENT,3012 },3013};3014 3015static struct clk_regmap g12a_vapb_0_div = {3016 .data = &(struct clk_regmap_div_data){3017 .offset = HHI_VAPBCLK_CNTL,3018 .shift = 0,3019 .width = 7,3020 },3021 .hw.init = &(struct clk_init_data){3022 .name = "vapb_0_div",3023 .ops = &clk_regmap_divider_ops,3024 .parent_hws = (const struct clk_hw *[]) {3025 &g12a_vapb_0_sel.hw3026 },3027 .num_parents = 1,3028 .flags = CLK_SET_RATE_PARENT,3029 },3030};3031 3032static struct clk_regmap g12a_vapb_0 = {3033 .data = &(struct clk_regmap_gate_data){3034 .offset = HHI_VAPBCLK_CNTL,3035 .bit_idx = 8,3036 },3037 .hw.init = &(struct clk_init_data) {3038 .name = "vapb_0",3039 .ops = &clk_regmap_gate_ops,3040 .parent_hws = (const struct clk_hw *[]) {3041 &g12a_vapb_0_div.hw3042 },3043 .num_parents = 1,3044 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3045 },3046};3047 3048static struct clk_regmap g12a_vapb_1_sel = {3049 .data = &(struct clk_regmap_mux_data){3050 .offset = HHI_VAPBCLK_CNTL,3051 .mask = 0x3,3052 .shift = 25,3053 },3054 .hw.init = &(struct clk_init_data){3055 .name = "vapb_1_sel",3056 .ops = &clk_regmap_mux_ops,3057 .parent_hws = g12a_vapb_parent_hws,3058 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),3059 .flags = CLK_SET_RATE_NO_REPARENT,3060 },3061};3062 3063static struct clk_regmap g12a_vapb_1_div = {3064 .data = &(struct clk_regmap_div_data){3065 .offset = HHI_VAPBCLK_CNTL,3066 .shift = 16,3067 .width = 7,3068 },3069 .hw.init = &(struct clk_init_data){3070 .name = "vapb_1_div",3071 .ops = &clk_regmap_divider_ops,3072 .parent_hws = (const struct clk_hw *[]) {3073 &g12a_vapb_1_sel.hw3074 },3075 .num_parents = 1,3076 .flags = CLK_SET_RATE_PARENT,3077 },3078};3079 3080static struct clk_regmap g12a_vapb_1 = {3081 .data = &(struct clk_regmap_gate_data){3082 .offset = HHI_VAPBCLK_CNTL,3083 .bit_idx = 24,3084 },3085 .hw.init = &(struct clk_init_data) {3086 .name = "vapb_1",3087 .ops = &clk_regmap_gate_ops,3088 .parent_hws = (const struct clk_hw *[]) {3089 &g12a_vapb_1_div.hw3090 },3091 .num_parents = 1,3092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3093 },3094};3095 3096static struct clk_regmap g12a_vapb_sel = {3097 .data = &(struct clk_regmap_mux_data){3098 .offset = HHI_VAPBCLK_CNTL,3099 .mask = 1,3100 .shift = 31,3101 },3102 .hw.init = &(struct clk_init_data){3103 .name = "vapb_sel",3104 .ops = &clk_regmap_mux_ops,3105 /*3106 * bit 31 selects from 2 possible parents:3107 * vapb_0 or vapb_13108 */3109 .parent_hws = (const struct clk_hw *[]) {3110 &g12a_vapb_0.hw,3111 &g12a_vapb_1.hw,3112 },3113 .num_parents = 2,3114 .flags = CLK_SET_RATE_NO_REPARENT,3115 },3116};3117 3118static struct clk_regmap g12a_vapb = {3119 .data = &(struct clk_regmap_gate_data){3120 .offset = HHI_VAPBCLK_CNTL,3121 .bit_idx = 30,3122 },3123 .hw.init = &(struct clk_init_data) {3124 .name = "vapb",3125 .ops = &clk_regmap_gate_ops,3126 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },3127 .num_parents = 1,3128 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3129 },3130};3131 3132static const struct clk_hw *g12a_vclk_parent_hws[] = {3133 &g12a_vid_pll.hw,3134 &g12a_gp0_pll.hw,3135 &g12a_hifi_pll.hw,3136 &g12a_mpll1.hw,3137 &g12a_fclk_div3.hw,3138 &g12a_fclk_div4.hw,3139 &g12a_fclk_div5.hw,3140 &g12a_fclk_div7.hw,3141};3142 3143static struct clk_regmap g12a_vclk_sel = {3144 .data = &(struct clk_regmap_mux_data){3145 .offset = HHI_VID_CLK_CNTL,3146 .mask = 0x7,3147 .shift = 16,3148 },3149 .hw.init = &(struct clk_init_data){3150 .name = "vclk_sel",3151 .ops = &clk_regmap_mux_ops,3152 .parent_hws = g12a_vclk_parent_hws,3153 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),3154 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3155 },3156};3157 3158static struct clk_regmap g12a_vclk2_sel = {3159 .data = &(struct clk_regmap_mux_data){3160 .offset = HHI_VIID_CLK_CNTL,3161 .mask = 0x7,3162 .shift = 16,3163 },3164 .hw.init = &(struct clk_init_data){3165 .name = "vclk2_sel",3166 .ops = &clk_regmap_mux_ops,3167 .parent_hws = g12a_vclk_parent_hws,3168 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),3169 .flags = CLK_SET_RATE_NO_REPARENT,3170 },3171};3172 3173static struct clk_regmap g12a_vclk_input = {3174 .data = &(struct clk_regmap_gate_data){3175 .offset = HHI_VID_CLK_DIV,3176 .bit_idx = 16,3177 },3178 .hw.init = &(struct clk_init_data) {3179 .name = "vclk_input",3180 .ops = &clk_regmap_gate_ops,3181 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },3182 .num_parents = 1,3183 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3184 },3185};3186 3187static struct clk_regmap g12a_vclk2_input = {3188 .data = &(struct clk_regmap_gate_data){3189 .offset = HHI_VIID_CLK_DIV,3190 .bit_idx = 16,3191 },3192 .hw.init = &(struct clk_init_data) {3193 .name = "vclk2_input",3194 .ops = &clk_regmap_gate_ops,3195 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },3196 .num_parents = 1,3197 },3198};3199 3200static struct clk_regmap g12a_vclk_div = {3201 .data = &(struct clk_regmap_div_data){3202 .offset = HHI_VID_CLK_DIV,3203 .shift = 0,3204 .width = 8,3205 },3206 .hw.init = &(struct clk_init_data){3207 .name = "vclk_div",3208 .ops = &clk_regmap_divider_ops,3209 .parent_hws = (const struct clk_hw *[]) {3210 &g12a_vclk_input.hw3211 },3212 .num_parents = 1,3213 .flags = CLK_GET_RATE_NOCACHE,3214 },3215};3216 3217static struct clk_regmap g12a_vclk2_div = {3218 .data = &(struct meson_vclk_div_data){3219 .div = {3220 .reg_off = HHI_VIID_CLK_DIV,3221 .shift = 0,3222 .width = 8,3223 },3224 .enable = {3225 .reg_off = HHI_VIID_CLK_DIV,3226 .shift = 16,3227 .width = 1,3228 },3229 .reset = {3230 .reg_off = HHI_VIID_CLK_DIV,3231 .shift = 17,3232 .width = 1,3233 },3234 .flags = CLK_DIVIDER_ROUND_CLOSEST,3235 },3236 .hw.init = &(struct clk_init_data){3237 .name = "vclk2_div",3238 .ops = &meson_vclk_div_ops,3239 .parent_hws = (const struct clk_hw *[]) {3240 &g12a_vclk2_input.hw3241 },3242 .num_parents = 1,3243 .flags = CLK_SET_RATE_GATE,3244 },3245};3246 3247static struct clk_regmap g12a_vclk = {3248 .data = &(struct clk_regmap_gate_data){3249 .offset = HHI_VID_CLK_CNTL,3250 .bit_idx = 19,3251 },3252 .hw.init = &(struct clk_init_data) {3253 .name = "vclk",3254 .ops = &clk_regmap_gate_ops,3255 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },3256 .num_parents = 1,3257 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3258 },3259};3260 3261static struct clk_regmap g12a_vclk2 = {3262 .data = &(struct meson_vclk_gate_data){3263 .enable = {3264 .reg_off = HHI_VIID_CLK_CNTL,3265 .shift = 19,3266 .width = 1,3267 },3268 .reset = {3269 .reg_off = HHI_VIID_CLK_CNTL,3270 .shift = 15,3271 .width = 1,3272 },3273 },3274 .hw.init = &(struct clk_init_data) {3275 .name = "vclk2",3276 .ops = &meson_vclk_gate_ops,3277 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },3278 .num_parents = 1,3279 .flags = CLK_SET_RATE_PARENT,3280 },3281};3282 3283static struct clk_regmap g12a_vclk_div1 = {3284 .data = &(struct clk_regmap_gate_data){3285 .offset = HHI_VID_CLK_CNTL,3286 .bit_idx = 0,3287 },3288 .hw.init = &(struct clk_init_data) {3289 .name = "vclk_div1",3290 .ops = &clk_regmap_gate_ops,3291 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },3292 .num_parents = 1,3293 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3294 },3295};3296 3297static struct clk_regmap g12a_vclk_div2_en = {3298 .data = &(struct clk_regmap_gate_data){3299 .offset = HHI_VID_CLK_CNTL,3300 .bit_idx = 1,3301 },3302 .hw.init = &(struct clk_init_data) {3303 .name = "vclk_div2_en",3304 .ops = &clk_regmap_gate_ops,3305 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },3306 .num_parents = 1,3307 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3308 },3309};3310 3311static struct clk_regmap g12a_vclk_div4_en = {3312 .data = &(struct clk_regmap_gate_data){3313 .offset = HHI_VID_CLK_CNTL,3314 .bit_idx = 2,3315 },3316 .hw.init = &(struct clk_init_data) {3317 .name = "vclk_div4_en",3318 .ops = &clk_regmap_gate_ops,3319 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },3320 .num_parents = 1,3321 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3322 },3323};3324 3325static struct clk_regmap g12a_vclk_div6_en = {3326 .data = &(struct clk_regmap_gate_data){3327 .offset = HHI_VID_CLK_CNTL,3328 .bit_idx = 3,3329 },3330 .hw.init = &(struct clk_init_data) {3331 .name = "vclk_div6_en",3332 .ops = &clk_regmap_gate_ops,3333 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },3334 .num_parents = 1,3335 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3336 },3337};3338 3339static struct clk_regmap g12a_vclk_div12_en = {3340 .data = &(struct clk_regmap_gate_data){3341 .offset = HHI_VID_CLK_CNTL,3342 .bit_idx = 4,3343 },3344 .hw.init = &(struct clk_init_data) {3345 .name = "vclk_div12_en",3346 .ops = &clk_regmap_gate_ops,3347 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },3348 .num_parents = 1,3349 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3350 },3351};3352 3353static struct clk_regmap g12a_vclk2_div1 = {3354 .data = &(struct clk_regmap_gate_data){3355 .offset = HHI_VIID_CLK_CNTL,3356 .bit_idx = 0,3357 },3358 .hw.init = &(struct clk_init_data) {3359 .name = "vclk2_div1",3360 .ops = &clk_regmap_gate_ops,3361 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },3362 .num_parents = 1,3363 .flags = CLK_SET_RATE_PARENT,3364 },3365};3366 3367static struct clk_regmap g12a_vclk2_div2_en = {3368 .data = &(struct clk_regmap_gate_data){3369 .offset = HHI_VIID_CLK_CNTL,3370 .bit_idx = 1,3371 },3372 .hw.init = &(struct clk_init_data) {3373 .name = "vclk2_div2_en",3374 .ops = &clk_regmap_gate_ops,3375 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },3376 .num_parents = 1,3377 .flags = CLK_SET_RATE_PARENT,3378 },3379};3380 3381static struct clk_regmap g12a_vclk2_div4_en = {3382 .data = &(struct clk_regmap_gate_data){3383 .offset = HHI_VIID_CLK_CNTL,3384 .bit_idx = 2,3385 },3386 .hw.init = &(struct clk_init_data) {3387 .name = "vclk2_div4_en",3388 .ops = &clk_regmap_gate_ops,3389 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },3390 .num_parents = 1,3391 .flags = CLK_SET_RATE_PARENT,3392 },3393};3394 3395static struct clk_regmap g12a_vclk2_div6_en = {3396 .data = &(struct clk_regmap_gate_data){3397 .offset = HHI_VIID_CLK_CNTL,3398 .bit_idx = 3,3399 },3400 .hw.init = &(struct clk_init_data) {3401 .name = "vclk2_div6_en",3402 .ops = &clk_regmap_gate_ops,3403 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },3404 .num_parents = 1,3405 .flags = CLK_SET_RATE_PARENT,3406 },3407};3408 3409static struct clk_regmap g12a_vclk2_div12_en = {3410 .data = &(struct clk_regmap_gate_data){3411 .offset = HHI_VIID_CLK_CNTL,3412 .bit_idx = 4,3413 },3414 .hw.init = &(struct clk_init_data) {3415 .name = "vclk2_div12_en",3416 .ops = &clk_regmap_gate_ops,3417 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },3418 .num_parents = 1,3419 .flags = CLK_SET_RATE_PARENT,3420 },3421};3422 3423static struct clk_fixed_factor g12a_vclk_div2 = {3424 .mult = 1,3425 .div = 2,3426 .hw.init = &(struct clk_init_data){3427 .name = "vclk_div2",3428 .ops = &clk_fixed_factor_ops,3429 .parent_hws = (const struct clk_hw *[]) {3430 &g12a_vclk_div2_en.hw3431 },3432 .num_parents = 1,3433 },3434};3435 3436static struct clk_fixed_factor g12a_vclk_div4 = {3437 .mult = 1,3438 .div = 4,3439 .hw.init = &(struct clk_init_data){3440 .name = "vclk_div4",3441 .ops = &clk_fixed_factor_ops,3442 .parent_hws = (const struct clk_hw *[]) {3443 &g12a_vclk_div4_en.hw3444 },3445 .num_parents = 1,3446 },3447};3448 3449static struct clk_fixed_factor g12a_vclk_div6 = {3450 .mult = 1,3451 .div = 6,3452 .hw.init = &(struct clk_init_data){3453 .name = "vclk_div6",3454 .ops = &clk_fixed_factor_ops,3455 .parent_hws = (const struct clk_hw *[]) {3456 &g12a_vclk_div6_en.hw3457 },3458 .num_parents = 1,3459 },3460};3461 3462static struct clk_fixed_factor g12a_vclk_div12 = {3463 .mult = 1,3464 .div = 12,3465 .hw.init = &(struct clk_init_data){3466 .name = "vclk_div12",3467 .ops = &clk_fixed_factor_ops,3468 .parent_hws = (const struct clk_hw *[]) {3469 &g12a_vclk_div12_en.hw3470 },3471 .num_parents = 1,3472 },3473};3474 3475static struct clk_fixed_factor g12a_vclk2_div2 = {3476 .mult = 1,3477 .div = 2,3478 .hw.init = &(struct clk_init_data){3479 .name = "vclk2_div2",3480 .ops = &clk_fixed_factor_ops,3481 .parent_hws = (const struct clk_hw *[]) {3482 &g12a_vclk2_div2_en.hw3483 },3484 .num_parents = 1,3485 .flags = CLK_SET_RATE_PARENT,3486 },3487};3488 3489static struct clk_fixed_factor g12a_vclk2_div4 = {3490 .mult = 1,3491 .div = 4,3492 .hw.init = &(struct clk_init_data){3493 .name = "vclk2_div4",3494 .ops = &clk_fixed_factor_ops,3495 .parent_hws = (const struct clk_hw *[]) {3496 &g12a_vclk2_div4_en.hw3497 },3498 .num_parents = 1,3499 .flags = CLK_SET_RATE_PARENT,3500 },3501};3502 3503static struct clk_fixed_factor g12a_vclk2_div6 = {3504 .mult = 1,3505 .div = 6,3506 .hw.init = &(struct clk_init_data){3507 .name = "vclk2_div6",3508 .ops = &clk_fixed_factor_ops,3509 .parent_hws = (const struct clk_hw *[]) {3510 &g12a_vclk2_div6_en.hw3511 },3512 .num_parents = 1,3513 .flags = CLK_SET_RATE_PARENT,3514 },3515};3516 3517static struct clk_fixed_factor g12a_vclk2_div12 = {3518 .mult = 1,3519 .div = 12,3520 .hw.init = &(struct clk_init_data){3521 .name = "vclk2_div12",3522 .ops = &clk_fixed_factor_ops,3523 .parent_hws = (const struct clk_hw *[]) {3524 &g12a_vclk2_div12_en.hw3525 },3526 .num_parents = 1,3527 .flags = CLK_SET_RATE_PARENT,3528 },3529};3530 3531static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };3532static const struct clk_hw *g12a_cts_parent_hws[] = {3533 &g12a_vclk_div1.hw,3534 &g12a_vclk_div2.hw,3535 &g12a_vclk_div4.hw,3536 &g12a_vclk_div6.hw,3537 &g12a_vclk_div12.hw,3538 &g12a_vclk2_div1.hw,3539 &g12a_vclk2_div2.hw,3540 &g12a_vclk2_div4.hw,3541 &g12a_vclk2_div6.hw,3542 &g12a_vclk2_div12.hw,3543};3544 3545static struct clk_regmap g12a_cts_enci_sel = {3546 .data = &(struct clk_regmap_mux_data){3547 .offset = HHI_VID_CLK_DIV,3548 .mask = 0xf,3549 .shift = 28,3550 .table = mux_table_cts_sel,3551 },3552 .hw.init = &(struct clk_init_data){3553 .name = "cts_enci_sel",3554 .ops = &clk_regmap_mux_ops,3555 .parent_hws = g12a_cts_parent_hws,3556 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),3557 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3558 },3559};3560 3561static struct clk_regmap g12a_cts_encp_sel = {3562 .data = &(struct clk_regmap_mux_data){3563 .offset = HHI_VID_CLK_DIV,3564 .mask = 0xf,3565 .shift = 20,3566 .table = mux_table_cts_sel,3567 },3568 .hw.init = &(struct clk_init_data){3569 .name = "cts_encp_sel",3570 .ops = &clk_regmap_mux_ops,3571 .parent_hws = g12a_cts_parent_hws,3572 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),3573 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3574 },3575};3576 3577static struct clk_regmap g12a_cts_encl_sel = {3578 .data = &(struct clk_regmap_mux_data){3579 .offset = HHI_VIID_CLK_DIV,3580 .mask = 0xf,3581 .shift = 12,3582 .table = mux_table_cts_sel,3583 },3584 .hw.init = &(struct clk_init_data){3585 .name = "cts_encl_sel",3586 .ops = &clk_regmap_mux_ops,3587 .parent_hws = g12a_cts_parent_hws,3588 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),3589 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,3590 },3591};3592 3593static struct clk_regmap g12a_cts_vdac_sel = {3594 .data = &(struct clk_regmap_mux_data){3595 .offset = HHI_VIID_CLK_DIV,3596 .mask = 0xf,3597 .shift = 28,3598 .table = mux_table_cts_sel,3599 },3600 .hw.init = &(struct clk_init_data){3601 .name = "cts_vdac_sel",3602 .ops = &clk_regmap_mux_ops,3603 .parent_hws = g12a_cts_parent_hws,3604 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),3605 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3606 },3607};3608 3609/* TOFIX: add support for cts_tcon */3610static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };3611static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {3612 &g12a_vclk_div1.hw,3613 &g12a_vclk_div2.hw,3614 &g12a_vclk_div4.hw,3615 &g12a_vclk_div6.hw,3616 &g12a_vclk_div12.hw,3617 &g12a_vclk2_div1.hw,3618 &g12a_vclk2_div2.hw,3619 &g12a_vclk2_div4.hw,3620 &g12a_vclk2_div6.hw,3621 &g12a_vclk2_div12.hw,3622};3623 3624static struct clk_regmap g12a_hdmi_tx_sel = {3625 .data = &(struct clk_regmap_mux_data){3626 .offset = HHI_HDMI_CLK_CNTL,3627 .mask = 0xf,3628 .shift = 16,3629 .table = mux_table_hdmi_tx_sel,3630 },3631 .hw.init = &(struct clk_init_data){3632 .name = "hdmi_tx_sel",3633 .ops = &clk_regmap_mux_ops,3634 .parent_hws = g12a_cts_hdmi_tx_parent_hws,3635 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),3636 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3637 },3638};3639 3640static struct clk_regmap g12a_cts_enci = {3641 .data = &(struct clk_regmap_gate_data){3642 .offset = HHI_VID_CLK_CNTL2,3643 .bit_idx = 0,3644 },3645 .hw.init = &(struct clk_init_data) {3646 .name = "cts_enci",3647 .ops = &clk_regmap_gate_ops,3648 .parent_hws = (const struct clk_hw *[]) {3649 &g12a_cts_enci_sel.hw3650 },3651 .num_parents = 1,3652 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3653 },3654};3655 3656static struct clk_regmap g12a_cts_encp = {3657 .data = &(struct clk_regmap_gate_data){3658 .offset = HHI_VID_CLK_CNTL2,3659 .bit_idx = 2,3660 },3661 .hw.init = &(struct clk_init_data) {3662 .name = "cts_encp",3663 .ops = &clk_regmap_gate_ops,3664 .parent_hws = (const struct clk_hw *[]) {3665 &g12a_cts_encp_sel.hw3666 },3667 .num_parents = 1,3668 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3669 },3670};3671 3672static struct clk_regmap g12a_cts_encl = {3673 .data = &(struct clk_regmap_gate_data){3674 .offset = HHI_VID_CLK_CNTL2,3675 .bit_idx = 3,3676 },3677 .hw.init = &(struct clk_init_data) {3678 .name = "cts_encl",3679 .ops = &clk_regmap_gate_ops,3680 .parent_hws = (const struct clk_hw *[]) {3681 &g12a_cts_encl_sel.hw3682 },3683 .num_parents = 1,3684 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3685 },3686};3687 3688static struct clk_regmap g12a_cts_vdac = {3689 .data = &(struct clk_regmap_gate_data){3690 .offset = HHI_VID_CLK_CNTL2,3691 .bit_idx = 4,3692 },3693 .hw.init = &(struct clk_init_data) {3694 .name = "cts_vdac",3695 .ops = &clk_regmap_gate_ops,3696 .parent_hws = (const struct clk_hw *[]) {3697 &g12a_cts_vdac_sel.hw3698 },3699 .num_parents = 1,3700 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3701 },3702};3703 3704static struct clk_regmap g12a_hdmi_tx = {3705 .data = &(struct clk_regmap_gate_data){3706 .offset = HHI_VID_CLK_CNTL2,3707 .bit_idx = 5,3708 },3709 .hw.init = &(struct clk_init_data) {3710 .name = "hdmi_tx",3711 .ops = &clk_regmap_gate_ops,3712 .parent_hws = (const struct clk_hw *[]) {3713 &g12a_hdmi_tx_sel.hw3714 },3715 .num_parents = 1,3716 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3717 },3718};3719 3720/* MIPI DSI Host Clocks */3721 3722static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {3723 &g12a_vid_pll.hw,3724 &g12a_gp0_pll.hw,3725 &g12a_hifi_pll.hw,3726 &g12a_mpll1.hw,3727 &g12a_fclk_div2.hw,3728 &g12a_fclk_div2p5.hw,3729 &g12a_fclk_div3.hw,3730 &g12a_fclk_div7.hw,3731};3732 3733static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {3734 .data = &(struct clk_regmap_mux_data){3735 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,3736 .mask = 0x7,3737 .shift = 12,3738 .flags = CLK_MUX_ROUND_CLOSEST,3739 },3740 .hw.init = &(struct clk_init_data){3741 .name = "mipi_dsi_pxclk_sel",3742 .ops = &clk_regmap_mux_ops,3743 .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,3744 .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),3745 .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,3746 },3747};3748 3749/*3750 * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value3751 * when setting a clock whith this node in the clock path, but doesn't garantee the divider3752 * is at /1 at boot until a rate is set.3753 */3754static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {3755 { .val = 0, .div = 1 },3756 { /* sentinel */ },3757};3758 3759static struct clk_regmap g12a_mipi_dsi_pxclk_div = {3760 .data = &(struct clk_regmap_div_data){3761 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,3762 .shift = 0,3763 .width = 7,3764 .table = g12a_mipi_dsi_pxclk_div_table,3765 },3766 .hw.init = &(struct clk_init_data){3767 .name = "mipi_dsi_pxclk_div",3768 .ops = &clk_regmap_divider_ops,3769 .parent_hws = (const struct clk_hw *[]) {3770 &g12a_mipi_dsi_pxclk_sel.hw3771 },3772 .num_parents = 1,3773 .flags = CLK_SET_RATE_PARENT,3774 },3775};3776 3777static struct clk_regmap g12a_mipi_dsi_pxclk = {3778 .data = &(struct clk_regmap_gate_data){3779 .offset = HHI_MIPIDSI_PHY_CLK_CNTL,3780 .bit_idx = 8,3781 },3782 .hw.init = &(struct clk_init_data) {3783 .name = "mipi_dsi_pxclk",3784 .ops = &clk_regmap_gate_ops,3785 .parent_hws = (const struct clk_hw *[]) {3786 &g12a_mipi_dsi_pxclk_div.hw3787 },3788 .num_parents = 1,3789 .flags = CLK_SET_RATE_PARENT,3790 },3791};3792 3793/* MIPI ISP Clocks */3794 3795static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {3796 { .fw_name = "xtal", },3797 { .hw = &g12a_gp0_pll.hw },3798 { .hw = &g12a_hifi_pll.hw },3799 { .hw = &g12a_fclk_div2p5.hw },3800 { .hw = &g12a_fclk_div3.hw },3801 { .hw = &g12a_fclk_div4.hw },3802 { .hw = &g12a_fclk_div5.hw },3803 { .hw = &g12a_fclk_div7.hw },3804};3805 3806static struct clk_regmap g12b_mipi_isp_sel = {3807 .data = &(struct clk_regmap_mux_data){3808 .offset = HHI_ISP_CLK_CNTL,3809 .mask = 7,3810 .shift = 9,3811 },3812 .hw.init = &(struct clk_init_data){3813 .name = "mipi_isp_sel",3814 .ops = &clk_regmap_mux_ops,3815 .parent_data = g12b_mipi_isp_parent_data,3816 .num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),3817 },3818};3819 3820static struct clk_regmap g12b_mipi_isp_div = {3821 .data = &(struct clk_regmap_div_data){3822 .offset = HHI_ISP_CLK_CNTL,3823 .shift = 0,3824 .width = 7,3825 },3826 .hw.init = &(struct clk_init_data){3827 .name = "mipi_isp_div",3828 .ops = &clk_regmap_divider_ops,3829 .parent_hws = (const struct clk_hw *[]) {3830 &g12b_mipi_isp_sel.hw3831 },3832 .num_parents = 1,3833 .flags = CLK_SET_RATE_PARENT,3834 },3835};3836 3837static struct clk_regmap g12b_mipi_isp = {3838 .data = &(struct clk_regmap_gate_data){3839 .offset = HHI_ISP_CLK_CNTL,3840 .bit_idx = 8,3841 },3842 .hw.init = &(struct clk_init_data) {3843 .name = "mipi_isp",3844 .ops = &clk_regmap_gate_ops,3845 .parent_hws = (const struct clk_hw *[]) {3846 &g12b_mipi_isp_div.hw3847 },3848 .num_parents = 1,3849 .flags = CLK_SET_RATE_PARENT,3850 },3851};3852 3853/* HDMI Clocks */3854 3855static const struct clk_parent_data g12a_hdmi_parent_data[] = {3856 { .fw_name = "xtal", },3857 { .hw = &g12a_fclk_div4.hw },3858 { .hw = &g12a_fclk_div3.hw },3859 { .hw = &g12a_fclk_div5.hw },3860};3861 3862static struct clk_regmap g12a_hdmi_sel = {3863 .data = &(struct clk_regmap_mux_data){3864 .offset = HHI_HDMI_CLK_CNTL,3865 .mask = 0x3,3866 .shift = 9,3867 .flags = CLK_MUX_ROUND_CLOSEST,3868 },3869 .hw.init = &(struct clk_init_data){3870 .name = "hdmi_sel",3871 .ops = &clk_regmap_mux_ops,3872 .parent_data = g12a_hdmi_parent_data,3873 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),3874 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,3875 },3876};3877 3878static struct clk_regmap g12a_hdmi_div = {3879 .data = &(struct clk_regmap_div_data){3880 .offset = HHI_HDMI_CLK_CNTL,3881 .shift = 0,3882 .width = 7,3883 },3884 .hw.init = &(struct clk_init_data){3885 .name = "hdmi_div",3886 .ops = &clk_regmap_divider_ops,3887 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },3888 .num_parents = 1,3889 .flags = CLK_GET_RATE_NOCACHE,3890 },3891};3892 3893static struct clk_regmap g12a_hdmi = {3894 .data = &(struct clk_regmap_gate_data){3895 .offset = HHI_HDMI_CLK_CNTL,3896 .bit_idx = 8,3897 },3898 .hw.init = &(struct clk_init_data) {3899 .name = "hdmi",3900 .ops = &clk_regmap_gate_ops,3901 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },3902 .num_parents = 1,3903 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,3904 },3905};3906 3907/*3908 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)3909 * muxed by a glitch-free switch. The CCF can manage this glitch-free3910 * mux because it does top-to-bottom updates the each clock tree and3911 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.3912 */3913static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {3914 { .fw_name = "xtal", },3915 { .hw = &g12a_gp0_pll.hw },3916 { .hw = &g12a_hifi_pll.hw },3917 { .hw = &g12a_fclk_div2p5.hw },3918 { .hw = &g12a_fclk_div3.hw },3919 { .hw = &g12a_fclk_div4.hw },3920 { .hw = &g12a_fclk_div5.hw },3921 { .hw = &g12a_fclk_div7.hw },3922};3923 3924static struct clk_regmap g12a_mali_0_sel = {3925 .data = &(struct clk_regmap_mux_data){3926 .offset = HHI_MALI_CLK_CNTL,3927 .mask = 0x7,3928 .shift = 9,3929 },3930 .hw.init = &(struct clk_init_data){3931 .name = "mali_0_sel",3932 .ops = &clk_regmap_mux_ops,3933 .parent_data = g12a_mali_0_1_parent_data,3934 .num_parents = 8,3935 /*3936 * Don't request the parent to change the rate because3937 * all GPU frequencies can be derived from the fclk_*3938 * clocks and one special GP0_PLL setting. This is3939 * important because we need the MPLL clocks for audio.3940 */3941 .flags = 0,3942 },3943};3944 3945static struct clk_regmap g12a_mali_0_div = {3946 .data = &(struct clk_regmap_div_data){3947 .offset = HHI_MALI_CLK_CNTL,3948 .shift = 0,3949 .width = 7,3950 },3951 .hw.init = &(struct clk_init_data){3952 .name = "mali_0_div",3953 .ops = &clk_regmap_divider_ops,3954 .parent_hws = (const struct clk_hw *[]) {3955 &g12a_mali_0_sel.hw3956 },3957 .num_parents = 1,3958 .flags = CLK_SET_RATE_PARENT,3959 },3960};3961 3962static struct clk_regmap g12a_mali_0 = {3963 .data = &(struct clk_regmap_gate_data){3964 .offset = HHI_MALI_CLK_CNTL,3965 .bit_idx = 8,3966 },3967 .hw.init = &(struct clk_init_data){3968 .name = "mali_0",3969 .ops = &clk_regmap_gate_ops,3970 .parent_hws = (const struct clk_hw *[]) {3971 &g12a_mali_0_div.hw3972 },3973 .num_parents = 1,3974 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,3975 },3976};3977 3978static struct clk_regmap g12a_mali_1_sel = {3979 .data = &(struct clk_regmap_mux_data){3980 .offset = HHI_MALI_CLK_CNTL,3981 .mask = 0x7,3982 .shift = 25,3983 },3984 .hw.init = &(struct clk_init_data){3985 .name = "mali_1_sel",3986 .ops = &clk_regmap_mux_ops,3987 .parent_data = g12a_mali_0_1_parent_data,3988 .num_parents = 8,3989 /*3990 * Don't request the parent to change the rate because3991 * all GPU frequencies can be derived from the fclk_*3992 * clocks and one special GP0_PLL setting. This is3993 * important because we need the MPLL clocks for audio.3994 */3995 .flags = 0,3996 },3997};3998 3999static struct clk_regmap g12a_mali_1_div = {4000 .data = &(struct clk_regmap_div_data){4001 .offset = HHI_MALI_CLK_CNTL,4002 .shift = 16,4003 .width = 7,4004 },4005 .hw.init = &(struct clk_init_data){4006 .name = "mali_1_div",4007 .ops = &clk_regmap_divider_ops,4008 .parent_hws = (const struct clk_hw *[]) {4009 &g12a_mali_1_sel.hw4010 },4011 .num_parents = 1,4012 .flags = CLK_SET_RATE_PARENT,4013 },4014};4015 4016static struct clk_regmap g12a_mali_1 = {4017 .data = &(struct clk_regmap_gate_data){4018 .offset = HHI_MALI_CLK_CNTL,4019 .bit_idx = 24,4020 },4021 .hw.init = &(struct clk_init_data){4022 .name = "mali_1",4023 .ops = &clk_regmap_gate_ops,4024 .parent_hws = (const struct clk_hw *[]) {4025 &g12a_mali_1_div.hw4026 },4027 .num_parents = 1,4028 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,4029 },4030};4031 4032static const struct clk_hw *g12a_mali_parent_hws[] = {4033 &g12a_mali_0.hw,4034 &g12a_mali_1.hw,4035};4036 4037static struct clk_regmap g12a_mali = {4038 .data = &(struct clk_regmap_mux_data){4039 .offset = HHI_MALI_CLK_CNTL,4040 .mask = 1,4041 .shift = 31,4042 },4043 .hw.init = &(struct clk_init_data){4044 .name = "mali",4045 .ops = &clk_regmap_mux_ops,4046 .parent_hws = g12a_mali_parent_hws,4047 .num_parents = 2,4048 .flags = CLK_SET_RATE_PARENT,4049 },4050};4051 4052static struct clk_regmap g12a_ts_div = {4053 .data = &(struct clk_regmap_div_data){4054 .offset = HHI_TS_CLK_CNTL,4055 .shift = 0,4056 .width = 8,4057 },4058 .hw.init = &(struct clk_init_data){4059 .name = "ts_div",4060 .ops = &clk_regmap_divider_ro_ops,4061 .parent_data = &(const struct clk_parent_data) {4062 .fw_name = "xtal",4063 },4064 .num_parents = 1,4065 },4066};4067 4068static struct clk_regmap g12a_ts = {4069 .data = &(struct clk_regmap_gate_data){4070 .offset = HHI_TS_CLK_CNTL,4071 .bit_idx = 8,4072 },4073 .hw.init = &(struct clk_init_data){4074 .name = "ts",4075 .ops = &clk_regmap_gate_ops,4076 .parent_hws = (const struct clk_hw *[]) {4077 &g12a_ts_div.hw4078 },4079 .num_parents = 1,4080 },4081};4082 4083/* SPICC SCLK source clock */4084 4085static const struct clk_parent_data spicc_sclk_parent_data[] = {4086 { .fw_name = "xtal", },4087 { .hw = &g12a_clk81.hw },4088 { .hw = &g12a_fclk_div4.hw },4089 { .hw = &g12a_fclk_div3.hw },4090 { .hw = &g12a_fclk_div5.hw },4091 { .hw = &g12a_fclk_div7.hw },4092};4093 4094static struct clk_regmap g12a_spicc0_sclk_sel = {4095 .data = &(struct clk_regmap_mux_data){4096 .offset = HHI_SPICC_CLK_CNTL,4097 .mask = 7,4098 .shift = 7,4099 },4100 .hw.init = &(struct clk_init_data){4101 .name = "spicc0_sclk_sel",4102 .ops = &clk_regmap_mux_ops,4103 .parent_data = spicc_sclk_parent_data,4104 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),4105 },4106};4107 4108static struct clk_regmap g12a_spicc0_sclk_div = {4109 .data = &(struct clk_regmap_div_data){4110 .offset = HHI_SPICC_CLK_CNTL,4111 .shift = 0,4112 .width = 6,4113 },4114 .hw.init = &(struct clk_init_data){4115 .name = "spicc0_sclk_div",4116 .ops = &clk_regmap_divider_ops,4117 .parent_hws = (const struct clk_hw *[]) {4118 &g12a_spicc0_sclk_sel.hw4119 },4120 .num_parents = 1,4121 .flags = CLK_SET_RATE_PARENT,4122 },4123};4124 4125static struct clk_regmap g12a_spicc0_sclk = {4126 .data = &(struct clk_regmap_gate_data){4127 .offset = HHI_SPICC_CLK_CNTL,4128 .bit_idx = 6,4129 },4130 .hw.init = &(struct clk_init_data){4131 .name = "spicc0_sclk",4132 .ops = &clk_regmap_gate_ops,4133 .parent_hws = (const struct clk_hw *[]) {4134 &g12a_spicc0_sclk_div.hw4135 },4136 .num_parents = 1,4137 .flags = CLK_SET_RATE_PARENT,4138 },4139};4140 4141static struct clk_regmap g12a_spicc1_sclk_sel = {4142 .data = &(struct clk_regmap_mux_data){4143 .offset = HHI_SPICC_CLK_CNTL,4144 .mask = 7,4145 .shift = 23,4146 },4147 .hw.init = &(struct clk_init_data){4148 .name = "spicc1_sclk_sel",4149 .ops = &clk_regmap_mux_ops,4150 .parent_data = spicc_sclk_parent_data,4151 .num_parents = ARRAY_SIZE(spicc_sclk_parent_data),4152 },4153};4154 4155static struct clk_regmap g12a_spicc1_sclk_div = {4156 .data = &(struct clk_regmap_div_data){4157 .offset = HHI_SPICC_CLK_CNTL,4158 .shift = 16,4159 .width = 6,4160 },4161 .hw.init = &(struct clk_init_data){4162 .name = "spicc1_sclk_div",4163 .ops = &clk_regmap_divider_ops,4164 .parent_hws = (const struct clk_hw *[]) {4165 &g12a_spicc1_sclk_sel.hw4166 },4167 .num_parents = 1,4168 .flags = CLK_SET_RATE_PARENT,4169 },4170};4171 4172static struct clk_regmap g12a_spicc1_sclk = {4173 .data = &(struct clk_regmap_gate_data){4174 .offset = HHI_SPICC_CLK_CNTL,4175 .bit_idx = 22,4176 },4177 .hw.init = &(struct clk_init_data){4178 .name = "spicc1_sclk",4179 .ops = &clk_regmap_gate_ops,4180 .parent_hws = (const struct clk_hw *[]) {4181 &g12a_spicc1_sclk_div.hw4182 },4183 .num_parents = 1,4184 .flags = CLK_SET_RATE_PARENT,4185 },4186};4187 4188/* Neural Network Accelerator source clock */4189 4190static const struct clk_parent_data nna_clk_parent_data[] = {4191 { .fw_name = "xtal", },4192 { .hw = &g12a_gp0_pll.hw, },4193 { .hw = &g12a_hifi_pll.hw, },4194 { .hw = &g12a_fclk_div2p5.hw, },4195 { .hw = &g12a_fclk_div3.hw, },4196 { .hw = &g12a_fclk_div4.hw, },4197 { .hw = &g12a_fclk_div5.hw, },4198 { .hw = &g12a_fclk_div7.hw },4199};4200 4201static struct clk_regmap sm1_nna_axi_clk_sel = {4202 .data = &(struct clk_regmap_mux_data){4203 .offset = HHI_NNA_CLK_CNTL,4204 .mask = 7,4205 .shift = 9,4206 },4207 .hw.init = &(struct clk_init_data){4208 .name = "nna_axi_clk_sel",4209 .ops = &clk_regmap_mux_ops,4210 .parent_data = nna_clk_parent_data,4211 .num_parents = ARRAY_SIZE(nna_clk_parent_data),4212 },4213};4214 4215static struct clk_regmap sm1_nna_axi_clk_div = {4216 .data = &(struct clk_regmap_div_data){4217 .offset = HHI_NNA_CLK_CNTL,4218 .shift = 0,4219 .width = 7,4220 },4221 .hw.init = &(struct clk_init_data){4222 .name = "nna_axi_clk_div",4223 .ops = &clk_regmap_divider_ops,4224 .parent_hws = (const struct clk_hw *[]) {4225 &sm1_nna_axi_clk_sel.hw4226 },4227 .num_parents = 1,4228 .flags = CLK_SET_RATE_PARENT,4229 },4230};4231 4232static struct clk_regmap sm1_nna_axi_clk = {4233 .data = &(struct clk_regmap_gate_data){4234 .offset = HHI_NNA_CLK_CNTL,4235 .bit_idx = 8,4236 },4237 .hw.init = &(struct clk_init_data){4238 .name = "nna_axi_clk",4239 .ops = &clk_regmap_gate_ops,4240 .parent_hws = (const struct clk_hw *[]) {4241 &sm1_nna_axi_clk_div.hw4242 },4243 .num_parents = 1,4244 .flags = CLK_SET_RATE_PARENT,4245 },4246};4247 4248static struct clk_regmap sm1_nna_core_clk_sel = {4249 .data = &(struct clk_regmap_mux_data){4250 .offset = HHI_NNA_CLK_CNTL,4251 .mask = 7,4252 .shift = 25,4253 },4254 .hw.init = &(struct clk_init_data){4255 .name = "nna_core_clk_sel",4256 .ops = &clk_regmap_mux_ops,4257 .parent_data = nna_clk_parent_data,4258 .num_parents = ARRAY_SIZE(nna_clk_parent_data),4259 },4260};4261 4262static struct clk_regmap sm1_nna_core_clk_div = {4263 .data = &(struct clk_regmap_div_data){4264 .offset = HHI_NNA_CLK_CNTL,4265 .shift = 16,4266 .width = 7,4267 },4268 .hw.init = &(struct clk_init_data){4269 .name = "nna_core_clk_div",4270 .ops = &clk_regmap_divider_ops,4271 .parent_hws = (const struct clk_hw *[]) {4272 &sm1_nna_core_clk_sel.hw4273 },4274 .num_parents = 1,4275 .flags = CLK_SET_RATE_PARENT,4276 },4277};4278 4279static struct clk_regmap sm1_nna_core_clk = {4280 .data = &(struct clk_regmap_gate_data){4281 .offset = HHI_NNA_CLK_CNTL,4282 .bit_idx = 24,4283 },4284 .hw.init = &(struct clk_init_data){4285 .name = "nna_core_clk",4286 .ops = &clk_regmap_gate_ops,4287 .parent_hws = (const struct clk_hw *[]) {4288 &sm1_nna_core_clk_div.hw4289 },4290 .num_parents = 1,4291 .flags = CLK_SET_RATE_PARENT,4292 },4293};4294 4295#define MESON_GATE(_name, _reg, _bit) \4296 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)4297 4298#define MESON_GATE_RO(_name, _reg, _bit) \4299 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)4300 4301/* Everything Else (EE) domain gates */4302static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);4303static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);4304static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);4305static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);4306static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);4307static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);4308static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);4309static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);4310static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);4311static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);4312static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);4313static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);4314static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);4315static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);4316static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);4317static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);4318static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);4319static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);4320static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4);4321static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);4322static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);4323static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);4324 4325static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);4326static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);4327static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);4328static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);4329static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);4330static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);4331static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);4332static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);4333static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);4334static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);4335static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);4336static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);4337static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);4338 4339static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);4340static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);4341static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);4342static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);4343static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);4344static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);4345static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17);4346static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);4347static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);4348static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);4349static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28);4350static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29);4351static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);4352 4353static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);4354static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);4355static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);4356static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);4357static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);4358static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);4359static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);4360static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);4361static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);4362static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);4363static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);4364static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);4365static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);4366static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);4367static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);4368static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);4369static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);4370static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);4371static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);4372 4373static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);4374static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);4375static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);4376static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);4377static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);4378 4379/* Array of all clocks provided by this provider */4380static struct clk_hw *g12a_hw_clks[] = {4381 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,4382 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,4383 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,4384 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,4385 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,4386 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,4387 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,4388 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,4389 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,4390 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,4391 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,4392 [CLKID_CLK81] = &g12a_clk81.hw,4393 [CLKID_MPLL0] = &g12a_mpll0.hw,4394 [CLKID_MPLL1] = &g12a_mpll1.hw,4395 [CLKID_MPLL2] = &g12a_mpll2.hw,4396 [CLKID_MPLL3] = &g12a_mpll3.hw,4397 [CLKID_DDR] = &g12a_ddr.hw,4398 [CLKID_DOS] = &g12a_dos.hw,4399 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,4400 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,4401 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,4402 [CLKID_ISA] = &g12a_isa.hw,4403 [CLKID_PL301] = &g12a_pl301.hw,4404 [CLKID_PERIPHS] = &g12a_periphs.hw,4405 [CLKID_SPICC0] = &g12a_spicc_0.hw,4406 [CLKID_I2C] = &g12a_i2c.hw,4407 [CLKID_SANA] = &g12a_sana.hw,4408 [CLKID_SD] = &g12a_sd.hw,4409 [CLKID_RNG0] = &g12a_rng0.hw,4410 [CLKID_UART0] = &g12a_uart0.hw,4411 [CLKID_SPICC1] = &g12a_spicc_1.hw,4412 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,4413 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,4414 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,4415 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,4416 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,4417 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,4418 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,4419 [CLKID_AUDIO] = &g12a_audio.hw,4420 [CLKID_ETH] = &g12a_eth_core.hw,4421 [CLKID_DEMUX] = &g12a_demux.hw,4422 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,4423 [CLKID_ADC] = &g12a_adc.hw,4424 [CLKID_UART1] = &g12a_uart1.hw,4425 [CLKID_G2D] = &g12a_g2d.hw,4426 [CLKID_RESET] = &g12a_reset.hw,4427 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,4428 [CLKID_PARSER] = &g12a_parser.hw,4429 [CLKID_USB] = &g12a_usb_general.hw,4430 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,4431 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,4432 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,4433 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,4434 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,4435 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,4436 [CLKID_BT656] = &g12a_bt656.hw,4437 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,4438 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,4439 [CLKID_UART2] = &g12a_uart2.hw,4440 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,4441 [CLKID_GIC] = &g12a_gic.hw,4442 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,4443 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,4444 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,4445 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,4446 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,4447 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,4448 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,4449 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,4450 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,4451 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,4452 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,4453 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,4454 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,4455 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,4456 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,4457 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,4458 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,4459 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,4460 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,4461 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,4462 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,4463 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,4464 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,4465 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,4466 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,4467 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,4468 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,4469 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,4470 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,4471 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,4472 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,4473 [CLKID_IEC958] = &g12a_iec958_gate.hw,4474 [CLKID_ENC480P] = &g12a_enc480p.hw,4475 [CLKID_RNG1] = &g12a_rng1.hw,4476 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,4477 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,4478 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,4479 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,4480 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,4481 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,4482 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,4483 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,4484 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,4485 [CLKID_DMA] = &g12a_dma.hw,4486 [CLKID_EFUSE] = &g12a_efuse.hw,4487 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,4488 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,4489 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,4490 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,4491 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,4492 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,4493 [CLKID_VPU_0] = &g12a_vpu_0.hw,4494 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,4495 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,4496 [CLKID_VPU_1] = &g12a_vpu_1.hw,4497 [CLKID_VPU] = &g12a_vpu.hw,4498 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,4499 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,4500 [CLKID_VAPB_0] = &g12a_vapb_0.hw,4501 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,4502 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,4503 [CLKID_VAPB_1] = &g12a_vapb_1.hw,4504 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,4505 [CLKID_VAPB] = &g12a_vapb.hw,4506 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,4507 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,4508 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,4509 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,4510 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,4511 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,4512 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,4513 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,4514 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,4515 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,4516 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,4517 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,4518 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,4519 [CLKID_VCLK] = &g12a_vclk.hw,4520 [CLKID_VCLK2] = &g12a_vclk2.hw,4521 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,4522 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,4523 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,4524 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,4525 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,4526 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,4527 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,4528 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,4529 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,4530 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,4531 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,4532 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,4533 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,4534 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,4535 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,4536 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,4537 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,4538 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,4539 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,4540 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,4541 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,4542 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,4543 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,4544 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,4545 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,4546 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,4547 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,4548 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,4549 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,4550 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,4551 [CLKID_HDMI] = &g12a_hdmi.hw,4552 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,4553 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,4554 [CLKID_MALI_0] = &g12a_mali_0.hw,4555 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,4556 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,4557 [CLKID_MALI_1] = &g12a_mali_1.hw,4558 [CLKID_MALI] = &g12a_mali.hw,4559 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,4560 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,4561 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,4562 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,4563 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,4564 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,4565 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,4566 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,4567 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,4568 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,4569 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,4570 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,4571 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,4572 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,4573 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,4574 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,4575 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,4576 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,4577 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,4578 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,4579 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,4580 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,4581 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,4582 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,4583 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,4584 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,4585 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,4586 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,4587 [CLKID_VDEC_1] = &g12a_vdec_1.hw,4588 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,4589 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,4590 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,4591 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,4592 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,4593 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,4594 [CLKID_TS_DIV] = &g12a_ts_div.hw,4595 [CLKID_TS] = &g12a_ts.hw,4596 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,4597 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,4598 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,4599 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,4600 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,4601 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,4602 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,4603 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,4604 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,4605};4606 4607static struct clk_hw *g12b_hw_clks[] = {4608 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,4609 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,4610 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,4611 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,4612 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,4613 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,4614 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,4615 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,4616 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,4617 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,4618 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,4619 [CLKID_CLK81] = &g12a_clk81.hw,4620 [CLKID_MPLL0] = &g12a_mpll0.hw,4621 [CLKID_MPLL1] = &g12a_mpll1.hw,4622 [CLKID_MPLL2] = &g12a_mpll2.hw,4623 [CLKID_MPLL3] = &g12a_mpll3.hw,4624 [CLKID_DDR] = &g12a_ddr.hw,4625 [CLKID_DOS] = &g12a_dos.hw,4626 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,4627 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,4628 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,4629 [CLKID_ISA] = &g12a_isa.hw,4630 [CLKID_PL301] = &g12a_pl301.hw,4631 [CLKID_PERIPHS] = &g12a_periphs.hw,4632 [CLKID_SPICC0] = &g12a_spicc_0.hw,4633 [CLKID_I2C] = &g12a_i2c.hw,4634 [CLKID_SANA] = &g12a_sana.hw,4635 [CLKID_SD] = &g12a_sd.hw,4636 [CLKID_RNG0] = &g12a_rng0.hw,4637 [CLKID_UART0] = &g12a_uart0.hw,4638 [CLKID_SPICC1] = &g12a_spicc_1.hw,4639 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,4640 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,4641 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,4642 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,4643 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,4644 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,4645 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,4646 [CLKID_AUDIO] = &g12a_audio.hw,4647 [CLKID_ETH] = &g12a_eth_core.hw,4648 [CLKID_DEMUX] = &g12a_demux.hw,4649 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,4650 [CLKID_ADC] = &g12a_adc.hw,4651 [CLKID_UART1] = &g12a_uart1.hw,4652 [CLKID_G2D] = &g12a_g2d.hw,4653 [CLKID_RESET] = &g12a_reset.hw,4654 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,4655 [CLKID_PARSER] = &g12a_parser.hw,4656 [CLKID_USB] = &g12a_usb_general.hw,4657 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,4658 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,4659 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,4660 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,4661 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,4662 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,4663 [CLKID_BT656] = &g12a_bt656.hw,4664 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,4665 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,4666 [CLKID_UART2] = &g12a_uart2.hw,4667 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,4668 [CLKID_GIC] = &g12a_gic.hw,4669 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,4670 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,4671 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,4672 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,4673 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,4674 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,4675 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,4676 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,4677 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,4678 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,4679 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,4680 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,4681 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,4682 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,4683 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,4684 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,4685 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,4686 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,4687 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,4688 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,4689 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,4690 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,4691 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,4692 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,4693 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,4694 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,4695 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,4696 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,4697 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,4698 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,4699 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,4700 [CLKID_IEC958] = &g12a_iec958_gate.hw,4701 [CLKID_ENC480P] = &g12a_enc480p.hw,4702 [CLKID_RNG1] = &g12a_rng1.hw,4703 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,4704 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,4705 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,4706 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,4707 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,4708 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,4709 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,4710 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,4711 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,4712 [CLKID_DMA] = &g12a_dma.hw,4713 [CLKID_EFUSE] = &g12a_efuse.hw,4714 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,4715 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,4716 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,4717 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,4718 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,4719 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,4720 [CLKID_VPU_0] = &g12a_vpu_0.hw,4721 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,4722 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,4723 [CLKID_VPU_1] = &g12a_vpu_1.hw,4724 [CLKID_VPU] = &g12a_vpu.hw,4725 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,4726 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,4727 [CLKID_VAPB_0] = &g12a_vapb_0.hw,4728 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,4729 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,4730 [CLKID_VAPB_1] = &g12a_vapb_1.hw,4731 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,4732 [CLKID_VAPB] = &g12a_vapb.hw,4733 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,4734 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,4735 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,4736 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,4737 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,4738 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,4739 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,4740 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,4741 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,4742 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,4743 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,4744 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,4745 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,4746 [CLKID_VCLK] = &g12a_vclk.hw,4747 [CLKID_VCLK2] = &g12a_vclk2.hw,4748 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,4749 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,4750 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,4751 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,4752 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,4753 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,4754 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,4755 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,4756 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,4757 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,4758 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,4759 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,4760 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,4761 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,4762 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,4763 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,4764 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,4765 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,4766 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,4767 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,4768 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,4769 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,4770 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,4771 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,4772 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,4773 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,4774 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,4775 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,4776 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,4777 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,4778 [CLKID_HDMI] = &g12a_hdmi.hw,4779 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,4780 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,4781 [CLKID_MALI_0] = &g12a_mali_0.hw,4782 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,4783 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,4784 [CLKID_MALI_1] = &g12a_mali_1.hw,4785 [CLKID_MALI] = &g12a_mali.hw,4786 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,4787 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,4788 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,4789 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,4790 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,4791 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,4792 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,4793 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,4794 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,4795 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,4796 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,4797 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,4798 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,4799 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,4800 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,4801 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,4802 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,4803 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,4804 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,4805 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,4806 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,4807 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,4808 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,4809 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,4810 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,4811 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,4812 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,4813 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,4814 [CLKID_VDEC_1] = &g12a_vdec_1.hw,4815 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,4816 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,4817 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,4818 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,4819 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,4820 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,4821 [CLKID_TS_DIV] = &g12a_ts_div.hw,4822 [CLKID_TS] = &g12a_ts.hw,4823 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,4824 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,4825 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,4826 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,4827 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,4828 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,4829 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,4830 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,4831 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,4832 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,4833 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,4834 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,4835 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,4836 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,4837 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,4838 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,4839 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,4840 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,4841 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,4842 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,4843 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,4844 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,4845 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,4846 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,4847 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,4848 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,4849 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,4850 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,4851 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,4852 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,4853 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,4854 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,4855 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,4856 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,4857 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,4858 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,4859 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,4860 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,4861 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,4862 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,4863 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,4864 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,4865 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,4866 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,4867 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,4868 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,4869 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,4870 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,4871 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,4872 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,4873};4874 4875static struct clk_hw *sm1_hw_clks[] = {4876 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,4877 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,4878 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,4879 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,4880 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,4881 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,4882 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,4883 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,4884 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,4885 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,4886 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,4887 [CLKID_CLK81] = &g12a_clk81.hw,4888 [CLKID_MPLL0] = &g12a_mpll0.hw,4889 [CLKID_MPLL1] = &g12a_mpll1.hw,4890 [CLKID_MPLL2] = &g12a_mpll2.hw,4891 [CLKID_MPLL3] = &g12a_mpll3.hw,4892 [CLKID_DDR] = &g12a_ddr.hw,4893 [CLKID_DOS] = &g12a_dos.hw,4894 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,4895 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,4896 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,4897 [CLKID_ISA] = &g12a_isa.hw,4898 [CLKID_PL301] = &g12a_pl301.hw,4899 [CLKID_PERIPHS] = &g12a_periphs.hw,4900 [CLKID_SPICC0] = &g12a_spicc_0.hw,4901 [CLKID_I2C] = &g12a_i2c.hw,4902 [CLKID_SANA] = &g12a_sana.hw,4903 [CLKID_SD] = &g12a_sd.hw,4904 [CLKID_RNG0] = &g12a_rng0.hw,4905 [CLKID_UART0] = &g12a_uart0.hw,4906 [CLKID_SPICC1] = &g12a_spicc_1.hw,4907 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,4908 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,4909 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,4910 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,4911 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,4912 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,4913 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,4914 [CLKID_AUDIO] = &g12a_audio.hw,4915 [CLKID_ETH] = &g12a_eth_core.hw,4916 [CLKID_DEMUX] = &g12a_demux.hw,4917 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,4918 [CLKID_ADC] = &g12a_adc.hw,4919 [CLKID_UART1] = &g12a_uart1.hw,4920 [CLKID_G2D] = &g12a_g2d.hw,4921 [CLKID_RESET] = &g12a_reset.hw,4922 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,4923 [CLKID_PARSER] = &g12a_parser.hw,4924 [CLKID_USB] = &g12a_usb_general.hw,4925 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,4926 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,4927 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,4928 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,4929 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,4930 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,4931 [CLKID_BT656] = &g12a_bt656.hw,4932 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,4933 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,4934 [CLKID_UART2] = &g12a_uart2.hw,4935 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,4936 [CLKID_GIC] = &g12a_gic.hw,4937 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,4938 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,4939 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,4940 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,4941 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,4942 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,4943 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,4944 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,4945 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,4946 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,4947 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,4948 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,4949 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,4950 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,4951 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,4952 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,4953 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,4954 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,4955 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,4956 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,4957 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,4958 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,4959 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,4960 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,4961 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,4962 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,4963 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,4964 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,4965 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,4966 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,4967 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,4968 [CLKID_IEC958] = &g12a_iec958_gate.hw,4969 [CLKID_ENC480P] = &g12a_enc480p.hw,4970 [CLKID_RNG1] = &g12a_rng1.hw,4971 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,4972 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,4973 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,4974 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,4975 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,4976 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,4977 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,4978 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,4979 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,4980 [CLKID_DMA] = &g12a_dma.hw,4981 [CLKID_EFUSE] = &g12a_efuse.hw,4982 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,4983 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,4984 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,4985 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,4986 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,4987 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,4988 [CLKID_VPU_0] = &g12a_vpu_0.hw,4989 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,4990 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,4991 [CLKID_VPU_1] = &g12a_vpu_1.hw,4992 [CLKID_VPU] = &g12a_vpu.hw,4993 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,4994 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,4995 [CLKID_VAPB_0] = &g12a_vapb_0.hw,4996 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,4997 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,4998 [CLKID_VAPB_1] = &g12a_vapb_1.hw,4999 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,5000 [CLKID_VAPB] = &g12a_vapb.hw,5001 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,5002 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,5003 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,5004 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,5005 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,5006 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,5007 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,5008 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,5009 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,5010 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,5011 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,5012 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,5013 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,5014 [CLKID_VCLK] = &g12a_vclk.hw,5015 [CLKID_VCLK2] = &g12a_vclk2.hw,5016 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,5017 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,5018 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,5019 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,5020 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,5021 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,5022 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,5023 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,5024 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,5025 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,5026 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,5027 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,5028 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,5029 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,5030 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,5031 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,5032 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,5033 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,5034 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,5035 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,5036 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,5037 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,5038 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,5039 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,5040 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,5041 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,5042 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,5043 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,5044 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,5045 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,5046 [CLKID_HDMI] = &g12a_hdmi.hw,5047 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,5048 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,5049 [CLKID_MALI_0] = &g12a_mali_0.hw,5050 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,5051 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,5052 [CLKID_MALI_1] = &g12a_mali_1.hw,5053 [CLKID_MALI] = &g12a_mali.hw,5054 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,5055 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,5056 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,5057 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,5058 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,5059 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,5060 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,5061 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,5062 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,5063 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,5064 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,5065 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,5066 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,5067 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,5068 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,5069 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,5070 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,5071 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,5072 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,5073 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,5074 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,5075 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,5076 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,5077 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,5078 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,5079 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,5080 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,5081 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,5082 [CLKID_VDEC_1] = &g12a_vdec_1.hw,5083 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,5084 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,5085 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,5086 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,5087 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,5088 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,5089 [CLKID_TS_DIV] = &g12a_ts_div.hw,5090 [CLKID_TS] = &g12a_ts.hw,5091 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,5092 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,5093 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,5094 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,5095 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,5096 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,5097 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,5098 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,5099 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,5100 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,5101 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,5102 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,5103 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,5104 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,5105 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,5106 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,5107 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,5108 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,5109 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,5110 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,5111 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,5112 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,5113 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,5114 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,5115 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,5116 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,5117 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,5118 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,5119 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,5120};5121 5122/* Convenience table to populate regmap in .probe */5123static struct clk_regmap *const g12a_clk_regmaps[] = {5124 &g12a_clk81,5125 &g12a_dos,5126 &g12a_ddr,5127 &g12a_audio_locker,5128 &g12a_mipi_dsi_host,5129 &g12a_eth_phy,5130 &g12a_isa,5131 &g12a_pl301,5132 &g12a_periphs,5133 &g12a_spicc_0,5134 &g12a_i2c,5135 &g12a_sana,5136 &g12a_sd,5137 &g12a_rng0,5138 &g12a_uart0,5139 &g12a_spicc_1,5140 &g12a_hiu_reg,5141 &g12a_mipi_dsi_phy,5142 &g12a_assist_misc,5143 &g12a_emmc_a,5144 &g12a_emmc_b,5145 &g12a_emmc_c,5146 &g12a_audio_codec,5147 &g12a_audio,5148 &g12a_eth_core,5149 &g12a_demux,5150 &g12a_audio_ififo,5151 &g12a_adc,5152 &g12a_uart1,5153 &g12a_g2d,5154 &g12a_reset,5155 &g12a_pcie_comb,5156 &g12a_parser,5157 &g12a_usb_general,5158 &g12a_pcie_phy,5159 &g12a_ahb_arb0,5160 &g12a_ahb_data_bus,5161 &g12a_ahb_ctrl_bus,5162 &g12a_htx_hdcp22,5163 &g12a_htx_pclk,5164 &g12a_bt656,5165 &g12a_usb1_to_ddr,5166 &g12a_mmc_pclk,5167 &g12a_uart2,5168 &g12a_vpu_intr,5169 &g12a_gic,5170 &g12a_sd_emmc_a_clk0,5171 &g12a_sd_emmc_b_clk0,5172 &g12a_sd_emmc_c_clk0,5173 &g12a_mpeg_clk_div,5174 &g12a_sd_emmc_a_clk0_div,5175 &g12a_sd_emmc_b_clk0_div,5176 &g12a_sd_emmc_c_clk0_div,5177 &g12a_mpeg_clk_sel,5178 &g12a_sd_emmc_a_clk0_sel,5179 &g12a_sd_emmc_b_clk0_sel,5180 &g12a_sd_emmc_c_clk0_sel,5181 &g12a_mpll0,5182 &g12a_mpll1,5183 &g12a_mpll2,5184 &g12a_mpll3,5185 &g12a_mpll0_div,5186 &g12a_mpll1_div,5187 &g12a_mpll2_div,5188 &g12a_mpll3_div,5189 &g12a_fixed_pll,5190 &g12a_sys_pll,5191 &g12a_gp0_pll,5192 &g12a_hifi_pll,5193 &g12a_vclk2_venci0,5194 &g12a_vclk2_venci1,5195 &g12a_vclk2_vencp0,5196 &g12a_vclk2_vencp1,5197 &g12a_vclk2_venct0,5198 &g12a_vclk2_venct1,5199 &g12a_vclk2_other,5200 &g12a_vclk2_enci,5201 &g12a_vclk2_encp,5202 &g12a_dac_clk,5203 &g12a_aoclk_gate,5204 &g12a_iec958_gate,5205 &g12a_enc480p,5206 &g12a_rng1,5207 &g12a_vclk2_enct,5208 &g12a_vclk2_encl,5209 &g12a_vclk2_venclmmc,5210 &g12a_vclk2_vencl,5211 &g12a_vclk2_other1,5212 &g12a_fixed_pll_dco,5213 &g12a_sys_pll_dco,5214 &g12a_gp0_pll_dco,5215 &g12a_hifi_pll_dco,5216 &g12a_fclk_div2,5217 &g12a_fclk_div3,5218 &g12a_fclk_div4,5219 &g12a_fclk_div5,5220 &g12a_fclk_div7,5221 &g12a_fclk_div2p5,5222 &g12a_dma,5223 &g12a_efuse,5224 &g12a_rom_boot,5225 &g12a_reset_sec,5226 &g12a_sec_ahb_apb3,5227 &g12a_vpu_0_sel,5228 &g12a_vpu_0_div,5229 &g12a_vpu_0,5230 &g12a_vpu_1_sel,5231 &g12a_vpu_1_div,5232 &g12a_vpu_1,5233 &g12a_vpu,5234 &g12a_vapb_0_sel,5235 &g12a_vapb_0_div,5236 &g12a_vapb_0,5237 &g12a_vapb_1_sel,5238 &g12a_vapb_1_div,5239 &g12a_vapb_1,5240 &g12a_vapb_sel,5241 &g12a_vapb,5242 &g12a_hdmi_pll_dco,5243 &g12a_hdmi_pll_od,5244 &g12a_hdmi_pll_od2,5245 &g12a_hdmi_pll,5246 &g12a_vid_pll_div,5247 &g12a_vid_pll_sel,5248 &g12a_vid_pll,5249 &g12a_vclk_sel,5250 &g12a_vclk2_sel,5251 &g12a_vclk_input,5252 &g12a_vclk2_input,5253 &g12a_vclk_div,5254 &g12a_vclk2_div,5255 &g12a_vclk,5256 &g12a_vclk2,5257 &g12a_vclk_div1,5258 &g12a_vclk_div2_en,5259 &g12a_vclk_div4_en,5260 &g12a_vclk_div6_en,5261 &g12a_vclk_div12_en,5262 &g12a_vclk2_div1,5263 &g12a_vclk2_div2_en,5264 &g12a_vclk2_div4_en,5265 &g12a_vclk2_div6_en,5266 &g12a_vclk2_div12_en,5267 &g12a_cts_enci_sel,5268 &g12a_cts_encp_sel,5269 &g12a_cts_encl_sel,5270 &g12a_cts_vdac_sel,5271 &g12a_hdmi_tx_sel,5272 &g12a_cts_enci,5273 &g12a_cts_encp,5274 &g12a_cts_encl,5275 &g12a_cts_vdac,5276 &g12a_hdmi_tx,5277 &g12a_hdmi_sel,5278 &g12a_hdmi_div,5279 &g12a_hdmi,5280 &g12a_mali_0_sel,5281 &g12a_mali_0_div,5282 &g12a_mali_0,5283 &g12a_mali_1_sel,5284 &g12a_mali_1_div,5285 &g12a_mali_1,5286 &g12a_mali,5287 &g12a_mpll_50m,5288 &g12a_sys_pll_div16_en,5289 &g12a_cpu_clk_premux0,5290 &g12a_cpu_clk_mux0_div,5291 &g12a_cpu_clk_postmux0,5292 &g12a_cpu_clk_premux1,5293 &g12a_cpu_clk_mux1_div,5294 &g12a_cpu_clk_postmux1,5295 &g12a_cpu_clk_dyn,5296 &g12a_cpu_clk,5297 &g12a_cpu_clk_div16_en,5298 &g12a_cpu_clk_apb_div,5299 &g12a_cpu_clk_apb,5300 &g12a_cpu_clk_atb_div,5301 &g12a_cpu_clk_atb,5302 &g12a_cpu_clk_axi_div,5303 &g12a_cpu_clk_axi,5304 &g12a_cpu_clk_trace_div,5305 &g12a_cpu_clk_trace,5306 &g12a_pcie_pll_od,5307 &g12a_pcie_pll_dco,5308 &g12a_vdec_1_sel,5309 &g12a_vdec_1_div,5310 &g12a_vdec_1,5311 &g12a_vdec_hevc_sel,5312 &g12a_vdec_hevc_div,5313 &g12a_vdec_hevc,5314 &g12a_vdec_hevcf_sel,5315 &g12a_vdec_hevcf_div,5316 &g12a_vdec_hevcf,5317 &g12a_ts_div,5318 &g12a_ts,5319 &g12b_cpu_clk,5320 &g12b_sys1_pll_dco,5321 &g12b_sys1_pll,5322 &g12b_sys1_pll_div16_en,5323 &g12b_cpub_clk_premux0,5324 &g12b_cpub_clk_mux0_div,5325 &g12b_cpub_clk_postmux0,5326 &g12b_cpub_clk_premux1,5327 &g12b_cpub_clk_mux1_div,5328 &g12b_cpub_clk_postmux1,5329 &g12b_cpub_clk_dyn,5330 &g12b_cpub_clk,5331 &g12b_cpub_clk_div16_en,5332 &g12b_cpub_clk_apb_sel,5333 &g12b_cpub_clk_apb,5334 &g12b_cpub_clk_atb_sel,5335 &g12b_cpub_clk_atb,5336 &g12b_cpub_clk_axi_sel,5337 &g12b_cpub_clk_axi,5338 &g12b_cpub_clk_trace_sel,5339 &g12b_cpub_clk_trace,5340 &sm1_gp1_pll_dco,5341 &sm1_gp1_pll,5342 &sm1_dsu_clk_premux0,5343 &sm1_dsu_clk_premux1,5344 &sm1_dsu_clk_mux0_div,5345 &sm1_dsu_clk_postmux0,5346 &sm1_dsu_clk_mux1_div,5347 &sm1_dsu_clk_postmux1,5348 &sm1_dsu_clk_dyn,5349 &sm1_dsu_final_clk,5350 &sm1_dsu_clk,5351 &sm1_cpu1_clk,5352 &sm1_cpu2_clk,5353 &sm1_cpu3_clk,5354 &g12a_spicc0_sclk_sel,5355 &g12a_spicc0_sclk_div,5356 &g12a_spicc0_sclk,5357 &g12a_spicc1_sclk_sel,5358 &g12a_spicc1_sclk_div,5359 &g12a_spicc1_sclk,5360 &sm1_nna_axi_clk_sel,5361 &sm1_nna_axi_clk_div,5362 &sm1_nna_axi_clk,5363 &sm1_nna_core_clk_sel,5364 &sm1_nna_core_clk_div,5365 &sm1_nna_core_clk,5366 &g12a_mipi_dsi_pxclk_sel,5367 &g12a_mipi_dsi_pxclk_div,5368 &g12a_mipi_dsi_pxclk,5369 &g12b_mipi_isp_sel,5370 &g12b_mipi_isp_div,5371 &g12b_mipi_isp,5372 &g12b_mipi_isp_gate,5373 &g12b_csi_phy1,5374 &g12b_csi_phy0,5375};5376 5377static const struct reg_sequence g12a_init_regs[] = {5378 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },5379};5380 5381#define DVFS_CON_ID "dvfs"5382 5383static int meson_g12a_dvfs_setup_common(struct device *dev,5384 struct clk_hw **hws)5385{5386 struct clk *notifier_clk;5387 struct clk_hw *xtal;5388 int ret;5389 5390 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);5391 5392 /* Setup clock notifier for cpu_clk_postmux0 */5393 g12a_cpu_clk_postmux0_nb_data.xtal = xtal;5394 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,5395 DVFS_CON_ID);5396 ret = devm_clk_notifier_register(dev, notifier_clk,5397 &g12a_cpu_clk_postmux0_nb_data.nb);5398 if (ret) {5399 dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");5400 return ret;5401 }5402 5403 /* Setup clock notifier for cpu_clk_dyn mux */5404 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,5405 DVFS_CON_ID);5406 ret = devm_clk_notifier_register(dev, notifier_clk,5407 &g12a_cpu_clk_mux_nb);5408 if (ret) {5409 dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");5410 return ret;5411 }5412 5413 return 0;5414}5415 5416static int meson_g12b_dvfs_setup(struct platform_device *pdev)5417{5418 struct clk_hw **hws = g12b_hw_clks;5419 struct device *dev = &pdev->dev;5420 struct clk *notifier_clk;5421 struct clk_hw *xtal;5422 int ret;5423 5424 ret = meson_g12a_dvfs_setup_common(dev, hws);5425 if (ret)5426 return ret;5427 5428 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);5429 5430 /* Setup clock notifier for cpu_clk mux */5431 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,5432 DVFS_CON_ID);5433 ret = devm_clk_notifier_register(dev, notifier_clk,5434 &g12a_cpu_clk_mux_nb);5435 if (ret) {5436 dev_err(dev, "failed to register the cpu_clk notifier\n");5437 return ret;5438 }5439 5440 /* Setup clock notifier for sys1_pll */5441 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,5442 DVFS_CON_ID);5443 ret = devm_clk_notifier_register(dev, notifier_clk,5444 &g12b_cpu_clk_sys1_pll_nb_data.nb);5445 if (ret) {5446 dev_err(dev, "failed to register the sys1_pll notifier\n");5447 return ret;5448 }5449 5450 /* Add notifiers for the second CPU cluster */5451 5452 /* Setup clock notifier for cpub_clk_postmux0 */5453 g12b_cpub_clk_postmux0_nb_data.xtal = xtal;5454 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,5455 DVFS_CON_ID);5456 ret = devm_clk_notifier_register(dev, notifier_clk,5457 &g12b_cpub_clk_postmux0_nb_data.nb);5458 if (ret) {5459 dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");5460 return ret;5461 }5462 5463 /* Setup clock notifier for cpub_clk_dyn mux */5464 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");5465 ret = devm_clk_notifier_register(dev, notifier_clk,5466 &g12a_cpu_clk_mux_nb);5467 if (ret) {5468 dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");5469 return ret;5470 }5471 5472 /* Setup clock notifier for cpub_clk mux */5473 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);5474 ret = devm_clk_notifier_register(dev, notifier_clk,5475 &g12a_cpu_clk_mux_nb);5476 if (ret) {5477 dev_err(dev, "failed to register the cpub_clk notifier\n");5478 return ret;5479 }5480 5481 /* Setup clock notifier for sys_pll */5482 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);5483 ret = devm_clk_notifier_register(dev, notifier_clk,5484 &g12b_cpub_clk_sys_pll_nb_data.nb);5485 if (ret) {5486 dev_err(dev, "failed to register the sys_pll notifier\n");5487 return ret;5488 }5489 5490 return 0;5491}5492 5493static int meson_g12a_dvfs_setup(struct platform_device *pdev)5494{5495 struct clk_hw **hws = g12a_hw_clks;5496 struct device *dev = &pdev->dev;5497 struct clk *notifier_clk;5498 int ret;5499 5500 ret = meson_g12a_dvfs_setup_common(dev, hws);5501 if (ret)5502 return ret;5503 5504 /* Setup clock notifier for cpu_clk mux */5505 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);5506 ret = devm_clk_notifier_register(dev, notifier_clk,5507 &g12a_cpu_clk_mux_nb);5508 if (ret) {5509 dev_err(dev, "failed to register the cpu_clk notifier\n");5510 return ret;5511 }5512 5513 /* Setup clock notifier for sys_pll */5514 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);5515 ret = devm_clk_notifier_register(dev, notifier_clk,5516 &g12a_sys_pll_nb_data.nb);5517 if (ret) {5518 dev_err(dev, "failed to register the sys_pll notifier\n");5519 return ret;5520 }5521 5522 return 0;5523}5524 5525struct meson_g12a_data {5526 const struct meson_eeclkc_data eeclkc_data;5527 int (*dvfs_setup)(struct platform_device *pdev);5528};5529 5530static int meson_g12a_probe(struct platform_device *pdev)5531{5532 const struct meson_eeclkc_data *eeclkc_data;5533 const struct meson_g12a_data *g12a_data;5534 int ret;5535 5536 eeclkc_data = of_device_get_match_data(&pdev->dev);5537 if (!eeclkc_data)5538 return -EINVAL;5539 5540 ret = meson_eeclkc_probe(pdev);5541 if (ret)5542 return ret;5543 5544 g12a_data = container_of(eeclkc_data, struct meson_g12a_data,5545 eeclkc_data);5546 5547 if (g12a_data->dvfs_setup)5548 return g12a_data->dvfs_setup(pdev);5549 5550 return 0;5551}5552 5553static const struct meson_g12a_data g12a_clkc_data = {5554 .eeclkc_data = {5555 .regmap_clks = g12a_clk_regmaps,5556 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),5557 .hw_clks = {5558 .hws = g12a_hw_clks,5559 .num = ARRAY_SIZE(g12a_hw_clks),5560 },5561 .init_regs = g12a_init_regs,5562 .init_count = ARRAY_SIZE(g12a_init_regs),5563 },5564 .dvfs_setup = meson_g12a_dvfs_setup,5565};5566 5567static const struct meson_g12a_data g12b_clkc_data = {5568 .eeclkc_data = {5569 .regmap_clks = g12a_clk_regmaps,5570 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),5571 .hw_clks = {5572 .hws = g12b_hw_clks,5573 .num = ARRAY_SIZE(g12b_hw_clks),5574 },5575 },5576 .dvfs_setup = meson_g12b_dvfs_setup,5577};5578 5579static const struct meson_g12a_data sm1_clkc_data = {5580 .eeclkc_data = {5581 .regmap_clks = g12a_clk_regmaps,5582 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),5583 .hw_clks = {5584 .hws = sm1_hw_clks,5585 .num = ARRAY_SIZE(sm1_hw_clks),5586 },5587 },5588 .dvfs_setup = meson_g12a_dvfs_setup,5589};5590 5591static const struct of_device_id clkc_match_table[] = {5592 {5593 .compatible = "amlogic,g12a-clkc",5594 .data = &g12a_clkc_data.eeclkc_data5595 },5596 {5597 .compatible = "amlogic,g12b-clkc",5598 .data = &g12b_clkc_data.eeclkc_data5599 },5600 {5601 .compatible = "amlogic,sm1-clkc",5602 .data = &sm1_clkc_data.eeclkc_data5603 },5604 {}5605};5606MODULE_DEVICE_TABLE(of, clkc_match_table);5607 5608static struct platform_driver g12a_driver = {5609 .probe = meson_g12a_probe,5610 .driver = {5611 .name = "g12a-clkc",5612 .of_match_table = clkc_match_table,5613 },5614};5615module_platform_driver(g12a_driver);5616 5617MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver");5618MODULE_LICENSE("GPL");5619MODULE_IMPORT_NS(CLK_MESON);5620