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1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */2/*3 * Copyright (c) 2016 Amlogic, Inc.4 * Author: Michael Turquette <mturquette@baylibre.com>5 *6 * Copyright (c) 2018 Amlogic, inc.7 * Author: Qiufang Dai <qiufang.dai@amlogic.com>8 * Author: Jian Hu <jian.hu@amlogic.com>9 *10 */11#ifndef __G12A_H12#define __G12A_H13 14/*15 * Clock controller register offsets16 *17 * Register offsets from the data sheet must be multiplied by 4 before18 * adding them to the base address to get the right value.19 */20#define HHI_MIPI_CNTL0 0x00021#define HHI_MIPI_CNTL1 0x00422#define HHI_MIPI_CNTL2 0x00823#define HHI_MIPI_STS 0x00C24#define HHI_GP0_PLL_CNTL0 0x04025#define HHI_GP0_PLL_CNTL1 0x04426#define HHI_GP0_PLL_CNTL2 0x04827#define HHI_GP0_PLL_CNTL3 0x04C28#define HHI_GP0_PLL_CNTL4 0x05029#define HHI_GP0_PLL_CNTL5 0x05430#define HHI_GP0_PLL_CNTL6 0x05831#define HHI_GP0_PLL_STS 0x05C32#define HHI_GP1_PLL_CNTL0 0x06033#define HHI_GP1_PLL_CNTL1 0x06434#define HHI_GP1_PLL_CNTL2 0x06835#define HHI_GP1_PLL_CNTL3 0x06C36#define HHI_GP1_PLL_CNTL4 0x07037#define HHI_GP1_PLL_CNTL5 0x07438#define HHI_GP1_PLL_CNTL6 0x07839#define HHI_GP1_PLL_STS 0x07C40#define HHI_PCIE_PLL_CNTL0 0x09841#define HHI_PCIE_PLL_CNTL1 0x09C42#define HHI_PCIE_PLL_CNTL2 0x0A043#define HHI_PCIE_PLL_CNTL3 0x0A444#define HHI_PCIE_PLL_CNTL4 0x0A845#define HHI_PCIE_PLL_CNTL5 0x0AC46#define HHI_PCIE_PLL_STS 0x0B847#define HHI_HIFI_PLL_CNTL0 0x0D848#define HHI_HIFI_PLL_CNTL1 0x0DC49#define HHI_HIFI_PLL_CNTL2 0x0E050#define HHI_HIFI_PLL_CNTL3 0x0E451#define HHI_HIFI_PLL_CNTL4 0x0E852#define HHI_HIFI_PLL_CNTL5 0x0EC53#define HHI_HIFI_PLL_CNTL6 0x0F054#define HHI_VIID_CLK_DIV 0x12855#define HHI_VIID_CLK_CNTL 0x12C56#define HHI_GCLK_MPEG0 0x14057#define HHI_GCLK_MPEG1 0x14458#define HHI_GCLK_MPEG2 0x14859#define HHI_GCLK_OTHER 0x15060#define HHI_GCLK_OTHER2 0x15461#define HHI_SYS_CPU_CLK_CNTL1 0x15c62#define HHI_VID_CLK_DIV 0x16463#define HHI_MPEG_CLK_CNTL 0x17464#define HHI_AUD_CLK_CNTL 0x17865#define HHI_VID_CLK_CNTL 0x17c66#define HHI_TS_CLK_CNTL 0x19067#define HHI_VID_CLK_CNTL2 0x19468#define HHI_SYS_CPU_CLK_CNTL0 0x19c69#define HHI_VID_PLL_CLK_DIV 0x1A070#define HHI_MALI_CLK_CNTL 0x1b071#define HHI_VPU_CLKC_CNTL 0x1b472#define HHI_VPU_CLK_CNTL 0x1bC73#define HHI_ISP_CLK_CNTL 0x1C074#define HHI_NNA_CLK_CNTL 0x1C875#define HHI_HDMI_CLK_CNTL 0x1CC76#define HHI_VDEC_CLK_CNTL 0x1E077#define HHI_VDEC2_CLK_CNTL 0x1E478#define HHI_VDEC3_CLK_CNTL 0x1E879#define HHI_VDEC4_CLK_CNTL 0x1EC80#define HHI_HDCP22_CLK_CNTL 0x1F081#define HHI_VAPBCLK_CNTL 0x1F482#define HHI_SYS_CPUB_CLK_CNTL1 0x20083#define HHI_SYS_CPUB_CLK_CNTL 0x20884#define HHI_VPU_CLKB_CNTL 0x20C85#define HHI_SYS_CPU_CLK_CNTL2 0x21086#define HHI_SYS_CPU_CLK_CNTL3 0x21487#define HHI_SYS_CPU_CLK_CNTL4 0x21888#define HHI_SYS_CPU_CLK_CNTL5 0x21c89#define HHI_SYS_CPU_CLK_CNTL6 0x22090#define HHI_GEN_CLK_CNTL 0x22891#define HHI_VDIN_MEAS_CLK_CNTL 0x25092#define HHI_MIPIDSI_PHY_CLK_CNTL 0x25493#define HHI_NAND_CLK_CNTL 0x25C94#define HHI_SD_EMMC_CLK_CNTL 0x26495#define HHI_MPLL_CNTL0 0x27896#define HHI_MPLL_CNTL1 0x27C97#define HHI_MPLL_CNTL2 0x28098#define HHI_MPLL_CNTL3 0x28499#define HHI_MPLL_CNTL4 0x288100#define HHI_MPLL_CNTL5 0x28c101#define HHI_MPLL_CNTL6 0x290102#define HHI_MPLL_CNTL7 0x294103#define HHI_MPLL_CNTL8 0x298104#define HHI_FIX_PLL_CNTL0 0x2A0105#define HHI_FIX_PLL_CNTL1 0x2A4106#define HHI_FIX_PLL_CNTL3 0x2AC107#define HHI_SYS_PLL_CNTL0 0x2f4108#define HHI_SYS_PLL_CNTL1 0x2f8109#define HHI_SYS_PLL_CNTL2 0x2fc110#define HHI_SYS_PLL_CNTL3 0x300111#define HHI_SYS_PLL_CNTL4 0x304112#define HHI_SYS_PLL_CNTL5 0x308113#define HHI_SYS_PLL_CNTL6 0x30c114#define HHI_HDMI_PLL_CNTL0 0x320115#define HHI_HDMI_PLL_CNTL1 0x324116#define HHI_HDMI_PLL_CNTL2 0x328117#define HHI_HDMI_PLL_CNTL3 0x32c118#define HHI_HDMI_PLL_CNTL4 0x330119#define HHI_HDMI_PLL_CNTL5 0x334120#define HHI_HDMI_PLL_CNTL6 0x338121#define HHI_SPICC_CLK_CNTL 0x3dc122#define HHI_SYS1_PLL_CNTL0 0x380123#define HHI_SYS1_PLL_CNTL1 0x384124#define HHI_SYS1_PLL_CNTL2 0x388125#define HHI_SYS1_PLL_CNTL3 0x38c126#define HHI_SYS1_PLL_CNTL4 0x390127#define HHI_SYS1_PLL_CNTL5 0x394128#define HHI_SYS1_PLL_CNTL6 0x398129 130#endif /* __G12A_H */131