3575 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2016 AmLogic, Inc.4 * Michael Turquette <mturquette@baylibre.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/init.h>9#include <linux/mod_devicetable.h>10#include <linux/platform_device.h>11#include <linux/module.h>12 13#include "gxbb.h"14#include "clk-regmap.h"15#include "clk-pll.h"16#include "clk-mpll.h"17#include "meson-eeclk.h"18#include "vid-pll-div.h"19 20#include <dt-bindings/clock/gxbb-clkc.h>21 22static DEFINE_SPINLOCK(meson_clk_lock);23 24static const struct pll_params_table gxbb_gp0_pll_params_table[] = {25 PLL_PARAMS(32, 1),26 PLL_PARAMS(33, 1),27 PLL_PARAMS(34, 1),28 PLL_PARAMS(35, 1),29 PLL_PARAMS(36, 1),30 PLL_PARAMS(37, 1),31 PLL_PARAMS(38, 1),32 PLL_PARAMS(39, 1),33 PLL_PARAMS(40, 1),34 PLL_PARAMS(41, 1),35 PLL_PARAMS(42, 1),36 PLL_PARAMS(43, 1),37 PLL_PARAMS(44, 1),38 PLL_PARAMS(45, 1),39 PLL_PARAMS(46, 1),40 PLL_PARAMS(47, 1),41 PLL_PARAMS(48, 1),42 PLL_PARAMS(49, 1),43 PLL_PARAMS(50, 1),44 PLL_PARAMS(51, 1),45 PLL_PARAMS(52, 1),46 PLL_PARAMS(53, 1),47 PLL_PARAMS(54, 1),48 PLL_PARAMS(55, 1),49 PLL_PARAMS(56, 1),50 PLL_PARAMS(57, 1),51 PLL_PARAMS(58, 1),52 PLL_PARAMS(59, 1),53 PLL_PARAMS(60, 1),54 PLL_PARAMS(61, 1),55 PLL_PARAMS(62, 1),56 { /* sentinel */ },57};58 59static const struct pll_params_table gxl_gp0_pll_params_table[] = {60 PLL_PARAMS(42, 1),61 PLL_PARAMS(43, 1),62 PLL_PARAMS(44, 1),63 PLL_PARAMS(45, 1),64 PLL_PARAMS(46, 1),65 PLL_PARAMS(47, 1),66 PLL_PARAMS(48, 1),67 PLL_PARAMS(49, 1),68 PLL_PARAMS(50, 1),69 PLL_PARAMS(51, 1),70 PLL_PARAMS(52, 1),71 PLL_PARAMS(53, 1),72 PLL_PARAMS(54, 1),73 PLL_PARAMS(55, 1),74 PLL_PARAMS(56, 1),75 PLL_PARAMS(57, 1),76 PLL_PARAMS(58, 1),77 PLL_PARAMS(59, 1),78 PLL_PARAMS(60, 1),79 PLL_PARAMS(61, 1),80 PLL_PARAMS(62, 1),81 PLL_PARAMS(63, 1),82 PLL_PARAMS(64, 1),83 PLL_PARAMS(65, 1),84 PLL_PARAMS(66, 1),85 { /* sentinel */ },86};87 88static struct clk_regmap gxbb_fixed_pll_dco = {89 .data = &(struct meson_clk_pll_data){90 .en = {91 .reg_off = HHI_MPLL_CNTL,92 .shift = 30,93 .width = 1,94 },95 .m = {96 .reg_off = HHI_MPLL_CNTL,97 .shift = 0,98 .width = 9,99 },100 .n = {101 .reg_off = HHI_MPLL_CNTL,102 .shift = 9,103 .width = 5,104 },105 .frac = {106 .reg_off = HHI_MPLL_CNTL2,107 .shift = 0,108 .width = 12,109 },110 .l = {111 .reg_off = HHI_MPLL_CNTL,112 .shift = 31,113 .width = 1,114 },115 .rst = {116 .reg_off = HHI_MPLL_CNTL,117 .shift = 29,118 .width = 1,119 },120 },121 .hw.init = &(struct clk_init_data){122 .name = "fixed_pll_dco",123 .ops = &meson_clk_pll_ro_ops,124 .parent_data = &(const struct clk_parent_data) {125 .fw_name = "xtal",126 },127 .num_parents = 1,128 },129};130 131static struct clk_regmap gxbb_fixed_pll = {132 .data = &(struct clk_regmap_div_data){133 .offset = HHI_MPLL_CNTL,134 .shift = 16,135 .width = 2,136 .flags = CLK_DIVIDER_POWER_OF_TWO,137 },138 .hw.init = &(struct clk_init_data){139 .name = "fixed_pll",140 .ops = &clk_regmap_divider_ro_ops,141 .parent_hws = (const struct clk_hw *[]) {142 &gxbb_fixed_pll_dco.hw143 },144 .num_parents = 1,145 /*146 * This clock won't ever change at runtime so147 * CLK_SET_RATE_PARENT is not required148 */149 },150};151 152static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {153 .mult = 2,154 .div = 1,155 .hw.init = &(struct clk_init_data){156 .name = "hdmi_pll_pre_mult",157 .ops = &clk_fixed_factor_ops,158 .parent_data = &(const struct clk_parent_data) {159 .fw_name = "xtal",160 },161 .num_parents = 1,162 },163};164 165static struct clk_regmap gxbb_hdmi_pll_dco = {166 .data = &(struct meson_clk_pll_data){167 .en = {168 .reg_off = HHI_HDMI_PLL_CNTL,169 .shift = 30,170 .width = 1,171 },172 .m = {173 .reg_off = HHI_HDMI_PLL_CNTL,174 .shift = 0,175 .width = 9,176 },177 .n = {178 .reg_off = HHI_HDMI_PLL_CNTL,179 .shift = 9,180 .width = 5,181 },182 .frac = {183 .reg_off = HHI_HDMI_PLL_CNTL2,184 .shift = 0,185 .width = 12,186 },187 .l = {188 .reg_off = HHI_HDMI_PLL_CNTL,189 .shift = 31,190 .width = 1,191 },192 .rst = {193 .reg_off = HHI_HDMI_PLL_CNTL,194 .shift = 28,195 .width = 1,196 },197 },198 .hw.init = &(struct clk_init_data){199 .name = "hdmi_pll_dco",200 .ops = &meson_clk_pll_ro_ops,201 .parent_hws = (const struct clk_hw *[]) {202 &gxbb_hdmi_pll_pre_mult.hw203 },204 .num_parents = 1,205 /*206 * Display directly handle hdmi pll registers ATM, we need207 * NOCACHE to keep our view of the clock as accurate as possible208 */209 .flags = CLK_GET_RATE_NOCACHE,210 },211};212 213static struct clk_regmap gxl_hdmi_pll_dco = {214 .data = &(struct meson_clk_pll_data){215 .en = {216 .reg_off = HHI_HDMI_PLL_CNTL,217 .shift = 30,218 .width = 1,219 },220 .m = {221 .reg_off = HHI_HDMI_PLL_CNTL,222 .shift = 0,223 .width = 9,224 },225 .n = {226 .reg_off = HHI_HDMI_PLL_CNTL,227 .shift = 9,228 .width = 5,229 },230 /*231 * On gxl, there is a register shift due to232 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,233 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB234 * instead which is defined at the same offset.235 */236 .frac = {237 .reg_off = HHI_HDMI_PLL_CNTL2,238 .shift = 0,239 .width = 10,240 },241 .l = {242 .reg_off = HHI_HDMI_PLL_CNTL,243 .shift = 31,244 .width = 1,245 },246 .rst = {247 .reg_off = HHI_HDMI_PLL_CNTL,248 .shift = 28,249 .width = 1,250 },251 },252 .hw.init = &(struct clk_init_data){253 .name = "hdmi_pll_dco",254 .ops = &meson_clk_pll_ro_ops,255 .parent_data = &(const struct clk_parent_data) {256 .fw_name = "xtal",257 },258 .num_parents = 1,259 /*260 * Display directly handle hdmi pll registers ATM, we need261 * NOCACHE to keep our view of the clock as accurate as possible262 */263 .flags = CLK_GET_RATE_NOCACHE,264 },265};266 267static struct clk_regmap gxbb_hdmi_pll_od = {268 .data = &(struct clk_regmap_div_data){269 .offset = HHI_HDMI_PLL_CNTL2,270 .shift = 16,271 .width = 2,272 .flags = CLK_DIVIDER_POWER_OF_TWO,273 },274 .hw.init = &(struct clk_init_data){275 .name = "hdmi_pll_od",276 .ops = &clk_regmap_divider_ro_ops,277 .parent_hws = (const struct clk_hw *[]) {278 &gxbb_hdmi_pll_dco.hw279 },280 .num_parents = 1,281 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,282 },283};284 285static struct clk_regmap gxbb_hdmi_pll_od2 = {286 .data = &(struct clk_regmap_div_data){287 .offset = HHI_HDMI_PLL_CNTL2,288 .shift = 22,289 .width = 2,290 .flags = CLK_DIVIDER_POWER_OF_TWO,291 },292 .hw.init = &(struct clk_init_data){293 .name = "hdmi_pll_od2",294 .ops = &clk_regmap_divider_ro_ops,295 .parent_hws = (const struct clk_hw *[]) {296 &gxbb_hdmi_pll_od.hw297 },298 .num_parents = 1,299 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,300 },301};302 303static struct clk_regmap gxbb_hdmi_pll = {304 .data = &(struct clk_regmap_div_data){305 .offset = HHI_HDMI_PLL_CNTL2,306 .shift = 18,307 .width = 2,308 .flags = CLK_DIVIDER_POWER_OF_TWO,309 },310 .hw.init = &(struct clk_init_data){311 .name = "hdmi_pll",312 .ops = &clk_regmap_divider_ro_ops,313 .parent_hws = (const struct clk_hw *[]) {314 &gxbb_hdmi_pll_od2.hw315 },316 .num_parents = 1,317 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,318 },319};320 321static struct clk_regmap gxl_hdmi_pll_od = {322 .data = &(struct clk_regmap_div_data){323 .offset = HHI_HDMI_PLL_CNTL + 8,324 .shift = 21,325 .width = 2,326 .flags = CLK_DIVIDER_POWER_OF_TWO,327 },328 .hw.init = &(struct clk_init_data){329 .name = "hdmi_pll_od",330 .ops = &clk_regmap_divider_ro_ops,331 .parent_hws = (const struct clk_hw *[]) {332 &gxl_hdmi_pll_dco.hw333 },334 .num_parents = 1,335 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,336 },337};338 339static struct clk_regmap gxl_hdmi_pll_od2 = {340 .data = &(struct clk_regmap_div_data){341 .offset = HHI_HDMI_PLL_CNTL + 8,342 .shift = 23,343 .width = 2,344 .flags = CLK_DIVIDER_POWER_OF_TWO,345 },346 .hw.init = &(struct clk_init_data){347 .name = "hdmi_pll_od2",348 .ops = &clk_regmap_divider_ro_ops,349 .parent_hws = (const struct clk_hw *[]) {350 &gxl_hdmi_pll_od.hw351 },352 .num_parents = 1,353 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,354 },355};356 357static struct clk_regmap gxl_hdmi_pll = {358 .data = &(struct clk_regmap_div_data){359 .offset = HHI_HDMI_PLL_CNTL + 8,360 .shift = 19,361 .width = 2,362 .flags = CLK_DIVIDER_POWER_OF_TWO,363 },364 .hw.init = &(struct clk_init_data){365 .name = "hdmi_pll",366 .ops = &clk_regmap_divider_ro_ops,367 .parent_hws = (const struct clk_hw *[]) {368 &gxl_hdmi_pll_od2.hw369 },370 .num_parents = 1,371 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,372 },373};374 375static struct clk_regmap gxbb_sys_pll_dco = {376 .data = &(struct meson_clk_pll_data){377 .en = {378 .reg_off = HHI_SYS_PLL_CNTL,379 .shift = 30,380 .width = 1,381 },382 .m = {383 .reg_off = HHI_SYS_PLL_CNTL,384 .shift = 0,385 .width = 9,386 },387 .n = {388 .reg_off = HHI_SYS_PLL_CNTL,389 .shift = 9,390 .width = 5,391 },392 .l = {393 .reg_off = HHI_SYS_PLL_CNTL,394 .shift = 31,395 .width = 1,396 },397 .rst = {398 .reg_off = HHI_SYS_PLL_CNTL,399 .shift = 29,400 .width = 1,401 },402 },403 .hw.init = &(struct clk_init_data){404 .name = "sys_pll_dco",405 .ops = &meson_clk_pll_ro_ops,406 .parent_data = &(const struct clk_parent_data) {407 .fw_name = "xtal",408 },409 .num_parents = 1,410 },411};412 413static struct clk_regmap gxbb_sys_pll = {414 .data = &(struct clk_regmap_div_data){415 .offset = HHI_SYS_PLL_CNTL,416 .shift = 10,417 .width = 2,418 .flags = CLK_DIVIDER_POWER_OF_TWO,419 },420 .hw.init = &(struct clk_init_data){421 .name = "sys_pll",422 .ops = &clk_regmap_divider_ro_ops,423 .parent_hws = (const struct clk_hw *[]) {424 &gxbb_sys_pll_dco.hw425 },426 .num_parents = 1,427 .flags = CLK_SET_RATE_PARENT,428 },429};430 431static const struct reg_sequence gxbb_gp0_init_regs[] = {432 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },433 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },434 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },435};436 437static struct clk_regmap gxbb_gp0_pll_dco = {438 .data = &(struct meson_clk_pll_data){439 .en = {440 .reg_off = HHI_GP0_PLL_CNTL,441 .shift = 30,442 .width = 1,443 },444 .m = {445 .reg_off = HHI_GP0_PLL_CNTL,446 .shift = 0,447 .width = 9,448 },449 .n = {450 .reg_off = HHI_GP0_PLL_CNTL,451 .shift = 9,452 .width = 5,453 },454 .l = {455 .reg_off = HHI_GP0_PLL_CNTL,456 .shift = 31,457 .width = 1,458 },459 .rst = {460 .reg_off = HHI_GP0_PLL_CNTL,461 .shift = 29,462 .width = 1,463 },464 .table = gxbb_gp0_pll_params_table,465 .init_regs = gxbb_gp0_init_regs,466 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),467 },468 .hw.init = &(struct clk_init_data){469 .name = "gp0_pll_dco",470 .ops = &meson_clk_pll_ops,471 .parent_data = &(const struct clk_parent_data) {472 .fw_name = "xtal",473 },474 .num_parents = 1,475 },476};477 478static const struct reg_sequence gxl_gp0_init_regs[] = {479 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },480 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },481 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },482 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },483 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },484};485 486static struct clk_regmap gxl_gp0_pll_dco = {487 .data = &(struct meson_clk_pll_data){488 .en = {489 .reg_off = HHI_GP0_PLL_CNTL,490 .shift = 30,491 .width = 1,492 },493 .m = {494 .reg_off = HHI_GP0_PLL_CNTL,495 .shift = 0,496 .width = 9,497 },498 .n = {499 .reg_off = HHI_GP0_PLL_CNTL,500 .shift = 9,501 .width = 5,502 },503 .frac = {504 .reg_off = HHI_GP0_PLL_CNTL1,505 .shift = 0,506 .width = 10,507 },508 .l = {509 .reg_off = HHI_GP0_PLL_CNTL,510 .shift = 31,511 .width = 1,512 },513 .rst = {514 .reg_off = HHI_GP0_PLL_CNTL,515 .shift = 29,516 .width = 1,517 },518 .table = gxl_gp0_pll_params_table,519 .init_regs = gxl_gp0_init_regs,520 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),521 },522 .hw.init = &(struct clk_init_data){523 .name = "gp0_pll_dco",524 .ops = &meson_clk_pll_ops,525 .parent_data = &(const struct clk_parent_data) {526 .fw_name = "xtal",527 },528 .num_parents = 1,529 },530};531 532static struct clk_regmap gxbb_gp0_pll = {533 .data = &(struct clk_regmap_div_data){534 .offset = HHI_GP0_PLL_CNTL,535 .shift = 16,536 .width = 2,537 .flags = CLK_DIVIDER_POWER_OF_TWO,538 },539 .hw.init = &(struct clk_init_data){540 .name = "gp0_pll",541 .ops = &clk_regmap_divider_ops,542 .parent_data = &(const struct clk_parent_data) {543 /*544 * Note:545 * GXL and GXBB have different gp0_pll_dco (with546 * different struct clk_hw). We fallback to the global547 * naming string mechanism so gp0_pll picks up the548 * appropriate one.549 */550 .name = "gp0_pll_dco",551 .index = -1,552 },553 .num_parents = 1,554 .flags = CLK_SET_RATE_PARENT,555 },556};557 558static struct clk_fixed_factor gxbb_fclk_div2_div = {559 .mult = 1,560 .div = 2,561 .hw.init = &(struct clk_init_data){562 .name = "fclk_div2_div",563 .ops = &clk_fixed_factor_ops,564 .parent_hws = (const struct clk_hw *[]) {565 &gxbb_fixed_pll.hw566 },567 .num_parents = 1,568 },569};570 571static struct clk_regmap gxbb_fclk_div2 = {572 .data = &(struct clk_regmap_gate_data){573 .offset = HHI_MPLL_CNTL6,574 .bit_idx = 27,575 },576 .hw.init = &(struct clk_init_data){577 .name = "fclk_div2",578 .ops = &clk_regmap_gate_ops,579 .parent_hws = (const struct clk_hw *[]) {580 &gxbb_fclk_div2_div.hw581 },582 .num_parents = 1,583 .flags = CLK_IS_CRITICAL,584 },585};586 587static struct clk_fixed_factor gxbb_fclk_div3_div = {588 .mult = 1,589 .div = 3,590 .hw.init = &(struct clk_init_data){591 .name = "fclk_div3_div",592 .ops = &clk_fixed_factor_ops,593 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },594 .num_parents = 1,595 },596};597 598static struct clk_regmap gxbb_fclk_div3 = {599 .data = &(struct clk_regmap_gate_data){600 .offset = HHI_MPLL_CNTL6,601 .bit_idx = 28,602 },603 .hw.init = &(struct clk_init_data){604 .name = "fclk_div3",605 .ops = &clk_regmap_gate_ops,606 .parent_hws = (const struct clk_hw *[]) {607 &gxbb_fclk_div3_div.hw608 },609 .num_parents = 1,610 /*611 * FIXME:612 * This clock, as fdiv2, is used by the SCPI FW and is required613 * by the platform to operate correctly.614 * Until the following condition are met, we need this clock to615 * be marked as critical:616 * a) The SCPI generic driver claims and enable all the clocks617 * it needs618 * b) CCF has a clock hand-off mechanism to make the sure the619 * clock stays on until the proper driver comes along620 */621 .flags = CLK_IS_CRITICAL,622 },623};624 625static struct clk_fixed_factor gxbb_fclk_div4_div = {626 .mult = 1,627 .div = 4,628 .hw.init = &(struct clk_init_data){629 .name = "fclk_div4_div",630 .ops = &clk_fixed_factor_ops,631 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },632 .num_parents = 1,633 },634};635 636static struct clk_regmap gxbb_fclk_div4 = {637 .data = &(struct clk_regmap_gate_data){638 .offset = HHI_MPLL_CNTL6,639 .bit_idx = 29,640 },641 .hw.init = &(struct clk_init_data){642 .name = "fclk_div4",643 .ops = &clk_regmap_gate_ops,644 .parent_hws = (const struct clk_hw *[]) {645 &gxbb_fclk_div4_div.hw646 },647 .num_parents = 1,648 },649};650 651static struct clk_fixed_factor gxbb_fclk_div5_div = {652 .mult = 1,653 .div = 5,654 .hw.init = &(struct clk_init_data){655 .name = "fclk_div5_div",656 .ops = &clk_fixed_factor_ops,657 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },658 .num_parents = 1,659 },660};661 662static struct clk_regmap gxbb_fclk_div5 = {663 .data = &(struct clk_regmap_gate_data){664 .offset = HHI_MPLL_CNTL6,665 .bit_idx = 30,666 },667 .hw.init = &(struct clk_init_data){668 .name = "fclk_div5",669 .ops = &clk_regmap_gate_ops,670 .parent_hws = (const struct clk_hw *[]) {671 &gxbb_fclk_div5_div.hw672 },673 .num_parents = 1,674 },675};676 677static struct clk_fixed_factor gxbb_fclk_div7_div = {678 .mult = 1,679 .div = 7,680 .hw.init = &(struct clk_init_data){681 .name = "fclk_div7_div",682 .ops = &clk_fixed_factor_ops,683 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },684 .num_parents = 1,685 },686};687 688static struct clk_regmap gxbb_fclk_div7 = {689 .data = &(struct clk_regmap_gate_data){690 .offset = HHI_MPLL_CNTL6,691 .bit_idx = 31,692 },693 .hw.init = &(struct clk_init_data){694 .name = "fclk_div7",695 .ops = &clk_regmap_gate_ops,696 .parent_hws = (const struct clk_hw *[]) {697 &gxbb_fclk_div7_div.hw698 },699 .num_parents = 1,700 },701};702 703static struct clk_regmap gxbb_mpll_prediv = {704 .data = &(struct clk_regmap_div_data){705 .offset = HHI_MPLL_CNTL5,706 .shift = 12,707 .width = 1,708 },709 .hw.init = &(struct clk_init_data){710 .name = "mpll_prediv",711 .ops = &clk_regmap_divider_ro_ops,712 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },713 .num_parents = 1,714 },715};716 717static struct clk_regmap gxbb_mpll0_div = {718 .data = &(struct meson_clk_mpll_data){719 .sdm = {720 .reg_off = HHI_MPLL_CNTL7,721 .shift = 0,722 .width = 14,723 },724 .sdm_en = {725 .reg_off = HHI_MPLL_CNTL,726 .shift = 25,727 .width = 1,728 },729 .n2 = {730 .reg_off = HHI_MPLL_CNTL7,731 .shift = 16,732 .width = 9,733 },734 .lock = &meson_clk_lock,735 },736 .hw.init = &(struct clk_init_data){737 .name = "mpll0_div",738 .ops = &meson_clk_mpll_ops,739 .parent_hws = (const struct clk_hw *[]) {740 &gxbb_mpll_prediv.hw741 },742 .num_parents = 1,743 },744};745 746static struct clk_regmap gxl_mpll0_div = {747 .data = &(struct meson_clk_mpll_data){748 .sdm = {749 .reg_off = HHI_MPLL_CNTL7,750 .shift = 0,751 .width = 14,752 },753 .sdm_en = {754 .reg_off = HHI_MPLL_CNTL7,755 .shift = 15,756 .width = 1,757 },758 .n2 = {759 .reg_off = HHI_MPLL_CNTL7,760 .shift = 16,761 .width = 9,762 },763 .lock = &meson_clk_lock,764 },765 .hw.init = &(struct clk_init_data){766 .name = "mpll0_div",767 .ops = &meson_clk_mpll_ops,768 .parent_hws = (const struct clk_hw *[]) {769 &gxbb_mpll_prediv.hw770 },771 .num_parents = 1,772 },773};774 775static struct clk_regmap gxbb_mpll0 = {776 .data = &(struct clk_regmap_gate_data){777 .offset = HHI_MPLL_CNTL7,778 .bit_idx = 14,779 },780 .hw.init = &(struct clk_init_data){781 .name = "mpll0",782 .ops = &clk_regmap_gate_ops,783 .parent_data = &(const struct clk_parent_data) {784 /*785 * Note:786 * GXL and GXBB have different SDM_EN registers. We787 * fallback to the global naming string mechanism so788 * mpll0_div picks up the appropriate one.789 */790 .name = "mpll0_div",791 .index = -1,792 },793 .num_parents = 1,794 .flags = CLK_SET_RATE_PARENT,795 },796};797 798static struct clk_regmap gxbb_mpll1_div = {799 .data = &(struct meson_clk_mpll_data){800 .sdm = {801 .reg_off = HHI_MPLL_CNTL8,802 .shift = 0,803 .width = 14,804 },805 .sdm_en = {806 .reg_off = HHI_MPLL_CNTL8,807 .shift = 15,808 .width = 1,809 },810 .n2 = {811 .reg_off = HHI_MPLL_CNTL8,812 .shift = 16,813 .width = 9,814 },815 .lock = &meson_clk_lock,816 },817 .hw.init = &(struct clk_init_data){818 .name = "mpll1_div",819 .ops = &meson_clk_mpll_ops,820 .parent_hws = (const struct clk_hw *[]) {821 &gxbb_mpll_prediv.hw822 },823 .num_parents = 1,824 },825};826 827static struct clk_regmap gxbb_mpll1 = {828 .data = &(struct clk_regmap_gate_data){829 .offset = HHI_MPLL_CNTL8,830 .bit_idx = 14,831 },832 .hw.init = &(struct clk_init_data){833 .name = "mpll1",834 .ops = &clk_regmap_gate_ops,835 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },836 .num_parents = 1,837 .flags = CLK_SET_RATE_PARENT,838 },839};840 841static struct clk_regmap gxbb_mpll2_div = {842 .data = &(struct meson_clk_mpll_data){843 .sdm = {844 .reg_off = HHI_MPLL_CNTL9,845 .shift = 0,846 .width = 14,847 },848 .sdm_en = {849 .reg_off = HHI_MPLL_CNTL9,850 .shift = 15,851 .width = 1,852 },853 .n2 = {854 .reg_off = HHI_MPLL_CNTL9,855 .shift = 16,856 .width = 9,857 },858 .lock = &meson_clk_lock,859 },860 .hw.init = &(struct clk_init_data){861 .name = "mpll2_div",862 .ops = &meson_clk_mpll_ops,863 .parent_hws = (const struct clk_hw *[]) {864 &gxbb_mpll_prediv.hw865 },866 .num_parents = 1,867 },868};869 870static struct clk_regmap gxbb_mpll2 = {871 .data = &(struct clk_regmap_gate_data){872 .offset = HHI_MPLL_CNTL9,873 .bit_idx = 14,874 },875 .hw.init = &(struct clk_init_data){876 .name = "mpll2",877 .ops = &clk_regmap_gate_ops,878 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },879 .num_parents = 1,880 .flags = CLK_SET_RATE_PARENT,881 },882};883 884static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };885static const struct clk_parent_data clk81_parent_data[] = {886 { .fw_name = "xtal", },887 { .hw = &gxbb_fclk_div7.hw },888 { .hw = &gxbb_mpll1.hw },889 { .hw = &gxbb_mpll2.hw },890 { .hw = &gxbb_fclk_div4.hw },891 { .hw = &gxbb_fclk_div3.hw },892 { .hw = &gxbb_fclk_div5.hw },893};894 895static struct clk_regmap gxbb_mpeg_clk_sel = {896 .data = &(struct clk_regmap_mux_data){897 .offset = HHI_MPEG_CLK_CNTL,898 .mask = 0x7,899 .shift = 12,900 .table = mux_table_clk81,901 },902 .hw.init = &(struct clk_init_data){903 .name = "mpeg_clk_sel",904 .ops = &clk_regmap_mux_ro_ops,905 /*906 * bits 14:12 selects from 8 possible parents:907 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,908 * fclk_div4, fclk_div3, fclk_div5909 */910 .parent_data = clk81_parent_data,911 .num_parents = ARRAY_SIZE(clk81_parent_data),912 },913};914 915static struct clk_regmap gxbb_mpeg_clk_div = {916 .data = &(struct clk_regmap_div_data){917 .offset = HHI_MPEG_CLK_CNTL,918 .shift = 0,919 .width = 7,920 },921 .hw.init = &(struct clk_init_data){922 .name = "mpeg_clk_div",923 .ops = &clk_regmap_divider_ro_ops,924 .parent_hws = (const struct clk_hw *[]) {925 &gxbb_mpeg_clk_sel.hw926 },927 .num_parents = 1,928 },929};930 931/* the mother of dragons gates */932static struct clk_regmap gxbb_clk81 = {933 .data = &(struct clk_regmap_gate_data){934 .offset = HHI_MPEG_CLK_CNTL,935 .bit_idx = 7,936 },937 .hw.init = &(struct clk_init_data){938 .name = "clk81",939 .ops = &clk_regmap_gate_ops,940 .parent_hws = (const struct clk_hw *[]) {941 &gxbb_mpeg_clk_div.hw942 },943 .num_parents = 1,944 .flags = CLK_IS_CRITICAL,945 },946};947 948static struct clk_regmap gxbb_sar_adc_clk_sel = {949 .data = &(struct clk_regmap_mux_data){950 .offset = HHI_SAR_CLK_CNTL,951 .mask = 0x3,952 .shift = 9,953 },954 .hw.init = &(struct clk_init_data){955 .name = "sar_adc_clk_sel",956 .ops = &clk_regmap_mux_ops,957 /* NOTE: The datasheet doesn't list the parents for bit 10 */958 .parent_data = (const struct clk_parent_data []) {959 { .fw_name = "xtal", },960 { .hw = &gxbb_clk81.hw },961 },962 .num_parents = 2,963 },964};965 966static struct clk_regmap gxbb_sar_adc_clk_div = {967 .data = &(struct clk_regmap_div_data){968 .offset = HHI_SAR_CLK_CNTL,969 .shift = 0,970 .width = 8,971 },972 .hw.init = &(struct clk_init_data){973 .name = "sar_adc_clk_div",974 .ops = &clk_regmap_divider_ops,975 .parent_hws = (const struct clk_hw *[]) {976 &gxbb_sar_adc_clk_sel.hw977 },978 .num_parents = 1,979 .flags = CLK_SET_RATE_PARENT,980 },981};982 983static struct clk_regmap gxbb_sar_adc_clk = {984 .data = &(struct clk_regmap_gate_data){985 .offset = HHI_SAR_CLK_CNTL,986 .bit_idx = 8,987 },988 .hw.init = &(struct clk_init_data){989 .name = "sar_adc_clk",990 .ops = &clk_regmap_gate_ops,991 .parent_hws = (const struct clk_hw *[]) {992 &gxbb_sar_adc_clk_div.hw993 },994 .num_parents = 1,995 .flags = CLK_SET_RATE_PARENT,996 },997};998 999/*1000 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)1001 * muxed by a glitch-free switch. The CCF can manage this glitch-free1002 * mux because it does top-to-bottom updates the each clock tree and1003 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.1004 */1005 1006static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {1007 { .fw_name = "xtal", },1008 { .hw = &gxbb_gp0_pll.hw },1009 { .hw = &gxbb_mpll2.hw },1010 { .hw = &gxbb_mpll1.hw },1011 { .hw = &gxbb_fclk_div7.hw },1012 { .hw = &gxbb_fclk_div4.hw },1013 { .hw = &gxbb_fclk_div3.hw },1014 { .hw = &gxbb_fclk_div5.hw },1015};1016 1017static struct clk_regmap gxbb_mali_0_sel = {1018 .data = &(struct clk_regmap_mux_data){1019 .offset = HHI_MALI_CLK_CNTL,1020 .mask = 0x7,1021 .shift = 9,1022 },1023 .hw.init = &(struct clk_init_data){1024 .name = "mali_0_sel",1025 .ops = &clk_regmap_mux_ops,1026 .parent_data = gxbb_mali_0_1_parent_data,1027 .num_parents = 8,1028 /*1029 * Don't request the parent to change the rate because1030 * all GPU frequencies can be derived from the fclk_*1031 * clocks and one special GP0_PLL setting. This is1032 * important because we need the MPLL clocks for audio.1033 */1034 .flags = 0,1035 },1036};1037 1038static struct clk_regmap gxbb_mali_0_div = {1039 .data = &(struct clk_regmap_div_data){1040 .offset = HHI_MALI_CLK_CNTL,1041 .shift = 0,1042 .width = 7,1043 },1044 .hw.init = &(struct clk_init_data){1045 .name = "mali_0_div",1046 .ops = &clk_regmap_divider_ops,1047 .parent_hws = (const struct clk_hw *[]) {1048 &gxbb_mali_0_sel.hw1049 },1050 .num_parents = 1,1051 .flags = CLK_SET_RATE_PARENT,1052 },1053};1054 1055static struct clk_regmap gxbb_mali_0 = {1056 .data = &(struct clk_regmap_gate_data){1057 .offset = HHI_MALI_CLK_CNTL,1058 .bit_idx = 8,1059 },1060 .hw.init = &(struct clk_init_data){1061 .name = "mali_0",1062 .ops = &clk_regmap_gate_ops,1063 .parent_hws = (const struct clk_hw *[]) {1064 &gxbb_mali_0_div.hw1065 },1066 .num_parents = 1,1067 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,1068 },1069};1070 1071static struct clk_regmap gxbb_mali_1_sel = {1072 .data = &(struct clk_regmap_mux_data){1073 .offset = HHI_MALI_CLK_CNTL,1074 .mask = 0x7,1075 .shift = 25,1076 },1077 .hw.init = &(struct clk_init_data){1078 .name = "mali_1_sel",1079 .ops = &clk_regmap_mux_ops,1080 .parent_data = gxbb_mali_0_1_parent_data,1081 .num_parents = 8,1082 /*1083 * Don't request the parent to change the rate because1084 * all GPU frequencies can be derived from the fclk_*1085 * clocks and one special GP0_PLL setting. This is1086 * important because we need the MPLL clocks for audio.1087 */1088 .flags = 0,1089 },1090};1091 1092static struct clk_regmap gxbb_mali_1_div = {1093 .data = &(struct clk_regmap_div_data){1094 .offset = HHI_MALI_CLK_CNTL,1095 .shift = 16,1096 .width = 7,1097 },1098 .hw.init = &(struct clk_init_data){1099 .name = "mali_1_div",1100 .ops = &clk_regmap_divider_ops,1101 .parent_hws = (const struct clk_hw *[]) {1102 &gxbb_mali_1_sel.hw1103 },1104 .num_parents = 1,1105 .flags = CLK_SET_RATE_PARENT,1106 },1107};1108 1109static struct clk_regmap gxbb_mali_1 = {1110 .data = &(struct clk_regmap_gate_data){1111 .offset = HHI_MALI_CLK_CNTL,1112 .bit_idx = 24,1113 },1114 .hw.init = &(struct clk_init_data){1115 .name = "mali_1",1116 .ops = &clk_regmap_gate_ops,1117 .parent_hws = (const struct clk_hw *[]) {1118 &gxbb_mali_1_div.hw1119 },1120 .num_parents = 1,1121 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,1122 },1123};1124 1125static const struct clk_hw *gxbb_mali_parent_hws[] = {1126 &gxbb_mali_0.hw,1127 &gxbb_mali_1.hw,1128};1129 1130static struct clk_regmap gxbb_mali = {1131 .data = &(struct clk_regmap_mux_data){1132 .offset = HHI_MALI_CLK_CNTL,1133 .mask = 1,1134 .shift = 31,1135 },1136 .hw.init = &(struct clk_init_data){1137 .name = "mali",1138 .ops = &clk_regmap_mux_ops,1139 .parent_hws = gxbb_mali_parent_hws,1140 .num_parents = 2,1141 .flags = CLK_SET_RATE_PARENT,1142 },1143};1144 1145static struct clk_regmap gxbb_cts_amclk_sel = {1146 .data = &(struct clk_regmap_mux_data){1147 .offset = HHI_AUD_CLK_CNTL,1148 .mask = 0x3,1149 .shift = 9,1150 .table = (u32[]){ 1, 2, 3 },1151 .flags = CLK_MUX_ROUND_CLOSEST,1152 },1153 .hw.init = &(struct clk_init_data){1154 .name = "cts_amclk_sel",1155 .ops = &clk_regmap_mux_ops,1156 .parent_hws = (const struct clk_hw *[]) {1157 &gxbb_mpll0.hw,1158 &gxbb_mpll1.hw,1159 &gxbb_mpll2.hw,1160 },1161 .num_parents = 3,1162 },1163};1164 1165static struct clk_regmap gxbb_cts_amclk_div = {1166 .data = &(struct clk_regmap_div_data) {1167 .offset = HHI_AUD_CLK_CNTL,1168 .shift = 0,1169 .width = 8,1170 .flags = CLK_DIVIDER_ROUND_CLOSEST,1171 },1172 .hw.init = &(struct clk_init_data){1173 .name = "cts_amclk_div",1174 .ops = &clk_regmap_divider_ops,1175 .parent_hws = (const struct clk_hw *[]) {1176 &gxbb_cts_amclk_sel.hw1177 },1178 .num_parents = 1,1179 .flags = CLK_SET_RATE_PARENT,1180 },1181};1182 1183static struct clk_regmap gxbb_cts_amclk = {1184 .data = &(struct clk_regmap_gate_data){1185 .offset = HHI_AUD_CLK_CNTL,1186 .bit_idx = 8,1187 },1188 .hw.init = &(struct clk_init_data){1189 .name = "cts_amclk",1190 .ops = &clk_regmap_gate_ops,1191 .parent_hws = (const struct clk_hw *[]) {1192 &gxbb_cts_amclk_div.hw1193 },1194 .num_parents = 1,1195 .flags = CLK_SET_RATE_PARENT,1196 },1197};1198 1199static struct clk_regmap gxbb_cts_mclk_i958_sel = {1200 .data = &(struct clk_regmap_mux_data){1201 .offset = HHI_AUD_CLK_CNTL2,1202 .mask = 0x3,1203 .shift = 25,1204 .table = (u32[]){ 1, 2, 3 },1205 .flags = CLK_MUX_ROUND_CLOSEST,1206 },1207 .hw.init = &(struct clk_init_data) {1208 .name = "cts_mclk_i958_sel",1209 .ops = &clk_regmap_mux_ops,1210 .parent_hws = (const struct clk_hw *[]) {1211 &gxbb_mpll0.hw,1212 &gxbb_mpll1.hw,1213 &gxbb_mpll2.hw,1214 },1215 .num_parents = 3,1216 },1217};1218 1219static struct clk_regmap gxbb_cts_mclk_i958_div = {1220 .data = &(struct clk_regmap_div_data){1221 .offset = HHI_AUD_CLK_CNTL2,1222 .shift = 16,1223 .width = 8,1224 .flags = CLK_DIVIDER_ROUND_CLOSEST,1225 },1226 .hw.init = &(struct clk_init_data) {1227 .name = "cts_mclk_i958_div",1228 .ops = &clk_regmap_divider_ops,1229 .parent_hws = (const struct clk_hw *[]) {1230 &gxbb_cts_mclk_i958_sel.hw1231 },1232 .num_parents = 1,1233 .flags = CLK_SET_RATE_PARENT,1234 },1235};1236 1237static struct clk_regmap gxbb_cts_mclk_i958 = {1238 .data = &(struct clk_regmap_gate_data){1239 .offset = HHI_AUD_CLK_CNTL2,1240 .bit_idx = 24,1241 },1242 .hw.init = &(struct clk_init_data){1243 .name = "cts_mclk_i958",1244 .ops = &clk_regmap_gate_ops,1245 .parent_hws = (const struct clk_hw *[]) {1246 &gxbb_cts_mclk_i958_div.hw1247 },1248 .num_parents = 1,1249 .flags = CLK_SET_RATE_PARENT,1250 },1251};1252 1253static struct clk_regmap gxbb_cts_i958 = {1254 .data = &(struct clk_regmap_mux_data){1255 .offset = HHI_AUD_CLK_CNTL2,1256 .mask = 0x1,1257 .shift = 27,1258 },1259 .hw.init = &(struct clk_init_data){1260 .name = "cts_i958",1261 .ops = &clk_regmap_mux_ops,1262 .parent_hws = (const struct clk_hw *[]) {1263 &gxbb_cts_amclk.hw,1264 &gxbb_cts_mclk_i958.hw1265 },1266 .num_parents = 2,1267 /*1268 *The parent is specific to origin of the audio data. Let the1269 * consumer choose the appropriate parent1270 */1271 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,1272 },1273};1274 1275static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {1276 { .fw_name = "xtal", },1277 /*1278 * FIXME: This clock is provided by the ao clock controller but the1279 * clock is not yet part of the binding of this controller, so string1280 * name must be use to set this parent.1281 */1282 { .name = "cts_slow_oscin", .index = -1 },1283 { .hw = &gxbb_fclk_div3.hw },1284 { .hw = &gxbb_fclk_div5.hw },1285};1286 1287static struct clk_regmap gxbb_32k_clk_sel = {1288 .data = &(struct clk_regmap_mux_data){1289 .offset = HHI_32K_CLK_CNTL,1290 .mask = 0x3,1291 .shift = 16,1292 },1293 .hw.init = &(struct clk_init_data){1294 .name = "32k_clk_sel",1295 .ops = &clk_regmap_mux_ops,1296 .parent_data = gxbb_32k_clk_parent_data,1297 .num_parents = 4,1298 .flags = CLK_SET_RATE_PARENT,1299 },1300};1301 1302static struct clk_regmap gxbb_32k_clk_div = {1303 .data = &(struct clk_regmap_div_data){1304 .offset = HHI_32K_CLK_CNTL,1305 .shift = 0,1306 .width = 14,1307 },1308 .hw.init = &(struct clk_init_data){1309 .name = "32k_clk_div",1310 .ops = &clk_regmap_divider_ops,1311 .parent_hws = (const struct clk_hw *[]) {1312 &gxbb_32k_clk_sel.hw1313 },1314 .num_parents = 1,1315 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,1316 },1317};1318 1319static struct clk_regmap gxbb_32k_clk = {1320 .data = &(struct clk_regmap_gate_data){1321 .offset = HHI_32K_CLK_CNTL,1322 .bit_idx = 15,1323 },1324 .hw.init = &(struct clk_init_data){1325 .name = "32k_clk",1326 .ops = &clk_regmap_gate_ops,1327 .parent_hws = (const struct clk_hw *[]) {1328 &gxbb_32k_clk_div.hw1329 },1330 .num_parents = 1,1331 .flags = CLK_SET_RATE_PARENT,1332 },1333};1334 1335static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {1336 { .fw_name = "xtal", },1337 { .hw = &gxbb_fclk_div2.hw },1338 { .hw = &gxbb_fclk_div3.hw },1339 { .hw = &gxbb_fclk_div5.hw },1340 { .hw = &gxbb_fclk_div7.hw },1341 /*1342 * Following these parent clocks, we should also have had mpll2, mpll31343 * and gp0_pll but these clocks are too precious to be used here. All1344 * the necessary rates for MMC and NAND operation can be acheived using1345 * xtal or fclk_div clocks1346 */1347};1348 1349/* SDIO clock */1350static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {1351 .data = &(struct clk_regmap_mux_data){1352 .offset = HHI_SD_EMMC_CLK_CNTL,1353 .mask = 0x7,1354 .shift = 9,1355 },1356 .hw.init = &(struct clk_init_data) {1357 .name = "sd_emmc_a_clk0_sel",1358 .ops = &clk_regmap_mux_ops,1359 .parent_data = gxbb_sd_emmc_clk0_parent_data,1360 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),1361 .flags = CLK_SET_RATE_PARENT,1362 },1363};1364 1365static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {1366 .data = &(struct clk_regmap_div_data){1367 .offset = HHI_SD_EMMC_CLK_CNTL,1368 .shift = 0,1369 .width = 7,1370 .flags = CLK_DIVIDER_ROUND_CLOSEST,1371 },1372 .hw.init = &(struct clk_init_data) {1373 .name = "sd_emmc_a_clk0_div",1374 .ops = &clk_regmap_divider_ops,1375 .parent_hws = (const struct clk_hw *[]) {1376 &gxbb_sd_emmc_a_clk0_sel.hw1377 },1378 .num_parents = 1,1379 .flags = CLK_SET_RATE_PARENT,1380 },1381};1382 1383static struct clk_regmap gxbb_sd_emmc_a_clk0 = {1384 .data = &(struct clk_regmap_gate_data){1385 .offset = HHI_SD_EMMC_CLK_CNTL,1386 .bit_idx = 7,1387 },1388 .hw.init = &(struct clk_init_data){1389 .name = "sd_emmc_a_clk0",1390 .ops = &clk_regmap_gate_ops,1391 .parent_hws = (const struct clk_hw *[]) {1392 &gxbb_sd_emmc_a_clk0_div.hw1393 },1394 .num_parents = 1,1395 .flags = CLK_SET_RATE_PARENT,1396 },1397};1398 1399/* SDcard clock */1400static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {1401 .data = &(struct clk_regmap_mux_data){1402 .offset = HHI_SD_EMMC_CLK_CNTL,1403 .mask = 0x7,1404 .shift = 25,1405 },1406 .hw.init = &(struct clk_init_data) {1407 .name = "sd_emmc_b_clk0_sel",1408 .ops = &clk_regmap_mux_ops,1409 .parent_data = gxbb_sd_emmc_clk0_parent_data,1410 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),1411 .flags = CLK_SET_RATE_PARENT,1412 },1413};1414 1415static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {1416 .data = &(struct clk_regmap_div_data){1417 .offset = HHI_SD_EMMC_CLK_CNTL,1418 .shift = 16,1419 .width = 7,1420 .flags = CLK_DIVIDER_ROUND_CLOSEST,1421 },1422 .hw.init = &(struct clk_init_data) {1423 .name = "sd_emmc_b_clk0_div",1424 .ops = &clk_regmap_divider_ops,1425 .parent_hws = (const struct clk_hw *[]) {1426 &gxbb_sd_emmc_b_clk0_sel.hw1427 },1428 .num_parents = 1,1429 .flags = CLK_SET_RATE_PARENT,1430 },1431};1432 1433static struct clk_regmap gxbb_sd_emmc_b_clk0 = {1434 .data = &(struct clk_regmap_gate_data){1435 .offset = HHI_SD_EMMC_CLK_CNTL,1436 .bit_idx = 23,1437 },1438 .hw.init = &(struct clk_init_data){1439 .name = "sd_emmc_b_clk0",1440 .ops = &clk_regmap_gate_ops,1441 .parent_hws = (const struct clk_hw *[]) {1442 &gxbb_sd_emmc_b_clk0_div.hw1443 },1444 .num_parents = 1,1445 .flags = CLK_SET_RATE_PARENT,1446 },1447};1448 1449/* EMMC/NAND clock */1450static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {1451 .data = &(struct clk_regmap_mux_data){1452 .offset = HHI_NAND_CLK_CNTL,1453 .mask = 0x7,1454 .shift = 9,1455 },1456 .hw.init = &(struct clk_init_data) {1457 .name = "sd_emmc_c_clk0_sel",1458 .ops = &clk_regmap_mux_ops,1459 .parent_data = gxbb_sd_emmc_clk0_parent_data,1460 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),1461 .flags = CLK_SET_RATE_PARENT,1462 },1463};1464 1465static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {1466 .data = &(struct clk_regmap_div_data){1467 .offset = HHI_NAND_CLK_CNTL,1468 .shift = 0,1469 .width = 7,1470 .flags = CLK_DIVIDER_ROUND_CLOSEST,1471 },1472 .hw.init = &(struct clk_init_data) {1473 .name = "sd_emmc_c_clk0_div",1474 .ops = &clk_regmap_divider_ops,1475 .parent_hws = (const struct clk_hw *[]) {1476 &gxbb_sd_emmc_c_clk0_sel.hw1477 },1478 .num_parents = 1,1479 .flags = CLK_SET_RATE_PARENT,1480 },1481};1482 1483static struct clk_regmap gxbb_sd_emmc_c_clk0 = {1484 .data = &(struct clk_regmap_gate_data){1485 .offset = HHI_NAND_CLK_CNTL,1486 .bit_idx = 7,1487 },1488 .hw.init = &(struct clk_init_data){1489 .name = "sd_emmc_c_clk0",1490 .ops = &clk_regmap_gate_ops,1491 .parent_hws = (const struct clk_hw *[]) {1492 &gxbb_sd_emmc_c_clk0_div.hw1493 },1494 .num_parents = 1,1495 .flags = CLK_SET_RATE_PARENT,1496 },1497};1498 1499/* VPU Clock */1500 1501static const struct clk_hw *gxbb_vpu_parent_hws[] = {1502 &gxbb_fclk_div4.hw,1503 &gxbb_fclk_div3.hw,1504 &gxbb_fclk_div5.hw,1505 &gxbb_fclk_div7.hw,1506};1507 1508static struct clk_regmap gxbb_vpu_0_sel = {1509 .data = &(struct clk_regmap_mux_data){1510 .offset = HHI_VPU_CLK_CNTL,1511 .mask = 0x3,1512 .shift = 9,1513 },1514 .hw.init = &(struct clk_init_data){1515 .name = "vpu_0_sel",1516 .ops = &clk_regmap_mux_ops,1517 /*1518 * bits 9:10 selects from 4 possible parents:1519 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,1520 */1521 .parent_hws = gxbb_vpu_parent_hws,1522 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),1523 .flags = CLK_SET_RATE_NO_REPARENT,1524 },1525};1526 1527static struct clk_regmap gxbb_vpu_0_div = {1528 .data = &(struct clk_regmap_div_data){1529 .offset = HHI_VPU_CLK_CNTL,1530 .shift = 0,1531 .width = 7,1532 },1533 .hw.init = &(struct clk_init_data){1534 .name = "vpu_0_div",1535 .ops = &clk_regmap_divider_ops,1536 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },1537 .num_parents = 1,1538 .flags = CLK_SET_RATE_PARENT,1539 },1540};1541 1542static struct clk_regmap gxbb_vpu_0 = {1543 .data = &(struct clk_regmap_gate_data){1544 .offset = HHI_VPU_CLK_CNTL,1545 .bit_idx = 8,1546 },1547 .hw.init = &(struct clk_init_data) {1548 .name = "vpu_0",1549 .ops = &clk_regmap_gate_ops,1550 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },1551 .num_parents = 1,1552 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1553 },1554};1555 1556static struct clk_regmap gxbb_vpu_1_sel = {1557 .data = &(struct clk_regmap_mux_data){1558 .offset = HHI_VPU_CLK_CNTL,1559 .mask = 0x3,1560 .shift = 25,1561 },1562 .hw.init = &(struct clk_init_data){1563 .name = "vpu_1_sel",1564 .ops = &clk_regmap_mux_ops,1565 /*1566 * bits 25:26 selects from 4 possible parents:1567 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,1568 */1569 .parent_hws = gxbb_vpu_parent_hws,1570 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),1571 .flags = CLK_SET_RATE_NO_REPARENT,1572 },1573};1574 1575static struct clk_regmap gxbb_vpu_1_div = {1576 .data = &(struct clk_regmap_div_data){1577 .offset = HHI_VPU_CLK_CNTL,1578 .shift = 16,1579 .width = 7,1580 },1581 .hw.init = &(struct clk_init_data){1582 .name = "vpu_1_div",1583 .ops = &clk_regmap_divider_ops,1584 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },1585 .num_parents = 1,1586 .flags = CLK_SET_RATE_PARENT,1587 },1588};1589 1590static struct clk_regmap gxbb_vpu_1 = {1591 .data = &(struct clk_regmap_gate_data){1592 .offset = HHI_VPU_CLK_CNTL,1593 .bit_idx = 24,1594 },1595 .hw.init = &(struct clk_init_data) {1596 .name = "vpu_1",1597 .ops = &clk_regmap_gate_ops,1598 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },1599 .num_parents = 1,1600 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1601 },1602};1603 1604static struct clk_regmap gxbb_vpu = {1605 .data = &(struct clk_regmap_mux_data){1606 .offset = HHI_VPU_CLK_CNTL,1607 .mask = 1,1608 .shift = 31,1609 },1610 .hw.init = &(struct clk_init_data){1611 .name = "vpu",1612 .ops = &clk_regmap_mux_ops,1613 /*1614 * bit 31 selects from 2 possible parents:1615 * vpu_0 or vpu_11616 */1617 .parent_hws = (const struct clk_hw *[]) {1618 &gxbb_vpu_0.hw,1619 &gxbb_vpu_1.hw1620 },1621 .num_parents = 2,1622 .flags = CLK_SET_RATE_NO_REPARENT,1623 },1624};1625 1626/* VAPB Clock */1627 1628static const struct clk_hw *gxbb_vapb_parent_hws[] = {1629 &gxbb_fclk_div4.hw,1630 &gxbb_fclk_div3.hw,1631 &gxbb_fclk_div5.hw,1632 &gxbb_fclk_div7.hw,1633};1634 1635static struct clk_regmap gxbb_vapb_0_sel = {1636 .data = &(struct clk_regmap_mux_data){1637 .offset = HHI_VAPBCLK_CNTL,1638 .mask = 0x3,1639 .shift = 9,1640 },1641 .hw.init = &(struct clk_init_data){1642 .name = "vapb_0_sel",1643 .ops = &clk_regmap_mux_ops,1644 /*1645 * bits 9:10 selects from 4 possible parents:1646 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,1647 */1648 .parent_hws = gxbb_vapb_parent_hws,1649 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),1650 .flags = CLK_SET_RATE_NO_REPARENT,1651 },1652};1653 1654static struct clk_regmap gxbb_vapb_0_div = {1655 .data = &(struct clk_regmap_div_data){1656 .offset = HHI_VAPBCLK_CNTL,1657 .shift = 0,1658 .width = 7,1659 },1660 .hw.init = &(struct clk_init_data){1661 .name = "vapb_0_div",1662 .ops = &clk_regmap_divider_ops,1663 .parent_hws = (const struct clk_hw *[]) {1664 &gxbb_vapb_0_sel.hw1665 },1666 .num_parents = 1,1667 .flags = CLK_SET_RATE_PARENT,1668 },1669};1670 1671static struct clk_regmap gxbb_vapb_0 = {1672 .data = &(struct clk_regmap_gate_data){1673 .offset = HHI_VAPBCLK_CNTL,1674 .bit_idx = 8,1675 },1676 .hw.init = &(struct clk_init_data) {1677 .name = "vapb_0",1678 .ops = &clk_regmap_gate_ops,1679 .parent_hws = (const struct clk_hw *[]) {1680 &gxbb_vapb_0_div.hw1681 },1682 .num_parents = 1,1683 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1684 },1685};1686 1687static struct clk_regmap gxbb_vapb_1_sel = {1688 .data = &(struct clk_regmap_mux_data){1689 .offset = HHI_VAPBCLK_CNTL,1690 .mask = 0x3,1691 .shift = 25,1692 },1693 .hw.init = &(struct clk_init_data){1694 .name = "vapb_1_sel",1695 .ops = &clk_regmap_mux_ops,1696 /*1697 * bits 25:26 selects from 4 possible parents:1698 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,1699 */1700 .parent_hws = gxbb_vapb_parent_hws,1701 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),1702 .flags = CLK_SET_RATE_NO_REPARENT,1703 },1704};1705 1706static struct clk_regmap gxbb_vapb_1_div = {1707 .data = &(struct clk_regmap_div_data){1708 .offset = HHI_VAPBCLK_CNTL,1709 .shift = 16,1710 .width = 7,1711 },1712 .hw.init = &(struct clk_init_data){1713 .name = "vapb_1_div",1714 .ops = &clk_regmap_divider_ops,1715 .parent_hws = (const struct clk_hw *[]) {1716 &gxbb_vapb_1_sel.hw1717 },1718 .num_parents = 1,1719 .flags = CLK_SET_RATE_PARENT,1720 },1721};1722 1723static struct clk_regmap gxbb_vapb_1 = {1724 .data = &(struct clk_regmap_gate_data){1725 .offset = HHI_VAPBCLK_CNTL,1726 .bit_idx = 24,1727 },1728 .hw.init = &(struct clk_init_data) {1729 .name = "vapb_1",1730 .ops = &clk_regmap_gate_ops,1731 .parent_hws = (const struct clk_hw *[]) {1732 &gxbb_vapb_1_div.hw1733 },1734 .num_parents = 1,1735 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1736 },1737};1738 1739static struct clk_regmap gxbb_vapb_sel = {1740 .data = &(struct clk_regmap_mux_data){1741 .offset = HHI_VAPBCLK_CNTL,1742 .mask = 1,1743 .shift = 31,1744 },1745 .hw.init = &(struct clk_init_data){1746 .name = "vapb_sel",1747 .ops = &clk_regmap_mux_ops,1748 /*1749 * bit 31 selects from 2 possible parents:1750 * vapb_0 or vapb_11751 */1752 .parent_hws = (const struct clk_hw *[]) {1753 &gxbb_vapb_0.hw,1754 &gxbb_vapb_1.hw1755 },1756 .num_parents = 2,1757 .flags = CLK_SET_RATE_NO_REPARENT,1758 },1759};1760 1761static struct clk_regmap gxbb_vapb = {1762 .data = &(struct clk_regmap_gate_data){1763 .offset = HHI_VAPBCLK_CNTL,1764 .bit_idx = 30,1765 },1766 .hw.init = &(struct clk_init_data) {1767 .name = "vapb",1768 .ops = &clk_regmap_gate_ops,1769 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },1770 .num_parents = 1,1771 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1772 },1773};1774 1775/* Video Clocks */1776 1777static struct clk_regmap gxbb_vid_pll_div = {1778 .data = &(struct meson_vid_pll_div_data){1779 .val = {1780 .reg_off = HHI_VID_PLL_CLK_DIV,1781 .shift = 0,1782 .width = 15,1783 },1784 .sel = {1785 .reg_off = HHI_VID_PLL_CLK_DIV,1786 .shift = 16,1787 .width = 2,1788 },1789 },1790 .hw.init = &(struct clk_init_data) {1791 .name = "vid_pll_div",1792 .ops = &meson_vid_pll_div_ro_ops,1793 .parent_data = &(const struct clk_parent_data) {1794 /*1795 * Note:1796 * GXL and GXBB have different hdmi_plls (with1797 * different struct clk_hw). We fallback to the global1798 * naming string mechanism so vid_pll_div picks up the1799 * appropriate one.1800 */1801 .name = "hdmi_pll",1802 .index = -1,1803 },1804 .num_parents = 1,1805 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,1806 },1807};1808 1809static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {1810 { .hw = &gxbb_vid_pll_div.hw },1811 /*1812 * Note:1813 * GXL and GXBB have different hdmi_plls (with1814 * different struct clk_hw). We fallback to the global1815 * naming string mechanism so vid_pll_div picks up the1816 * appropriate one.1817 */1818 { .name = "hdmi_pll", .index = -1 },1819};1820 1821static struct clk_regmap gxbb_vid_pll_sel = {1822 .data = &(struct clk_regmap_mux_data){1823 .offset = HHI_VID_PLL_CLK_DIV,1824 .mask = 0x1,1825 .shift = 18,1826 },1827 .hw.init = &(struct clk_init_data){1828 .name = "vid_pll_sel",1829 .ops = &clk_regmap_mux_ops,1830 /*1831 * bit 18 selects from 2 possible parents:1832 * vid_pll_div or hdmi_pll1833 */1834 .parent_data = gxbb_vid_pll_parent_data,1835 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),1836 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,1837 },1838};1839 1840static struct clk_regmap gxbb_vid_pll = {1841 .data = &(struct clk_regmap_gate_data){1842 .offset = HHI_VID_PLL_CLK_DIV,1843 .bit_idx = 19,1844 },1845 .hw.init = &(struct clk_init_data) {1846 .name = "vid_pll",1847 .ops = &clk_regmap_gate_ops,1848 .parent_hws = (const struct clk_hw *[]) {1849 &gxbb_vid_pll_sel.hw1850 },1851 .num_parents = 1,1852 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1853 },1854};1855 1856static const struct clk_hw *gxbb_vclk_parent_hws[] = {1857 &gxbb_vid_pll.hw,1858 &gxbb_fclk_div4.hw,1859 &gxbb_fclk_div3.hw,1860 &gxbb_fclk_div5.hw,1861 &gxbb_vid_pll.hw,1862 &gxbb_fclk_div7.hw,1863 &gxbb_mpll1.hw,1864};1865 1866static struct clk_regmap gxbb_vclk_sel = {1867 .data = &(struct clk_regmap_mux_data){1868 .offset = HHI_VID_CLK_CNTL,1869 .mask = 0x7,1870 .shift = 16,1871 },1872 .hw.init = &(struct clk_init_data){1873 .name = "vclk_sel",1874 .ops = &clk_regmap_mux_ops,1875 /*1876 * bits 16:18 selects from 8 possible parents:1877 * vid_pll, fclk_div4, fclk_div3, fclk_div5,1878 * vid_pll, fclk_div7, mp11879 */1880 .parent_hws = gxbb_vclk_parent_hws,1881 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),1882 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,1883 },1884};1885 1886static struct clk_regmap gxbb_vclk2_sel = {1887 .data = &(struct clk_regmap_mux_data){1888 .offset = HHI_VIID_CLK_CNTL,1889 .mask = 0x7,1890 .shift = 16,1891 },1892 .hw.init = &(struct clk_init_data){1893 .name = "vclk2_sel",1894 .ops = &clk_regmap_mux_ops,1895 /*1896 * bits 16:18 selects from 8 possible parents:1897 * vid_pll, fclk_div4, fclk_div3, fclk_div5,1898 * vid_pll, fclk_div7, mp11899 */1900 .parent_hws = gxbb_vclk_parent_hws,1901 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),1902 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,1903 },1904};1905 1906static struct clk_regmap gxbb_vclk_input = {1907 .data = &(struct clk_regmap_gate_data){1908 .offset = HHI_VID_CLK_DIV,1909 .bit_idx = 16,1910 },1911 .hw.init = &(struct clk_init_data) {1912 .name = "vclk_input",1913 .ops = &clk_regmap_gate_ops,1914 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },1915 .num_parents = 1,1916 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1917 },1918};1919 1920static struct clk_regmap gxbb_vclk2_input = {1921 .data = &(struct clk_regmap_gate_data){1922 .offset = HHI_VIID_CLK_DIV,1923 .bit_idx = 16,1924 },1925 .hw.init = &(struct clk_init_data) {1926 .name = "vclk2_input",1927 .ops = &clk_regmap_gate_ops,1928 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },1929 .num_parents = 1,1930 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1931 },1932};1933 1934static struct clk_regmap gxbb_vclk_div = {1935 .data = &(struct clk_regmap_div_data){1936 .offset = HHI_VID_CLK_DIV,1937 .shift = 0,1938 .width = 8,1939 },1940 .hw.init = &(struct clk_init_data){1941 .name = "vclk_div",1942 .ops = &clk_regmap_divider_ops,1943 .parent_hws = (const struct clk_hw *[]) {1944 &gxbb_vclk_input.hw1945 },1946 .num_parents = 1,1947 .flags = CLK_GET_RATE_NOCACHE,1948 },1949};1950 1951static struct clk_regmap gxbb_vclk2_div = {1952 .data = &(struct clk_regmap_div_data){1953 .offset = HHI_VIID_CLK_DIV,1954 .shift = 0,1955 .width = 8,1956 },1957 .hw.init = &(struct clk_init_data){1958 .name = "vclk2_div",1959 .ops = &clk_regmap_divider_ops,1960 .parent_hws = (const struct clk_hw *[]) {1961 &gxbb_vclk2_input.hw1962 },1963 .num_parents = 1,1964 .flags = CLK_GET_RATE_NOCACHE,1965 },1966};1967 1968static struct clk_regmap gxbb_vclk = {1969 .data = &(struct clk_regmap_gate_data){1970 .offset = HHI_VID_CLK_CNTL,1971 .bit_idx = 19,1972 },1973 .hw.init = &(struct clk_init_data) {1974 .name = "vclk",1975 .ops = &clk_regmap_gate_ops,1976 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },1977 .num_parents = 1,1978 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1979 },1980};1981 1982static struct clk_regmap gxbb_vclk2 = {1983 .data = &(struct clk_regmap_gate_data){1984 .offset = HHI_VIID_CLK_CNTL,1985 .bit_idx = 19,1986 },1987 .hw.init = &(struct clk_init_data) {1988 .name = "vclk2",1989 .ops = &clk_regmap_gate_ops,1990 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },1991 .num_parents = 1,1992 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1993 },1994};1995 1996static struct clk_regmap gxbb_vclk_div1 = {1997 .data = &(struct clk_regmap_gate_data){1998 .offset = HHI_VID_CLK_CNTL,1999 .bit_idx = 0,2000 },2001 .hw.init = &(struct clk_init_data) {2002 .name = "vclk_div1",2003 .ops = &clk_regmap_gate_ops,2004 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },2005 .num_parents = 1,2006 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2007 },2008};2009 2010static struct clk_regmap gxbb_vclk_div2_en = {2011 .data = &(struct clk_regmap_gate_data){2012 .offset = HHI_VID_CLK_CNTL,2013 .bit_idx = 1,2014 },2015 .hw.init = &(struct clk_init_data) {2016 .name = "vclk_div2_en",2017 .ops = &clk_regmap_gate_ops,2018 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },2019 .num_parents = 1,2020 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2021 },2022};2023 2024static struct clk_regmap gxbb_vclk_div4_en = {2025 .data = &(struct clk_regmap_gate_data){2026 .offset = HHI_VID_CLK_CNTL,2027 .bit_idx = 2,2028 },2029 .hw.init = &(struct clk_init_data) {2030 .name = "vclk_div4_en",2031 .ops = &clk_regmap_gate_ops,2032 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },2033 .num_parents = 1,2034 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2035 },2036};2037 2038static struct clk_regmap gxbb_vclk_div6_en = {2039 .data = &(struct clk_regmap_gate_data){2040 .offset = HHI_VID_CLK_CNTL,2041 .bit_idx = 3,2042 },2043 .hw.init = &(struct clk_init_data) {2044 .name = "vclk_div6_en",2045 .ops = &clk_regmap_gate_ops,2046 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },2047 .num_parents = 1,2048 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2049 },2050};2051 2052static struct clk_regmap gxbb_vclk_div12_en = {2053 .data = &(struct clk_regmap_gate_data){2054 .offset = HHI_VID_CLK_CNTL,2055 .bit_idx = 4,2056 },2057 .hw.init = &(struct clk_init_data) {2058 .name = "vclk_div12_en",2059 .ops = &clk_regmap_gate_ops,2060 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },2061 .num_parents = 1,2062 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2063 },2064};2065 2066static struct clk_regmap gxbb_vclk2_div1 = {2067 .data = &(struct clk_regmap_gate_data){2068 .offset = HHI_VIID_CLK_CNTL,2069 .bit_idx = 0,2070 },2071 .hw.init = &(struct clk_init_data) {2072 .name = "vclk2_div1",2073 .ops = &clk_regmap_gate_ops,2074 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },2075 .num_parents = 1,2076 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2077 },2078};2079 2080static struct clk_regmap gxbb_vclk2_div2_en = {2081 .data = &(struct clk_regmap_gate_data){2082 .offset = HHI_VIID_CLK_CNTL,2083 .bit_idx = 1,2084 },2085 .hw.init = &(struct clk_init_data) {2086 .name = "vclk2_div2_en",2087 .ops = &clk_regmap_gate_ops,2088 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },2089 .num_parents = 1,2090 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2091 },2092};2093 2094static struct clk_regmap gxbb_vclk2_div4_en = {2095 .data = &(struct clk_regmap_gate_data){2096 .offset = HHI_VIID_CLK_CNTL,2097 .bit_idx = 2,2098 },2099 .hw.init = &(struct clk_init_data) {2100 .name = "vclk2_div4_en",2101 .ops = &clk_regmap_gate_ops,2102 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },2103 .num_parents = 1,2104 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2105 },2106};2107 2108static struct clk_regmap gxbb_vclk2_div6_en = {2109 .data = &(struct clk_regmap_gate_data){2110 .offset = HHI_VIID_CLK_CNTL,2111 .bit_idx = 3,2112 },2113 .hw.init = &(struct clk_init_data) {2114 .name = "vclk2_div6_en",2115 .ops = &clk_regmap_gate_ops,2116 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },2117 .num_parents = 1,2118 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2119 },2120};2121 2122static struct clk_regmap gxbb_vclk2_div12_en = {2123 .data = &(struct clk_regmap_gate_data){2124 .offset = HHI_VIID_CLK_CNTL,2125 .bit_idx = 4,2126 },2127 .hw.init = &(struct clk_init_data) {2128 .name = "vclk2_div12_en",2129 .ops = &clk_regmap_gate_ops,2130 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },2131 .num_parents = 1,2132 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2133 },2134};2135 2136static struct clk_fixed_factor gxbb_vclk_div2 = {2137 .mult = 1,2138 .div = 2,2139 .hw.init = &(struct clk_init_data){2140 .name = "vclk_div2",2141 .ops = &clk_fixed_factor_ops,2142 .parent_hws = (const struct clk_hw *[]) {2143 &gxbb_vclk_div2_en.hw2144 },2145 .num_parents = 1,2146 },2147};2148 2149static struct clk_fixed_factor gxbb_vclk_div4 = {2150 .mult = 1,2151 .div = 4,2152 .hw.init = &(struct clk_init_data){2153 .name = "vclk_div4",2154 .ops = &clk_fixed_factor_ops,2155 .parent_hws = (const struct clk_hw *[]) {2156 &gxbb_vclk_div4_en.hw2157 },2158 .num_parents = 1,2159 },2160};2161 2162static struct clk_fixed_factor gxbb_vclk_div6 = {2163 .mult = 1,2164 .div = 6,2165 .hw.init = &(struct clk_init_data){2166 .name = "vclk_div6",2167 .ops = &clk_fixed_factor_ops,2168 .parent_hws = (const struct clk_hw *[]) {2169 &gxbb_vclk_div6_en.hw2170 },2171 .num_parents = 1,2172 },2173};2174 2175static struct clk_fixed_factor gxbb_vclk_div12 = {2176 .mult = 1,2177 .div = 12,2178 .hw.init = &(struct clk_init_data){2179 .name = "vclk_div12",2180 .ops = &clk_fixed_factor_ops,2181 .parent_hws = (const struct clk_hw *[]) {2182 &gxbb_vclk_div12_en.hw2183 },2184 .num_parents = 1,2185 },2186};2187 2188static struct clk_fixed_factor gxbb_vclk2_div2 = {2189 .mult = 1,2190 .div = 2,2191 .hw.init = &(struct clk_init_data){2192 .name = "vclk2_div2",2193 .ops = &clk_fixed_factor_ops,2194 .parent_hws = (const struct clk_hw *[]) {2195 &gxbb_vclk2_div2_en.hw2196 },2197 .num_parents = 1,2198 },2199};2200 2201static struct clk_fixed_factor gxbb_vclk2_div4 = {2202 .mult = 1,2203 .div = 4,2204 .hw.init = &(struct clk_init_data){2205 .name = "vclk2_div4",2206 .ops = &clk_fixed_factor_ops,2207 .parent_hws = (const struct clk_hw *[]) {2208 &gxbb_vclk2_div4_en.hw2209 },2210 .num_parents = 1,2211 },2212};2213 2214static struct clk_fixed_factor gxbb_vclk2_div6 = {2215 .mult = 1,2216 .div = 6,2217 .hw.init = &(struct clk_init_data){2218 .name = "vclk2_div6",2219 .ops = &clk_fixed_factor_ops,2220 .parent_hws = (const struct clk_hw *[]) {2221 &gxbb_vclk2_div6_en.hw2222 },2223 .num_parents = 1,2224 },2225};2226 2227static struct clk_fixed_factor gxbb_vclk2_div12 = {2228 .mult = 1,2229 .div = 12,2230 .hw.init = &(struct clk_init_data){2231 .name = "vclk2_div12",2232 .ops = &clk_fixed_factor_ops,2233 .parent_hws = (const struct clk_hw *[]) {2234 &gxbb_vclk2_div12_en.hw2235 },2236 .num_parents = 1,2237 },2238};2239 2240static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };2241static const struct clk_hw *gxbb_cts_parent_hws[] = {2242 &gxbb_vclk_div1.hw,2243 &gxbb_vclk_div2.hw,2244 &gxbb_vclk_div4.hw,2245 &gxbb_vclk_div6.hw,2246 &gxbb_vclk_div12.hw,2247 &gxbb_vclk2_div1.hw,2248 &gxbb_vclk2_div2.hw,2249 &gxbb_vclk2_div4.hw,2250 &gxbb_vclk2_div6.hw,2251 &gxbb_vclk2_div12.hw,2252};2253 2254static struct clk_regmap gxbb_cts_enci_sel = {2255 .data = &(struct clk_regmap_mux_data){2256 .offset = HHI_VID_CLK_DIV,2257 .mask = 0xf,2258 .shift = 28,2259 .table = mux_table_cts_sel,2260 },2261 .hw.init = &(struct clk_init_data){2262 .name = "cts_enci_sel",2263 .ops = &clk_regmap_mux_ops,2264 .parent_hws = gxbb_cts_parent_hws,2265 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),2266 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2267 },2268};2269 2270static struct clk_regmap gxbb_cts_encp_sel = {2271 .data = &(struct clk_regmap_mux_data){2272 .offset = HHI_VID_CLK_DIV,2273 .mask = 0xf,2274 .shift = 20,2275 .table = mux_table_cts_sel,2276 },2277 .hw.init = &(struct clk_init_data){2278 .name = "cts_encp_sel",2279 .ops = &clk_regmap_mux_ops,2280 .parent_hws = gxbb_cts_parent_hws,2281 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),2282 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2283 },2284};2285 2286static struct clk_regmap gxbb_cts_vdac_sel = {2287 .data = &(struct clk_regmap_mux_data){2288 .offset = HHI_VIID_CLK_DIV,2289 .mask = 0xf,2290 .shift = 28,2291 .table = mux_table_cts_sel,2292 },2293 .hw.init = &(struct clk_init_data){2294 .name = "cts_vdac_sel",2295 .ops = &clk_regmap_mux_ops,2296 .parent_hws = gxbb_cts_parent_hws,2297 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),2298 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2299 },2300};2301 2302/* TOFIX: add support for cts_tcon */2303static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };2304static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {2305 &gxbb_vclk_div1.hw,2306 &gxbb_vclk_div2.hw,2307 &gxbb_vclk_div4.hw,2308 &gxbb_vclk_div6.hw,2309 &gxbb_vclk_div12.hw,2310 &gxbb_vclk2_div1.hw,2311 &gxbb_vclk2_div2.hw,2312 &gxbb_vclk2_div4.hw,2313 &gxbb_vclk2_div6.hw,2314 &gxbb_vclk2_div12.hw,2315};2316 2317static struct clk_regmap gxbb_hdmi_tx_sel = {2318 .data = &(struct clk_regmap_mux_data){2319 .offset = HHI_HDMI_CLK_CNTL,2320 .mask = 0xf,2321 .shift = 16,2322 .table = mux_table_hdmi_tx_sel,2323 },2324 .hw.init = &(struct clk_init_data){2325 .name = "hdmi_tx_sel",2326 .ops = &clk_regmap_mux_ops,2327 /*2328 * bits 31:28 selects from 12 possible parents:2329 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div122330 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,2331 * cts_tcon2332 */2333 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,2334 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),2335 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2336 },2337};2338 2339static struct clk_regmap gxbb_cts_enci = {2340 .data = &(struct clk_regmap_gate_data){2341 .offset = HHI_VID_CLK_CNTL2,2342 .bit_idx = 0,2343 },2344 .hw.init = &(struct clk_init_data) {2345 .name = "cts_enci",2346 .ops = &clk_regmap_gate_ops,2347 .parent_hws = (const struct clk_hw *[]) {2348 &gxbb_cts_enci_sel.hw2349 },2350 .num_parents = 1,2351 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2352 },2353};2354 2355static struct clk_regmap gxbb_cts_encp = {2356 .data = &(struct clk_regmap_gate_data){2357 .offset = HHI_VID_CLK_CNTL2,2358 .bit_idx = 2,2359 },2360 .hw.init = &(struct clk_init_data) {2361 .name = "cts_encp",2362 .ops = &clk_regmap_gate_ops,2363 .parent_hws = (const struct clk_hw *[]) {2364 &gxbb_cts_encp_sel.hw2365 },2366 .num_parents = 1,2367 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2368 },2369};2370 2371static struct clk_regmap gxbb_cts_vdac = {2372 .data = &(struct clk_regmap_gate_data){2373 .offset = HHI_VID_CLK_CNTL2,2374 .bit_idx = 4,2375 },2376 .hw.init = &(struct clk_init_data) {2377 .name = "cts_vdac",2378 .ops = &clk_regmap_gate_ops,2379 .parent_hws = (const struct clk_hw *[]) {2380 &gxbb_cts_vdac_sel.hw2381 },2382 .num_parents = 1,2383 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2384 },2385};2386 2387static struct clk_regmap gxbb_hdmi_tx = {2388 .data = &(struct clk_regmap_gate_data){2389 .offset = HHI_VID_CLK_CNTL2,2390 .bit_idx = 5,2391 },2392 .hw.init = &(struct clk_init_data) {2393 .name = "hdmi_tx",2394 .ops = &clk_regmap_gate_ops,2395 .parent_hws = (const struct clk_hw *[]) {2396 &gxbb_hdmi_tx_sel.hw2397 },2398 .num_parents = 1,2399 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2400 },2401};2402 2403/* HDMI Clocks */2404 2405static const struct clk_parent_data gxbb_hdmi_parent_data[] = {2406 { .fw_name = "xtal", },2407 { .hw = &gxbb_fclk_div4.hw },2408 { .hw = &gxbb_fclk_div3.hw },2409 { .hw = &gxbb_fclk_div5.hw },2410};2411 2412static struct clk_regmap gxbb_hdmi_sel = {2413 .data = &(struct clk_regmap_mux_data){2414 .offset = HHI_HDMI_CLK_CNTL,2415 .mask = 0x3,2416 .shift = 9,2417 .flags = CLK_MUX_ROUND_CLOSEST,2418 },2419 .hw.init = &(struct clk_init_data){2420 .name = "hdmi_sel",2421 .ops = &clk_regmap_mux_ops,2422 .parent_data = gxbb_hdmi_parent_data,2423 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),2424 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,2425 },2426};2427 2428static struct clk_regmap gxbb_hdmi_div = {2429 .data = &(struct clk_regmap_div_data){2430 .offset = HHI_HDMI_CLK_CNTL,2431 .shift = 0,2432 .width = 7,2433 },2434 .hw.init = &(struct clk_init_data){2435 .name = "hdmi_div",2436 .ops = &clk_regmap_divider_ops,2437 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },2438 .num_parents = 1,2439 .flags = CLK_GET_RATE_NOCACHE,2440 },2441};2442 2443static struct clk_regmap gxbb_hdmi = {2444 .data = &(struct clk_regmap_gate_data){2445 .offset = HHI_HDMI_CLK_CNTL,2446 .bit_idx = 8,2447 },2448 .hw.init = &(struct clk_init_data) {2449 .name = "hdmi",2450 .ops = &clk_regmap_gate_ops,2451 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },2452 .num_parents = 1,2453 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,2454 },2455};2456 2457/* VDEC clocks */2458 2459static const struct clk_hw *gxbb_vdec_parent_hws[] = {2460 &gxbb_fclk_div4.hw,2461 &gxbb_fclk_div3.hw,2462 &gxbb_fclk_div5.hw,2463 &gxbb_fclk_div7.hw,2464};2465 2466static struct clk_regmap gxbb_vdec_1_sel = {2467 .data = &(struct clk_regmap_mux_data){2468 .offset = HHI_VDEC_CLK_CNTL,2469 .mask = 0x3,2470 .shift = 9,2471 .flags = CLK_MUX_ROUND_CLOSEST,2472 },2473 .hw.init = &(struct clk_init_data){2474 .name = "vdec_1_sel",2475 .ops = &clk_regmap_mux_ops,2476 .parent_hws = gxbb_vdec_parent_hws,2477 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),2478 .flags = CLK_SET_RATE_PARENT,2479 },2480};2481 2482static struct clk_regmap gxbb_vdec_1_div = {2483 .data = &(struct clk_regmap_div_data){2484 .offset = HHI_VDEC_CLK_CNTL,2485 .shift = 0,2486 .width = 7,2487 .flags = CLK_DIVIDER_ROUND_CLOSEST,2488 },2489 .hw.init = &(struct clk_init_data){2490 .name = "vdec_1_div",2491 .ops = &clk_regmap_divider_ops,2492 .parent_hws = (const struct clk_hw *[]) {2493 &gxbb_vdec_1_sel.hw2494 },2495 .num_parents = 1,2496 .flags = CLK_SET_RATE_PARENT,2497 },2498};2499 2500static struct clk_regmap gxbb_vdec_1 = {2501 .data = &(struct clk_regmap_gate_data){2502 .offset = HHI_VDEC_CLK_CNTL,2503 .bit_idx = 8,2504 },2505 .hw.init = &(struct clk_init_data) {2506 .name = "vdec_1",2507 .ops = &clk_regmap_gate_ops,2508 .parent_hws = (const struct clk_hw *[]) {2509 &gxbb_vdec_1_div.hw2510 },2511 .num_parents = 1,2512 .flags = CLK_SET_RATE_PARENT,2513 },2514};2515 2516static struct clk_regmap gxbb_vdec_hevc_sel = {2517 .data = &(struct clk_regmap_mux_data){2518 .offset = HHI_VDEC2_CLK_CNTL,2519 .mask = 0x3,2520 .shift = 25,2521 .flags = CLK_MUX_ROUND_CLOSEST,2522 },2523 .hw.init = &(struct clk_init_data){2524 .name = "vdec_hevc_sel",2525 .ops = &clk_regmap_mux_ops,2526 .parent_hws = gxbb_vdec_parent_hws,2527 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),2528 .flags = CLK_SET_RATE_PARENT,2529 },2530};2531 2532static struct clk_regmap gxbb_vdec_hevc_div = {2533 .data = &(struct clk_regmap_div_data){2534 .offset = HHI_VDEC2_CLK_CNTL,2535 .shift = 16,2536 .width = 7,2537 .flags = CLK_DIVIDER_ROUND_CLOSEST,2538 },2539 .hw.init = &(struct clk_init_data){2540 .name = "vdec_hevc_div",2541 .ops = &clk_regmap_divider_ops,2542 .parent_hws = (const struct clk_hw *[]) {2543 &gxbb_vdec_hevc_sel.hw2544 },2545 .num_parents = 1,2546 .flags = CLK_SET_RATE_PARENT,2547 },2548};2549 2550static struct clk_regmap gxbb_vdec_hevc = {2551 .data = &(struct clk_regmap_gate_data){2552 .offset = HHI_VDEC2_CLK_CNTL,2553 .bit_idx = 24,2554 },2555 .hw.init = &(struct clk_init_data) {2556 .name = "vdec_hevc",2557 .ops = &clk_regmap_gate_ops,2558 .parent_hws = (const struct clk_hw *[]) {2559 &gxbb_vdec_hevc_div.hw2560 },2561 .num_parents = 1,2562 .flags = CLK_SET_RATE_PARENT,2563 },2564};2565 2566static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,2567 9, 10, 11, 13, 14, };2568static const struct clk_parent_data gen_clk_parent_data[] = {2569 { .fw_name = "xtal", },2570 { .hw = &gxbb_vdec_1.hw },2571 { .hw = &gxbb_vdec_hevc.hw },2572 { .hw = &gxbb_mpll0.hw },2573 { .hw = &gxbb_mpll1.hw },2574 { .hw = &gxbb_mpll2.hw },2575 { .hw = &gxbb_fclk_div4.hw },2576 { .hw = &gxbb_fclk_div3.hw },2577 { .hw = &gxbb_fclk_div5.hw },2578 { .hw = &gxbb_fclk_div7.hw },2579 { .hw = &gxbb_gp0_pll.hw },2580};2581 2582static struct clk_regmap gxbb_gen_clk_sel = {2583 .data = &(struct clk_regmap_mux_data){2584 .offset = HHI_GEN_CLK_CNTL,2585 .mask = 0xf,2586 .shift = 12,2587 .table = mux_table_gen_clk,2588 },2589 .hw.init = &(struct clk_init_data){2590 .name = "gen_clk_sel",2591 .ops = &clk_regmap_mux_ops,2592 /*2593 * bits 15:12 selects from 14 possible parents:2594 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],2595 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,2596 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll2597 */2598 .parent_data = gen_clk_parent_data,2599 .num_parents = ARRAY_SIZE(gen_clk_parent_data),2600 },2601};2602 2603static struct clk_regmap gxbb_gen_clk_div = {2604 .data = &(struct clk_regmap_div_data){2605 .offset = HHI_GEN_CLK_CNTL,2606 .shift = 0,2607 .width = 11,2608 },2609 .hw.init = &(struct clk_init_data){2610 .name = "gen_clk_div",2611 .ops = &clk_regmap_divider_ops,2612 .parent_hws = (const struct clk_hw *[]) {2613 &gxbb_gen_clk_sel.hw2614 },2615 .num_parents = 1,2616 .flags = CLK_SET_RATE_PARENT,2617 },2618};2619 2620static struct clk_regmap gxbb_gen_clk = {2621 .data = &(struct clk_regmap_gate_data){2622 .offset = HHI_GEN_CLK_CNTL,2623 .bit_idx = 7,2624 },2625 .hw.init = &(struct clk_init_data){2626 .name = "gen_clk",2627 .ops = &clk_regmap_gate_ops,2628 .parent_hws = (const struct clk_hw *[]) {2629 &gxbb_gen_clk_div.hw2630 },2631 .num_parents = 1,2632 .flags = CLK_SET_RATE_PARENT,2633 },2634};2635 2636#define MESON_GATE(_name, _reg, _bit) \2637 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)2638 2639/* Everything Else (EE) domain gates */2640static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);2641static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);2642static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);2643static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);2644static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);2645static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);2646static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);2647static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);2648static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);2649static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);2650static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);2651static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);2652static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);2653static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);2654static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);2655static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);2656static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);2657static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);2658static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);2659static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);2660static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);2661static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);2662static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);2663 2664static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);2665static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);2666static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);2667static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);2668static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);2669static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);2670static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);2671static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);2672static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);2673static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);2674static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);2675static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);2676static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);2677static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);2678static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);2679static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);2680static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);2681 2682static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);2683static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);2684static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);2685static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);2686static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);2687static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);2688static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);2689static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);2690static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);2691static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);2692static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);2693static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);2694static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);2695 2696static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);2697static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);2698static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);2699static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);2700static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);2701static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);2702static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);2703static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);2704static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);2705static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);2706static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);2707static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);2708static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);2709static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);2710static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);2711static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);2712 2713/* Always On (AO) domain gates */2714 2715static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);2716static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);2717static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);2718static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);2719static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);2720 2721/* AIU gates */2722static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);2723static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);2724static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);2725static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);2726static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);2727static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);2728static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);2729static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);2730 2731/* Array of all clocks provided by this provider */2732 2733static struct clk_hw *gxbb_hw_clks[] = {2734 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,2735 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,2736 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,2737 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,2738 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,2739 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,2740 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,2741 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,2742 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,2743 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,2744 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,2745 [CLKID_CLK81] = &gxbb_clk81.hw,2746 [CLKID_MPLL0] = &gxbb_mpll0.hw,2747 [CLKID_MPLL1] = &gxbb_mpll1.hw,2748 [CLKID_MPLL2] = &gxbb_mpll2.hw,2749 [CLKID_DDR] = &gxbb_ddr.hw,2750 [CLKID_DOS] = &gxbb_dos.hw,2751 [CLKID_ISA] = &gxbb_isa.hw,2752 [CLKID_PL301] = &gxbb_pl301.hw,2753 [CLKID_PERIPHS] = &gxbb_periphs.hw,2754 [CLKID_SPICC] = &gxbb_spicc.hw,2755 [CLKID_I2C] = &gxbb_i2c.hw,2756 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,2757 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,2758 [CLKID_RNG0] = &gxbb_rng0.hw,2759 [CLKID_UART0] = &gxbb_uart0.hw,2760 [CLKID_SDHC] = &gxbb_sdhc.hw,2761 [CLKID_STREAM] = &gxbb_stream.hw,2762 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,2763 [CLKID_SDIO] = &gxbb_sdio.hw,2764 [CLKID_ABUF] = &gxbb_abuf.hw,2765 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,2766 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,2767 [CLKID_SPI] = &gxbb_spi.hw,2768 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,2769 [CLKID_ETH] = &gxbb_eth.hw,2770 [CLKID_DEMUX] = &gxbb_demux.hw,2771 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,2772 [CLKID_IEC958] = &gxbb_iec958.hw,2773 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,2774 [CLKID_AMCLK] = &gxbb_amclk.hw,2775 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,2776 [CLKID_MIXER] = &gxbb_mixer.hw,2777 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,2778 [CLKID_ADC] = &gxbb_adc.hw,2779 [CLKID_BLKMV] = &gxbb_blkmv.hw,2780 [CLKID_AIU] = &gxbb_aiu.hw,2781 [CLKID_UART1] = &gxbb_uart1.hw,2782 [CLKID_G2D] = &gxbb_g2d.hw,2783 [CLKID_USB0] = &gxbb_usb0.hw,2784 [CLKID_USB1] = &gxbb_usb1.hw,2785 [CLKID_RESET] = &gxbb_reset.hw,2786 [CLKID_NAND] = &gxbb_nand.hw,2787 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,2788 [CLKID_USB] = &gxbb_usb.hw,2789 [CLKID_VDIN1] = &gxbb_vdin1.hw,2790 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,2791 [CLKID_EFUSE] = &gxbb_efuse.hw,2792 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,2793 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,2794 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,2795 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,2796 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,2797 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,2798 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,2799 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,2800 [CLKID_DVIN] = &gxbb_dvin.hw,2801 [CLKID_UART2] = &gxbb_uart2.hw,2802 [CLKID_SANA] = &gxbb_sana.hw,2803 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,2804 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,2805 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,2806 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,2807 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,2808 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,2809 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,2810 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,2811 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,2812 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,2813 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,2814 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,2815 [CLKID_ENC480P] = &gxbb_enc480p.hw,2816 [CLKID_RNG1] = &gxbb_rng1.hw,2817 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,2818 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,2819 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,2820 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,2821 [CLKID_EDP] = &gxbb_edp.hw,2822 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,2823 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,2824 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,2825 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,2826 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,2827 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,2828 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,2829 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,2830 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,2831 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,2832 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,2833 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,2834 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,2835 [CLKID_MALI_0] = &gxbb_mali_0.hw,2836 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,2837 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,2838 [CLKID_MALI_1] = &gxbb_mali_1.hw,2839 [CLKID_MALI] = &gxbb_mali.hw,2840 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,2841 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,2842 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,2843 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,2844 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,2845 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,2846 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,2847 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,2848 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,2849 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,2850 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,2851 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,2852 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,2853 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,2854 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,2855 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,2856 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,2857 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,2858 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,2859 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,2860 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,2861 [CLKID_VPU_0] = &gxbb_vpu_0.hw,2862 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,2863 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,2864 [CLKID_VPU_1] = &gxbb_vpu_1.hw,2865 [CLKID_VPU] = &gxbb_vpu.hw,2866 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,2867 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,2868 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,2869 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,2870 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,2871 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,2872 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,2873 [CLKID_VAPB] = &gxbb_vapb.hw,2874 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,2875 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,2876 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,2877 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,2878 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,2879 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,2880 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,2881 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,2882 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,2883 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,2884 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,2885 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,2886 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,2887 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,2888 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,2889 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,2890 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,2891 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,2892 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,2893 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,2894 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,2895 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,2896 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,2897 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,2898 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,2899 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,2900 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,2901 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,2902 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,2903 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,2904 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,2905 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,2906 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,2907 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,2908 [CLKID_VCLK] = &gxbb_vclk.hw,2909 [CLKID_VCLK2] = &gxbb_vclk2.hw,2910 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,2911 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,2912 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,2913 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,2914 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,2915 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,2916 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,2917 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,2918 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,2919 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,2920 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,2921 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,2922 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,2923 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,2924 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,2925 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,2926 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,2927 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,2928 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,2929 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,2930 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,2931 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,2932 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,2933 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,2934 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,2935 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,2936 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,2937 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,2938 [CLKID_HDMI] = &gxbb_hdmi.hw,2939};2940 2941static struct clk_hw *gxl_hw_clks[] = {2942 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,2943 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,2944 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,2945 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,2946 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,2947 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,2948 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,2949 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,2950 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,2951 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,2952 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,2953 [CLKID_CLK81] = &gxbb_clk81.hw,2954 [CLKID_MPLL0] = &gxbb_mpll0.hw,2955 [CLKID_MPLL1] = &gxbb_mpll1.hw,2956 [CLKID_MPLL2] = &gxbb_mpll2.hw,2957 [CLKID_DDR] = &gxbb_ddr.hw,2958 [CLKID_DOS] = &gxbb_dos.hw,2959 [CLKID_ISA] = &gxbb_isa.hw,2960 [CLKID_PL301] = &gxbb_pl301.hw,2961 [CLKID_PERIPHS] = &gxbb_periphs.hw,2962 [CLKID_SPICC] = &gxbb_spicc.hw,2963 [CLKID_I2C] = &gxbb_i2c.hw,2964 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,2965 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,2966 [CLKID_RNG0] = &gxbb_rng0.hw,2967 [CLKID_UART0] = &gxbb_uart0.hw,2968 [CLKID_SDHC] = &gxbb_sdhc.hw,2969 [CLKID_STREAM] = &gxbb_stream.hw,2970 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,2971 [CLKID_SDIO] = &gxbb_sdio.hw,2972 [CLKID_ABUF] = &gxbb_abuf.hw,2973 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,2974 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,2975 [CLKID_SPI] = &gxbb_spi.hw,2976 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,2977 [CLKID_ETH] = &gxbb_eth.hw,2978 [CLKID_DEMUX] = &gxbb_demux.hw,2979 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,2980 [CLKID_IEC958] = &gxbb_iec958.hw,2981 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,2982 [CLKID_AMCLK] = &gxbb_amclk.hw,2983 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,2984 [CLKID_MIXER] = &gxbb_mixer.hw,2985 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,2986 [CLKID_ADC] = &gxbb_adc.hw,2987 [CLKID_BLKMV] = &gxbb_blkmv.hw,2988 [CLKID_AIU] = &gxbb_aiu.hw,2989 [CLKID_UART1] = &gxbb_uart1.hw,2990 [CLKID_G2D] = &gxbb_g2d.hw,2991 [CLKID_USB0] = &gxbb_usb0.hw,2992 [CLKID_USB1] = &gxbb_usb1.hw,2993 [CLKID_RESET] = &gxbb_reset.hw,2994 [CLKID_NAND] = &gxbb_nand.hw,2995 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,2996 [CLKID_USB] = &gxbb_usb.hw,2997 [CLKID_VDIN1] = &gxbb_vdin1.hw,2998 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,2999 [CLKID_EFUSE] = &gxbb_efuse.hw,3000 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,3001 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,3002 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,3003 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,3004 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,3005 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,3006 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,3007 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,3008 [CLKID_DVIN] = &gxbb_dvin.hw,3009 [CLKID_UART2] = &gxbb_uart2.hw,3010 [CLKID_SANA] = &gxbb_sana.hw,3011 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,3012 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,3013 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,3014 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,3015 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,3016 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,3017 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,3018 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,3019 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,3020 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,3021 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,3022 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,3023 [CLKID_ENC480P] = &gxbb_enc480p.hw,3024 [CLKID_RNG1] = &gxbb_rng1.hw,3025 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,3026 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,3027 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,3028 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,3029 [CLKID_EDP] = &gxbb_edp.hw,3030 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,3031 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,3032 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,3033 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,3034 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,3035 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,3036 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,3037 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,3038 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,3039 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,3040 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,3041 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,3042 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,3043 [CLKID_MALI_0] = &gxbb_mali_0.hw,3044 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,3045 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,3046 [CLKID_MALI_1] = &gxbb_mali_1.hw,3047 [CLKID_MALI] = &gxbb_mali.hw,3048 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,3049 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,3050 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,3051 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,3052 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,3053 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,3054 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,3055 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,3056 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,3057 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,3058 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,3059 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,3060 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,3061 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,3062 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,3063 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,3064 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,3065 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,3066 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,3067 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,3068 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,3069 [CLKID_VPU_0] = &gxbb_vpu_0.hw,3070 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,3071 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,3072 [CLKID_VPU_1] = &gxbb_vpu_1.hw,3073 [CLKID_VPU] = &gxbb_vpu.hw,3074 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,3075 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,3076 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,3077 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,3078 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,3079 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,3080 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,3081 [CLKID_VAPB] = &gxbb_vapb.hw,3082 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,3083 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,3084 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,3085 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,3086 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,3087 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,3088 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,3089 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,3090 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,3091 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,3092 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,3093 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,3094 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,3095 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,3096 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,3097 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,3098 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,3099 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,3100 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,3101 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,3102 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,3103 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,3104 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,3105 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,3106 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,3107 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,3108 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,3109 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,3110 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,3111 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,3112 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,3113 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,3114 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,3115 [CLKID_VCLK] = &gxbb_vclk.hw,3116 [CLKID_VCLK2] = &gxbb_vclk2.hw,3117 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,3118 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,3119 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,3120 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,3121 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,3122 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,3123 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,3124 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,3125 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,3126 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,3127 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,3128 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,3129 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,3130 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,3131 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,3132 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,3133 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,3134 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,3135 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,3136 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,3137 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,3138 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,3139 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,3140 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,3141 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,3142 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,3143 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,3144 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,3145 [CLKID_HDMI] = &gxbb_hdmi.hw,3146 [CLKID_ACODEC] = &gxl_acodec.hw,3147};3148 3149static struct clk_regmap *const gxbb_clk_regmaps[] = {3150 &gxbb_clk81,3151 &gxbb_ddr,3152 &gxbb_dos,3153 &gxbb_isa,3154 &gxbb_pl301,3155 &gxbb_periphs,3156 &gxbb_spicc,3157 &gxbb_i2c,3158 &gxbb_sar_adc,3159 &gxbb_smart_card,3160 &gxbb_rng0,3161 &gxbb_uart0,3162 &gxbb_sdhc,3163 &gxbb_stream,3164 &gxbb_async_fifo,3165 &gxbb_sdio,3166 &gxbb_abuf,3167 &gxbb_hiu_iface,3168 &gxbb_assist_misc,3169 &gxbb_spi,3170 &gxbb_i2s_spdif,3171 &gxbb_eth,3172 &gxbb_demux,3173 &gxbb_aiu_glue,3174 &gxbb_iec958,3175 &gxbb_i2s_out,3176 &gxbb_amclk,3177 &gxbb_aififo2,3178 &gxbb_mixer,3179 &gxbb_mixer_iface,3180 &gxbb_adc,3181 &gxbb_blkmv,3182 &gxbb_aiu,3183 &gxbb_uart1,3184 &gxbb_g2d,3185 &gxbb_usb0,3186 &gxbb_usb1,3187 &gxbb_reset,3188 &gxbb_nand,3189 &gxbb_dos_parser,3190 &gxbb_usb,3191 &gxbb_vdin1,3192 &gxbb_ahb_arb0,3193 &gxbb_efuse,3194 &gxbb_boot_rom,3195 &gxbb_ahb_data_bus,3196 &gxbb_ahb_ctrl_bus,3197 &gxbb_hdmi_intr_sync,3198 &gxbb_hdmi_pclk,3199 &gxbb_usb1_ddr_bridge,3200 &gxbb_usb0_ddr_bridge,3201 &gxbb_mmc_pclk,3202 &gxbb_dvin,3203 &gxbb_uart2,3204 &gxbb_sana,3205 &gxbb_vpu_intr,3206 &gxbb_sec_ahb_ahb3_bridge,3207 &gxbb_clk81_a53,3208 &gxbb_vclk2_venci0,3209 &gxbb_vclk2_venci1,3210 &gxbb_vclk2_vencp0,3211 &gxbb_vclk2_vencp1,3212 &gxbb_gclk_venci_int0,3213 &gxbb_gclk_vencp_int,3214 &gxbb_dac_clk,3215 &gxbb_aoclk_gate,3216 &gxbb_iec958_gate,3217 &gxbb_enc480p,3218 &gxbb_rng1,3219 &gxbb_gclk_venci_int1,3220 &gxbb_vclk2_venclmcc,3221 &gxbb_vclk2_vencl,3222 &gxbb_vclk_other,3223 &gxbb_edp,3224 &gxbb_ao_media_cpu,3225 &gxbb_ao_ahb_sram,3226 &gxbb_ao_ahb_bus,3227 &gxbb_ao_iface,3228 &gxbb_ao_i2c,3229 &gxbb_emmc_a,3230 &gxbb_emmc_b,3231 &gxbb_emmc_c,3232 &gxbb_sar_adc_clk,3233 &gxbb_mali_0,3234 &gxbb_mali_1,3235 &gxbb_cts_amclk,3236 &gxbb_cts_mclk_i958,3237 &gxbb_32k_clk,3238 &gxbb_sd_emmc_a_clk0,3239 &gxbb_sd_emmc_b_clk0,3240 &gxbb_sd_emmc_c_clk0,3241 &gxbb_vpu_0,3242 &gxbb_vpu_1,3243 &gxbb_vapb_0,3244 &gxbb_vapb_1,3245 &gxbb_vapb,3246 &gxbb_mpeg_clk_div,3247 &gxbb_sar_adc_clk_div,3248 &gxbb_mali_0_div,3249 &gxbb_mali_1_div,3250 &gxbb_cts_mclk_i958_div,3251 &gxbb_32k_clk_div,3252 &gxbb_sd_emmc_a_clk0_div,3253 &gxbb_sd_emmc_b_clk0_div,3254 &gxbb_sd_emmc_c_clk0_div,3255 &gxbb_vpu_0_div,3256 &gxbb_vpu_1_div,3257 &gxbb_vapb_0_div,3258 &gxbb_vapb_1_div,3259 &gxbb_mpeg_clk_sel,3260 &gxbb_sar_adc_clk_sel,3261 &gxbb_mali_0_sel,3262 &gxbb_mali_1_sel,3263 &gxbb_mali,3264 &gxbb_cts_amclk_sel,3265 &gxbb_cts_mclk_i958_sel,3266 &gxbb_cts_i958,3267 &gxbb_32k_clk_sel,3268 &gxbb_sd_emmc_a_clk0_sel,3269 &gxbb_sd_emmc_b_clk0_sel,3270 &gxbb_sd_emmc_c_clk0_sel,3271 &gxbb_vpu_0_sel,3272 &gxbb_vpu_1_sel,3273 &gxbb_vpu,3274 &gxbb_vapb_0_sel,3275 &gxbb_vapb_1_sel,3276 &gxbb_vapb_sel,3277 &gxbb_mpll0,3278 &gxbb_mpll1,3279 &gxbb_mpll2,3280 &gxbb_mpll0_div,3281 &gxbb_mpll1_div,3282 &gxbb_mpll2_div,3283 &gxbb_cts_amclk_div,3284 &gxbb_fixed_pll,3285 &gxbb_sys_pll,3286 &gxbb_mpll_prediv,3287 &gxbb_fclk_div2,3288 &gxbb_fclk_div3,3289 &gxbb_fclk_div4,3290 &gxbb_fclk_div5,3291 &gxbb_fclk_div7,3292 &gxbb_vdec_1_sel,3293 &gxbb_vdec_1_div,3294 &gxbb_vdec_1,3295 &gxbb_vdec_hevc_sel,3296 &gxbb_vdec_hevc_div,3297 &gxbb_vdec_hevc,3298 &gxbb_gen_clk_sel,3299 &gxbb_gen_clk_div,3300 &gxbb_gen_clk,3301 &gxbb_fixed_pll_dco,3302 &gxbb_sys_pll_dco,3303 &gxbb_gp0_pll,3304 &gxbb_vid_pll,3305 &gxbb_vid_pll_sel,3306 &gxbb_vid_pll_div,3307 &gxbb_vclk,3308 &gxbb_vclk_sel,3309 &gxbb_vclk_div,3310 &gxbb_vclk_input,3311 &gxbb_vclk_div1,3312 &gxbb_vclk_div2_en,3313 &gxbb_vclk_div4_en,3314 &gxbb_vclk_div6_en,3315 &gxbb_vclk_div12_en,3316 &gxbb_vclk2,3317 &gxbb_vclk2_sel,3318 &gxbb_vclk2_div,3319 &gxbb_vclk2_input,3320 &gxbb_vclk2_div1,3321 &gxbb_vclk2_div2_en,3322 &gxbb_vclk2_div4_en,3323 &gxbb_vclk2_div6_en,3324 &gxbb_vclk2_div12_en,3325 &gxbb_cts_enci,3326 &gxbb_cts_enci_sel,3327 &gxbb_cts_encp,3328 &gxbb_cts_encp_sel,3329 &gxbb_cts_vdac,3330 &gxbb_cts_vdac_sel,3331 &gxbb_hdmi_tx,3332 &gxbb_hdmi_tx_sel,3333 &gxbb_hdmi_sel,3334 &gxbb_hdmi_div,3335 &gxbb_hdmi,3336 &gxbb_gp0_pll_dco,3337 &gxbb_hdmi_pll,3338 &gxbb_hdmi_pll_od,3339 &gxbb_hdmi_pll_od2,3340 &gxbb_hdmi_pll_dco,3341};3342 3343static struct clk_regmap *const gxl_clk_regmaps[] = {3344 &gxbb_clk81,3345 &gxbb_ddr,3346 &gxbb_dos,3347 &gxbb_isa,3348 &gxbb_pl301,3349 &gxbb_periphs,3350 &gxbb_spicc,3351 &gxbb_i2c,3352 &gxbb_sar_adc,3353 &gxbb_smart_card,3354 &gxbb_rng0,3355 &gxbb_uart0,3356 &gxbb_sdhc,3357 &gxbb_stream,3358 &gxbb_async_fifo,3359 &gxbb_sdio,3360 &gxbb_abuf,3361 &gxbb_hiu_iface,3362 &gxbb_assist_misc,3363 &gxbb_spi,3364 &gxbb_i2s_spdif,3365 &gxbb_eth,3366 &gxbb_demux,3367 &gxbb_aiu_glue,3368 &gxbb_iec958,3369 &gxbb_i2s_out,3370 &gxbb_amclk,3371 &gxbb_aififo2,3372 &gxbb_mixer,3373 &gxbb_mixer_iface,3374 &gxbb_adc,3375 &gxbb_blkmv,3376 &gxbb_aiu,3377 &gxbb_uart1,3378 &gxbb_g2d,3379 &gxbb_usb0,3380 &gxbb_usb1,3381 &gxbb_reset,3382 &gxbb_nand,3383 &gxbb_dos_parser,3384 &gxbb_usb,3385 &gxbb_vdin1,3386 &gxbb_ahb_arb0,3387 &gxbb_efuse,3388 &gxbb_boot_rom,3389 &gxbb_ahb_data_bus,3390 &gxbb_ahb_ctrl_bus,3391 &gxbb_hdmi_intr_sync,3392 &gxbb_hdmi_pclk,3393 &gxbb_usb1_ddr_bridge,3394 &gxbb_usb0_ddr_bridge,3395 &gxbb_mmc_pclk,3396 &gxbb_dvin,3397 &gxbb_uart2,3398 &gxbb_sana,3399 &gxbb_vpu_intr,3400 &gxbb_sec_ahb_ahb3_bridge,3401 &gxbb_clk81_a53,3402 &gxbb_vclk2_venci0,3403 &gxbb_vclk2_venci1,3404 &gxbb_vclk2_vencp0,3405 &gxbb_vclk2_vencp1,3406 &gxbb_gclk_venci_int0,3407 &gxbb_gclk_vencp_int,3408 &gxbb_dac_clk,3409 &gxbb_aoclk_gate,3410 &gxbb_iec958_gate,3411 &gxbb_enc480p,3412 &gxbb_rng1,3413 &gxbb_gclk_venci_int1,3414 &gxbb_vclk2_venclmcc,3415 &gxbb_vclk2_vencl,3416 &gxbb_vclk_other,3417 &gxbb_edp,3418 &gxbb_ao_media_cpu,3419 &gxbb_ao_ahb_sram,3420 &gxbb_ao_ahb_bus,3421 &gxbb_ao_iface,3422 &gxbb_ao_i2c,3423 &gxbb_emmc_a,3424 &gxbb_emmc_b,3425 &gxbb_emmc_c,3426 &gxbb_sar_adc_clk,3427 &gxbb_mali_0,3428 &gxbb_mali_1,3429 &gxbb_cts_amclk,3430 &gxbb_cts_mclk_i958,3431 &gxbb_32k_clk,3432 &gxbb_sd_emmc_a_clk0,3433 &gxbb_sd_emmc_b_clk0,3434 &gxbb_sd_emmc_c_clk0,3435 &gxbb_vpu_0,3436 &gxbb_vpu_1,3437 &gxbb_vapb_0,3438 &gxbb_vapb_1,3439 &gxbb_vapb,3440 &gxbb_mpeg_clk_div,3441 &gxbb_sar_adc_clk_div,3442 &gxbb_mali_0_div,3443 &gxbb_mali_1_div,3444 &gxbb_cts_mclk_i958_div,3445 &gxbb_32k_clk_div,3446 &gxbb_sd_emmc_a_clk0_div,3447 &gxbb_sd_emmc_b_clk0_div,3448 &gxbb_sd_emmc_c_clk0_div,3449 &gxbb_vpu_0_div,3450 &gxbb_vpu_1_div,3451 &gxbb_vapb_0_div,3452 &gxbb_vapb_1_div,3453 &gxbb_mpeg_clk_sel,3454 &gxbb_sar_adc_clk_sel,3455 &gxbb_mali_0_sel,3456 &gxbb_mali_1_sel,3457 &gxbb_mali,3458 &gxbb_cts_amclk_sel,3459 &gxbb_cts_mclk_i958_sel,3460 &gxbb_cts_i958,3461 &gxbb_32k_clk_sel,3462 &gxbb_sd_emmc_a_clk0_sel,3463 &gxbb_sd_emmc_b_clk0_sel,3464 &gxbb_sd_emmc_c_clk0_sel,3465 &gxbb_vpu_0_sel,3466 &gxbb_vpu_1_sel,3467 &gxbb_vpu,3468 &gxbb_vapb_0_sel,3469 &gxbb_vapb_1_sel,3470 &gxbb_vapb_sel,3471 &gxbb_mpll0,3472 &gxbb_mpll1,3473 &gxbb_mpll2,3474 &gxl_mpll0_div,3475 &gxbb_mpll1_div,3476 &gxbb_mpll2_div,3477 &gxbb_cts_amclk_div,3478 &gxbb_fixed_pll,3479 &gxbb_sys_pll,3480 &gxbb_mpll_prediv,3481 &gxbb_fclk_div2,3482 &gxbb_fclk_div3,3483 &gxbb_fclk_div4,3484 &gxbb_fclk_div5,3485 &gxbb_fclk_div7,3486 &gxbb_vdec_1_sel,3487 &gxbb_vdec_1_div,3488 &gxbb_vdec_1,3489 &gxbb_vdec_hevc_sel,3490 &gxbb_vdec_hevc_div,3491 &gxbb_vdec_hevc,3492 &gxbb_gen_clk_sel,3493 &gxbb_gen_clk_div,3494 &gxbb_gen_clk,3495 &gxbb_fixed_pll_dco,3496 &gxbb_sys_pll_dco,3497 &gxbb_gp0_pll,3498 &gxbb_vid_pll,3499 &gxbb_vid_pll_sel,3500 &gxbb_vid_pll_div,3501 &gxbb_vclk,3502 &gxbb_vclk_sel,3503 &gxbb_vclk_div,3504 &gxbb_vclk_input,3505 &gxbb_vclk_div1,3506 &gxbb_vclk_div2_en,3507 &gxbb_vclk_div4_en,3508 &gxbb_vclk_div6_en,3509 &gxbb_vclk_div12_en,3510 &gxbb_vclk2,3511 &gxbb_vclk2_sel,3512 &gxbb_vclk2_div,3513 &gxbb_vclk2_input,3514 &gxbb_vclk2_div1,3515 &gxbb_vclk2_div2_en,3516 &gxbb_vclk2_div4_en,3517 &gxbb_vclk2_div6_en,3518 &gxbb_vclk2_div12_en,3519 &gxbb_cts_enci,3520 &gxbb_cts_enci_sel,3521 &gxbb_cts_encp,3522 &gxbb_cts_encp_sel,3523 &gxbb_cts_vdac,3524 &gxbb_cts_vdac_sel,3525 &gxbb_hdmi_tx,3526 &gxbb_hdmi_tx_sel,3527 &gxbb_hdmi_sel,3528 &gxbb_hdmi_div,3529 &gxbb_hdmi,3530 &gxl_gp0_pll_dco,3531 &gxl_hdmi_pll,3532 &gxl_hdmi_pll_od,3533 &gxl_hdmi_pll_od2,3534 &gxl_hdmi_pll_dco,3535 &gxl_acodec,3536};3537 3538static const struct meson_eeclkc_data gxbb_clkc_data = {3539 .regmap_clks = gxbb_clk_regmaps,3540 .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),3541 .hw_clks = {3542 .hws = gxbb_hw_clks,3543 .num = ARRAY_SIZE(gxbb_hw_clks),3544 },3545};3546 3547static const struct meson_eeclkc_data gxl_clkc_data = {3548 .regmap_clks = gxl_clk_regmaps,3549 .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),3550 .hw_clks = {3551 .hws = gxl_hw_clks,3552 .num = ARRAY_SIZE(gxl_hw_clks),3553 },3554};3555 3556static const struct of_device_id clkc_match_table[] = {3557 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },3558 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },3559 {},3560};3561MODULE_DEVICE_TABLE(of, clkc_match_table);3562 3563static struct platform_driver gxbb_driver = {3564 .probe = meson_eeclkc_probe,3565 .driver = {3566 .name = "gxbb-clkc",3567 .of_match_table = clkc_match_table,3568 },3569};3570module_platform_driver(gxbb_driver);3571 3572MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");3573MODULE_LICENSE("GPL");3574MODULE_IMPORT_NS(CLK_MESON);3575