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1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved4 * Author: Yu Tu <yu.tu@amlogic.com>5 */6 7#ifndef __MESON_S4_PERIPHERALS_H__8#define __MESON_S4_PERIPHERALS_H__9 10#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x00811#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c12#define CLKCTRL_RTC_CTRL 0x01013#define CLKCTRL_SYS_CLK_CTRL0 0x04014#define CLKCTRL_SYS_CLK_EN0_REG0 0x04415#define CLKCTRL_SYS_CLK_EN0_REG1 0x04816#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c17#define CLKCTRL_SYS_CLK_EN0_REG3 0x05018#define CLKCTRL_CECA_CTRL0 0x08819#define CLKCTRL_CECA_CTRL1 0x08c20#define CLKCTRL_CECB_CTRL0 0x09021#define CLKCTRL_CECB_CTRL1 0x09422#define CLKCTRL_SC_CLK_CTRL 0x09823#define CLKCTRL_CLK12_24_CTRL 0x0a824#define CLKCTRL_VID_CLK_CTRL 0x0c025#define CLKCTRL_VID_CLK_CTRL2 0x0c426#define CLKCTRL_VID_CLK_DIV 0x0c827#define CLKCTRL_VIID_CLK_DIV 0x0cc28#define CLKCTRL_VIID_CLK_CTRL 0x0d029#define CLKCTRL_HDMI_CLK_CTRL 0x0e030#define CLKCTRL_VID_PLL_CLK_DIV 0x0e431#define CLKCTRL_VPU_CLK_CTRL 0x0e832#define CLKCTRL_VPU_CLKB_CTRL 0x0ec33#define CLKCTRL_VPU_CLKC_CTRL 0x0f034#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f435#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f836#define CLKCTRL_VAPBCLK_CTRL 0x0fc37#define CLKCTRL_HDCP22_CTRL 0x10038#define CLKCTRL_VDEC_CLK_CTRL 0x14039#define CLKCTRL_VDEC2_CLK_CTRL 0x14440#define CLKCTRL_VDEC3_CLK_CTRL 0x14841#define CLKCTRL_VDEC4_CLK_CTRL 0x14c42#define CLKCTRL_TS_CLK_CTRL 0x15843#define CLKCTRL_MALI_CLK_CTRL 0x15c44#define CLKCTRL_NAND_CLK_CTRL 0x16845#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c46#define CLKCTRL_SPICC_CLK_CTRL 0x17447#define CLKCTRL_GEN_CLK_CTRL 0x17848#define CLKCTRL_SAR_CLK_CTRL 0x17c49#define CLKCTRL_PWM_CLK_AB_CTRL 0x18050#define CLKCTRL_PWM_CLK_CD_CTRL 0x18451#define CLKCTRL_PWM_CLK_EF_CTRL 0x18852#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c53#define CLKCTRL_PWM_CLK_IJ_CTRL 0x19054#define CLKCTRL_DEMOD_CLK_CTRL 0x20055 56#endif /* __MESON_S4_PERIPHERALS_H__ */57