39 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */2/*3 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved4 * Author: Yu Tu <yu.tu@amlogic.com>5 */6 7#ifndef __MESON_S4_PLL_H__8#define __MESON_S4_PLL_H__9 10#define ANACTRL_FIXPLL_CTRL0 0x04011#define ANACTRL_FIXPLL_CTRL1 0x04412#define ANACTRL_FIXPLL_CTRL3 0x04c13#define ANACTRL_GP0PLL_CTRL0 0x08014#define ANACTRL_GP0PLL_CTRL1 0x08415#define ANACTRL_GP0PLL_CTRL2 0x08816#define ANACTRL_GP0PLL_CTRL3 0x08c17#define ANACTRL_GP0PLL_CTRL4 0x09018#define ANACTRL_GP0PLL_CTRL5 0x09419#define ANACTRL_GP0PLL_CTRL6 0x09820#define ANACTRL_HIFIPLL_CTRL0 0x10021#define ANACTRL_HIFIPLL_CTRL1 0x10422#define ANACTRL_HIFIPLL_CTRL2 0x10823#define ANACTRL_HIFIPLL_CTRL3 0x10c24#define ANACTRL_HIFIPLL_CTRL4 0x11025#define ANACTRL_HIFIPLL_CTRL5 0x11426#define ANACTRL_HIFIPLL_CTRL6 0x11827#define ANACTRL_MPLL_CTRL0 0x18028#define ANACTRL_MPLL_CTRL1 0x18429#define ANACTRL_MPLL_CTRL2 0x18830#define ANACTRL_MPLL_CTRL3 0x18c31#define ANACTRL_MPLL_CTRL4 0x19032#define ANACTRL_MPLL_CTRL5 0x19433#define ANACTRL_MPLL_CTRL6 0x19834#define ANACTRL_MPLL_CTRL7 0x19c35#define ANACTRL_MPLL_CTRL8 0x1a036#define ANACTRL_HDMIPLL_CTRL0 0x1c037 38#endif /* __MESON_S4_PLL_H__ */39