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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2012 Freescale Semiconductor, Inc.4 */5 6#ifndef __MXS_CLK_H7#define __MXS_CLK_H8 9struct clk;10 11#include <linux/clk-provider.h>12#include <linux/spinlock.h>13 14#define SET 0x415#define CLR 0x816 17extern spinlock_t mxs_lock;18 19int mxs_clk_wait(void __iomem *reg, u8 shift);20 21struct clk *mxs_clk_pll(const char *name, const char *parent_name,22 void __iomem *base, u8 power, unsigned long rate);23 24struct clk *mxs_clk_ref(const char *name, const char *parent_name,25 void __iomem *reg, u8 idx);26 27struct clk *mxs_clk_div(const char *name, const char *parent_name,28 void __iomem *reg, u8 shift, u8 width, u8 busy);29 30struct clk *mxs_clk_frac(const char *name, const char *parent_name,31 void __iomem *reg, u8 shift, u8 width, u8 busy);32 33static inline struct clk *mxs_clk_fixed(const char *name, int rate)34{35 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);36}37 38static inline struct clk *mxs_clk_gate(const char *name,39 const char *parent_name, void __iomem *reg, u8 shift)40{41 return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,42 reg, shift, CLK_GATE_SET_TO_DISABLE,43 &mxs_lock);44}45 46static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,47 u8 shift, u8 width, const char *const *parent_names, int num_parents)48{49 return clk_register_mux(NULL, name, parent_names, num_parents,50 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,51 reg, shift, width, 0, &mxs_lock);52}53 54static inline struct clk *mxs_clk_fixed_factor(const char *name,55 const char *parent_name, unsigned int mult, unsigned int div)56{57 return clk_register_fixed_factor(NULL, name, parent_name,58 CLK_SET_RATE_PARENT, mult, div);59}60 61#endif /* __MXS_CLK_H */62