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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Pistachio SoC clock controllers4 *5 * Copyright (C) 2014 Google, Inc.6 */7 8#include <linux/clk-provider.h>9#include <linux/init.h>10#include <linux/io.h>11#include <linux/kernel.h>12#include <linux/of.h>13 14#include <dt-bindings/clock/pistachio-clk.h>15 16#include "clk.h"17 18static struct pistachio_gate pistachio_gates[] __initdata = {19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),29 GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),30 GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),31 GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),32 GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),33 GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),34 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),35 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),36 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),37 GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),38 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),39 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),40 GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),41 GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",42 0x104, 22),43 GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),44 GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),45 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),46 GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),47 GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),48 GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),49};50 51static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {52 FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),53 FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),54};55 56static struct pistachio_div pistachio_divs[] __initdata = {57 DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",58 0x204, 2),59 DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),60 DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",61 0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),62 DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",63 0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),64 DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",65 0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),66 DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",67 0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),68 DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),69 DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),71 DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),72 DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),73 DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),74 DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",75 0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),76 DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,77 CLK_DIVIDER_ROUND_CLOSEST),78 DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",79 0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),80 DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,81 CLK_DIVIDER_ROUND_CLOSEST),82 DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),83 DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",84 0x248, 3),85 DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),86 DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",87 0x250, 3),88 DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),89 DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",90 "event_timer_mux", 0x258, 3),91 DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",92 0x25c, 12),93 DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",94 "aux_adc_internal", 0x260, 3),95 DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),96 DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),97 DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),98 DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),99 DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),100 DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",101 0x278, 3),102 DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),103};104 105PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };106PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };107PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };108PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };109PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };110PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };111PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };112PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };113PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };114PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };115PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",116 "rpu_l_pll_mux" };117PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };118PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };119PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };120PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };121PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };122 123static struct pistachio_mux pistachio_muxes[] __initdata = {124 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,125 0x200, 0),126 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),127 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),128 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),129 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),130 MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),131 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),132 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),133 MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),134 MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),135 MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),136 MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),137 MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),138 MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),139 MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),140 MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),141};142 143static struct pistachio_pll pistachio_plls[] __initdata = {144 PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),145 PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",146 PLL_GF40LP_FRAC, 0xc),147 PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),148 PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),149 PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),150 PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),151 PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),152};153 154PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",155 "rpu_l_pll_mux", "sys_pll_mux",156 "wifi_pll_mux", "bt_pll_mux" };157static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };158 159static unsigned int pistachio_critical_clks_core[] __initdata = {160 CLK_MIPS161};162 163static unsigned int pistachio_critical_clks_sys[] __initdata = {164 PERIPH_CLK_SYS,165 PERIPH_CLK_SYS_BUS,166 PERIPH_CLK_DDR,167 PERIPH_CLK_ROM,168};169 170static void __init pistachio_clk_init(struct device_node *np)171{172 struct pistachio_clk_provider *p;173 struct clk *debug_clk;174 175 p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);176 if (!p)177 return;178 179 pistachio_clk_register_pll(p, pistachio_plls,180 ARRAY_SIZE(pistachio_plls));181 pistachio_clk_register_mux(p, pistachio_muxes,182 ARRAY_SIZE(pistachio_muxes));183 pistachio_clk_register_div(p, pistachio_divs,184 ARRAY_SIZE(pistachio_divs));185 pistachio_clk_register_fixed_factor(p, pistachio_ffs,186 ARRAY_SIZE(pistachio_ffs));187 pistachio_clk_register_gate(p, pistachio_gates,188 ARRAY_SIZE(pistachio_gates));189 190 debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,191 ARRAY_SIZE(mux_debug),192 CLK_SET_RATE_NO_REPARENT,193 p->base + 0x200, 18, 0x1f, 0,194 mux_debug_idx, NULL);195 p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;196 197 pistachio_clk_register_provider(p);198 199 pistachio_clk_force_enable(p, pistachio_critical_clks_core,200 ARRAY_SIZE(pistachio_critical_clks_core));201}202CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);203 204static struct pistachio_gate pistachio_periph_gates[] __initdata = {205 GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),206 GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),207 GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),208 GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),209 GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",210 0x100, 4),211 GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",212 0x100, 5),213 GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),214 GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),215 GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),216 GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),217 GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),218 GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),219 GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),220 GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),221};222 223static struct pistachio_div pistachio_periph_divs[] __initdata = {224 DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),225 DIV(PERIPH_CLK_COUNTER_FAST_DIV, "counter_fast_div", "periph_sys",226 0x110, 7),227 DIV(PERIPH_CLK_COUNTER_SLOW_PRE_DIV, "counter_slow_pre_div",228 "periph_sys", 0x114, 7),229 DIV(PERIPH_CLK_COUNTER_SLOW_DIV, "counter_slow_div",230 "counter_slow_pre_div", 0x118, 7),231 DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,232 CLK_DIVIDER_ROUND_CLOSEST),233 DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,234 CLK_DIVIDER_ROUND_CLOSEST),235 DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,236 CLK_DIVIDER_ROUND_CLOSEST),237 DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,238 CLK_DIVIDER_ROUND_CLOSEST),239 DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),240 DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),241 DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),242 DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),243 DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),244 DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),245 DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),246 DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),247 DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),248 DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),249 DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),250 DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),251};252 253static void __init pistachio_clk_periph_init(struct device_node *np)254{255 struct pistachio_clk_provider *p;256 257 p = pistachio_clk_alloc_provider(np, PERIPH_CLK_NR_CLKS);258 if (!p)259 return;260 261 pistachio_clk_register_div(p, pistachio_periph_divs,262 ARRAY_SIZE(pistachio_periph_divs));263 pistachio_clk_register_gate(p, pistachio_periph_gates,264 ARRAY_SIZE(pistachio_periph_gates));265 266 pistachio_clk_register_provider(p);267 268 pistachio_clk_force_enable(p, pistachio_critical_clks_sys,269 ARRAY_SIZE(pistachio_critical_clks_sys));270}271CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",272 pistachio_clk_periph_init);273 274static struct pistachio_gate pistachio_sys_gates[] __initdata = {275 GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),276 GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),277 GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),278 GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),279 GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),280 GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),281 GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),282 GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),283 GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),284 GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),285 GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),286 GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),287 GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),288 GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),289 GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),290 GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),291 GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),292 GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),293 GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),294 GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),295 GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),296 GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),297 GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),298};299 300static void __init pistachio_cr_periph_init(struct device_node *np)301{302 struct pistachio_clk_provider *p;303 304 p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);305 if (!p)306 return;307 308 pistachio_clk_register_gate(p, pistachio_sys_gates,309 ARRAY_SIZE(pistachio_sys_gates));310 311 pistachio_clk_register_provider(p);312}313CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",314 pistachio_cr_periph_init);315 316static struct pistachio_gate pistachio_ext_gates[] __initdata = {317 GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),318 GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)319};320 321static void __init pistachio_cr_top_init(struct device_node *np)322{323 struct pistachio_clk_provider *p;324 325 p = pistachio_clk_alloc_provider(np, EXT_CLK_NR_CLKS);326 if (!p)327 return;328 329 pistachio_clk_register_gate(p, pistachio_ext_gates,330 ARRAY_SIZE(pistachio_ext_gates));331 332 pistachio_clk_register_provider(p);333}334CLK_OF_DECLARE(pistachio_cr_top, "img,pistachio-cr-top",335 pistachio_cr_top_init);336