231 lines · c
1// SPDX-License-Identifier: GPL-2.02// Copyright (c) 2018, The Linux Foundation. All rights reserved.3#include <linux/clk-provider.h>4#include <linux/module.h>5#include <linux/of.h>6#include <linux/platform_device.h>7#include <linux/regmap.h>8 9#include "clk-alpha-pll.h"10 11static struct clk_alpha_pll ipq_pll_huayra = {12 .offset = 0x0,13 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],14 .flags = SUPPORTS_DYNAMIC_UPDATE,15 .clkr = {16 .enable_reg = 0x0,17 .enable_mask = BIT(0),18 .hw.init = &(const struct clk_init_data) {19 .name = "a53pll",20 .parent_data = &(const struct clk_parent_data) {21 .fw_name = "xo",22 },23 .num_parents = 1,24 .ops = &clk_alpha_pll_huayra_ops,25 },26 },27};28 29static struct clk_alpha_pll ipq_pll_stromer = {30 .offset = 0x0,31 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],32 .flags = SUPPORTS_DYNAMIC_UPDATE,33 .clkr = {34 .enable_reg = 0x0,35 .enable_mask = BIT(0),36 .hw.init = &(const struct clk_init_data) {37 .name = "a53pll",38 .parent_data = &(const struct clk_parent_data) {39 .fw_name = "xo",40 },41 .num_parents = 1,42 .ops = &clk_alpha_pll_stromer_ops,43 },44 },45};46 47static struct clk_alpha_pll ipq_pll_stromer_plus = {48 .offset = 0x0,49 /*50 * The register offsets of the Stromer Plus PLL used in IPQ533251 * are the same as the Stromer PLL's offsets.52 */53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],54 .flags = SUPPORTS_DYNAMIC_UPDATE,55 .clkr = {56 .enable_reg = 0x0,57 .enable_mask = BIT(0),58 .hw.init = &(const struct clk_init_data) {59 .name = "a53pll",60 .parent_data = &(const struct clk_parent_data) {61 .fw_name = "xo",62 },63 .num_parents = 1,64 .ops = &clk_alpha_pll_stromer_plus_ops,65 },66 },67};68 69/* 1.008 GHz configuration */70static const struct alpha_pll_config ipq5018_pll_config = {71 .l = 0x2a,72 .config_ctl_val = 0x4001075b,73 .main_output_mask = BIT(0),74 .aux_output_mask = BIT(1),75 .early_output_mask = BIT(3),76 .alpha_en_mask = BIT(24),77 .status_val = 0x3,78 .status_mask = GENMASK(10, 8),79 .lock_det = BIT(2),80 .test_ctl_hi_val = 0x00400003,81};82 83static const struct alpha_pll_config ipq5332_pll_config = {84 .l = 0x2d,85 .config_ctl_val = 0x4001075b,86 .main_output_mask = BIT(0),87 .aux_output_mask = BIT(1),88 .early_output_mask = BIT(3),89 .alpha_en_mask = BIT(24),90 .status_val = 0x3,91 .status_mask = GENMASK(10, 8),92 .lock_det = BIT(2),93 .test_ctl_hi_val = 0x00400003,94};95 96static const struct alpha_pll_config ipq6018_pll_config = {97 .l = 0x37,98 .config_ctl_val = 0x240d4828,99 .config_ctl_hi_val = 0x6,100 .early_output_mask = BIT(3),101 .aux2_output_mask = BIT(2),102 .aux_output_mask = BIT(1),103 .main_output_mask = BIT(0),104 .test_ctl_val = 0x1c0000C0,105 .test_ctl_hi_val = 0x4000,106};107 108static const struct alpha_pll_config ipq8074_pll_config = {109 .l = 0x48,110 .config_ctl_val = 0x200d4828,111 .config_ctl_hi_val = 0x6,112 .early_output_mask = BIT(3),113 .aux2_output_mask = BIT(2),114 .aux_output_mask = BIT(1),115 .main_output_mask = BIT(0),116 .test_ctl_val = 0x1c000000,117 .test_ctl_hi_val = 0x4000,118};119 120static const struct alpha_pll_config ipq9574_pll_config = {121 .l = 0x3b,122 .config_ctl_val = 0x200d4828,123 .config_ctl_hi_val = 0x6,124 .early_output_mask = BIT(3),125 .aux2_output_mask = BIT(2),126 .aux_output_mask = BIT(1),127 .main_output_mask = BIT(0),128 .test_ctl_val = 0x0,129 .test_ctl_hi_val = 0x4000,130};131 132struct apss_pll_data {133 int pll_type;134 struct clk_alpha_pll *pll;135 const struct alpha_pll_config *pll_config;136};137 138static const struct apss_pll_data ipq5018_pll_data = {139 .pll_type = CLK_ALPHA_PLL_TYPE_STROMER,140 .pll = &ipq_pll_stromer,141 .pll_config = &ipq5018_pll_config,142};143 144static const struct apss_pll_data ipq5332_pll_data = {145 .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,146 .pll = &ipq_pll_stromer_plus,147 .pll_config = &ipq5332_pll_config,148};149 150static const struct apss_pll_data ipq8074_pll_data = {151 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,152 .pll = &ipq_pll_huayra,153 .pll_config = &ipq8074_pll_config,154};155 156static const struct apss_pll_data ipq6018_pll_data = {157 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,158 .pll = &ipq_pll_huayra,159 .pll_config = &ipq6018_pll_config,160};161 162static const struct apss_pll_data ipq9574_pll_data = {163 .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,164 .pll = &ipq_pll_huayra,165 .pll_config = &ipq9574_pll_config,166};167 168static const struct regmap_config ipq_pll_regmap_config = {169 .reg_bits = 32,170 .reg_stride = 4,171 .val_bits = 32,172 .max_register = 0x40,173 .fast_io = true,174};175 176static int apss_ipq_pll_probe(struct platform_device *pdev)177{178 const struct apss_pll_data *data;179 struct device *dev = &pdev->dev;180 struct regmap *regmap;181 void __iomem *base;182 int ret;183 184 base = devm_platform_ioremap_resource(pdev, 0);185 if (IS_ERR(base))186 return PTR_ERR(base);187 188 regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);189 if (IS_ERR(regmap))190 return PTR_ERR(regmap);191 192 data = of_device_get_match_data(&pdev->dev);193 if (!data)194 return -ENODEV;195 196 if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)197 clk_alpha_pll_configure(data->pll, regmap, data->pll_config);198 else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||199 data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)200 clk_stromer_pll_configure(data->pll, regmap, data->pll_config);201 202 ret = devm_clk_register_regmap(dev, &data->pll->clkr);203 if (ret)204 return ret;205 206 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,207 &data->pll->clkr.hw);208}209 210static const struct of_device_id apss_ipq_pll_match_table[] = {211 { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },212 { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },213 { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },214 { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },215 { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },216 { }217};218MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);219 220static struct platform_driver apss_ipq_pll_driver = {221 .probe = apss_ipq_pll_probe,222 .driver = {223 .name = "qcom-ipq-apss-pll",224 .of_match_table = apss_ipq_pll_match_table,225 },226};227module_platform_driver(apss_ipq_pll_driver);228 229MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");230MODULE_LICENSE("GPL v2");231