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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2017, Linaro Limited4 * Author: Georgi Djakov <georgi.djakov@linaro.org>5 */6 7#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__8#define __QCOM_CLK_REGMAP_MUX_DIV_H__9 10#include <linux/clk-provider.h>11#include "clk-regmap.h"12 13/**14 * struct mux_div_clk - combined mux/divider clock15 * @reg_offset: offset of the mux/divider register16 * @hid_width: number of bits in half integer divider17 * @hid_shift: lowest bit of hid value field18 * @src_width: number of bits in source select19 * @src_shift: lowest bit of source select field20 * @div: the divider raw configuration value21 * @src: the mux index which will be used if the clock is enabled22 * @parent_map: map from parent_names index to src_sel field23 * @clkr: handle between common and hardware-specific interfaces24 * @pclk: the input PLL clock25 * @clk_nb: clock notifier for rate changes of the input PLL26 */27struct clk_regmap_mux_div {28 u32 reg_offset;29 u32 hid_width;30 u32 hid_shift;31 u32 src_width;32 u32 src_shift;33 u32 div;34 u32 src;35 const u32 *parent_map;36 struct clk_regmap clkr;37 struct clk *pclk;38 struct notifier_block clk_nb;39};40 41extern const struct clk_ops clk_regmap_mux_div_ops;42extern int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);43 44#endif45