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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2016, Linaro Limited4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.5 */6 7#include <linux/clk-provider.h>8#include <linux/err.h>9#include <linux/export.h>10#include <linux/init.h>11#include <linux/kernel.h>12#include <linux/module.h>13#include <linux/mutex.h>14#include <linux/mfd/qcom_rpm.h>15#include <linux/of.h>16#include <linux/platform_device.h>17 18#include <dt-bindings/mfd/qcom-rpm.h>19#include <dt-bindings/clock/qcom,rpmcc.h>20 21#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c6322#define QCOM_RPM_SCALING_ENABLE_ID 0x223#define QCOM_RPM_XO_MODE_ON 0x224 25static const struct clk_parent_data gcc_pxo[] = {26 { .fw_name = "pxo", .name = "pxo_board" },27};28 29static const struct clk_parent_data gcc_cxo[] = {30 { .fw_name = "cxo", .name = "cxo_board" },31};32 33#define DEFINE_CLK_RPM(_name, r_id) \34 static struct clk_rpm clk_rpm_##_name##_a_clk; \35 static struct clk_rpm clk_rpm_##_name##_clk = { \36 .rpm_clk_id = (r_id), \37 .peer = &clk_rpm_##_name##_a_clk, \38 .rate = INT_MAX, \39 .hw.init = &(struct clk_init_data){ \40 .ops = &clk_rpm_ops, \41 .name = #_name "_clk", \42 .parent_data = gcc_pxo, \43 .num_parents = ARRAY_SIZE(gcc_pxo), \44 }, \45 }; \46 static struct clk_rpm clk_rpm_##_name##_a_clk = { \47 .rpm_clk_id = (r_id), \48 .peer = &clk_rpm_##_name##_clk, \49 .active_only = true, \50 .rate = INT_MAX, \51 .hw.init = &(struct clk_init_data){ \52 .ops = &clk_rpm_ops, \53 .name = #_name "_a_clk", \54 .parent_data = gcc_pxo, \55 .num_parents = ARRAY_SIZE(gcc_pxo), \56 }, \57 }58 59#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \60 static struct clk_rpm clk_rpm_##_name##_clk = { \61 .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \62 .xo_offset = (offset), \63 .hw.init = &(struct clk_init_data){ \64 .ops = &clk_rpm_xo_ops, \65 .name = #_name "_clk", \66 .parent_data = gcc_cxo, \67 .num_parents = ARRAY_SIZE(gcc_cxo), \68 }, \69 }70 71#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \72 static struct clk_rpm clk_rpm_##_name##_clk = { \73 .rpm_clk_id = (r_id), \74 .rate = (r), \75 .hw.init = &(struct clk_init_data){ \76 .ops = &clk_rpm_fixed_ops, \77 .name = #_name "_clk", \78 .parent_data = gcc_pxo, \79 .num_parents = ARRAY_SIZE(gcc_pxo), \80 }, \81 }82 83#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)84 85struct rpm_cc;86 87struct clk_rpm {88 const int rpm_clk_id;89 const int xo_offset;90 const bool active_only;91 unsigned long rate;92 bool enabled;93 bool branch;94 struct clk_rpm *peer;95 struct clk_hw hw;96 struct qcom_rpm *rpm;97 struct rpm_cc *rpm_cc;98};99 100struct rpm_cc {101 struct clk_rpm **clks;102 size_t num_clks;103 u32 xo_buffer_value;104 struct mutex xo_lock;105};106 107struct rpm_clk_desc {108 struct clk_rpm **clks;109 size_t num_clks;110};111 112static DEFINE_MUTEX(rpm_clk_lock);113 114static int clk_rpm_handoff(struct clk_rpm *r)115{116 int ret;117 u32 value = INT_MAX;118 119 /*120 * The vendor tree simply reads the status for this121 * RPM clock.122 */123 if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||124 r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)125 return 0;126 127 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,128 r->rpm_clk_id, &value, 1);129 if (ret)130 return ret;131 ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,132 r->rpm_clk_id, &value, 1);133 if (ret)134 return ret;135 136 return 0;137}138 139static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)140{141 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */142 143 return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,144 r->rpm_clk_id, &value, 1);145}146 147static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)148{149 u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */150 151 return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,152 r->rpm_clk_id, &value, 1);153}154 155static void to_active_sleep(struct clk_rpm *r, unsigned long rate,156 unsigned long *active, unsigned long *sleep)157{158 *active = rate;159 160 /*161 * Active-only clocks don't care what the rate is during sleep. So,162 * they vote for zero.163 */164 if (r->active_only)165 *sleep = 0;166 else167 *sleep = *active;168}169 170static int clk_rpm_prepare(struct clk_hw *hw)171{172 struct clk_rpm *r = to_clk_rpm(hw);173 struct clk_rpm *peer = r->peer;174 unsigned long this_rate = 0, this_sleep_rate = 0;175 unsigned long peer_rate = 0, peer_sleep_rate = 0;176 unsigned long active_rate, sleep_rate;177 int ret = 0;178 179 mutex_lock(&rpm_clk_lock);180 181 /* Don't send requests to the RPM if the rate has not been set. */182 if (!r->rate)183 goto out;184 185 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);186 187 /* Take peer clock's rate into account only if it's enabled. */188 if (peer->enabled)189 to_active_sleep(peer, peer->rate,190 &peer_rate, &peer_sleep_rate);191 192 active_rate = max(this_rate, peer_rate);193 194 if (r->branch)195 active_rate = !!active_rate;196 197 ret = clk_rpm_set_rate_active(r, active_rate);198 if (ret)199 goto out;200 201 sleep_rate = max(this_sleep_rate, peer_sleep_rate);202 if (r->branch)203 sleep_rate = !!sleep_rate;204 205 ret = clk_rpm_set_rate_sleep(r, sleep_rate);206 if (ret)207 /* Undo the active set vote and restore it */208 ret = clk_rpm_set_rate_active(r, peer_rate);209 210out:211 if (!ret)212 r->enabled = true;213 214 mutex_unlock(&rpm_clk_lock);215 216 return ret;217}218 219static void clk_rpm_unprepare(struct clk_hw *hw)220{221 struct clk_rpm *r = to_clk_rpm(hw);222 struct clk_rpm *peer = r->peer;223 unsigned long peer_rate = 0, peer_sleep_rate = 0;224 unsigned long active_rate, sleep_rate;225 int ret;226 227 mutex_lock(&rpm_clk_lock);228 229 if (!r->rate)230 goto out;231 232 /* Take peer clock's rate into account only if it's enabled. */233 if (peer->enabled)234 to_active_sleep(peer, peer->rate, &peer_rate,235 &peer_sleep_rate);236 237 active_rate = r->branch ? !!peer_rate : peer_rate;238 ret = clk_rpm_set_rate_active(r, active_rate);239 if (ret)240 goto out;241 242 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;243 ret = clk_rpm_set_rate_sleep(r, sleep_rate);244 if (ret)245 goto out;246 247 r->enabled = false;248 249out:250 mutex_unlock(&rpm_clk_lock);251}252 253static int clk_rpm_xo_prepare(struct clk_hw *hw)254{255 struct clk_rpm *r = to_clk_rpm(hw);256 struct rpm_cc *rcc = r->rpm_cc;257 int ret, clk_id = r->rpm_clk_id;258 u32 value;259 260 mutex_lock(&rcc->xo_lock);261 262 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);263 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);264 if (!ret) {265 r->enabled = true;266 rcc->xo_buffer_value = value;267 }268 269 mutex_unlock(&rcc->xo_lock);270 271 return ret;272}273 274static void clk_rpm_xo_unprepare(struct clk_hw *hw)275{276 struct clk_rpm *r = to_clk_rpm(hw);277 struct rpm_cc *rcc = r->rpm_cc;278 int ret, clk_id = r->rpm_clk_id;279 u32 value;280 281 mutex_lock(&rcc->xo_lock);282 283 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);284 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);285 if (!ret) {286 r->enabled = false;287 rcc->xo_buffer_value = value;288 }289 290 mutex_unlock(&rcc->xo_lock);291}292 293static int clk_rpm_fixed_prepare(struct clk_hw *hw)294{295 struct clk_rpm *r = to_clk_rpm(hw);296 u32 value = 1;297 int ret;298 299 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,300 r->rpm_clk_id, &value, 1);301 if (!ret)302 r->enabled = true;303 304 return ret;305}306 307static void clk_rpm_fixed_unprepare(struct clk_hw *hw)308{309 struct clk_rpm *r = to_clk_rpm(hw);310 u32 value = 0;311 int ret;312 313 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,314 r->rpm_clk_id, &value, 1);315 if (!ret)316 r->enabled = false;317}318 319static int clk_rpm_set_rate(struct clk_hw *hw,320 unsigned long rate, unsigned long parent_rate)321{322 struct clk_rpm *r = to_clk_rpm(hw);323 struct clk_rpm *peer = r->peer;324 unsigned long active_rate, sleep_rate;325 unsigned long this_rate = 0, this_sleep_rate = 0;326 unsigned long peer_rate = 0, peer_sleep_rate = 0;327 int ret = 0;328 329 mutex_lock(&rpm_clk_lock);330 331 if (!r->enabled)332 goto out;333 334 to_active_sleep(r, rate, &this_rate, &this_sleep_rate);335 336 /* Take peer clock's rate into account only if it's enabled. */337 if (peer->enabled)338 to_active_sleep(peer, peer->rate,339 &peer_rate, &peer_sleep_rate);340 341 active_rate = max(this_rate, peer_rate);342 ret = clk_rpm_set_rate_active(r, active_rate);343 if (ret)344 goto out;345 346 sleep_rate = max(this_sleep_rate, peer_sleep_rate);347 ret = clk_rpm_set_rate_sleep(r, sleep_rate);348 if (ret)349 goto out;350 351 r->rate = rate;352 353out:354 mutex_unlock(&rpm_clk_lock);355 356 return ret;357}358 359static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,360 unsigned long *parent_rate)361{362 /*363 * RPM handles rate rounding and we don't have a way to364 * know what the rate will be, so just return whatever365 * rate is requested.366 */367 return rate;368}369 370static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,371 unsigned long parent_rate)372{373 struct clk_rpm *r = to_clk_rpm(hw);374 375 /*376 * RPM handles rate rounding and we don't have a way to377 * know what the rate will be, so just return whatever378 * rate was set.379 */380 return r->rate;381}382 383static const struct clk_ops clk_rpm_xo_ops = {384 .prepare = clk_rpm_xo_prepare,385 .unprepare = clk_rpm_xo_unprepare,386};387 388static const struct clk_ops clk_rpm_fixed_ops = {389 .prepare = clk_rpm_fixed_prepare,390 .unprepare = clk_rpm_fixed_unprepare,391 .round_rate = clk_rpm_round_rate,392 .recalc_rate = clk_rpm_recalc_rate,393};394 395static const struct clk_ops clk_rpm_ops = {396 .prepare = clk_rpm_prepare,397 .unprepare = clk_rpm_unprepare,398 .set_rate = clk_rpm_set_rate,399 .round_rate = clk_rpm_round_rate,400 .recalc_rate = clk_rpm_recalc_rate,401};402 403DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);404DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);405DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);406DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);407DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);408DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);409DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);410DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);411DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);412 413DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);414DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);415DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);416 417DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);418 419DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);420DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);421DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);422DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);423DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);424 425static struct clk_rpm *msm8660_clks[] = {426 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,427 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,428 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,429 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,430 [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,431 [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,432 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,433 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,434 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,435 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,436 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,437 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,438 [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,439 [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,440 [RPM_SMI_CLK] = &clk_rpm_smi_clk,441 [RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,442 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,443 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,444 [RPM_PLL4_CLK] = &clk_rpm_pll4_clk,445};446 447static const struct rpm_clk_desc rpm_clk_msm8660 = {448 .clks = msm8660_clks,449 .num_clks = ARRAY_SIZE(msm8660_clks),450};451 452static struct clk_rpm *apq8064_clks[] = {453 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,454 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,455 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,456 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,457 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,458 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,459 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,460 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,461 [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,462 [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,463 [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,464 [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,465 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,466 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,467 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,468 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,469 [RPM_QDSS_CLK] = &clk_rpm_qdss_clk,470 [RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,471 [RPM_XO_D0] = &clk_rpm_xo_d0_clk,472 [RPM_XO_D1] = &clk_rpm_xo_d1_clk,473 [RPM_XO_A0] = &clk_rpm_xo_a0_clk,474 [RPM_XO_A1] = &clk_rpm_xo_a1_clk,475 [RPM_XO_A2] = &clk_rpm_xo_a2_clk,476};477 478static const struct rpm_clk_desc rpm_clk_apq8064 = {479 .clks = apq8064_clks,480 .num_clks = ARRAY_SIZE(apq8064_clks),481};482 483static struct clk_rpm *ipq806x_clks[] = {484 [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,485 [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,486 [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,487 [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,488 [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,489 [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,490 [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,491 [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,492 [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,493 [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,494 [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,495 [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,496 [RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,497 [RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,498 [RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,499 [RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,500};501 502static const struct rpm_clk_desc rpm_clk_ipq806x = {503 .clks = ipq806x_clks,504 .num_clks = ARRAY_SIZE(ipq806x_clks),505};506 507static const struct of_device_id rpm_clk_match_table[] = {508 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },509 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },510 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },511 { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },512 { }513};514MODULE_DEVICE_TABLE(of, rpm_clk_match_table);515 516static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,517 void *data)518{519 struct rpm_cc *rcc = data;520 unsigned int idx = clkspec->args[0];521 522 if (idx >= rcc->num_clks) {523 pr_err("%s: invalid index %u\n", __func__, idx);524 return ERR_PTR(-EINVAL);525 }526 527 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);528}529 530static int rpm_clk_probe(struct platform_device *pdev)531{532 struct rpm_cc *rcc;533 int ret;534 size_t num_clks, i;535 struct qcom_rpm *rpm;536 struct clk_rpm **rpm_clks;537 const struct rpm_clk_desc *desc;538 539 rpm = dev_get_drvdata(pdev->dev.parent);540 if (!rpm) {541 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");542 return -ENODEV;543 }544 545 desc = of_device_get_match_data(&pdev->dev);546 if (!desc)547 return -EINVAL;548 549 rpm_clks = desc->clks;550 num_clks = desc->num_clks;551 552 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);553 if (!rcc)554 return -ENOMEM;555 556 rcc->clks = rpm_clks;557 rcc->num_clks = num_clks;558 mutex_init(&rcc->xo_lock);559 560 for (i = 0; i < num_clks; i++) {561 if (!rpm_clks[i])562 continue;563 564 rpm_clks[i]->rpm = rpm;565 rpm_clks[i]->rpm_cc = rcc;566 567 ret = clk_rpm_handoff(rpm_clks[i]);568 if (ret)569 goto err;570 }571 572 for (i = 0; i < num_clks; i++) {573 if (!rpm_clks[i])574 continue;575 576 ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);577 if (ret)578 goto err;579 }580 581 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,582 rcc);583 if (ret)584 goto err;585 586 return 0;587err:588 dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);589 return ret;590}591 592static struct platform_driver rpm_clk_driver = {593 .driver = {594 .name = "qcom-clk-rpm",595 .of_match_table = rpm_clk_match_table,596 },597 .probe = rpm_clk_probe,598};599 600static int __init rpm_clk_init(void)601{602 return platform_driver_register(&rpm_clk_driver);603}604core_initcall(rpm_clk_init);605 606static void __exit rpm_clk_exit(void)607{608 platform_driver_unregister(&rpm_clk_driver);609}610module_exit(rpm_clk_exit);611 612MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");613MODULE_LICENSE("GPL v2");614MODULE_ALIAS("platform:qcom-clk-rpm");615