1364 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2016, Linaro Limited4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.5 */6 7#include <linux/clk-provider.h>8#include <linux/err.h>9#include <linux/export.h>10#include <linux/init.h>11#include <linux/kernel.h>12#include <linux/module.h>13#include <linux/mutex.h>14#include <linux/of.h>15#include <linux/platform_device.h>16#include <linux/soc/qcom/smd-rpm.h>17 18#include <dt-bindings/clock/qcom,rpmcc.h>19 20#define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \21 type, r_id, key, ao_rate, ao_flags) \22 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \23 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \24 .rpm_res_type = (type), \25 .rpm_clk_id = (r_id), \26 .rpm_key = (key), \27 .peer = &clk_smd_rpm_##_prefix##_active, \28 .rate = INT_MAX, \29 .hw.init = &(struct clk_init_data){ \30 .ops = &clk_smd_rpm_ops, \31 .name = #_name, \32 .parent_data = &(const struct clk_parent_data){ \33 .fw_name = "xo", \34 .name = "xo_board", \35 }, \36 .num_parents = 1, \37 }, \38 }; \39 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \40 .rpm_res_type = (type), \41 .rpm_clk_id = (r_id), \42 .active_only = true, \43 .rpm_key = (key), \44 .peer = &clk_smd_rpm_##_prefix##_name, \45 .rate = (ao_rate), \46 .hw.init = &(struct clk_init_data){ \47 .ops = &clk_smd_rpm_ops, \48 .name = #_active, \49 .parent_data = &(const struct clk_parent_data){ \50 .fw_name = "xo", \51 .name = "xo_board", \52 }, \53 .num_parents = 1, \54 .flags = (ao_flags), \55 }, \56 }57 58#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\59 ao_rate, ao_flags) \60 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \61 type, r_id, key, ao_rate, ao_flags)62 63#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\64 type, r_id, r, key, ao_flags) \65 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \66 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \67 .rpm_res_type = (type), \68 .rpm_clk_id = (r_id), \69 .rpm_key = (key), \70 .branch = true, \71 .peer = &clk_smd_rpm_##_prefix##_active, \72 .rate = (r), \73 .hw.init = &(struct clk_init_data){ \74 .ops = &clk_smd_rpm_branch_ops, \75 .name = #_name, \76 .parent_data = &(const struct clk_parent_data){ \77 .fw_name = "xo", \78 .name = "xo_board", \79 }, \80 .num_parents = 1, \81 }, \82 }; \83 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \84 .rpm_res_type = (type), \85 .rpm_clk_id = (r_id), \86 .active_only = true, \87 .rpm_key = (key), \88 .branch = true, \89 .peer = &clk_smd_rpm_##_prefix##_name, \90 .rate = (r), \91 .hw.init = &(struct clk_init_data){ \92 .ops = &clk_smd_rpm_branch_ops, \93 .name = #_active, \94 .parent_data = &(const struct clk_parent_data){ \95 .fw_name = "xo", \96 .name = "xo_board", \97 }, \98 .num_parents = 1, \99 .flags = (ao_flags), \100 }, \101 }102 103#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \104 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \105 _name, _active, type, r_id, r, key, 0)106 107#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \108 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \109 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)110 111#define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \112 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \113 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \114 QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)115 116#define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \117 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \118 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \119 QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags)120 121#define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \122 __DEFINE_CLK_SMD_RPM( \123 _name##_clk_src, _name##_a_clk_src, \124 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0)125 126#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \127 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \128 _name##_clk, _name##_a_clk, \129 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0)130 131#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \132 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \133 _name, _name##_a, type, \134 r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags)135 136#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \137 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \138 type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0)139 140#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \141 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \142 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \143 QCOM_RPM_KEY_SOFTWARE_ENABLE)144 145#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \146 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \147 _name, _name##_a, \148 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \149 QCOM_RPM_KEY_SOFTWARE_ENABLE, 0)150 151#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \152 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \153 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \154 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \155 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)156 157#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)158 159static struct qcom_smd_rpm *rpmcc_smd_rpm;160 161struct clk_smd_rpm {162 const int rpm_res_type;163 const int rpm_key;164 const int rpm_clk_id;165 const bool active_only;166 bool enabled;167 bool branch;168 struct clk_smd_rpm *peer;169 struct clk_hw hw;170 unsigned long rate;171};172 173struct rpm_smd_clk_desc {174 struct clk_smd_rpm **clks;175 size_t num_clks;176 177 /*178 * Interconnect clocks are managed by the icc framework, this driver179 * only kickstarts them so that they don't get gated between180 * clk_smd_rpm_enable_scaling() and interconnect driver initialization.181 */182 const struct clk_smd_rpm ** const icc_clks;183 size_t num_icc_clks;184 bool scaling_before_handover;185};186 187static DEFINE_MUTEX(rpm_smd_clk_lock);188 189static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r)190{191 int ret;192 struct clk_smd_rpm_req req = {193 .key = cpu_to_le32(r->rpm_key),194 .nbytes = cpu_to_le32(sizeof(u32)),195 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),196 };197 198 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,199 r->rpm_res_type, r->rpm_clk_id, &req,200 sizeof(req));201 if (ret)202 return ret;203 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,204 r->rpm_res_type, r->rpm_clk_id, &req,205 sizeof(req));206 if (ret)207 return ret;208 209 return 0;210}211 212static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,213 unsigned long rate)214{215 struct clk_smd_rpm_req req = {216 .key = cpu_to_le32(r->rpm_key),217 .nbytes = cpu_to_le32(sizeof(u32)),218 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */219 };220 221 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,222 r->rpm_res_type, r->rpm_clk_id, &req,223 sizeof(req));224}225 226static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,227 unsigned long rate)228{229 struct clk_smd_rpm_req req = {230 .key = cpu_to_le32(r->rpm_key),231 .nbytes = cpu_to_le32(sizeof(u32)),232 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */233 };234 235 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,236 r->rpm_res_type, r->rpm_clk_id, &req,237 sizeof(req));238}239 240static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,241 unsigned long *active, unsigned long *sleep)242{243 *active = rate;244 245 /*246 * Active-only clocks don't care what the rate is during sleep. So,247 * they vote for zero.248 */249 if (r->active_only)250 *sleep = 0;251 else252 *sleep = *active;253}254 255static int clk_smd_rpm_prepare(struct clk_hw *hw)256{257 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);258 struct clk_smd_rpm *peer = r->peer;259 unsigned long this_rate = 0, this_sleep_rate = 0;260 unsigned long peer_rate = 0, peer_sleep_rate = 0;261 unsigned long active_rate, sleep_rate;262 int ret = 0;263 264 mutex_lock(&rpm_smd_clk_lock);265 266 /* Don't send requests to the RPM if the rate has not been set. */267 if (!r->rate)268 goto out;269 270 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);271 272 /* Take peer clock's rate into account only if it's enabled. */273 if (peer->enabled)274 to_active_sleep(peer, peer->rate,275 &peer_rate, &peer_sleep_rate);276 277 active_rate = max(this_rate, peer_rate);278 279 if (r->branch)280 active_rate = !!active_rate;281 282 ret = clk_smd_rpm_set_rate_active(r, active_rate);283 if (ret)284 goto out;285 286 sleep_rate = max(this_sleep_rate, peer_sleep_rate);287 if (r->branch)288 sleep_rate = !!sleep_rate;289 290 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);291 if (ret)292 /* Undo the active set vote and restore it */293 ret = clk_smd_rpm_set_rate_active(r, peer_rate);294 295out:296 if (!ret)297 r->enabled = true;298 299 mutex_unlock(&rpm_smd_clk_lock);300 301 return ret;302}303 304static void clk_smd_rpm_unprepare(struct clk_hw *hw)305{306 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);307 struct clk_smd_rpm *peer = r->peer;308 unsigned long peer_rate = 0, peer_sleep_rate = 0;309 unsigned long active_rate, sleep_rate;310 int ret;311 312 mutex_lock(&rpm_smd_clk_lock);313 314 if (!r->rate)315 goto out;316 317 /* Take peer clock's rate into account only if it's enabled. */318 if (peer->enabled)319 to_active_sleep(peer, peer->rate, &peer_rate,320 &peer_sleep_rate);321 322 active_rate = r->branch ? !!peer_rate : peer_rate;323 ret = clk_smd_rpm_set_rate_active(r, active_rate);324 if (ret)325 goto out;326 327 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;328 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);329 if (ret)330 goto out;331 332 r->enabled = false;333 334out:335 mutex_unlock(&rpm_smd_clk_lock);336}337 338static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,339 unsigned long parent_rate)340{341 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);342 struct clk_smd_rpm *peer = r->peer;343 unsigned long active_rate, sleep_rate;344 unsigned long this_rate = 0, this_sleep_rate = 0;345 unsigned long peer_rate = 0, peer_sleep_rate = 0;346 int ret = 0;347 348 mutex_lock(&rpm_smd_clk_lock);349 350 if (!r->enabled)351 goto out;352 353 to_active_sleep(r, rate, &this_rate, &this_sleep_rate);354 355 /* Take peer clock's rate into account only if it's enabled. */356 if (peer->enabled)357 to_active_sleep(peer, peer->rate,358 &peer_rate, &peer_sleep_rate);359 360 active_rate = max(this_rate, peer_rate);361 ret = clk_smd_rpm_set_rate_active(r, active_rate);362 if (ret)363 goto out;364 365 sleep_rate = max(this_sleep_rate, peer_sleep_rate);366 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);367 if (ret)368 goto out;369 370 r->rate = rate;371 372out:373 mutex_unlock(&rpm_smd_clk_lock);374 375 return ret;376}377 378static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,379 unsigned long *parent_rate)380{381 /*382 * RPM handles rate rounding and we don't have a way to383 * know what the rate will be, so just return whatever384 * rate is requested.385 */386 return rate;387}388 389static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,390 unsigned long parent_rate)391{392 struct clk_smd_rpm *r = to_clk_smd_rpm(hw);393 394 /*395 * RPM handles rate rounding and we don't have a way to396 * know what the rate will be, so just return whatever397 * rate was set.398 */399 return r->rate;400}401 402static int clk_smd_rpm_enable_scaling(void)403{404 int ret;405 struct clk_smd_rpm_req req = {406 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),407 .nbytes = cpu_to_le32(sizeof(u32)),408 .value = cpu_to_le32(1),409 };410 411 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE,412 QCOM_SMD_RPM_MISC_CLK,413 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));414 if (ret) {415 pr_err("RPM clock scaling (sleep set) not enabled!\n");416 return ret;417 }418 419 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE,420 QCOM_SMD_RPM_MISC_CLK,421 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));422 if (ret) {423 pr_err("RPM clock scaling (active set) not enabled!\n");424 return ret;425 }426 427 pr_debug("%s: RPM clock scaling is enabled\n", __func__);428 return 0;429}430 431static const struct clk_ops clk_smd_rpm_ops = {432 .prepare = clk_smd_rpm_prepare,433 .unprepare = clk_smd_rpm_unprepare,434 .set_rate = clk_smd_rpm_set_rate,435 .round_rate = clk_smd_rpm_round_rate,436 .recalc_rate = clk_smd_rpm_recalc_rate,437};438 439static const struct clk_ops clk_smd_rpm_branch_ops = {440 .prepare = clk_smd_rpm_prepare,441 .unprepare = clk_smd_rpm_unprepare,442 .recalc_rate = clk_smd_rpm_recalc_rate,443};444 445/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */446DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL);447DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000);448DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1);449DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0);450 451DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);452 453DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000);454DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000);455DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1);456DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2);457 458DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL);459DEFINE_CLK_SMD_RPM_BUS(snoc, 1);460DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2);461DEFINE_CLK_SMD_RPM_BUS(cnoc, 2);462DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3);463DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0);464DEFINE_CLK_SMD_RPM_BUS(cnoc, 1);465DEFINE_CLK_SMD_RPM_BUS(snoc, 2);466DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5);467 468DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0);469DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1);470DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1);471DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2);472DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2);473 474DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0);475DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1);476DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2);477 478DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0);479 480DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0);481 482DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0);483DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0);484DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1);485 486DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0);487 488DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0);489 490DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0);491 492DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000);493DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000);494DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000);495DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000);496DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000);497DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000);498DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000);499DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000);500DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000);501 502DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000);503 504DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000);505DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000);506DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000);507DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000);508DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000);509 510DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000);511DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000);512DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000);513DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000);514 515static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = {516 &clk_smd_rpm_bimc_clk,517 &clk_smd_rpm_bus_0_pcnoc_clk,518};519 520static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = {521 &clk_smd_rpm_bimc_clk,522 &clk_smd_rpm_bus_0_pcnoc_clk,523 &clk_smd_rpm_bus_1_snoc_clk,524};525 526static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = {527 &clk_smd_rpm_bimc_clk,528 &clk_smd_rpm_bus_0_pcnoc_clk,529 &clk_smd_rpm_bus_1_snoc_clk,530 &clk_smd_rpm_bus_2_sysmmnoc_clk,531};532 533static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = {534 &clk_smd_rpm_bimc_clk,535 &clk_smd_rpm_bus_0_pcnoc_clk,536 &clk_smd_rpm_bus_1_snoc_clk,537 &clk_smd_rpm_bus_2_cnoc_clk,538 &clk_smd_rpm_ocmemgx_clk,539};540 541static const struct clk_smd_rpm *msm8996_icc_clks[] = {542 &clk_smd_rpm_bimc_clk,543 &clk_smd_rpm_branch_aggre1_noc_clk,544 &clk_smd_rpm_branch_aggre2_noc_clk,545 &clk_smd_rpm_bus_0_pcnoc_clk,546 &clk_smd_rpm_bus_1_snoc_clk,547 &clk_smd_rpm_bus_2_cnoc_clk,548 &clk_smd_rpm_mmssnoc_axi_rpm_clk,549};550 551static const struct clk_smd_rpm *msm8998_icc_clks[] = {552 &clk_smd_rpm_aggre1_noc_clk,553 &clk_smd_rpm_aggre2_noc_clk,554 &clk_smd_rpm_bimc_clk,555 &clk_smd_rpm_bus_1_snoc_clk,556 &clk_smd_rpm_bus_2_cnoc_clk,557 &clk_smd_rpm_mmssnoc_axi_rpm_clk,558};559 560static const struct clk_smd_rpm *sdm660_icc_clks[] = {561 &clk_smd_rpm_aggre2_noc_clk,562 &clk_smd_rpm_bimc_clk,563 &clk_smd_rpm_bus_1_snoc_clk,564 &clk_smd_rpm_bus_2_cnoc_clk,565 &clk_smd_rpm_mmssnoc_axi_rpm_clk,566};567 568static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = {569 &clk_smd_rpm_bimc_clk,570 &clk_smd_rpm_bus_1_cnoc_clk,571 &clk_smd_rpm_mmnrt_clk,572 &clk_smd_rpm_mmrt_clk,573 &clk_smd_rpm_qup_clk,574 &clk_smd_rpm_bus_2_snoc_clk,575};576 577static const struct clk_smd_rpm *qcm2290_icc_clks[] = {578 &clk_smd_rpm_bimc_clk,579 &clk_smd_rpm_bus_1_cnoc_clk,580 &clk_smd_rpm_mmnrt_clk,581 &clk_smd_rpm_mmrt_clk,582 &clk_smd_rpm_qup_clk,583 &clk_smd_rpm_bus_2_snoc_clk,584 &clk_smd_rpm_cpuss_gnoc_clk,585};586 587static struct clk_smd_rpm *msm8909_clks[] = {588 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,589 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,590 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,591 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,592 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,593 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,594 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,595 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,596 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,597 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,598 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,599 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,600 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,601 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,602 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,603 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,604 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,605 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,606 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,607 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,608};609 610static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {611 .clks = msm8909_clks,612 .num_clks = ARRAY_SIZE(msm8909_clks),613 .icc_clks = bimc_pcnoc_snoc_icc_clks,614 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),615};616 617static struct clk_smd_rpm *msm8916_clks[] = {618 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,619 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,620 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,621 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,622 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,623 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,624 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,625 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,626 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,627 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,628 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,629 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,630 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,631 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,632 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,633 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,634 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,635 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,636};637 638static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {639 .clks = msm8916_clks,640 .num_clks = ARRAY_SIZE(msm8916_clks),641 .icc_clks = bimc_pcnoc_snoc_icc_clks,642 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),643};644 645static struct clk_smd_rpm *msm8917_clks[] = {646 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,647 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,648 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,649 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,650 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,651 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,652 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,653 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,654 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,655 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,656 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,657 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,658 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,659 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,660 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,661 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,662 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,663 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,664};665 666static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {667 .clks = msm8917_clks,668 .num_clks = ARRAY_SIZE(msm8917_clks),669 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,670 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),671};672 673static struct clk_smd_rpm *msm8936_clks[] = {674 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,675 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,676 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,677 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,678 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,679 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,680 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,681 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,682 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,683 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,684 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,685 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,686 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,687 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,688 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,689 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,690 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,691 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,692 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,693 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,694};695 696static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {697 .clks = msm8936_clks,698 .num_clks = ARRAY_SIZE(msm8936_clks),699 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,700 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),701};702 703static struct clk_smd_rpm *msm8974_clks[] = {704 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,705 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,706 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,707 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,708 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,709 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,710 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,711 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,712 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0,713 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a,714 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1,715 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a,716 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0,717 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a,718 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1,719 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a,720 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2,721 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a,722 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk,723 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a,724 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,725 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,726 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,727 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,728 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin,729 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin,730 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin,731 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin,732 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin,733 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin,734 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin,735 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin,736 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin,737 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin,738};739 740static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {741 .clks = msm8974_clks,742 .num_clks = ARRAY_SIZE(msm8974_clks),743 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,744 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),745 .scaling_before_handover = true,746};747 748static struct clk_smd_rpm *msm8976_clks[] = {749 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,750 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,751 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,752 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,753 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,754 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,755 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,756 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,757 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,758 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,759 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,760 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,761 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,762 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,763 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,764 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,765 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,766 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,767};768 769static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {770 .clks = msm8976_clks,771 .num_clks = ARRAY_SIZE(msm8976_clks),772 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,773 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),774};775 776static struct clk_smd_rpm *msm8992_clks[] = {777 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,778 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,779 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,780 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,781 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,782 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,783 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,784 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,785 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,786 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,787 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,788 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,789 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,790 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,791 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,792 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,793 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,794 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,795 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,796 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,797 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,798 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,799 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,800 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,801 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,802 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,803 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,804 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,805 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,806 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,807 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,808 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,809 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,810 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,811 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,812 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,813 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,814 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,815 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,816 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,817};818 819static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {820 .clks = msm8992_clks,821 .num_clks = ARRAY_SIZE(msm8992_clks),822 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,823 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),824};825 826static struct clk_smd_rpm *msm8994_clks[] = {827 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,828 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,829 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src,830 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src,831 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,832 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,833 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,834 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,835 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,836 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,837 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,838 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,839 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,840 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,841 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,842 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,843 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,844 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,845 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,846 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,847 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,848 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,849 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk,850 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk,851 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk,852 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk,853 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,854 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,855 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,856 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,857 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,858 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,859 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,860 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,861 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,862 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,863 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,864 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,865 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk,866 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk,867 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk,868 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk,869};870 871static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {872 .clks = msm8994_clks,873 .num_clks = ARRAY_SIZE(msm8994_clks),874 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks,875 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks),876};877 878static struct clk_smd_rpm *msm8996_clks[] = {879 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,880 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,881 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,882 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,883 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,884 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,885 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,886 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,887 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,888 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,889 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,890 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,891 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,892 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,893 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,894 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,895 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,896 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,897 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,898 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,899 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,900 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,901 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,902 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,903 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,904 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,905 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,906 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,907 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,908 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,909 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,910 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,911};912 913static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {914 .clks = msm8996_clks,915 .num_clks = ARRAY_SIZE(msm8996_clks),916 .icc_clks = msm8996_icc_clks,917 .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks),918};919 920static struct clk_smd_rpm *qcs404_clks[] = {921 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,922 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,923 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,924 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,925 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,926 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,927 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,928 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,929 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,930 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,931 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,932 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,933 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,934 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,935 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,936 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,937 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk,938 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a,939 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin,940 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin,941};942 943static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {944 .clks = qcs404_clks,945 .num_clks = ARRAY_SIZE(qcs404_clks),946 .icc_clks = bimc_pcnoc_snoc_icc_clks,947 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks),948};949 950static struct clk_smd_rpm *msm8998_clks[] = {951 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,952 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,953 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,954 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,955 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,956 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,957 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,958 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,959 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,960 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,961 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3,962 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a,963 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,964 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,965 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,966 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,967 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,968 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,969 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,970 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,971 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,972 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,973 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,974 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,975 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,976 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,977 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,978 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,979 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,980 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,981 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,982 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,983 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3,984 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a,985 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,986 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,987 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,988 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,989 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin,990 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin,991};992 993static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {994 .clks = msm8998_clks,995 .num_clks = ARRAY_SIZE(msm8998_clks),996 .icc_clks = msm8998_icc_clks,997 .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks),998};999 1000static struct clk_smd_rpm *sdm660_clks[] = {1001 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1002 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1003 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,1004 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,1005 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1006 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1007 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,1008 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,1009 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,1010 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,1011 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,1012 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,1013 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1,1014 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a,1015 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1,1016 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a,1017 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,1018 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,1019 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,1020 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,1021 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,1022 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,1023 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin,1024 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin,1025 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin,1026 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin,1027 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin,1028 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin,1029};1030 1031static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {1032 .clks = sdm660_clks,1033 .num_clks = ARRAY_SIZE(sdm660_clks),1034 .icc_clks = sdm660_icc_clks,1035 .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks),1036};1037 1038static struct clk_smd_rpm *mdm9607_clks[] = {1039 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1040 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1041 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,1042 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,1043 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,1044 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,1045 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,1046 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,1047 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,1048 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,1049};1050 1051static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {1052 .clks = mdm9607_clks,1053 .num_clks = ARRAY_SIZE(mdm9607_clks),1054 .icc_clks = bimc_pcnoc_icc_clks,1055 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks),1056};1057 1058static struct clk_smd_rpm *msm8953_clks[] = {1059 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1060 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1061 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1062 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1063 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,1064 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,1065 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,1066 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,1067 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,1068 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,1069 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,1070 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,1071 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk,1072 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a,1073 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,1074 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,1075 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,1076 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,1077 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,1078 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,1079};1080 1081static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {1082 .clks = msm8953_clks,1083 .num_clks = ARRAY_SIZE(msm8953_clks),1084 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks,1085 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks),1086};1087 1088static struct clk_smd_rpm *sm6125_clks[] = {1089 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1090 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1091 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,1092 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,1093 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,1094 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,1095 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,1096 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,1097 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1098 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1099 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,1100 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,1101 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1,1102 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a,1103 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,1104 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,1105 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3,1106 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a,1107 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,1108 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,1109 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,1110 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,1111};1112 1113static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {1114 .clks = sm6125_clks,1115 .num_clks = ARRAY_SIZE(sm6125_clks),1116 .icc_clks = sm_qnoc_icc_clks,1117 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)1118};1119 1120/* SM6115 */1121static struct clk_smd_rpm *sm6115_clks[] = {1122 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1123 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1124 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,1125 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,1126 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1,1127 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a,1128 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,1129 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,1130 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1131 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1132 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,1133 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,1134 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,1135 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,1136 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,1137 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,1138 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin,1139 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin,1140 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin,1141 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin,1142};1143 1144static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {1145 .clks = sm6115_clks,1146 .num_clks = ARRAY_SIZE(sm6115_clks),1147 .icc_clks = sm_qnoc_icc_clks,1148 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)1149};1150 1151static struct clk_smd_rpm *sm6375_clks[] = {1152 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1153 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1154 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,1155 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,1156 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1157 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1158 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,1159 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,1160 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,1161 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,1162 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,1163 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,1164 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,1165 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,1166 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,1167 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,1168 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log,1169};1170 1171static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {1172 .clks = sm6375_clks,1173 .num_clks = ARRAY_SIZE(sm6375_clks),1174 .icc_clks = sm_qnoc_icc_clks,1175 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks)1176};1177 1178static struct clk_smd_rpm *qcm2290_clks[] = {1179 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,1180 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,1181 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk,1182 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk,1183 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2,1184 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a,1185 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3,1186 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a,1187 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk,1188 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk,1189 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk,1190 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk,1191 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk,1192 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk,1193 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk,1194 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk,1195 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk,1196 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk,1197 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk,1198 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk,1199 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk,1200 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk,1201 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,1202 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,1203};1204 1205static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {1206 .clks = qcm2290_clks,1207 .num_clks = ARRAY_SIZE(qcm2290_clks),1208 .icc_clks = qcm2290_icc_clks,1209 .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks)1210};1211 1212static const struct of_device_id rpm_smd_clk_match_table[] = {1213 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },1214 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },1215 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },1216 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },1217 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 },1218 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },1219 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },1220 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },1221 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },1222 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },1223 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },1224 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },1225 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },1226 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },1227 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },1228 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },1229 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },1230 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },1231 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 },1232 { }1233};1234MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);1235 1236static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,1237 void *data)1238{1239 const struct rpm_smd_clk_desc *desc = data;1240 unsigned int idx = clkspec->args[0];1241 1242 if (idx >= desc->num_clks) {1243 pr_err("%s: invalid index %u\n", __func__, idx);1244 return ERR_PTR(-EINVAL);1245 }1246 1247 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);1248}1249 1250static void rpm_smd_unregister_icc(void *data)1251{1252 struct platform_device *icc_pdev = data;1253 1254 platform_device_unregister(icc_pdev);1255}1256 1257static int rpm_smd_clk_probe(struct platform_device *pdev)1258{1259 int ret;1260 size_t num_clks, i;1261 struct clk_smd_rpm **rpm_smd_clks;1262 const struct rpm_smd_clk_desc *desc;1263 struct platform_device *icc_pdev;1264 1265 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent);1266 if (!rpmcc_smd_rpm) {1267 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");1268 return -ENODEV;1269 }1270 1271 desc = of_device_get_match_data(&pdev->dev);1272 if (!desc)1273 return -EINVAL;1274 1275 rpm_smd_clks = desc->clks;1276 num_clks = desc->num_clks;1277 1278 if (desc->scaling_before_handover) {1279 ret = clk_smd_rpm_enable_scaling();1280 if (ret)1281 goto err;1282 }1283 1284 for (i = 0; i < num_clks; i++) {1285 if (!rpm_smd_clks[i])1286 continue;1287 1288 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);1289 if (ret)1290 goto err;1291 }1292 1293 for (i = 0; i < desc->num_icc_clks; i++) {1294 if (!desc->icc_clks[i])1295 continue;1296 1297 ret = clk_smd_rpm_handoff(desc->icc_clks[i]);1298 if (ret)1299 goto err;1300 }1301 1302 if (!desc->scaling_before_handover) {1303 ret = clk_smd_rpm_enable_scaling();1304 if (ret)1305 goto err;1306 }1307 1308 for (i = 0; i < num_clks; i++) {1309 if (!rpm_smd_clks[i])1310 continue;1311 1312 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);1313 if (ret)1314 goto err;1315 }1316 1317 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,1318 (void *)desc);1319 if (ret)1320 goto err;1321 1322 icc_pdev = platform_device_register_data(pdev->dev.parent,1323 "icc_smd_rpm", -1, NULL, 0);1324 if (IS_ERR(icc_pdev)) {1325 dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n",1326 icc_pdev);1327 /* No need to unregister clocks because of this */1328 } else {1329 ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc,1330 icc_pdev);1331 if (ret)1332 goto err;1333 }1334 1335 return 0;1336err:1337 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);1338 return ret;1339}1340 1341static struct platform_driver rpm_smd_clk_driver = {1342 .driver = {1343 .name = "qcom-clk-smd-rpm",1344 .of_match_table = rpm_smd_clk_match_table,1345 },1346 .probe = rpm_smd_clk_probe,1347};1348 1349static int __init rpm_smd_clk_init(void)1350{1351 return platform_driver_register(&rpm_smd_clk_driver);1352}1353core_initcall(rpm_smd_clk_init);1354 1355static void __exit rpm_smd_clk_exit(void)1356{1357 platform_driver_unregister(&rpm_smd_clk_driver);1358}1359module_exit(rpm_smd_clk_exit);1360 1361MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");1362MODULE_LICENSE("GPL v2");1363MODULE_ALIAS("platform:qcom-clk-smd-rpm");1364