1807 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.4 * Copyright (c) 2022, Linaro Ltd.5 */6 7#include <linux/clk.h>8#include <linux/clk-provider.h>9#include <linux/err.h>10#include <linux/kernel.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/platform_device.h>14#include <linux/regmap.h>15#include <linux/pm_runtime.h>16 17#include <dt-bindings/clock/qcom,sm8450-dispcc.h>18 19#include "common.h"20#include "clk-alpha-pll.h"21#include "clk-branch.h"22#include "clk-pll.h"23#include "clk-rcg.h"24#include "clk-regmap.h"25#include "clk-regmap-divider.h"26#include "clk-regmap-mux.h"27#include "reset.h"28#include "gdsc.h"29 30/* Need to match the order of clocks in DT binding */31enum {32 DT_BI_TCXO,33 DT_BI_TCXO_AO,34 DT_AHB_CLK,35 DT_SLEEP_CLK,36 37 DT_DSI0_PHY_PLL_OUT_BYTECLK,38 DT_DSI0_PHY_PLL_OUT_DSICLK,39 DT_DSI1_PHY_PLL_OUT_BYTECLK,40 DT_DSI1_PHY_PLL_OUT_DSICLK,41 42 DT_DP0_PHY_PLL_LINK_CLK,43 DT_DP0_PHY_PLL_VCO_DIV_CLK,44 DT_DP1_PHY_PLL_LINK_CLK,45 DT_DP1_PHY_PLL_VCO_DIV_CLK,46 DT_DP2_PHY_PLL_LINK_CLK,47 DT_DP2_PHY_PLL_VCO_DIV_CLK,48 DT_DP3_PHY_PLL_LINK_CLK,49 DT_DP3_PHY_PLL_VCO_DIV_CLK,50};51 52#define DISP_CC_MISC_CMD 0xF00053 54enum {55 P_BI_TCXO,56 P_DISP_CC_PLL0_OUT_MAIN,57 P_DISP_CC_PLL1_OUT_EVEN,58 P_DISP_CC_PLL1_OUT_MAIN,59 P_DP0_PHY_PLL_LINK_CLK,60 P_DP0_PHY_PLL_VCO_DIV_CLK,61 P_DP1_PHY_PLL_LINK_CLK,62 P_DP1_PHY_PLL_VCO_DIV_CLK,63 P_DP2_PHY_PLL_LINK_CLK,64 P_DP2_PHY_PLL_VCO_DIV_CLK,65 P_DP3_PHY_PLL_LINK_CLK,66 P_DP3_PHY_PLL_VCO_DIV_CLK,67 P_DSI0_PHY_PLL_OUT_BYTECLK,68 P_DSI0_PHY_PLL_OUT_DSICLK,69 P_DSI1_PHY_PLL_OUT_BYTECLK,70 P_DSI1_PHY_PLL_OUT_DSICLK,71 P_SLEEP_CLK,72};73 74static const struct pll_vco lucid_evo_vco[] = {75 { 249600000, 2000000000, 0 },76};77 78static const struct alpha_pll_config disp_cc_pll0_config = {79 .l = 0xD,80 .alpha = 0x6492,81 .config_ctl_val = 0x20485699,82 .config_ctl_hi_val = 0x00182261,83 .config_ctl_hi1_val = 0x32AA299C,84 .user_ctl_val = 0x00000000,85 .user_ctl_hi_val = 0x00000805,86};87 88static struct clk_alpha_pll disp_cc_pll0 = {89 .offset = 0x0,90 .vco_table = lucid_evo_vco,91 .num_vco = ARRAY_SIZE(lucid_evo_vco),92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],93 .clkr = {94 .hw.init = &(struct clk_init_data) {95 .name = "disp_cc_pll0",96 .parent_data = &(const struct clk_parent_data) {97 .index = DT_BI_TCXO,98 },99 .num_parents = 1,100 .ops = &clk_alpha_pll_reset_lucid_evo_ops,101 },102 },103};104 105static const struct alpha_pll_config disp_cc_pll1_config = {106 .l = 0x1F,107 .alpha = 0x4000,108 .config_ctl_val = 0x20485699,109 .config_ctl_hi_val = 0x00182261,110 .config_ctl_hi1_val = 0x32AA299C,111 .user_ctl_val = 0x00000000,112 .user_ctl_hi_val = 0x00000805,113};114 115static struct clk_alpha_pll disp_cc_pll1 = {116 .offset = 0x1000,117 .vco_table = lucid_evo_vco,118 .num_vco = ARRAY_SIZE(lucid_evo_vco),119 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],120 .clkr = {121 .hw.init = &(struct clk_init_data) {122 .name = "disp_cc_pll1",123 .parent_data = &(const struct clk_parent_data) {124 .index = DT_BI_TCXO,125 },126 .num_parents = 1,127 .ops = &clk_alpha_pll_reset_lucid_evo_ops,128 },129 },130};131 132static const struct parent_map disp_cc_parent_map_0[] = {133 { P_BI_TCXO, 0 },134 { P_DP0_PHY_PLL_LINK_CLK, 1 },135 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },136 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },137 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },138 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },139};140 141static const struct clk_parent_data disp_cc_parent_data_0[] = {142 { .index = DT_BI_TCXO },143 { .index = DT_DP0_PHY_PLL_LINK_CLK },144 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },145 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },146 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },147 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },148};149 150static const struct parent_map disp_cc_parent_map_1[] = {151 { P_BI_TCXO, 0 },152};153 154static const struct clk_parent_data disp_cc_parent_data_1[] = {155 { .index = DT_BI_TCXO },156};157 158static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {159 { .index = DT_BI_TCXO_AO },160};161 162static const struct parent_map disp_cc_parent_map_2[] = {163 { P_BI_TCXO, 0 },164 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },165 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },166 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },167 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },168};169 170static const struct clk_parent_data disp_cc_parent_data_2[] = {171 { .index = DT_BI_TCXO },172 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },173 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },174 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },175 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },176};177 178static const struct parent_map disp_cc_parent_map_3[] = {179 { P_BI_TCXO, 0 },180 { P_DP0_PHY_PLL_LINK_CLK, 1 },181 { P_DP1_PHY_PLL_LINK_CLK, 2 },182 { P_DP2_PHY_PLL_LINK_CLK, 3 },183 { P_DP3_PHY_PLL_LINK_CLK, 4 },184};185 186static const struct clk_parent_data disp_cc_parent_data_3[] = {187 { .index = DT_BI_TCXO },188 { .index = DT_DP0_PHY_PLL_LINK_CLK },189 { .index = DT_DP1_PHY_PLL_LINK_CLK },190 { .index = DT_DP2_PHY_PLL_LINK_CLK },191 { .index = DT_DP3_PHY_PLL_LINK_CLK },192};193 194static const struct parent_map disp_cc_parent_map_4[] = {195 { P_BI_TCXO, 0 },196 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },197 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },198};199 200static const struct clk_parent_data disp_cc_parent_data_4[] = {201 { .index = DT_BI_TCXO },202 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },203 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },204};205 206static const struct parent_map disp_cc_parent_map_5[] = {207 { P_BI_TCXO, 0 },208 { P_DISP_CC_PLL0_OUT_MAIN, 1 },209 { P_DISP_CC_PLL1_OUT_MAIN, 4 },210 { P_DISP_CC_PLL1_OUT_EVEN, 6 },211};212 213static const struct clk_parent_data disp_cc_parent_data_5[] = {214 { .index = DT_BI_TCXO },215 { .hw = &disp_cc_pll0.clkr.hw },216 { .hw = &disp_cc_pll1.clkr.hw },217 { .hw = &disp_cc_pll1.clkr.hw },218};219 220static const struct parent_map disp_cc_parent_map_6[] = {221 { P_BI_TCXO, 0 },222 { P_DISP_CC_PLL1_OUT_MAIN, 4 },223 { P_DISP_CC_PLL1_OUT_EVEN, 6 },224};225 226static const struct clk_parent_data disp_cc_parent_data_6[] = {227 { .index = DT_BI_TCXO },228 { .hw = &disp_cc_pll1.clkr.hw },229 { .hw = &disp_cc_pll1.clkr.hw },230};231 232static const struct parent_map disp_cc_parent_map_7[] = {233 { P_SLEEP_CLK, 0 },234};235 236static const struct clk_parent_data disp_cc_parent_data_7[] = {237 { .index = DT_SLEEP_CLK },238};239 240static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {241 F(19200000, P_BI_TCXO, 1, 0, 0),242 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),243 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),244 { }245};246 247static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {248 .cmd_rcgr = 0x8324,249 .mnd_width = 0,250 .hid_width = 5,251 .parent_map = disp_cc_parent_map_6,252 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,253 .clkr.hw.init = &(struct clk_init_data) {254 .name = "disp_cc_mdss_ahb_clk_src",255 .parent_data = disp_cc_parent_data_6,256 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),257 .flags = CLK_SET_RATE_PARENT,258 .ops = &clk_rcg2_shared_ops,259 },260};261 262static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {263 F(19200000, P_BI_TCXO, 1, 0, 0),264 { }265};266 267static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {268 .cmd_rcgr = 0x8134,269 .mnd_width = 0,270 .hid_width = 5,271 .parent_map = disp_cc_parent_map_2,272 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,273 .clkr.hw.init = &(struct clk_init_data) {274 .name = "disp_cc_mdss_byte0_clk_src",275 .parent_data = disp_cc_parent_data_2,276 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),277 .flags = CLK_SET_RATE_PARENT,278 .ops = &clk_byte2_ops,279 },280};281 282static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {283 .cmd_rcgr = 0x8150,284 .mnd_width = 0,285 .hid_width = 5,286 .parent_map = disp_cc_parent_map_2,287 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,288 .clkr.hw.init = &(struct clk_init_data) {289 .name = "disp_cc_mdss_byte1_clk_src",290 .parent_data = disp_cc_parent_data_2,291 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),292 .flags = CLK_SET_RATE_PARENT,293 .ops = &clk_byte2_ops,294 },295};296 297static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {298 .cmd_rcgr = 0x81ec,299 .mnd_width = 0,300 .hid_width = 5,301 .parent_map = disp_cc_parent_map_1,302 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,303 .clkr.hw.init = &(struct clk_init_data) {304 .name = "disp_cc_mdss_dptx0_aux_clk_src",305 .parent_data = disp_cc_parent_data_1,306 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),307 .flags = CLK_SET_RATE_PARENT,308 .ops = &clk_rcg2_ops,309 },310};311 312static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {313 .cmd_rcgr = 0x819c,314 .mnd_width = 0,315 .hid_width = 5,316 .parent_map = disp_cc_parent_map_3,317 .clkr.hw.init = &(struct clk_init_data) {318 .name = "disp_cc_mdss_dptx0_link_clk_src",319 .parent_data = disp_cc_parent_data_3,320 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),321 .flags = CLK_SET_RATE_PARENT,322 .ops = &clk_byte2_ops,323 },324};325 326static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {327 .cmd_rcgr = 0x81bc,328 .mnd_width = 16,329 .hid_width = 5,330 .parent_map = disp_cc_parent_map_0,331 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,332 .clkr.hw.init = &(struct clk_init_data) {333 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",334 .parent_data = disp_cc_parent_data_0,335 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),336 .flags = CLK_SET_RATE_PARENT,337 .ops = &clk_dp_ops,338 },339};340 341static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {342 .cmd_rcgr = 0x81d4,343 .mnd_width = 16,344 .hid_width = 5,345 .parent_map = disp_cc_parent_map_0,346 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,347 .clkr.hw.init = &(struct clk_init_data) {348 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",349 .parent_data = disp_cc_parent_data_0,350 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),351 .flags = CLK_SET_RATE_PARENT,352 .ops = &clk_dp_ops,353 },354};355 356static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {357 .cmd_rcgr = 0x8254,358 .mnd_width = 0,359 .hid_width = 5,360 .parent_map = disp_cc_parent_map_1,361 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,362 .clkr.hw.init = &(struct clk_init_data) {363 .name = "disp_cc_mdss_dptx1_aux_clk_src",364 .parent_data = disp_cc_parent_data_1,365 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),366 .flags = CLK_SET_RATE_PARENT,367 .ops = &clk_dp_ops,368 },369};370 371static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {372 .cmd_rcgr = 0x8234,373 .mnd_width = 0,374 .hid_width = 5,375 .parent_map = disp_cc_parent_map_3,376 .clkr.hw.init = &(struct clk_init_data) {377 .name = "disp_cc_mdss_dptx1_link_clk_src",378 .parent_data = disp_cc_parent_data_3,379 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),380 .flags = CLK_SET_RATE_PARENT,381 .ops = &clk_byte2_ops,382 },383};384 385static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {386 .cmd_rcgr = 0x8204,387 .mnd_width = 16,388 .hid_width = 5,389 .parent_map = disp_cc_parent_map_0,390 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,391 .clkr.hw.init = &(struct clk_init_data) {392 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",393 .parent_data = disp_cc_parent_data_0,394 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),395 .flags = CLK_SET_RATE_PARENT,396 .ops = &clk_dp_ops,397 },398};399 400static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {401 .cmd_rcgr = 0x821c,402 .mnd_width = 16,403 .hid_width = 5,404 .parent_map = disp_cc_parent_map_0,405 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,406 .clkr.hw.init = &(struct clk_init_data) {407 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",408 .parent_data = disp_cc_parent_data_0,409 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),410 .flags = CLK_SET_RATE_PARENT,411 .ops = &clk_dp_ops,412 },413};414 415static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {416 .cmd_rcgr = 0x82bc,417 .mnd_width = 0,418 .hid_width = 5,419 .parent_map = disp_cc_parent_map_1,420 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,421 .clkr.hw.init = &(struct clk_init_data) {422 .name = "disp_cc_mdss_dptx2_aux_clk_src",423 .parent_data = disp_cc_parent_data_1,424 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),425 .flags = CLK_SET_RATE_PARENT,426 .ops = &clk_rcg2_ops,427 },428};429 430static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {431 .cmd_rcgr = 0x826c,432 .mnd_width = 0,433 .hid_width = 5,434 .parent_map = disp_cc_parent_map_3,435 .clkr.hw.init = &(struct clk_init_data) {436 .name = "disp_cc_mdss_dptx2_link_clk_src",437 .parent_data = disp_cc_parent_data_3,438 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),439 .flags = CLK_SET_RATE_PARENT,440 .ops = &clk_byte2_ops,441 },442};443 444static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {445 .cmd_rcgr = 0x828c,446 .mnd_width = 16,447 .hid_width = 5,448 .parent_map = disp_cc_parent_map_0,449 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,450 .clkr.hw.init = &(struct clk_init_data) {451 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",452 .parent_data = disp_cc_parent_data_0,453 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),454 .flags = CLK_SET_RATE_PARENT,455 .ops = &clk_dp_ops,456 },457};458 459static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {460 .cmd_rcgr = 0x82a4,461 .mnd_width = 16,462 .hid_width = 5,463 .parent_map = disp_cc_parent_map_0,464 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,465 .clkr.hw.init = &(struct clk_init_data) {466 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",467 .parent_data = disp_cc_parent_data_0,468 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),469 .flags = CLK_SET_RATE_PARENT,470 .ops = &clk_dp_ops,471 },472};473 474static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {475 .cmd_rcgr = 0x8308,476 .mnd_width = 0,477 .hid_width = 5,478 .parent_map = disp_cc_parent_map_1,479 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,480 .clkr.hw.init = &(struct clk_init_data) {481 .name = "disp_cc_mdss_dptx3_aux_clk_src",482 .parent_data = disp_cc_parent_data_1,483 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),484 .flags = CLK_SET_RATE_PARENT,485 .ops = &clk_rcg2_ops,486 },487};488 489static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {490 .cmd_rcgr = 0x82ec,491 .mnd_width = 0,492 .hid_width = 5,493 .parent_map = disp_cc_parent_map_3,494 .clkr.hw.init = &(struct clk_init_data) {495 .name = "disp_cc_mdss_dptx3_link_clk_src",496 .parent_data = disp_cc_parent_data_3,497 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),498 .flags = CLK_SET_RATE_PARENT,499 .ops = &clk_byte2_ops,500 },501};502 503static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {504 .cmd_rcgr = 0x82d4,505 .mnd_width = 16,506 .hid_width = 5,507 .parent_map = disp_cc_parent_map_0,508 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,509 .clkr.hw.init = &(struct clk_init_data) {510 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",511 .parent_data = disp_cc_parent_data_0,512 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),513 .flags = CLK_SET_RATE_PARENT,514 .ops = &clk_dp_ops,515 },516};517 518static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {519 .cmd_rcgr = 0x816c,520 .mnd_width = 0,521 .hid_width = 5,522 .parent_map = disp_cc_parent_map_4,523 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,524 .clkr.hw.init = &(struct clk_init_data) {525 .name = "disp_cc_mdss_esc0_clk_src",526 .parent_data = disp_cc_parent_data_4,527 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),528 .flags = CLK_SET_RATE_PARENT,529 .ops = &clk_rcg2_ops,530 },531};532 533static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {534 .cmd_rcgr = 0x8184,535 .mnd_width = 0,536 .hid_width = 5,537 .parent_map = disp_cc_parent_map_4,538 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,539 .clkr.hw.init = &(struct clk_init_data) {540 .name = "disp_cc_mdss_esc1_clk_src",541 .parent_data = disp_cc_parent_data_4,542 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),543 .flags = CLK_SET_RATE_PARENT,544 .ops = &clk_rcg2_ops,545 },546};547 548static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {549 F(19200000, P_BI_TCXO, 1, 0, 0),550 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),551 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),552 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),553 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),554 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),555 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),556 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),557 F(500000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),558 { }559};560 561static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {562 .cmd_rcgr = 0x80ec,563 .mnd_width = 0,564 .hid_width = 5,565 .parent_map = disp_cc_parent_map_5,566 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,567 .clkr.hw.init = &(struct clk_init_data) {568 .name = "disp_cc_mdss_mdp_clk_src",569 .parent_data = disp_cc_parent_data_5,570 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),571 .flags = CLK_SET_RATE_PARENT,572 .ops = &clk_rcg2_shared_ops,573 },574};575 576static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {577 .cmd_rcgr = 0x80bc,578 .mnd_width = 8,579 .hid_width = 5,580 .parent_map = disp_cc_parent_map_2,581 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,582 .clkr.hw.init = &(struct clk_init_data) {583 .name = "disp_cc_mdss_pclk0_clk_src",584 .parent_data = disp_cc_parent_data_2,585 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),586 .flags = CLK_SET_RATE_PARENT,587 .ops = &clk_pixel_ops,588 },589};590 591static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {592 .cmd_rcgr = 0x80d4,593 .mnd_width = 8,594 .hid_width = 5,595 .parent_map = disp_cc_parent_map_2,596 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,597 .clkr.hw.init = &(struct clk_init_data) {598 .name = "disp_cc_mdss_pclk1_clk_src",599 .parent_data = disp_cc_parent_data_2,600 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),601 .flags = CLK_SET_RATE_PARENT,602 .ops = &clk_pixel_ops,603 },604};605 606static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {607 F(19200000, P_BI_TCXO, 1, 0, 0),608 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),609 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),610 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),611 { }612};613 614static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {615 .cmd_rcgr = 0x8104,616 .mnd_width = 0,617 .hid_width = 5,618 .parent_map = disp_cc_parent_map_5,619 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,620 .clkr.hw.init = &(struct clk_init_data) {621 .name = "disp_cc_mdss_rot_clk_src",622 .parent_data = disp_cc_parent_data_5,623 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),624 .flags = CLK_SET_RATE_PARENT,625 .ops = &clk_rcg2_shared_ops,626 },627};628 629static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {630 .cmd_rcgr = 0x811c,631 .mnd_width = 0,632 .hid_width = 5,633 .parent_map = disp_cc_parent_map_1,634 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,635 .clkr.hw.init = &(struct clk_init_data) {636 .name = "disp_cc_mdss_vsync_clk_src",637 .parent_data = disp_cc_parent_data_1,638 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),639 .flags = CLK_SET_RATE_PARENT,640 .ops = &clk_rcg2_ops,641 },642};643 644static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {645 F(32000, P_SLEEP_CLK, 1, 0, 0),646 { }647};648 649static struct clk_rcg2 disp_cc_sleep_clk_src = {650 .cmd_rcgr = 0xe060,651 .mnd_width = 0,652 .hid_width = 5,653 .parent_map = disp_cc_parent_map_7,654 .freq_tbl = ftbl_disp_cc_sleep_clk_src,655 .clkr.hw.init = &(struct clk_init_data) {656 .name = "disp_cc_sleep_clk_src",657 .parent_data = disp_cc_parent_data_7,658 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),659 .flags = CLK_SET_RATE_PARENT,660 .ops = &clk_rcg2_ops,661 },662};663 664static struct clk_rcg2 disp_cc_xo_clk_src = {665 .cmd_rcgr = 0xe044,666 .mnd_width = 0,667 .hid_width = 5,668 .parent_map = disp_cc_parent_map_1,669 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,670 .clkr.hw.init = &(struct clk_init_data) {671 .name = "disp_cc_xo_clk_src",672 .parent_data = disp_cc_parent_data_1_ao,673 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),674 .flags = CLK_SET_RATE_PARENT,675 .ops = &clk_rcg2_ops,676 },677};678 679static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {680 .reg = 0x814c,681 .shift = 0,682 .width = 4,683 .clkr.hw.init = &(struct clk_init_data) {684 .name = "disp_cc_mdss_byte0_div_clk_src",685 .parent_hws = (const struct clk_hw*[]) {686 &disp_cc_mdss_byte0_clk_src.clkr.hw,687 },688 .num_parents = 1,689 .ops = &clk_regmap_div_ops,690 },691};692 693static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {694 .reg = 0x8168,695 .shift = 0,696 .width = 4,697 .clkr.hw.init = &(struct clk_init_data) {698 .name = "disp_cc_mdss_byte1_div_clk_src",699 .parent_hws = (const struct clk_hw*[]) {700 &disp_cc_mdss_byte1_clk_src.clkr.hw,701 },702 .num_parents = 1,703 .ops = &clk_regmap_div_ops,704 },705};706 707static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {708 .reg = 0x81b4,709 .shift = 0,710 .width = 4,711 .clkr.hw.init = &(struct clk_init_data) {712 .name = "disp_cc_mdss_dptx0_link_div_clk_src",713 .parent_hws = (const struct clk_hw*[]) {714 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,715 },716 .num_parents = 1,717 .flags = CLK_SET_RATE_PARENT,718 .ops = &clk_regmap_div_ro_ops,719 },720};721 722static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {723 .reg = 0x824c,724 .shift = 0,725 .width = 4,726 .clkr.hw.init = &(struct clk_init_data) {727 .name = "disp_cc_mdss_dptx1_link_div_clk_src",728 .parent_hws = (const struct clk_hw*[]) {729 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,730 },731 .num_parents = 1,732 .flags = CLK_SET_RATE_PARENT,733 .ops = &clk_regmap_div_ro_ops,734 },735};736 737static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {738 .reg = 0x8284,739 .shift = 0,740 .width = 4,741 .clkr.hw.init = &(struct clk_init_data) {742 .name = "disp_cc_mdss_dptx2_link_div_clk_src",743 .parent_hws = (const struct clk_hw*[]) {744 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,745 },746 .num_parents = 1,747 .flags = CLK_SET_RATE_PARENT,748 .ops = &clk_regmap_div_ro_ops,749 },750};751 752static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {753 .reg = 0x8304,754 .shift = 0,755 .width = 4,756 .clkr.hw.init = &(struct clk_init_data) {757 .name = "disp_cc_mdss_dptx3_link_div_clk_src",758 .parent_hws = (const struct clk_hw*[]) {759 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,760 },761 .num_parents = 1,762 .flags = CLK_SET_RATE_PARENT,763 .ops = &clk_regmap_div_ro_ops,764 },765};766 767static struct clk_branch disp_cc_mdss_ahb1_clk = {768 .halt_reg = 0xa020,769 .halt_check = BRANCH_HALT,770 .clkr = {771 .enable_reg = 0xa020,772 .enable_mask = BIT(0),773 .hw.init = &(struct clk_init_data) {774 .name = "disp_cc_mdss_ahb1_clk",775 .parent_hws = (const struct clk_hw*[]) {776 &disp_cc_mdss_ahb_clk_src.clkr.hw,777 },778 .num_parents = 1,779 .flags = CLK_SET_RATE_PARENT,780 .ops = &clk_branch2_ops,781 },782 },783};784 785static struct clk_branch disp_cc_mdss_ahb_clk = {786 .halt_reg = 0x80a4,787 .halt_check = BRANCH_HALT,788 .clkr = {789 .enable_reg = 0x80a4,790 .enable_mask = BIT(0),791 .hw.init = &(struct clk_init_data) {792 .name = "disp_cc_mdss_ahb_clk",793 .parent_hws = (const struct clk_hw*[]) {794 &disp_cc_mdss_ahb_clk_src.clkr.hw,795 },796 .num_parents = 1,797 .flags = CLK_SET_RATE_PARENT,798 .ops = &clk_branch2_ops,799 },800 },801};802 803static struct clk_branch disp_cc_mdss_byte0_clk = {804 .halt_reg = 0x8028,805 .halt_check = BRANCH_HALT,806 .clkr = {807 .enable_reg = 0x8028,808 .enable_mask = BIT(0),809 .hw.init = &(struct clk_init_data) {810 .name = "disp_cc_mdss_byte0_clk",811 .parent_hws = (const struct clk_hw*[]) {812 &disp_cc_mdss_byte0_clk_src.clkr.hw,813 },814 .num_parents = 1,815 .flags = CLK_SET_RATE_PARENT,816 .ops = &clk_branch2_ops,817 },818 },819};820 821static struct clk_branch disp_cc_mdss_byte0_intf_clk = {822 .halt_reg = 0x802c,823 .halt_check = BRANCH_HALT,824 .clkr = {825 .enable_reg = 0x802c,826 .enable_mask = BIT(0),827 .hw.init = &(struct clk_init_data) {828 .name = "disp_cc_mdss_byte0_intf_clk",829 .parent_hws = (const struct clk_hw*[]) {830 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,831 },832 .num_parents = 1,833 .flags = CLK_SET_RATE_PARENT,834 .ops = &clk_branch2_ops,835 },836 },837};838 839static struct clk_branch disp_cc_mdss_byte1_clk = {840 .halt_reg = 0x8030,841 .halt_check = BRANCH_HALT,842 .clkr = {843 .enable_reg = 0x8030,844 .enable_mask = BIT(0),845 .hw.init = &(struct clk_init_data) {846 .name = "disp_cc_mdss_byte1_clk",847 .parent_hws = (const struct clk_hw*[]) {848 &disp_cc_mdss_byte1_clk_src.clkr.hw,849 },850 .num_parents = 1,851 .flags = CLK_SET_RATE_PARENT,852 .ops = &clk_branch2_ops,853 },854 },855};856 857static struct clk_branch disp_cc_mdss_byte1_intf_clk = {858 .halt_reg = 0x8034,859 .halt_check = BRANCH_HALT,860 .clkr = {861 .enable_reg = 0x8034,862 .enable_mask = BIT(0),863 .hw.init = &(struct clk_init_data) {864 .name = "disp_cc_mdss_byte1_intf_clk",865 .parent_hws = (const struct clk_hw*[]) {866 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,867 },868 .num_parents = 1,869 .flags = CLK_SET_RATE_PARENT,870 .ops = &clk_branch2_ops,871 },872 },873};874 875static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {876 .halt_reg = 0x8058,877 .halt_check = BRANCH_HALT,878 .clkr = {879 .enable_reg = 0x8058,880 .enable_mask = BIT(0),881 .hw.init = &(struct clk_init_data) {882 .name = "disp_cc_mdss_dptx0_aux_clk",883 .parent_hws = (const struct clk_hw*[]) {884 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,885 },886 .num_parents = 1,887 .flags = CLK_SET_RATE_PARENT,888 .ops = &clk_branch2_ops,889 },890 },891};892 893static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {894 .halt_reg = 0x804c,895 .halt_check = BRANCH_HALT,896 .clkr = {897 .enable_reg = 0x804c,898 .enable_mask = BIT(0),899 .hw.init = &(struct clk_init_data) {900 .name = "disp_cc_mdss_dptx0_crypto_clk",901 .parent_hws = (const struct clk_hw*[]) {902 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,903 },904 .num_parents = 1,905 .flags = CLK_SET_RATE_PARENT,906 .ops = &clk_branch2_ops,907 },908 },909};910 911static struct clk_branch disp_cc_mdss_dptx0_link_clk = {912 .halt_reg = 0x8040,913 .halt_check = BRANCH_HALT,914 .clkr = {915 .enable_reg = 0x8040,916 .enable_mask = BIT(0),917 .hw.init = &(struct clk_init_data) {918 .name = "disp_cc_mdss_dptx0_link_clk",919 .parent_hws = (const struct clk_hw*[]) {920 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,921 },922 .num_parents = 1,923 .flags = CLK_SET_RATE_PARENT,924 .ops = &clk_branch2_ops,925 },926 },927};928 929static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {930 .halt_reg = 0x8048,931 .halt_check = BRANCH_HALT,932 .clkr = {933 .enable_reg = 0x8048,934 .enable_mask = BIT(0),935 .hw.init = &(struct clk_init_data) {936 .name = "disp_cc_mdss_dptx0_link_intf_clk",937 .parent_hws = (const struct clk_hw*[]) {938 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,939 },940 .num_parents = 1,941 .flags = CLK_SET_RATE_PARENT,942 .ops = &clk_branch2_ops,943 },944 },945};946 947static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {948 .halt_reg = 0x8050,949 .halt_check = BRANCH_HALT,950 .clkr = {951 .enable_reg = 0x8050,952 .enable_mask = BIT(0),953 .hw.init = &(struct clk_init_data) {954 .name = "disp_cc_mdss_dptx0_pixel0_clk",955 .parent_hws = (const struct clk_hw*[]) {956 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,957 },958 .num_parents = 1,959 .flags = CLK_SET_RATE_PARENT,960 .ops = &clk_branch2_ops,961 },962 },963};964 965static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {966 .halt_reg = 0x8054,967 .halt_check = BRANCH_HALT,968 .clkr = {969 .enable_reg = 0x8054,970 .enable_mask = BIT(0),971 .hw.init = &(struct clk_init_data) {972 .name = "disp_cc_mdss_dptx0_pixel1_clk",973 .parent_hws = (const struct clk_hw*[]) {974 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,975 },976 .num_parents = 1,977 .flags = CLK_SET_RATE_PARENT,978 .ops = &clk_branch2_ops,979 },980 },981};982 983static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {984 .halt_reg = 0x8044,985 .halt_check = BRANCH_HALT,986 .clkr = {987 .enable_reg = 0x8044,988 .enable_mask = BIT(0),989 .hw.init = &(struct clk_init_data) {990 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",991 .parent_hws = (const struct clk_hw*[]) {992 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,993 },994 .num_parents = 1,995 .flags = CLK_SET_RATE_PARENT,996 .ops = &clk_branch2_ops,997 },998 },999};1000 1001static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {1002 .halt_reg = 0x8074,1003 .halt_check = BRANCH_HALT,1004 .clkr = {1005 .enable_reg = 0x8074,1006 .enable_mask = BIT(0),1007 .hw.init = &(struct clk_init_data) {1008 .name = "disp_cc_mdss_dptx1_aux_clk",1009 .parent_hws = (const struct clk_hw*[]) {1010 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,1011 },1012 .num_parents = 1,1013 .flags = CLK_SET_RATE_PARENT,1014 .ops = &clk_branch2_ops,1015 },1016 },1017};1018 1019static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {1020 .halt_reg = 0x8070,1021 .halt_check = BRANCH_HALT,1022 .clkr = {1023 .enable_reg = 0x8070,1024 .enable_mask = BIT(0),1025 .hw.init = &(struct clk_init_data) {1026 .name = "disp_cc_mdss_dptx1_crypto_clk",1027 .parent_hws = (const struct clk_hw*[]) {1028 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,1029 },1030 .num_parents = 1,1031 .flags = CLK_SET_RATE_PARENT,1032 .ops = &clk_branch2_ops,1033 },1034 },1035};1036 1037static struct clk_branch disp_cc_mdss_dptx1_link_clk = {1038 .halt_reg = 0x8064,1039 .halt_check = BRANCH_HALT,1040 .clkr = {1041 .enable_reg = 0x8064,1042 .enable_mask = BIT(0),1043 .hw.init = &(struct clk_init_data) {1044 .name = "disp_cc_mdss_dptx1_link_clk",1045 .parent_hws = (const struct clk_hw*[]) {1046 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,1047 },1048 .num_parents = 1,1049 .flags = CLK_SET_RATE_PARENT,1050 .ops = &clk_branch2_ops,1051 },1052 },1053};1054 1055static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {1056 .halt_reg = 0x806c,1057 .halt_check = BRANCH_HALT,1058 .clkr = {1059 .enable_reg = 0x806c,1060 .enable_mask = BIT(0),1061 .hw.init = &(struct clk_init_data) {1062 .name = "disp_cc_mdss_dptx1_link_intf_clk",1063 .parent_hws = (const struct clk_hw*[]) {1064 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,1065 },1066 .num_parents = 1,1067 .flags = CLK_SET_RATE_PARENT,1068 .ops = &clk_branch2_ops,1069 },1070 },1071};1072 1073static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {1074 .halt_reg = 0x805c,1075 .halt_check = BRANCH_HALT,1076 .clkr = {1077 .enable_reg = 0x805c,1078 .enable_mask = BIT(0),1079 .hw.init = &(struct clk_init_data) {1080 .name = "disp_cc_mdss_dptx1_pixel0_clk",1081 .parent_hws = (const struct clk_hw*[]) {1082 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,1083 },1084 .num_parents = 1,1085 .flags = CLK_SET_RATE_PARENT,1086 .ops = &clk_branch2_ops,1087 },1088 },1089};1090 1091static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {1092 .halt_reg = 0x8060,1093 .halt_check = BRANCH_HALT,1094 .clkr = {1095 .enable_reg = 0x8060,1096 .enable_mask = BIT(0),1097 .hw.init = &(struct clk_init_data) {1098 .name = "disp_cc_mdss_dptx1_pixel1_clk",1099 .parent_hws = (const struct clk_hw*[]) {1100 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,1101 },1102 .num_parents = 1,1103 .flags = CLK_SET_RATE_PARENT,1104 .ops = &clk_branch2_ops,1105 },1106 },1107};1108 1109static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {1110 .halt_reg = 0x8068,1111 .halt_check = BRANCH_HALT,1112 .clkr = {1113 .enable_reg = 0x8068,1114 .enable_mask = BIT(0),1115 .hw.init = &(struct clk_init_data) {1116 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",1117 .parent_hws = (const struct clk_hw*[]) {1118 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,1119 },1120 .num_parents = 1,1121 .flags = CLK_SET_RATE_PARENT,1122 .ops = &clk_branch2_ops,1123 },1124 },1125};1126 1127static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {1128 .halt_reg = 0x808c,1129 .halt_check = BRANCH_HALT,1130 .clkr = {1131 .enable_reg = 0x808c,1132 .enable_mask = BIT(0),1133 .hw.init = &(struct clk_init_data) {1134 .name = "disp_cc_mdss_dptx2_aux_clk",1135 .parent_hws = (const struct clk_hw*[]) {1136 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,1137 },1138 .num_parents = 1,1139 .flags = CLK_SET_RATE_PARENT,1140 .ops = &clk_branch2_ops,1141 },1142 },1143};1144 1145static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {1146 .halt_reg = 0x8088,1147 .halt_check = BRANCH_HALT,1148 .clkr = {1149 .enable_reg = 0x8088,1150 .enable_mask = BIT(0),1151 .hw.init = &(struct clk_init_data) {1152 .name = "disp_cc_mdss_dptx2_crypto_clk",1153 .parent_hws = (const struct clk_hw*[]) {1154 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,1155 },1156 .num_parents = 1,1157 .flags = CLK_SET_RATE_PARENT,1158 .ops = &clk_branch2_ops,1159 },1160 },1161};1162 1163static struct clk_branch disp_cc_mdss_dptx2_link_clk = {1164 .halt_reg = 0x8080,1165 .halt_check = BRANCH_HALT,1166 .clkr = {1167 .enable_reg = 0x8080,1168 .enable_mask = BIT(0),1169 .hw.init = &(struct clk_init_data) {1170 .name = "disp_cc_mdss_dptx2_link_clk",1171 .parent_hws = (const struct clk_hw*[]) {1172 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,1173 },1174 .num_parents = 1,1175 .flags = CLK_SET_RATE_PARENT,1176 .ops = &clk_branch2_ops,1177 },1178 },1179};1180 1181static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {1182 .halt_reg = 0x8084,1183 .halt_check = BRANCH_HALT,1184 .clkr = {1185 .enable_reg = 0x8084,1186 .enable_mask = BIT(0),1187 .hw.init = &(struct clk_init_data) {1188 .name = "disp_cc_mdss_dptx2_link_intf_clk",1189 .parent_hws = (const struct clk_hw*[]) {1190 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,1191 },1192 .num_parents = 1,1193 .flags = CLK_SET_RATE_PARENT,1194 .ops = &clk_branch2_ops,1195 },1196 },1197};1198 1199static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {1200 .halt_reg = 0x8078,1201 .halt_check = BRANCH_HALT,1202 .clkr = {1203 .enable_reg = 0x8078,1204 .enable_mask = BIT(0),1205 .hw.init = &(struct clk_init_data) {1206 .name = "disp_cc_mdss_dptx2_pixel0_clk",1207 .parent_hws = (const struct clk_hw*[]) {1208 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,1209 },1210 .num_parents = 1,1211 .flags = CLK_SET_RATE_PARENT,1212 .ops = &clk_branch2_ops,1213 },1214 },1215};1216 1217static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {1218 .halt_reg = 0x807c,1219 .halt_check = BRANCH_HALT,1220 .clkr = {1221 .enable_reg = 0x807c,1222 .enable_mask = BIT(0),1223 .hw.init = &(struct clk_init_data) {1224 .name = "disp_cc_mdss_dptx2_pixel1_clk",1225 .parent_hws = (const struct clk_hw*[]) {1226 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,1227 },1228 .num_parents = 1,1229 .flags = CLK_SET_RATE_PARENT,1230 .ops = &clk_branch2_ops,1231 },1232 },1233};1234 1235static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {1236 .halt_reg = 0x809c,1237 .halt_check = BRANCH_HALT,1238 .clkr = {1239 .enable_reg = 0x809c,1240 .enable_mask = BIT(0),1241 .hw.init = &(struct clk_init_data) {1242 .name = "disp_cc_mdss_dptx3_aux_clk",1243 .parent_hws = (const struct clk_hw*[]) {1244 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,1245 },1246 .num_parents = 1,1247 .flags = CLK_SET_RATE_PARENT,1248 .ops = &clk_branch2_ops,1249 },1250 },1251};1252 1253static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {1254 .halt_reg = 0x80a0,1255 .halt_check = BRANCH_HALT,1256 .clkr = {1257 .enable_reg = 0x80a0,1258 .enable_mask = BIT(0),1259 .hw.init = &(struct clk_init_data) {1260 .name = "disp_cc_mdss_dptx3_crypto_clk",1261 .parent_hws = (const struct clk_hw*[]) {1262 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,1263 },1264 .num_parents = 1,1265 .flags = CLK_SET_RATE_PARENT,1266 .ops = &clk_branch2_ops,1267 },1268 },1269};1270 1271static struct clk_branch disp_cc_mdss_dptx3_link_clk = {1272 .halt_reg = 0x8094,1273 .halt_check = BRANCH_HALT,1274 .clkr = {1275 .enable_reg = 0x8094,1276 .enable_mask = BIT(0),1277 .hw.init = &(struct clk_init_data) {1278 .name = "disp_cc_mdss_dptx3_link_clk",1279 .parent_hws = (const struct clk_hw*[]) {1280 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,1281 },1282 .num_parents = 1,1283 .flags = CLK_SET_RATE_PARENT,1284 .ops = &clk_branch2_ops,1285 },1286 },1287};1288 1289static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {1290 .halt_reg = 0x8098,1291 .halt_check = BRANCH_HALT,1292 .clkr = {1293 .enable_reg = 0x8098,1294 .enable_mask = BIT(0),1295 .hw.init = &(struct clk_init_data) {1296 .name = "disp_cc_mdss_dptx3_link_intf_clk",1297 .parent_hws = (const struct clk_hw*[]) {1298 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,1299 },1300 .num_parents = 1,1301 .flags = CLK_SET_RATE_PARENT,1302 .ops = &clk_branch2_ops,1303 },1304 },1305};1306 1307static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {1308 .halt_reg = 0x8090,1309 .halt_check = BRANCH_HALT,1310 .clkr = {1311 .enable_reg = 0x8090,1312 .enable_mask = BIT(0),1313 .hw.init = &(struct clk_init_data) {1314 .name = "disp_cc_mdss_dptx3_pixel0_clk",1315 .parent_hws = (const struct clk_hw*[]) {1316 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,1317 },1318 .num_parents = 1,1319 .flags = CLK_SET_RATE_PARENT,1320 .ops = &clk_branch2_ops,1321 },1322 },1323};1324 1325static struct clk_branch disp_cc_mdss_esc0_clk = {1326 .halt_reg = 0x8038,1327 .halt_check = BRANCH_HALT,1328 .clkr = {1329 .enable_reg = 0x8038,1330 .enable_mask = BIT(0),1331 .hw.init = &(struct clk_init_data) {1332 .name = "disp_cc_mdss_esc0_clk",1333 .parent_hws = (const struct clk_hw*[]) {1334 &disp_cc_mdss_esc0_clk_src.clkr.hw,1335 },1336 .num_parents = 1,1337 .flags = CLK_SET_RATE_PARENT,1338 .ops = &clk_branch2_ops,1339 },1340 },1341};1342 1343static struct clk_branch disp_cc_mdss_esc1_clk = {1344 .halt_reg = 0x803c,1345 .halt_check = BRANCH_HALT,1346 .clkr = {1347 .enable_reg = 0x803c,1348 .enable_mask = BIT(0),1349 .hw.init = &(struct clk_init_data) {1350 .name = "disp_cc_mdss_esc1_clk",1351 .parent_hws = (const struct clk_hw*[]) {1352 &disp_cc_mdss_esc1_clk_src.clkr.hw,1353 },1354 .num_parents = 1,1355 .flags = CLK_SET_RATE_PARENT,1356 .ops = &clk_branch2_ops,1357 },1358 },1359};1360 1361static struct clk_branch disp_cc_mdss_mdp1_clk = {1362 .halt_reg = 0xa004,1363 .halt_check = BRANCH_HALT,1364 .clkr = {1365 .enable_reg = 0xa004,1366 .enable_mask = BIT(0),1367 .hw.init = &(struct clk_init_data) {1368 .name = "disp_cc_mdss_mdp1_clk",1369 .parent_hws = (const struct clk_hw*[]) {1370 &disp_cc_mdss_mdp_clk_src.clkr.hw,1371 },1372 .num_parents = 1,1373 .flags = CLK_SET_RATE_PARENT,1374 .ops = &clk_branch2_ops,1375 },1376 },1377};1378 1379static struct clk_branch disp_cc_mdss_mdp_clk = {1380 .halt_reg = 0x800c,1381 .halt_check = BRANCH_HALT,1382 .clkr = {1383 .enable_reg = 0x800c,1384 .enable_mask = BIT(0),1385 .hw.init = &(struct clk_init_data) {1386 .name = "disp_cc_mdss_mdp_clk",1387 .parent_hws = (const struct clk_hw*[]) {1388 &disp_cc_mdss_mdp_clk_src.clkr.hw,1389 },1390 .num_parents = 1,1391 .flags = CLK_SET_RATE_PARENT,1392 .ops = &clk_branch2_ops,1393 },1394 },1395};1396 1397static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {1398 .halt_reg = 0xa014,1399 .halt_check = BRANCH_HALT,1400 .clkr = {1401 .enable_reg = 0xa014,1402 .enable_mask = BIT(0),1403 .hw.init = &(struct clk_init_data) {1404 .name = "disp_cc_mdss_mdp_lut1_clk",1405 .parent_hws = (const struct clk_hw*[]) {1406 &disp_cc_mdss_mdp_clk_src.clkr.hw,1407 },1408 .num_parents = 1,1409 .flags = CLK_SET_RATE_PARENT,1410 .ops = &clk_branch2_ops,1411 },1412 },1413};1414 1415static struct clk_branch disp_cc_mdss_mdp_lut_clk = {1416 .halt_reg = 0x801c,1417 .halt_check = BRANCH_HALT_VOTED,1418 .clkr = {1419 .enable_reg = 0x801c,1420 .enable_mask = BIT(0),1421 .hw.init = &(struct clk_init_data) {1422 .name = "disp_cc_mdss_mdp_lut_clk",1423 .parent_hws = (const struct clk_hw*[]) {1424 &disp_cc_mdss_mdp_clk_src.clkr.hw,1425 },1426 .num_parents = 1,1427 .flags = CLK_SET_RATE_PARENT,1428 .ops = &clk_branch2_ops,1429 },1430 },1431};1432 1433static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {1434 .halt_reg = 0xc004,1435 .halt_check = BRANCH_HALT_VOTED,1436 .clkr = {1437 .enable_reg = 0xc004,1438 .enable_mask = BIT(0),1439 .hw.init = &(struct clk_init_data) {1440 .name = "disp_cc_mdss_non_gdsc_ahb_clk",1441 .parent_hws = (const struct clk_hw*[]) {1442 &disp_cc_mdss_ahb_clk_src.clkr.hw,1443 },1444 .num_parents = 1,1445 .flags = CLK_SET_RATE_PARENT,1446 .ops = &clk_branch2_ops,1447 },1448 },1449};1450 1451static struct clk_branch disp_cc_mdss_pclk0_clk = {1452 .halt_reg = 0x8004,1453 .halt_check = BRANCH_HALT,1454 .clkr = {1455 .enable_reg = 0x8004,1456 .enable_mask = BIT(0),1457 .hw.init = &(struct clk_init_data) {1458 .name = "disp_cc_mdss_pclk0_clk",1459 .parent_hws = (const struct clk_hw*[]) {1460 &disp_cc_mdss_pclk0_clk_src.clkr.hw,1461 },1462 .num_parents = 1,1463 .flags = CLK_SET_RATE_PARENT,1464 .ops = &clk_branch2_ops,1465 },1466 },1467};1468 1469static struct clk_branch disp_cc_mdss_pclk1_clk = {1470 .halt_reg = 0x8008,1471 .halt_check = BRANCH_HALT,1472 .clkr = {1473 .enable_reg = 0x8008,1474 .enable_mask = BIT(0),1475 .hw.init = &(struct clk_init_data) {1476 .name = "disp_cc_mdss_pclk1_clk",1477 .parent_hws = (const struct clk_hw*[]) {1478 &disp_cc_mdss_pclk1_clk_src.clkr.hw,1479 },1480 .num_parents = 1,1481 .flags = CLK_SET_RATE_PARENT,1482 .ops = &clk_branch2_ops,1483 },1484 },1485};1486 1487static struct clk_branch disp_cc_mdss_rot1_clk = {1488 .halt_reg = 0xa00c,1489 .halt_check = BRANCH_HALT,1490 .clkr = {1491 .enable_reg = 0xa00c,1492 .enable_mask = BIT(0),1493 .hw.init = &(struct clk_init_data) {1494 .name = "disp_cc_mdss_rot1_clk",1495 .parent_hws = (const struct clk_hw*[]) {1496 &disp_cc_mdss_rot_clk_src.clkr.hw,1497 },1498 .num_parents = 1,1499 .flags = CLK_SET_RATE_PARENT,1500 .ops = &clk_branch2_ops,1501 },1502 },1503};1504 1505static struct clk_branch disp_cc_mdss_rot_clk = {1506 .halt_reg = 0x8014,1507 .halt_check = BRANCH_HALT,1508 .clkr = {1509 .enable_reg = 0x8014,1510 .enable_mask = BIT(0),1511 .hw.init = &(struct clk_init_data) {1512 .name = "disp_cc_mdss_rot_clk",1513 .parent_hws = (const struct clk_hw*[]) {1514 &disp_cc_mdss_rot_clk_src.clkr.hw,1515 },1516 .num_parents = 1,1517 .flags = CLK_SET_RATE_PARENT,1518 .ops = &clk_branch2_ops,1519 },1520 },1521};1522 1523static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {1524 .halt_reg = 0xc00c,1525 .halt_check = BRANCH_HALT,1526 .clkr = {1527 .enable_reg = 0xc00c,1528 .enable_mask = BIT(0),1529 .hw.init = &(struct clk_init_data) {1530 .name = "disp_cc_mdss_rscc_ahb_clk",1531 .parent_hws = (const struct clk_hw*[]) {1532 &disp_cc_mdss_ahb_clk_src.clkr.hw,1533 },1534 .num_parents = 1,1535 .flags = CLK_SET_RATE_PARENT,1536 .ops = &clk_branch2_ops,1537 },1538 },1539};1540 1541static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {1542 .halt_reg = 0xc008,1543 .halt_check = BRANCH_HALT,1544 .clkr = {1545 .enable_reg = 0xc008,1546 .enable_mask = BIT(0),1547 .hw.init = &(struct clk_init_data) {1548 .name = "disp_cc_mdss_rscc_vsync_clk",1549 .parent_hws = (const struct clk_hw*[]) {1550 &disp_cc_mdss_vsync_clk_src.clkr.hw,1551 },1552 .num_parents = 1,1553 .flags = CLK_SET_RATE_PARENT,1554 .ops = &clk_branch2_ops,1555 },1556 },1557};1558 1559static struct clk_branch disp_cc_mdss_vsync1_clk = {1560 .halt_reg = 0xa01c,1561 .halt_check = BRANCH_HALT,1562 .clkr = {1563 .enable_reg = 0xa01c,1564 .enable_mask = BIT(0),1565 .hw.init = &(struct clk_init_data) {1566 .name = "disp_cc_mdss_vsync1_clk",1567 .parent_hws = (const struct clk_hw*[]) {1568 &disp_cc_mdss_vsync_clk_src.clkr.hw,1569 },1570 .num_parents = 1,1571 .flags = CLK_SET_RATE_PARENT,1572 .ops = &clk_branch2_ops,1573 },1574 },1575};1576 1577static struct clk_branch disp_cc_mdss_vsync_clk = {1578 .halt_reg = 0x8024,1579 .halt_check = BRANCH_HALT,1580 .clkr = {1581 .enable_reg = 0x8024,1582 .enable_mask = BIT(0),1583 .hw.init = &(struct clk_init_data) {1584 .name = "disp_cc_mdss_vsync_clk",1585 .parent_hws = (const struct clk_hw*[]) {1586 &disp_cc_mdss_vsync_clk_src.clkr.hw,1587 },1588 .num_parents = 1,1589 .flags = CLK_SET_RATE_PARENT,1590 .ops = &clk_branch2_ops,1591 },1592 },1593};1594 1595static struct clk_branch disp_cc_sleep_clk = {1596 .halt_reg = 0xe078,1597 .halt_check = BRANCH_HALT,1598 .clkr = {1599 .enable_reg = 0xe078,1600 .enable_mask = BIT(0),1601 .hw.init = &(struct clk_init_data) {1602 .name = "disp_cc_sleep_clk",1603 .parent_hws = (const struct clk_hw*[]) {1604 &disp_cc_sleep_clk_src.clkr.hw,1605 },1606 .num_parents = 1,1607 .flags = CLK_SET_RATE_PARENT,1608 .ops = &clk_branch2_ops,1609 },1610 },1611};1612 1613static struct gdsc mdss_gdsc = {1614 .gdscr = 0x9000,1615 .pd = {1616 .name = "mdss_gdsc",1617 },1618 .pwrsts = PWRSTS_OFF_ON,1619 .flags = HW_CTRL | RETAIN_FF_ENABLE,1620};1621 1622static struct gdsc mdss_int2_gdsc = {1623 .gdscr = 0xb000,1624 .pd = {1625 .name = "mdss_int2_gdsc",1626 },1627 .pwrsts = PWRSTS_OFF_ON,1628 .flags = HW_CTRL | RETAIN_FF_ENABLE,1629};1630 1631static struct clk_regmap *disp_cc_sm8450_clocks[] = {1632 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,1633 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,1634 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,1635 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,1636 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,1637 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,1638 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,1639 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,1640 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,1641 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,1642 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,1643 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,1644 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,1645 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,1646 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,1647 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,1648 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,1649 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,1650 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,1651 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,1652 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,1653 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,1654 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =1655 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,1656 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,1657 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,1658 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,1659 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,1660 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,1661 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,1662 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,1663 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,1664 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,1665 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,1666 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,1667 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =1668 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,1669 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,1670 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,1671 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,1672 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,1673 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,1674 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,1675 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,1676 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,1677 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,1678 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,1679 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,1680 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,1681 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,1682 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,1683 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,1684 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,1685 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,1686 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,1687 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,1688 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,1689 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,1690 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,1691 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,1692 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,1693 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,1694 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,1695 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,1696 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,1697 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,1698 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,1699 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,1700 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,1701 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,1702 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,1703 [DISP_CC_MDSS_ROT1_CLK] = &disp_cc_mdss_rot1_clk.clkr,1704 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,1705 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,1706 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,1707 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,1708 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,1709 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,1710 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,1711 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,1712 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,1713 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,1714 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,1715 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,1716};1717 1718static const struct qcom_reset_map disp_cc_sm8450_resets[] = {1719 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },1720 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },1721 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },1722};1723 1724static struct gdsc *disp_cc_sm8450_gdscs[] = {1725 [MDSS_GDSC] = &mdss_gdsc,1726 [MDSS_INT2_GDSC] = &mdss_int2_gdsc,1727};1728 1729static const struct regmap_config disp_cc_sm8450_regmap_config = {1730 .reg_bits = 32,1731 .reg_stride = 4,1732 .val_bits = 32,1733 .max_register = 0x11008,1734 .fast_io = true,1735};1736 1737static struct qcom_cc_desc disp_cc_sm8450_desc = {1738 .config = &disp_cc_sm8450_regmap_config,1739 .clks = disp_cc_sm8450_clocks,1740 .num_clks = ARRAY_SIZE(disp_cc_sm8450_clocks),1741 .resets = disp_cc_sm8450_resets,1742 .num_resets = ARRAY_SIZE(disp_cc_sm8450_resets),1743 .gdscs = disp_cc_sm8450_gdscs,1744 .num_gdscs = ARRAY_SIZE(disp_cc_sm8450_gdscs),1745};1746 1747static const struct of_device_id disp_cc_sm8450_match_table[] = {1748 { .compatible = "qcom,sm8450-dispcc" },1749 { }1750};1751MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);1752 1753static int disp_cc_sm8450_probe(struct platform_device *pdev)1754{1755 struct regmap *regmap;1756 int ret;1757 1758 ret = devm_pm_runtime_enable(&pdev->dev);1759 if (ret)1760 return ret;1761 1762 ret = pm_runtime_resume_and_get(&pdev->dev);1763 if (ret)1764 return ret;1765 1766 regmap = qcom_cc_map(pdev, &disp_cc_sm8450_desc);1767 if (IS_ERR(regmap)) {1768 ret = PTR_ERR(regmap);1769 goto err_put_rpm;1770 }1771 1772 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);1773 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);1774 1775 /* Enable clock gating for MDP clocks */1776 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);1777 1778 /* Keep some clocks always-on */1779 qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */1780 1781 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);1782 if (ret)1783 goto err_put_rpm;1784 1785 pm_runtime_put(&pdev->dev);1786 1787 return 0;1788 1789err_put_rpm:1790 pm_runtime_put_sync(&pdev->dev);1791 1792 return ret;1793}1794 1795static struct platform_driver disp_cc_sm8450_driver = {1796 .probe = disp_cc_sm8450_probe,1797 .driver = {1798 .name = "disp_cc-sm8450",1799 .of_match_table = disp_cc_sm8450_match_table,1800 },1801};1802 1803module_platform_driver(disp_cc_sm8450_driver);1804 1805MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");1806MODULE_LICENSE("GPL");1807