1719 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/err.h>8#include <linux/kernel.h>9#include <linux/mod_devicetable.h>10#include <linux/module.h>11#include <linux/platform_device.h>12#include <linux/pm_runtime.h>13#include <linux/regmap.h>14 15#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>16 17#include "common.h"18#include "clk-alpha-pll.h"19#include "clk-branch.h"20#include "clk-pll.h"21#include "clk-rcg.h"22#include "clk-regmap.h"23#include "clk-regmap-divider.h"24#include "reset.h"25#include "gdsc.h"26 27/* Need to match the order of clocks in DT binding */28enum {29 DT_BI_TCXO,30 DT_BI_TCXO_AO,31 DT_AHB_CLK,32 DT_SLEEP_CLK,33 34 DT_DSI0_PHY_PLL_OUT_BYTECLK,35 DT_DSI0_PHY_PLL_OUT_DSICLK,36 DT_DSI1_PHY_PLL_OUT_BYTECLK,37 DT_DSI1_PHY_PLL_OUT_DSICLK,38 39 DT_DP0_PHY_PLL_LINK_CLK,40 DT_DP0_PHY_PLL_VCO_DIV_CLK,41 DT_DP1_PHY_PLL_LINK_CLK,42 DT_DP1_PHY_PLL_VCO_DIV_CLK,43 DT_DP2_PHY_PLL_LINK_CLK,44 DT_DP2_PHY_PLL_VCO_DIV_CLK,45 DT_DP3_PHY_PLL_LINK_CLK,46 DT_DP3_PHY_PLL_VCO_DIV_CLK,47};48 49#define DISP_CC_MISC_CMD 0xF00050 51enum {52 P_BI_TCXO,53 P_BI_TCXO_AO,54 P_DISP_CC_PLL0_OUT_MAIN,55 P_DISP_CC_PLL1_OUT_EVEN,56 P_DISP_CC_PLL1_OUT_MAIN,57 P_DP0_PHY_PLL_LINK_CLK,58 P_DP0_PHY_PLL_VCO_DIV_CLK,59 P_DP1_PHY_PLL_LINK_CLK,60 P_DP1_PHY_PLL_VCO_DIV_CLK,61 P_DP2_PHY_PLL_LINK_CLK,62 P_DP2_PHY_PLL_VCO_DIV_CLK,63 P_DP3_PHY_PLL_LINK_CLK,64 P_DP3_PHY_PLL_VCO_DIV_CLK,65 P_DSI0_PHY_PLL_OUT_BYTECLK,66 P_DSI0_PHY_PLL_OUT_DSICLK,67 P_DSI1_PHY_PLL_OUT_BYTECLK,68 P_DSI1_PHY_PLL_OUT_DSICLK,69 P_SLEEP_CLK,70};71 72static const struct pll_vco lucid_ole_vco[] = {73 { 249600000, 2300000000, 0 },74};75 76static const struct alpha_pll_config disp_cc_pll0_config = {77 .l = 0xd,78 .alpha = 0x6492,79 .config_ctl_val = 0x20485699,80 .config_ctl_hi_val = 0x00182261,81 .config_ctl_hi1_val = 0x82aa299c,82 .test_ctl_val = 0x00000000,83 .test_ctl_hi_val = 0x00000003,84 .test_ctl_hi1_val = 0x00009000,85 .test_ctl_hi2_val = 0x00000034,86 .user_ctl_val = 0x00000000,87 .user_ctl_hi_val = 0x00000005,88};89 90static struct clk_alpha_pll disp_cc_pll0 = {91 .offset = 0x0,92 .vco_table = lucid_ole_vco,93 .num_vco = ARRAY_SIZE(lucid_ole_vco),94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],95 .clkr = {96 .hw.init = &(const struct clk_init_data) {97 .name = "disp_cc_pll0",98 .parent_data = &(const struct clk_parent_data) {99 .index = DT_BI_TCXO,100 },101 .num_parents = 1,102 .ops = &clk_alpha_pll_reset_lucid_ole_ops,103 },104 },105};106 107static const struct alpha_pll_config disp_cc_pll1_config = {108 .l = 0x1f,109 .alpha = 0x4000,110 .config_ctl_val = 0x20485699,111 .config_ctl_hi_val = 0x00182261,112 .config_ctl_hi1_val = 0x82aa299c,113 .test_ctl_val = 0x00000000,114 .test_ctl_hi_val = 0x00000003,115 .test_ctl_hi1_val = 0x00009000,116 .test_ctl_hi2_val = 0x00000034,117 .user_ctl_val = 0x00000000,118 .user_ctl_hi_val = 0x00000005,119};120 121static struct clk_alpha_pll disp_cc_pll1 = {122 .offset = 0x1000,123 .vco_table = lucid_ole_vco,124 .num_vco = ARRAY_SIZE(lucid_ole_vco),125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],126 .clkr = {127 .hw.init = &(const struct clk_init_data) {128 .name = "disp_cc_pll1",129 .parent_data = &(const struct clk_parent_data) {130 .index = DT_BI_TCXO,131 },132 .num_parents = 1,133 .ops = &clk_alpha_pll_reset_lucid_ole_ops,134 },135 },136};137 138static const struct parent_map disp_cc_parent_map_0[] = {139 { P_BI_TCXO, 0 },140 { P_DP0_PHY_PLL_LINK_CLK, 1 },141 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },142 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },143 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },144 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },145};146 147static const struct clk_parent_data disp_cc_parent_data_0[] = {148 { .index = DT_BI_TCXO },149 { .index = DT_DP0_PHY_PLL_LINK_CLK },150 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },151 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },152 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },153 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },154};155 156static const struct parent_map disp_cc_parent_map_1[] = {157 { P_BI_TCXO, 0 },158};159 160static const struct clk_parent_data disp_cc_parent_data_1[] = {161 { .index = DT_BI_TCXO },162};163 164static const struct clk_parent_data disp_cc_parent_data_1_ao[] = {165 { .index = DT_BI_TCXO_AO },166};167 168static const struct parent_map disp_cc_parent_map_2[] = {169 { P_BI_TCXO, 0 },170 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },171 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },172 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },173 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },174};175 176static const struct clk_parent_data disp_cc_parent_data_2[] = {177 { .index = DT_BI_TCXO },178 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },179 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },180 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },181 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },182};183 184static const struct parent_map disp_cc_parent_map_3[] = {185 { P_BI_TCXO, 0 },186 { P_DP0_PHY_PLL_LINK_CLK, 1 },187 { P_DP1_PHY_PLL_LINK_CLK, 2 },188 { P_DP2_PHY_PLL_LINK_CLK, 3 },189 { P_DP3_PHY_PLL_LINK_CLK, 4 },190};191 192static const struct clk_parent_data disp_cc_parent_data_3[] = {193 { .index = DT_BI_TCXO },194 { .index = DT_DP0_PHY_PLL_LINK_CLK },195 { .index = DT_DP1_PHY_PLL_LINK_CLK },196 { .index = DT_DP2_PHY_PLL_LINK_CLK },197 { .index = DT_DP3_PHY_PLL_LINK_CLK },198};199 200static const struct parent_map disp_cc_parent_map_4[] = {201 { P_BI_TCXO, 0 },202 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },203 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },204};205 206static const struct clk_parent_data disp_cc_parent_data_4[] = {207 { .index = DT_BI_TCXO },208 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },209 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },210};211 212static const struct parent_map disp_cc_parent_map_5[] = {213 { P_BI_TCXO, 0 },214 { P_DISP_CC_PLL1_OUT_MAIN, 4 },215 { P_DISP_CC_PLL1_OUT_EVEN, 6 },216};217 218static const struct clk_parent_data disp_cc_parent_data_5[] = {219 { .index = DT_BI_TCXO },220 { .hw = &disp_cc_pll1.clkr.hw },221 { .hw = &disp_cc_pll1.clkr.hw },222};223 224static const struct parent_map disp_cc_parent_map_6[] = {225 { P_BI_TCXO, 0 },226 { P_DISP_CC_PLL0_OUT_MAIN, 1 },227 { P_DISP_CC_PLL1_OUT_MAIN, 4 },228 { P_DISP_CC_PLL1_OUT_EVEN, 6 },229};230 231static const struct clk_parent_data disp_cc_parent_data_6[] = {232 { .index = DT_BI_TCXO },233 { .hw = &disp_cc_pll0.clkr.hw },234 { .hw = &disp_cc_pll1.clkr.hw },235 { .hw = &disp_cc_pll1.clkr.hw },236};237 238static const struct parent_map disp_cc_parent_map_7[] = {239 { P_SLEEP_CLK, 0 },240};241 242static const struct clk_parent_data disp_cc_parent_data_7[] = {243 { .index = DT_SLEEP_CLK },244};245 246static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {247 F(19200000, P_BI_TCXO, 1, 0, 0),248 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),249 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),250 { }251};252 253static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {254 .cmd_rcgr = 0x82ec,255 .mnd_width = 0,256 .hid_width = 5,257 .parent_map = disp_cc_parent_map_5,258 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,259 .clkr.hw.init = &(const struct clk_init_data) {260 .name = "disp_cc_mdss_ahb_clk_src",261 .parent_data = disp_cc_parent_data_5,262 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),263 .flags = CLK_SET_RATE_PARENT,264 .ops = &clk_rcg2_ops,265 },266};267 268static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {269 F(19200000, P_BI_TCXO, 1, 0, 0),270 { }271};272 273static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {274 .cmd_rcgr = 0x810c,275 .mnd_width = 0,276 .hid_width = 5,277 .parent_map = disp_cc_parent_map_2,278 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,279 .clkr.hw.init = &(const struct clk_init_data) {280 .name = "disp_cc_mdss_byte0_clk_src",281 .parent_data = disp_cc_parent_data_2,282 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),283 .flags = CLK_SET_RATE_PARENT,284 .ops = &clk_byte2_ops,285 },286};287 288static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {289 .cmd_rcgr = 0x8128,290 .mnd_width = 0,291 .hid_width = 5,292 .parent_map = disp_cc_parent_map_2,293 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,294 .clkr.hw.init = &(const struct clk_init_data) {295 .name = "disp_cc_mdss_byte1_clk_src",296 .parent_data = disp_cc_parent_data_2,297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),298 .flags = CLK_SET_RATE_PARENT,299 .ops = &clk_byte2_ops,300 },301};302 303static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {304 .cmd_rcgr = 0x81c0,305 .mnd_width = 0,306 .hid_width = 5,307 .parent_map = disp_cc_parent_map_1,308 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,309 .clkr.hw.init = &(const struct clk_init_data) {310 .name = "disp_cc_mdss_dptx0_aux_clk_src",311 .parent_data = disp_cc_parent_data_1,312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),313 .flags = CLK_SET_RATE_PARENT,314 .ops = &clk_rcg2_ops,315 },316};317 318static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {319 .cmd_rcgr = 0x8174,320 .mnd_width = 0,321 .hid_width = 5,322 .parent_map = disp_cc_parent_map_3,323 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,324 .clkr.hw.init = &(const struct clk_init_data) {325 .name = "disp_cc_mdss_dptx0_link_clk_src",326 .parent_data = disp_cc_parent_data_3,327 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),328 .flags = CLK_SET_RATE_PARENT,329 .ops = &clk_byte2_ops,330 },331};332 333static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {334 .cmd_rcgr = 0x8190,335 .mnd_width = 16,336 .hid_width = 5,337 .parent_map = disp_cc_parent_map_0,338 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,339 .clkr.hw.init = &(const struct clk_init_data) {340 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",341 .parent_data = disp_cc_parent_data_0,342 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),343 .flags = CLK_SET_RATE_PARENT,344 .ops = &clk_dp_ops,345 },346};347 348static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {349 .cmd_rcgr = 0x81a8,350 .mnd_width = 16,351 .hid_width = 5,352 .parent_map = disp_cc_parent_map_0,353 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,354 .clkr.hw.init = &(const struct clk_init_data) {355 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",356 .parent_data = disp_cc_parent_data_0,357 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),358 .flags = CLK_SET_RATE_PARENT,359 .ops = &clk_dp_ops,360 },361};362 363static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {364 .cmd_rcgr = 0x8224,365 .mnd_width = 0,366 .hid_width = 5,367 .parent_map = disp_cc_parent_map_1,368 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,369 .clkr.hw.init = &(const struct clk_init_data) {370 .name = "disp_cc_mdss_dptx1_aux_clk_src",371 .parent_data = disp_cc_parent_data_1,372 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),373 .flags = CLK_SET_RATE_PARENT,374 .ops = &clk_rcg2_ops,375 },376};377 378static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {379 .cmd_rcgr = 0x8208,380 .mnd_width = 0,381 .hid_width = 5,382 .parent_map = disp_cc_parent_map_3,383 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,384 .clkr.hw.init = &(const struct clk_init_data) {385 .name = "disp_cc_mdss_dptx1_link_clk_src",386 .parent_data = disp_cc_parent_data_3,387 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),388 .flags = CLK_SET_RATE_PARENT,389 .ops = &clk_byte2_ops,390 },391};392 393static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {394 .cmd_rcgr = 0x81d8,395 .mnd_width = 16,396 .hid_width = 5,397 .parent_map = disp_cc_parent_map_0,398 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,399 .clkr.hw.init = &(const struct clk_init_data) {400 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",401 .parent_data = disp_cc_parent_data_0,402 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),403 .flags = CLK_SET_RATE_PARENT,404 .ops = &clk_dp_ops,405 },406};407 408static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {409 .cmd_rcgr = 0x81f0,410 .mnd_width = 16,411 .hid_width = 5,412 .parent_map = disp_cc_parent_map_0,413 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,414 .clkr.hw.init = &(const struct clk_init_data) {415 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",416 .parent_data = disp_cc_parent_data_0,417 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),418 .flags = CLK_SET_RATE_PARENT,419 .ops = &clk_dp_ops,420 },421};422 423static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {424 .cmd_rcgr = 0x8288,425 .mnd_width = 0,426 .hid_width = 5,427 .parent_map = disp_cc_parent_map_1,428 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,429 .clkr.hw.init = &(const struct clk_init_data) {430 .name = "disp_cc_mdss_dptx2_aux_clk_src",431 .parent_data = disp_cc_parent_data_1,432 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),433 .flags = CLK_SET_RATE_PARENT,434 .ops = &clk_rcg2_ops,435 },436};437 438static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {439 .cmd_rcgr = 0x823c,440 .mnd_width = 0,441 .hid_width = 5,442 .parent_map = disp_cc_parent_map_3,443 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,444 .clkr.hw.init = &(const struct clk_init_data) {445 .name = "disp_cc_mdss_dptx2_link_clk_src",446 .parent_data = disp_cc_parent_data_3,447 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),448 .flags = CLK_SET_RATE_PARENT,449 .ops = &clk_byte2_ops,450 },451};452 453static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {454 .cmd_rcgr = 0x8258,455 .mnd_width = 16,456 .hid_width = 5,457 .parent_map = disp_cc_parent_map_0,458 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,459 .clkr.hw.init = &(const struct clk_init_data) {460 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",461 .parent_data = disp_cc_parent_data_0,462 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),463 .flags = CLK_SET_RATE_PARENT,464 .ops = &clk_dp_ops,465 },466};467 468static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {469 .cmd_rcgr = 0x8270,470 .mnd_width = 16,471 .hid_width = 5,472 .parent_map = disp_cc_parent_map_0,473 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,474 .clkr.hw.init = &(const struct clk_init_data) {475 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",476 .parent_data = disp_cc_parent_data_0,477 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),478 .flags = CLK_SET_RATE_PARENT,479 .ops = &clk_dp_ops,480 },481};482 483static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {484 .cmd_rcgr = 0x82d4,485 .mnd_width = 0,486 .hid_width = 5,487 .parent_map = disp_cc_parent_map_1,488 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,489 .clkr.hw.init = &(const struct clk_init_data) {490 .name = "disp_cc_mdss_dptx3_aux_clk_src",491 .parent_data = disp_cc_parent_data_1,492 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),493 .flags = CLK_SET_RATE_PARENT,494 .ops = &clk_rcg2_ops,495 },496};497 498static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {499 .cmd_rcgr = 0x82b8,500 .mnd_width = 0,501 .hid_width = 5,502 .parent_map = disp_cc_parent_map_3,503 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,504 .clkr.hw.init = &(const struct clk_init_data) {505 .name = "disp_cc_mdss_dptx3_link_clk_src",506 .parent_data = disp_cc_parent_data_3,507 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),508 .flags = CLK_SET_RATE_PARENT,509 .ops = &clk_byte2_ops,510 },511};512 513static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {514 .cmd_rcgr = 0x82a0,515 .mnd_width = 16,516 .hid_width = 5,517 .parent_map = disp_cc_parent_map_0,518 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,519 .clkr.hw.init = &(const struct clk_init_data) {520 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",521 .parent_data = disp_cc_parent_data_0,522 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),523 .flags = CLK_SET_RATE_PARENT,524 .ops = &clk_dp_ops,525 },526};527 528static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {529 .cmd_rcgr = 0x8144,530 .mnd_width = 0,531 .hid_width = 5,532 .parent_map = disp_cc_parent_map_4,533 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,534 .clkr.hw.init = &(const struct clk_init_data) {535 .name = "disp_cc_mdss_esc0_clk_src",536 .parent_data = disp_cc_parent_data_4,537 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),538 .flags = CLK_SET_RATE_PARENT,539 .ops = &clk_rcg2_ops,540 },541};542 543static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {544 .cmd_rcgr = 0x815c,545 .mnd_width = 0,546 .hid_width = 5,547 .parent_map = disp_cc_parent_map_4,548 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,549 .clkr.hw.init = &(const struct clk_init_data) {550 .name = "disp_cc_mdss_esc1_clk_src",551 .parent_data = disp_cc_parent_data_4,552 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),553 .flags = CLK_SET_RATE_PARENT,554 .ops = &clk_rcg2_ops,555 },556};557 558static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {559 F(19200000, P_BI_TCXO, 1, 0, 0),560 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),561 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),562 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),563 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),564 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),565 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),566 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),567 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),568 F(575000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),569 { }570};571 572static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {573 .cmd_rcgr = 0x80dc,574 .mnd_width = 0,575 .hid_width = 5,576 .parent_map = disp_cc_parent_map_6,577 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,578 .clkr.hw.init = &(const struct clk_init_data) {579 .name = "disp_cc_mdss_mdp_clk_src",580 .parent_data = disp_cc_parent_data_6,581 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),582 .flags = CLK_SET_RATE_PARENT,583 .ops = &clk_rcg2_shared_ops,584 },585};586 587static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {588 .cmd_rcgr = 0x80ac,589 .mnd_width = 8,590 .hid_width = 5,591 .parent_map = disp_cc_parent_map_2,592 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,593 .clkr.hw.init = &(const struct clk_init_data) {594 .name = "disp_cc_mdss_pclk0_clk_src",595 .parent_data = disp_cc_parent_data_2,596 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),597 .flags = CLK_SET_RATE_PARENT,598 .ops = &clk_pixel_ops,599 },600};601 602static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {603 .cmd_rcgr = 0x80c4,604 .mnd_width = 8,605 .hid_width = 5,606 .parent_map = disp_cc_parent_map_2,607 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,608 .clkr.hw.init = &(const struct clk_init_data) {609 .name = "disp_cc_mdss_pclk1_clk_src",610 .parent_data = disp_cc_parent_data_2,611 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),612 .flags = CLK_SET_RATE_PARENT,613 .ops = &clk_pixel_ops,614 },615};616 617static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {618 .cmd_rcgr = 0x80f4,619 .mnd_width = 0,620 .hid_width = 5,621 .parent_map = disp_cc_parent_map_1,622 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,623 .clkr.hw.init = &(const struct clk_init_data) {624 .name = "disp_cc_mdss_vsync_clk_src",625 .parent_data = disp_cc_parent_data_1,626 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),627 .flags = CLK_SET_RATE_PARENT,628 .ops = &clk_rcg2_ops,629 },630};631 632static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {633 F(32000, P_SLEEP_CLK, 1, 0, 0),634 { }635};636 637static struct clk_rcg2 disp_cc_sleep_clk_src = {638 .cmd_rcgr = 0xe05c,639 .mnd_width = 0,640 .hid_width = 5,641 .parent_map = disp_cc_parent_map_7,642 .freq_tbl = ftbl_disp_cc_sleep_clk_src,643 .clkr.hw.init = &(const struct clk_init_data) {644 .name = "disp_cc_sleep_clk_src",645 .parent_data = disp_cc_parent_data_7,646 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),647 .flags = CLK_SET_RATE_PARENT,648 .ops = &clk_rcg2_ops,649 },650};651 652static struct clk_rcg2 disp_cc_xo_clk_src = {653 .cmd_rcgr = 0xe03c,654 .mnd_width = 0,655 .hid_width = 5,656 .parent_map = disp_cc_parent_map_1,657 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,658 .clkr.hw.init = &(const struct clk_init_data) {659 .name = "disp_cc_xo_clk_src",660 .parent_data = disp_cc_parent_data_1_ao,661 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1_ao),662 .flags = CLK_SET_RATE_PARENT,663 .ops = &clk_rcg2_ops,664 },665};666 667static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {668 .reg = 0x8124,669 .shift = 0,670 .width = 4,671 .clkr.hw.init = &(const struct clk_init_data) {672 .name = "disp_cc_mdss_byte0_div_clk_src",673 .parent_hws = (const struct clk_hw*[]) {674 &disp_cc_mdss_byte0_clk_src.clkr.hw,675 },676 .num_parents = 1,677 .flags = CLK_SET_RATE_PARENT,678 .ops = &clk_regmap_div_ro_ops,679 },680};681 682static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {683 .reg = 0x8140,684 .shift = 0,685 .width = 4,686 .clkr.hw.init = &(const struct clk_init_data) {687 .name = "disp_cc_mdss_byte1_div_clk_src",688 .parent_hws = (const struct clk_hw*[]) {689 &disp_cc_mdss_byte1_clk_src.clkr.hw,690 },691 .num_parents = 1,692 .flags = CLK_SET_RATE_PARENT,693 .ops = &clk_regmap_div_ro_ops,694 },695};696 697static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {698 .reg = 0x818c,699 .shift = 0,700 .width = 4,701 .clkr.hw.init = &(const struct clk_init_data) {702 .name = "disp_cc_mdss_dptx0_link_div_clk_src",703 .parent_hws = (const struct clk_hw*[]) {704 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,705 },706 .num_parents = 1,707 .flags = CLK_SET_RATE_PARENT,708 .ops = &clk_regmap_div_ro_ops,709 },710};711 712static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {713 .reg = 0x8220,714 .shift = 0,715 .width = 4,716 .clkr.hw.init = &(const struct clk_init_data) {717 .name = "disp_cc_mdss_dptx1_link_div_clk_src",718 .parent_hws = (const struct clk_hw*[]) {719 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,720 },721 .num_parents = 1,722 .flags = CLK_SET_RATE_PARENT,723 .ops = &clk_regmap_div_ro_ops,724 },725};726 727static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {728 .reg = 0x8254,729 .shift = 0,730 .width = 4,731 .clkr.hw.init = &(const struct clk_init_data) {732 .name = "disp_cc_mdss_dptx2_link_div_clk_src",733 .parent_hws = (const struct clk_hw*[]) {734 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,735 },736 .num_parents = 1,737 .flags = CLK_SET_RATE_PARENT,738 .ops = &clk_regmap_div_ro_ops,739 },740};741 742static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {743 .reg = 0x82d0,744 .shift = 0,745 .width = 4,746 .clkr.hw.init = &(const struct clk_init_data) {747 .name = "disp_cc_mdss_dptx3_link_div_clk_src",748 .parent_hws = (const struct clk_hw*[]) {749 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,750 },751 .num_parents = 1,752 .flags = CLK_SET_RATE_PARENT,753 .ops = &clk_regmap_div_ro_ops,754 },755};756 757static struct clk_branch disp_cc_mdss_accu_clk = {758 .halt_reg = 0xe058,759 .halt_check = BRANCH_HALT_VOTED,760 .clkr = {761 .enable_reg = 0xe058,762 .enable_mask = BIT(0),763 .hw.init = &(const struct clk_init_data) {764 .name = "disp_cc_mdss_accu_clk",765 .parent_hws = (const struct clk_hw*[]) {766 &disp_cc_xo_clk_src.clkr.hw,767 },768 .num_parents = 1,769 .flags = CLK_SET_RATE_PARENT,770 .ops = &clk_branch2_ops,771 },772 },773};774 775static struct clk_branch disp_cc_mdss_ahb1_clk = {776 .halt_reg = 0xa020,777 .halt_check = BRANCH_HALT,778 .clkr = {779 .enable_reg = 0xa020,780 .enable_mask = BIT(0),781 .hw.init = &(const struct clk_init_data) {782 .name = "disp_cc_mdss_ahb1_clk",783 .parent_hws = (const struct clk_hw*[]) {784 &disp_cc_mdss_ahb_clk_src.clkr.hw,785 },786 .num_parents = 1,787 .flags = CLK_SET_RATE_PARENT,788 .ops = &clk_branch2_ops,789 },790 },791};792 793static struct clk_branch disp_cc_mdss_ahb_clk = {794 .halt_reg = 0x80a8,795 .halt_check = BRANCH_HALT,796 .clkr = {797 .enable_reg = 0x80a8,798 .enable_mask = BIT(0),799 .hw.init = &(const struct clk_init_data) {800 .name = "disp_cc_mdss_ahb_clk",801 .parent_hws = (const struct clk_hw*[]) {802 &disp_cc_mdss_ahb_clk_src.clkr.hw,803 },804 .num_parents = 1,805 .flags = CLK_SET_RATE_PARENT,806 .ops = &clk_branch2_ops,807 },808 },809};810 811static struct clk_branch disp_cc_mdss_byte0_clk = {812 .halt_reg = 0x8028,813 .halt_check = BRANCH_HALT,814 .clkr = {815 .enable_reg = 0x8028,816 .enable_mask = BIT(0),817 .hw.init = &(const struct clk_init_data) {818 .name = "disp_cc_mdss_byte0_clk",819 .parent_hws = (const struct clk_hw*[]) {820 &disp_cc_mdss_byte0_clk_src.clkr.hw,821 },822 .num_parents = 1,823 .flags = CLK_SET_RATE_PARENT,824 .ops = &clk_branch2_ops,825 },826 },827};828 829static struct clk_branch disp_cc_mdss_byte0_intf_clk = {830 .halt_reg = 0x802c,831 .halt_check = BRANCH_HALT,832 .clkr = {833 .enable_reg = 0x802c,834 .enable_mask = BIT(0),835 .hw.init = &(const struct clk_init_data) {836 .name = "disp_cc_mdss_byte0_intf_clk",837 .parent_hws = (const struct clk_hw*[]) {838 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,839 },840 .num_parents = 1,841 .flags = CLK_SET_RATE_PARENT,842 .ops = &clk_branch2_ops,843 },844 },845};846 847static struct clk_branch disp_cc_mdss_byte1_clk = {848 .halt_reg = 0x8030,849 .halt_check = BRANCH_HALT,850 .clkr = {851 .enable_reg = 0x8030,852 .enable_mask = BIT(0),853 .hw.init = &(const struct clk_init_data) {854 .name = "disp_cc_mdss_byte1_clk",855 .parent_hws = (const struct clk_hw*[]) {856 &disp_cc_mdss_byte1_clk_src.clkr.hw,857 },858 .num_parents = 1,859 .flags = CLK_SET_RATE_PARENT,860 .ops = &clk_branch2_ops,861 },862 },863};864 865static struct clk_branch disp_cc_mdss_byte1_intf_clk = {866 .halt_reg = 0x8034,867 .halt_check = BRANCH_HALT,868 .clkr = {869 .enable_reg = 0x8034,870 .enable_mask = BIT(0),871 .hw.init = &(const struct clk_init_data) {872 .name = "disp_cc_mdss_byte1_intf_clk",873 .parent_hws = (const struct clk_hw*[]) {874 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,875 },876 .num_parents = 1,877 .flags = CLK_SET_RATE_PARENT,878 .ops = &clk_branch2_ops,879 },880 },881};882 883static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {884 .halt_reg = 0x8058,885 .halt_check = BRANCH_HALT,886 .clkr = {887 .enable_reg = 0x8058,888 .enable_mask = BIT(0),889 .hw.init = &(const struct clk_init_data) {890 .name = "disp_cc_mdss_dptx0_aux_clk",891 .parent_hws = (const struct clk_hw*[]) {892 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,893 },894 .num_parents = 1,895 .flags = CLK_SET_RATE_PARENT,896 .ops = &clk_branch2_ops,897 },898 },899};900 901static struct clk_branch disp_cc_mdss_dptx0_link_clk = {902 .halt_reg = 0x8040,903 .halt_check = BRANCH_HALT,904 .clkr = {905 .enable_reg = 0x8040,906 .enable_mask = BIT(0),907 .hw.init = &(const struct clk_init_data) {908 .name = "disp_cc_mdss_dptx0_link_clk",909 .parent_hws = (const struct clk_hw*[]) {910 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,911 },912 .num_parents = 1,913 .flags = CLK_SET_RATE_PARENT,914 .ops = &clk_branch2_ops,915 },916 },917};918 919static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {920 .halt_reg = 0x8048,921 .halt_check = BRANCH_HALT,922 .clkr = {923 .enable_reg = 0x8048,924 .enable_mask = BIT(0),925 .hw.init = &(const struct clk_init_data) {926 .name = "disp_cc_mdss_dptx0_link_intf_clk",927 .parent_hws = (const struct clk_hw*[]) {928 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,929 },930 .num_parents = 1,931 .flags = CLK_SET_RATE_PARENT,932 .ops = &clk_branch2_ops,933 },934 },935};936 937static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {938 .halt_reg = 0x8050,939 .halt_check = BRANCH_HALT,940 .clkr = {941 .enable_reg = 0x8050,942 .enable_mask = BIT(0),943 .hw.init = &(const struct clk_init_data) {944 .name = "disp_cc_mdss_dptx0_pixel0_clk",945 .parent_hws = (const struct clk_hw*[]) {946 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,947 },948 .num_parents = 1,949 .flags = CLK_SET_RATE_PARENT,950 .ops = &clk_branch2_ops,951 },952 },953};954 955static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {956 .halt_reg = 0x8054,957 .halt_check = BRANCH_HALT,958 .clkr = {959 .enable_reg = 0x8054,960 .enable_mask = BIT(0),961 .hw.init = &(const struct clk_init_data) {962 .name = "disp_cc_mdss_dptx0_pixel1_clk",963 .parent_hws = (const struct clk_hw*[]) {964 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,965 },966 .num_parents = 1,967 .flags = CLK_SET_RATE_PARENT,968 .ops = &clk_branch2_ops,969 },970 },971};972 973static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {974 .halt_reg = 0x8044,975 .halt_check = BRANCH_HALT,976 .clkr = {977 .enable_reg = 0x8044,978 .enable_mask = BIT(0),979 .hw.init = &(const struct clk_init_data) {980 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",981 .parent_hws = (const struct clk_hw*[]) {982 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,983 },984 .num_parents = 1,985 .flags = CLK_SET_RATE_PARENT,986 .ops = &clk_branch2_ops,987 },988 },989};990 991static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {992 .halt_reg = 0x8074,993 .halt_check = BRANCH_HALT,994 .clkr = {995 .enable_reg = 0x8074,996 .enable_mask = BIT(0),997 .hw.init = &(const struct clk_init_data) {998 .name = "disp_cc_mdss_dptx1_aux_clk",999 .parent_hws = (const struct clk_hw*[]) {1000 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,1001 },1002 .num_parents = 1,1003 .flags = CLK_SET_RATE_PARENT,1004 .ops = &clk_branch2_ops,1005 },1006 },1007};1008 1009static struct clk_branch disp_cc_mdss_dptx1_link_clk = {1010 .halt_reg = 0x8064,1011 .halt_check = BRANCH_HALT,1012 .clkr = {1013 .enable_reg = 0x8064,1014 .enable_mask = BIT(0),1015 .hw.init = &(const struct clk_init_data) {1016 .name = "disp_cc_mdss_dptx1_link_clk",1017 .parent_hws = (const struct clk_hw*[]) {1018 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,1019 },1020 .num_parents = 1,1021 .flags = CLK_SET_RATE_PARENT,1022 .ops = &clk_branch2_ops,1023 },1024 },1025};1026 1027static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {1028 .halt_reg = 0x806c,1029 .halt_check = BRANCH_HALT,1030 .clkr = {1031 .enable_reg = 0x806c,1032 .enable_mask = BIT(0),1033 .hw.init = &(const struct clk_init_data) {1034 .name = "disp_cc_mdss_dptx1_link_intf_clk",1035 .parent_hws = (const struct clk_hw*[]) {1036 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,1037 },1038 .num_parents = 1,1039 .flags = CLK_SET_RATE_PARENT,1040 .ops = &clk_branch2_ops,1041 },1042 },1043};1044 1045static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {1046 .halt_reg = 0x805c,1047 .halt_check = BRANCH_HALT,1048 .clkr = {1049 .enable_reg = 0x805c,1050 .enable_mask = BIT(0),1051 .hw.init = &(const struct clk_init_data) {1052 .name = "disp_cc_mdss_dptx1_pixel0_clk",1053 .parent_hws = (const struct clk_hw*[]) {1054 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,1055 },1056 .num_parents = 1,1057 .flags = CLK_SET_RATE_PARENT,1058 .ops = &clk_branch2_ops,1059 },1060 },1061};1062 1063static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {1064 .halt_reg = 0x8060,1065 .halt_check = BRANCH_HALT,1066 .clkr = {1067 .enable_reg = 0x8060,1068 .enable_mask = BIT(0),1069 .hw.init = &(const struct clk_init_data) {1070 .name = "disp_cc_mdss_dptx1_pixel1_clk",1071 .parent_hws = (const struct clk_hw*[]) {1072 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,1073 },1074 .num_parents = 1,1075 .flags = CLK_SET_RATE_PARENT,1076 .ops = &clk_branch2_ops,1077 },1078 },1079};1080 1081static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {1082 .halt_reg = 0x8068,1083 .halt_check = BRANCH_HALT,1084 .clkr = {1085 .enable_reg = 0x8068,1086 .enable_mask = BIT(0),1087 .hw.init = &(const struct clk_init_data) {1088 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",1089 .parent_hws = (const struct clk_hw*[]) {1090 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,1091 },1092 .num_parents = 1,1093 .flags = CLK_SET_RATE_PARENT,1094 .ops = &clk_branch2_ops,1095 },1096 },1097};1098 1099static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {1100 .halt_reg = 0x8090,1101 .halt_check = BRANCH_HALT,1102 .clkr = {1103 .enable_reg = 0x8090,1104 .enable_mask = BIT(0),1105 .hw.init = &(const struct clk_init_data) {1106 .name = "disp_cc_mdss_dptx2_aux_clk",1107 .parent_hws = (const struct clk_hw*[]) {1108 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,1109 },1110 .num_parents = 1,1111 .flags = CLK_SET_RATE_PARENT,1112 .ops = &clk_branch2_ops,1113 },1114 },1115};1116 1117static struct clk_branch disp_cc_mdss_dptx2_link_clk = {1118 .halt_reg = 0x8080,1119 .halt_check = BRANCH_HALT,1120 .clkr = {1121 .enable_reg = 0x8080,1122 .enable_mask = BIT(0),1123 .hw.init = &(const struct clk_init_data) {1124 .name = "disp_cc_mdss_dptx2_link_clk",1125 .parent_hws = (const struct clk_hw*[]) {1126 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,1127 },1128 .num_parents = 1,1129 .flags = CLK_SET_RATE_PARENT,1130 .ops = &clk_branch2_ops,1131 },1132 },1133};1134 1135static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {1136 .halt_reg = 0x8084,1137 .halt_check = BRANCH_HALT,1138 .clkr = {1139 .enable_reg = 0x8084,1140 .enable_mask = BIT(0),1141 .hw.init = &(const struct clk_init_data) {1142 .name = "disp_cc_mdss_dptx2_link_intf_clk",1143 .parent_hws = (const struct clk_hw*[]) {1144 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,1145 },1146 .num_parents = 1,1147 .flags = CLK_SET_RATE_PARENT,1148 .ops = &clk_branch2_ops,1149 },1150 },1151};1152 1153static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {1154 .halt_reg = 0x8078,1155 .halt_check = BRANCH_HALT,1156 .clkr = {1157 .enable_reg = 0x8078,1158 .enable_mask = BIT(0),1159 .hw.init = &(const struct clk_init_data) {1160 .name = "disp_cc_mdss_dptx2_pixel0_clk",1161 .parent_hws = (const struct clk_hw*[]) {1162 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,1163 },1164 .num_parents = 1,1165 .flags = CLK_SET_RATE_PARENT,1166 .ops = &clk_branch2_ops,1167 },1168 },1169};1170 1171static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {1172 .halt_reg = 0x807c,1173 .halt_check = BRANCH_HALT,1174 .clkr = {1175 .enable_reg = 0x807c,1176 .enable_mask = BIT(0),1177 .hw.init = &(const struct clk_init_data) {1178 .name = "disp_cc_mdss_dptx2_pixel1_clk",1179 .parent_hws = (const struct clk_hw*[]) {1180 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,1181 },1182 .num_parents = 1,1183 .flags = CLK_SET_RATE_PARENT,1184 .ops = &clk_branch2_ops,1185 },1186 },1187};1188 1189static struct clk_branch disp_cc_mdss_dptx2_usb_router_link_intf_clk = {1190 .halt_reg = 0x8088,1191 .halt_check = BRANCH_HALT,1192 .clkr = {1193 .enable_reg = 0x8088,1194 .enable_mask = BIT(0),1195 .hw.init = &(const struct clk_init_data) {1196 .name = "disp_cc_mdss_dptx2_usb_router_link_intf_clk",1197 .parent_hws = (const struct clk_hw*[]) {1198 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,1199 },1200 .num_parents = 1,1201 .flags = CLK_SET_RATE_PARENT,1202 .ops = &clk_branch2_ops,1203 },1204 },1205};1206 1207static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {1208 .halt_reg = 0x80a0,1209 .halt_check = BRANCH_HALT,1210 .clkr = {1211 .enable_reg = 0x80a0,1212 .enable_mask = BIT(0),1213 .hw.init = &(const struct clk_init_data) {1214 .name = "disp_cc_mdss_dptx3_aux_clk",1215 .parent_hws = (const struct clk_hw*[]) {1216 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,1217 },1218 .num_parents = 1,1219 .flags = CLK_SET_RATE_PARENT,1220 .ops = &clk_branch2_ops,1221 },1222 },1223};1224 1225static struct clk_branch disp_cc_mdss_dptx3_link_clk = {1226 .halt_reg = 0x8098,1227 .halt_check = BRANCH_HALT,1228 .clkr = {1229 .enable_reg = 0x8098,1230 .enable_mask = BIT(0),1231 .hw.init = &(const struct clk_init_data) {1232 .name = "disp_cc_mdss_dptx3_link_clk",1233 .parent_hws = (const struct clk_hw*[]) {1234 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,1235 },1236 .num_parents = 1,1237 .flags = CLK_SET_RATE_PARENT,1238 .ops = &clk_branch2_ops,1239 },1240 },1241};1242 1243static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {1244 .halt_reg = 0x809c,1245 .halt_check = BRANCH_HALT,1246 .clkr = {1247 .enable_reg = 0x809c,1248 .enable_mask = BIT(0),1249 .hw.init = &(const struct clk_init_data) {1250 .name = "disp_cc_mdss_dptx3_link_intf_clk",1251 .parent_hws = (const struct clk_hw*[]) {1252 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,1253 },1254 .num_parents = 1,1255 .flags = CLK_SET_RATE_PARENT,1256 .ops = &clk_branch2_ops,1257 },1258 },1259};1260 1261static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {1262 .halt_reg = 0x8094,1263 .halt_check = BRANCH_HALT,1264 .clkr = {1265 .enable_reg = 0x8094,1266 .enable_mask = BIT(0),1267 .hw.init = &(const struct clk_init_data) {1268 .name = "disp_cc_mdss_dptx3_pixel0_clk",1269 .parent_hws = (const struct clk_hw*[]) {1270 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,1271 },1272 .num_parents = 1,1273 .flags = CLK_SET_RATE_PARENT,1274 .ops = &clk_branch2_ops,1275 },1276 },1277};1278 1279static struct clk_branch disp_cc_mdss_esc0_clk = {1280 .halt_reg = 0x8038,1281 .halt_check = BRANCH_HALT,1282 .clkr = {1283 .enable_reg = 0x8038,1284 .enable_mask = BIT(0),1285 .hw.init = &(const struct clk_init_data) {1286 .name = "disp_cc_mdss_esc0_clk",1287 .parent_hws = (const struct clk_hw*[]) {1288 &disp_cc_mdss_esc0_clk_src.clkr.hw,1289 },1290 .num_parents = 1,1291 .flags = CLK_SET_RATE_PARENT,1292 .ops = &clk_branch2_ops,1293 },1294 },1295};1296 1297static struct clk_branch disp_cc_mdss_esc1_clk = {1298 .halt_reg = 0x803c,1299 .halt_check = BRANCH_HALT,1300 .clkr = {1301 .enable_reg = 0x803c,1302 .enable_mask = BIT(0),1303 .hw.init = &(const struct clk_init_data) {1304 .name = "disp_cc_mdss_esc1_clk",1305 .parent_hws = (const struct clk_hw*[]) {1306 &disp_cc_mdss_esc1_clk_src.clkr.hw,1307 },1308 .num_parents = 1,1309 .flags = CLK_SET_RATE_PARENT,1310 .ops = &clk_branch2_ops,1311 },1312 },1313};1314 1315static struct clk_branch disp_cc_mdss_mdp1_clk = {1316 .halt_reg = 0xa004,1317 .halt_check = BRANCH_HALT,1318 .clkr = {1319 .enable_reg = 0xa004,1320 .enable_mask = BIT(0),1321 .hw.init = &(const struct clk_init_data) {1322 .name = "disp_cc_mdss_mdp1_clk",1323 .parent_hws = (const struct clk_hw*[]) {1324 &disp_cc_mdss_mdp_clk_src.clkr.hw,1325 },1326 .num_parents = 1,1327 .flags = CLK_SET_RATE_PARENT,1328 .ops = &clk_branch2_ops,1329 },1330 },1331};1332 1333static struct clk_branch disp_cc_mdss_mdp_clk = {1334 .halt_reg = 0x800c,1335 .halt_check = BRANCH_HALT,1336 .clkr = {1337 .enable_reg = 0x800c,1338 .enable_mask = BIT(0),1339 .hw.init = &(const struct clk_init_data) {1340 .name = "disp_cc_mdss_mdp_clk",1341 .parent_hws = (const struct clk_hw*[]) {1342 &disp_cc_mdss_mdp_clk_src.clkr.hw,1343 },1344 .num_parents = 1,1345 .flags = CLK_SET_RATE_PARENT,1346 .ops = &clk_branch2_ops,1347 },1348 },1349};1350 1351static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {1352 .halt_reg = 0xa010,1353 .halt_check = BRANCH_HALT,1354 .clkr = {1355 .enable_reg = 0xa010,1356 .enable_mask = BIT(0),1357 .hw.init = &(const struct clk_init_data) {1358 .name = "disp_cc_mdss_mdp_lut1_clk",1359 .parent_hws = (const struct clk_hw*[]) {1360 &disp_cc_mdss_mdp_clk_src.clkr.hw,1361 },1362 .num_parents = 1,1363 .flags = CLK_SET_RATE_PARENT,1364 .ops = &clk_branch2_ops,1365 },1366 },1367};1368 1369static struct clk_branch disp_cc_mdss_mdp_lut_clk = {1370 .halt_reg = 0x8018,1371 .halt_check = BRANCH_HALT_VOTED,1372 .clkr = {1373 .enable_reg = 0x8018,1374 .enable_mask = BIT(0),1375 .hw.init = &(const struct clk_init_data) {1376 .name = "disp_cc_mdss_mdp_lut_clk",1377 .parent_hws = (const struct clk_hw*[]) {1378 &disp_cc_mdss_mdp_clk_src.clkr.hw,1379 },1380 .num_parents = 1,1381 .flags = CLK_SET_RATE_PARENT,1382 .ops = &clk_branch2_ops,1383 },1384 },1385};1386 1387static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {1388 .halt_reg = 0xc004,1389 .halt_check = BRANCH_HALT_VOTED,1390 .clkr = {1391 .enable_reg = 0xc004,1392 .enable_mask = BIT(0),1393 .hw.init = &(const struct clk_init_data) {1394 .name = "disp_cc_mdss_non_gdsc_ahb_clk",1395 .parent_hws = (const struct clk_hw*[]) {1396 &disp_cc_mdss_ahb_clk_src.clkr.hw,1397 },1398 .num_parents = 1,1399 .flags = CLK_SET_RATE_PARENT,1400 .ops = &clk_branch2_ops,1401 },1402 },1403};1404 1405static struct clk_branch disp_cc_mdss_pclk0_clk = {1406 .halt_reg = 0x8004,1407 .halt_check = BRANCH_HALT,1408 .clkr = {1409 .enable_reg = 0x8004,1410 .enable_mask = BIT(0),1411 .hw.init = &(const struct clk_init_data) {1412 .name = "disp_cc_mdss_pclk0_clk",1413 .parent_hws = (const struct clk_hw*[]) {1414 &disp_cc_mdss_pclk0_clk_src.clkr.hw,1415 },1416 .num_parents = 1,1417 .flags = CLK_SET_RATE_PARENT,1418 .ops = &clk_branch2_ops,1419 },1420 },1421};1422 1423static struct clk_branch disp_cc_mdss_pclk1_clk = {1424 .halt_reg = 0x8008,1425 .halt_check = BRANCH_HALT,1426 .clkr = {1427 .enable_reg = 0x8008,1428 .enable_mask = BIT(0),1429 .hw.init = &(const struct clk_init_data) {1430 .name = "disp_cc_mdss_pclk1_clk",1431 .parent_hws = (const struct clk_hw*[]) {1432 &disp_cc_mdss_pclk1_clk_src.clkr.hw,1433 },1434 .num_parents = 1,1435 .flags = CLK_SET_RATE_PARENT,1436 .ops = &clk_branch2_ops,1437 },1438 },1439};1440 1441static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {1442 .halt_reg = 0xc00c,1443 .halt_check = BRANCH_HALT,1444 .clkr = {1445 .enable_reg = 0xc00c,1446 .enable_mask = BIT(0),1447 .hw.init = &(const struct clk_init_data) {1448 .name = "disp_cc_mdss_rscc_ahb_clk",1449 .parent_hws = (const struct clk_hw*[]) {1450 &disp_cc_mdss_ahb_clk_src.clkr.hw,1451 },1452 .num_parents = 1,1453 .flags = CLK_SET_RATE_PARENT,1454 .ops = &clk_branch2_ops,1455 },1456 },1457};1458 1459static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {1460 .halt_reg = 0xc008,1461 .halt_check = BRANCH_HALT,1462 .clkr = {1463 .enable_reg = 0xc008,1464 .enable_mask = BIT(0),1465 .hw.init = &(const struct clk_init_data) {1466 .name = "disp_cc_mdss_rscc_vsync_clk",1467 .parent_hws = (const struct clk_hw*[]) {1468 &disp_cc_mdss_vsync_clk_src.clkr.hw,1469 },1470 .num_parents = 1,1471 .flags = CLK_SET_RATE_PARENT,1472 .ops = &clk_branch2_ops,1473 },1474 },1475};1476 1477static struct clk_branch disp_cc_mdss_vsync1_clk = {1478 .halt_reg = 0xa01c,1479 .halt_check = BRANCH_HALT,1480 .clkr = {1481 .enable_reg = 0xa01c,1482 .enable_mask = BIT(0),1483 .hw.init = &(const struct clk_init_data) {1484 .name = "disp_cc_mdss_vsync1_clk",1485 .parent_hws = (const struct clk_hw*[]) {1486 &disp_cc_mdss_vsync_clk_src.clkr.hw,1487 },1488 .num_parents = 1,1489 .flags = CLK_SET_RATE_PARENT,1490 .ops = &clk_branch2_ops,1491 },1492 },1493};1494 1495static struct clk_branch disp_cc_mdss_vsync_clk = {1496 .halt_reg = 0x8024,1497 .halt_check = BRANCH_HALT,1498 .clkr = {1499 .enable_reg = 0x8024,1500 .enable_mask = BIT(0),1501 .hw.init = &(const struct clk_init_data) {1502 .name = "disp_cc_mdss_vsync_clk",1503 .parent_hws = (const struct clk_hw*[]) {1504 &disp_cc_mdss_vsync_clk_src.clkr.hw,1505 },1506 .num_parents = 1,1507 .flags = CLK_SET_RATE_PARENT,1508 .ops = &clk_branch2_ops,1509 },1510 },1511};1512 1513static struct gdsc mdss_gdsc = {1514 .gdscr = 0x9000,1515 .en_rest_wait_val = 0x2,1516 .en_few_wait_val = 0x2,1517 .clk_dis_wait_val = 0xf,1518 .pd = {1519 .name = "mdss_gdsc",1520 },1521 .pwrsts = PWRSTS_OFF_ON,1522 .flags = HW_CTRL | RETAIN_FF_ENABLE,1523};1524 1525static struct gdsc mdss_int2_gdsc = {1526 .gdscr = 0xb000,1527 .en_rest_wait_val = 0x2,1528 .en_few_wait_val = 0x2,1529 .clk_dis_wait_val = 0xf,1530 .pd = {1531 .name = "mdss_int2_gdsc",1532 },1533 .pwrsts = PWRSTS_OFF_ON,1534 .flags = HW_CTRL | RETAIN_FF_ENABLE,1535};1536 1537static struct clk_regmap *disp_cc_x1e80100_clocks[] = {1538 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,1539 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,1540 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,1541 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,1542 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,1543 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,1544 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,1545 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,1546 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,1547 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,1548 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,1549 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,1550 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,1551 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,1552 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,1553 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,1554 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,1555 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,1556 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,1557 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,1558 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,1559 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,1560 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =1561 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,1562 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,1563 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,1564 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,1565 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,1566 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,1567 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,1568 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,1569 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,1570 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,1571 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,1572 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =1573 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,1574 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,1575 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,1576 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,1577 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,1578 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,1579 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,1580 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,1581 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,1582 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,1583 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,1584 [DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK] =1585 &disp_cc_mdss_dptx2_usb_router_link_intf_clk.clkr,1586 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,1587 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,1588 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,1589 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,1590 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,1591 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,1592 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,1593 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,1594 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,1595 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,1596 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,1597 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,1598 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,1599 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,1600 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,1601 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,1602 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,1603 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,1604 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,1605 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,1606 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,1607 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,1608 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,1609 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,1610 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,1611 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,1612 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,1613 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,1614 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,1615 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,1616 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,1617};1618 1619static const struct qcom_reset_map disp_cc_x1e80100_resets[] = {1620 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },1621 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },1622 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },1623};1624 1625static struct gdsc *disp_cc_x1e80100_gdscs[] = {1626 [MDSS_GDSC] = &mdss_gdsc,1627 [MDSS_INT2_GDSC] = &mdss_int2_gdsc,1628};1629 1630static const struct regmap_config disp_cc_x1e80100_regmap_config = {1631 .reg_bits = 32,1632 .reg_stride = 4,1633 .val_bits = 32,1634 .max_register = 0x11008,1635 .fast_io = true,1636};1637 1638static const struct qcom_cc_desc disp_cc_x1e80100_desc = {1639 .config = &disp_cc_x1e80100_regmap_config,1640 .clks = disp_cc_x1e80100_clocks,1641 .num_clks = ARRAY_SIZE(disp_cc_x1e80100_clocks),1642 .resets = disp_cc_x1e80100_resets,1643 .num_resets = ARRAY_SIZE(disp_cc_x1e80100_resets),1644 .gdscs = disp_cc_x1e80100_gdscs,1645 .num_gdscs = ARRAY_SIZE(disp_cc_x1e80100_gdscs),1646};1647 1648static const struct of_device_id disp_cc_x1e80100_match_table[] = {1649 { .compatible = "qcom,x1e80100-dispcc" },1650 { }1651};1652MODULE_DEVICE_TABLE(of, disp_cc_x1e80100_match_table);1653 1654static int disp_cc_x1e80100_probe(struct platform_device *pdev)1655{1656 struct regmap *regmap;1657 int ret;1658 1659 ret = devm_pm_runtime_enable(&pdev->dev);1660 if (ret)1661 return ret;1662 1663 ret = pm_runtime_resume_and_get(&pdev->dev);1664 if (ret)1665 return ret;1666 1667 regmap = qcom_cc_map(pdev, &disp_cc_x1e80100_desc);1668 if (IS_ERR(regmap)) {1669 ret = PTR_ERR(regmap);1670 goto err_put_rpm;1671 }1672 1673 clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);1674 clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);1675 1676 /* Enable clock gating for MDP clocks */1677 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);1678 1679 /* Keep clocks always enabled */1680 qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */1681 qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */1682 1683 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_x1e80100_desc, regmap);1684 if (ret)1685 goto err_put_rpm;1686 1687 pm_runtime_put(&pdev->dev);1688 1689 return 0;1690 1691err_put_rpm:1692 pm_runtime_put_sync(&pdev->dev);1693 1694 return ret;1695}1696 1697static struct platform_driver disp_cc_x1e80100_driver = {1698 .probe = disp_cc_x1e80100_probe,1699 .driver = {1700 .name = "dispcc-x1e80100",1701 .of_match_table = disp_cc_x1e80100_match_table,1702 },1703};1704 1705static int __init disp_cc_x1e80100_init(void)1706{1707 return platform_driver_register(&disp_cc_x1e80100_driver);1708}1709subsys_initcall(disp_cc_x1e80100_init);1710 1711static void __exit disp_cc_x1e80100_exit(void)1712{1713 platform_driver_unregister(&disp_cc_x1e80100_driver);1714}1715module_exit(disp_cc_x1e80100_exit);1716 1717MODULE_DESCRIPTION("QTI Display Clock Controller X1E80100 Driver");1718MODULE_LICENSE("GPL");1719