2457 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/regmap.h>11 12#include <dt-bindings/clock/qcom,qdu1000-ecpricc.h>13 14#include "clk-alpha-pll.h"15#include "clk-branch.h"16#include "clk-rcg.h"17#include "clk-regmap.h"18#include "clk-regmap-divider.h"19#include "clk-regmap-mux.h"20#include "common.h"21#include "reset.h"22 23enum {24 DT_BI_TCXO,25 DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN,26 DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN,27 DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN,28 DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN,29 DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN,30 DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN,31};32 33enum {34 P_BI_TCXO,35 P_ECPRI_CC_PLL0_OUT_MAIN,36 P_ECPRI_CC_PLL1_OUT_MAIN,37 P_GCC_ECPRI_CC_GPLL0_OUT_MAIN,38 P_GCC_ECPRI_CC_GPLL1_OUT_EVEN,39 P_GCC_ECPRI_CC_GPLL2_OUT_MAIN,40 P_GCC_ECPRI_CC_GPLL3_OUT_MAIN,41 P_GCC_ECPRI_CC_GPLL4_OUT_MAIN,42 P_GCC_ECPRI_CC_GPLL5_OUT_EVEN,43};44 45static const struct pll_vco lucid_evo_vco[] = {46 { 249600000, 2020000000, 0 },47};48 49/* 700 MHz configuration */50static const struct alpha_pll_config ecpri_cc_pll0_config = {51 .l = 0x24,52 .alpha = 0x7555,53 .config_ctl_val = 0x20485699,54 .config_ctl_hi_val = 0x00182261,55 .config_ctl_hi1_val = 0x32aa299c,56 .user_ctl_val = 0x00000000,57 .user_ctl_hi_val = 0x00000805,58};59 60static struct clk_alpha_pll ecpri_cc_pll0 = {61 .offset = 0x0,62 .vco_table = lucid_evo_vco,63 .num_vco = ARRAY_SIZE(lucid_evo_vco),64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],65 .clkr = {66 .enable_reg = 0x0,67 .enable_mask = BIT(0),68 .hw.init = &(const struct clk_init_data) {69 .name = "ecpri_cc_pll0",70 .parent_data = &(const struct clk_parent_data) {71 .index = DT_BI_TCXO,72 },73 .num_parents = 1,74 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,75 },76 },77};78 79/* 806 MHz configuration */80static const struct alpha_pll_config ecpri_cc_pll1_config = {81 .l = 0x29,82 .alpha = 0xfaaa,83 .config_ctl_val = 0x20485699,84 .config_ctl_hi_val = 0x00182261,85 .config_ctl_hi1_val = 0x32aa299c,86 .user_ctl_val = 0x00000000,87 .user_ctl_hi_val = 0x00000805,88};89 90static struct clk_alpha_pll ecpri_cc_pll1 = {91 .offset = 0x1000,92 .vco_table = lucid_evo_vco,93 .num_vco = ARRAY_SIZE(lucid_evo_vco),94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],95 .clkr = {96 .enable_reg = 0x0,97 .enable_mask = BIT(1),98 .hw.init = &(const struct clk_init_data) {99 .name = "ecpri_cc_pll1",100 .parent_data = &(const struct clk_parent_data) {101 .index = DT_BI_TCXO,102 },103 .num_parents = 1,104 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,105 },106 },107};108 109static const struct parent_map ecpri_cc_parent_map_0[] = {110 { P_BI_TCXO, 0 },111 { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },112 { P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 2 },113 { P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },114 { P_ECPRI_CC_PLL1_OUT_MAIN, 4 },115 { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },116 { P_ECPRI_CC_PLL0_OUT_MAIN, 6 },117};118 119static const struct clk_parent_data ecpri_cc_parent_data_0[] = {120 { .index = DT_BI_TCXO },121 { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },122 { .index = DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN },123 { .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },124 { .hw = &ecpri_cc_pll1.clkr.hw },125 { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },126 { .hw = &ecpri_cc_pll0.clkr.hw },127};128 129static const struct parent_map ecpri_cc_parent_map_1[] = {130 { P_BI_TCXO, 0 },131 { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },132 { P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 2 },133 { P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 3 },134 { P_ECPRI_CC_PLL1_OUT_MAIN, 4 },135 { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },136 { P_ECPRI_CC_PLL0_OUT_MAIN, 6 },137};138 139static const struct clk_parent_data ecpri_cc_parent_data_1[] = {140 { .index = DT_BI_TCXO },141 { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },142 { .index = DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN },143 { .index = DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN },144 { .hw = &ecpri_cc_pll1.clkr.hw },145 { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },146 { .hw = &ecpri_cc_pll0.clkr.hw },147};148 149static const struct parent_map ecpri_cc_parent_map_2[] = {150 { P_BI_TCXO, 0 },151 { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },152 { P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },153 { P_ECPRI_CC_PLL1_OUT_MAIN, 4 },154 { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },155 { P_ECPRI_CC_PLL0_OUT_MAIN, 6 },156};157 158static const struct clk_parent_data ecpri_cc_parent_data_2[] = {159 { .index = DT_BI_TCXO },160 { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },161 { .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },162 { .hw = &ecpri_cc_pll1.clkr.hw },163 { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },164 { .hw = &ecpri_cc_pll0.clkr.hw },165};166 167static const struct freq_tbl ftbl_ecpri_cc_ecpri_clk_src[] = {168 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),169 { }170};171 172static struct clk_rcg2 ecpri_cc_ecpri_clk_src = {173 .cmd_rcgr = 0x9034,174 .mnd_width = 0,175 .hid_width = 5,176 .parent_map = ecpri_cc_parent_map_2,177 .freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,178 .clkr.hw.init = &(const struct clk_init_data) {179 .name = "ecpri_cc_ecpri_clk_src",180 .parent_data = ecpri_cc_parent_data_2,181 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),182 .ops = &clk_rcg2_shared_ops,183 },184};185 186static const struct freq_tbl ftbl_ecpri_cc_ecpri_dma_clk_src[] = {187 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),188 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),189 { }190};191 192static struct clk_rcg2 ecpri_cc_ecpri_dma_clk_src = {193 .cmd_rcgr = 0x9080,194 .mnd_width = 0,195 .hid_width = 5,196 .parent_map = ecpri_cc_parent_map_0,197 .freq_tbl = ftbl_ecpri_cc_ecpri_dma_clk_src,198 .clkr.hw.init = &(const struct clk_init_data) {199 .name = "ecpri_cc_ecpri_dma_clk_src",200 .parent_data = ecpri_cc_parent_data_0,201 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),202 .ops = &clk_rcg2_shared_ops,203 },204};205 206static const struct freq_tbl ftbl_ecpri_cc_ecpri_fast_clk_src[] = {207 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),208 F(600000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1, 0, 0),209 { }210};211 212static struct clk_rcg2 ecpri_cc_ecpri_fast_clk_src = {213 .cmd_rcgr = 0x904c,214 .mnd_width = 0,215 .hid_width = 5,216 .parent_map = ecpri_cc_parent_map_0,217 .freq_tbl = ftbl_ecpri_cc_ecpri_fast_clk_src,218 .clkr.hw.init = &(const struct clk_init_data) {219 .name = "ecpri_cc_ecpri_fast_clk_src",220 .parent_data = ecpri_cc_parent_data_0,221 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),222 .ops = &clk_rcg2_shared_ops,223 },224};225 226static const struct freq_tbl ftbl_ecpri_cc_ecpri_oran_clk_src[] = {227 F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),228 { }229};230 231static struct clk_rcg2 ecpri_cc_ecpri_oran_clk_src = {232 .cmd_rcgr = 0x9064,233 .mnd_width = 0,234 .hid_width = 5,235 .parent_map = ecpri_cc_parent_map_0,236 .freq_tbl = ftbl_ecpri_cc_ecpri_oran_clk_src,237 .clkr.hw.init = &(const struct clk_init_data) {238 .name = "ecpri_cc_ecpri_oran_clk_src",239 .parent_data = ecpri_cc_parent_data_0,240 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),241 .ops = &clk_rcg2_shared_ops,242 },243};244 245static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src[] = {246 F(201500000, P_ECPRI_CC_PLL1_OUT_MAIN, 4, 0, 0),247 F(403000000, P_ECPRI_CC_PLL1_OUT_MAIN, 2, 0, 0),248 F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),249 { }250};251 252static struct clk_rcg2 ecpri_cc_eth_100g_c2c0_hm_ff_clk_src = {253 .cmd_rcgr = 0x81b0,254 .mnd_width = 0,255 .hid_width = 5,256 .parent_map = ecpri_cc_parent_map_0,257 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,258 .clkr.hw.init = &(const struct clk_init_data) {259 .name = "ecpri_cc_eth_100g_c2c0_hm_ff_clk_src",260 .parent_data = ecpri_cc_parent_data_0,261 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),262 .ops = &clk_rcg2_shared_ops,263 },264};265 266static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src[] = {267 F(100000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 6, 0, 0),268 F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),269 { }270};271 272static struct clk_rcg2 ecpri_cc_eth_100g_c2c_hm_macsec_clk_src = {273 .cmd_rcgr = 0x8150,274 .mnd_width = 0,275 .hid_width = 5,276 .parent_map = ecpri_cc_parent_map_0,277 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,278 .clkr.hw.init = &(const struct clk_init_data) {279 .name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk_src",280 .parent_data = ecpri_cc_parent_data_0,281 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),282 .ops = &clk_rcg2_shared_ops,283 },284};285 286static struct clk_rcg2 ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src = {287 .cmd_rcgr = 0x81c8,288 .mnd_width = 0,289 .hid_width = 5,290 .parent_map = ecpri_cc_parent_map_0,291 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,292 .clkr.hw.init = &(const struct clk_init_data) {293 .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src",294 .parent_data = ecpri_cc_parent_data_0,295 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),296 .ops = &clk_rcg2_shared_ops,297 },298};299 300static struct clk_rcg2 ecpri_cc_eth_100g_fh0_hm_ff_clk_src = {301 .cmd_rcgr = 0x8168,302 .mnd_width = 0,303 .hid_width = 5,304 .parent_map = ecpri_cc_parent_map_0,305 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,306 .clkr.hw.init = &(const struct clk_init_data) {307 .name = "ecpri_cc_eth_100g_fh0_hm_ff_clk_src",308 .parent_data = ecpri_cc_parent_data_0,309 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),310 .ops = &clk_rcg2_shared_ops,311 },312};313 314static struct clk_rcg2 ecpri_cc_eth_100g_fh0_macsec_clk_src = {315 .cmd_rcgr = 0x8108,316 .mnd_width = 0,317 .hid_width = 5,318 .parent_map = ecpri_cc_parent_map_0,319 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,320 .clkr.hw.init = &(const struct clk_init_data) {321 .name = "ecpri_cc_eth_100g_fh0_macsec_clk_src",322 .parent_data = ecpri_cc_parent_data_0,323 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),324 .ops = &clk_rcg2_shared_ops,325 },326};327 328static struct clk_rcg2 ecpri_cc_eth_100g_fh1_hm_ff_clk_src = {329 .cmd_rcgr = 0x8180,330 .mnd_width = 0,331 .hid_width = 5,332 .parent_map = ecpri_cc_parent_map_0,333 .freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,334 .clkr.hw.init = &(const struct clk_init_data) {335 .name = "ecpri_cc_eth_100g_fh1_hm_ff_clk_src",336 .parent_data = ecpri_cc_parent_data_0,337 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),338 .ops = &clk_rcg2_shared_ops,339 },340};341 342static const struct freq_tbl ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src[] = {343 F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),344 { }345};346 347static struct clk_rcg2 ecpri_cc_eth_100g_fh1_macsec_clk_src = {348 .cmd_rcgr = 0x8120,349 .mnd_width = 0,350 .hid_width = 5,351 .parent_map = ecpri_cc_parent_map_0,352 .freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,353 .clkr.hw.init = &(const struct clk_init_data) {354 .name = "ecpri_cc_eth_100g_fh1_macsec_clk_src",355 .parent_data = ecpri_cc_parent_data_0,356 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),357 .ops = &clk_rcg2_shared_ops,358 },359};360 361static struct clk_rcg2 ecpri_cc_eth_100g_fh2_hm_ff_clk_src = {362 .cmd_rcgr = 0x8198,363 .mnd_width = 0,364 .hid_width = 5,365 .parent_map = ecpri_cc_parent_map_0,366 .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,367 .clkr.hw.init = &(const struct clk_init_data) {368 .name = "ecpri_cc_eth_100g_fh2_hm_ff_clk_src",369 .parent_data = ecpri_cc_parent_data_0,370 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),371 .ops = &clk_rcg2_shared_ops,372 },373};374 375static struct clk_rcg2 ecpri_cc_eth_100g_fh2_macsec_clk_src = {376 .cmd_rcgr = 0x8138,377 .mnd_width = 0,378 .hid_width = 5,379 .parent_map = ecpri_cc_parent_map_0,380 .freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,381 .clkr.hw.init = &(const struct clk_init_data) {382 .name = "ecpri_cc_eth_100g_fh2_macsec_clk_src",383 .parent_data = ecpri_cc_parent_data_0,384 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),385 .ops = &clk_rcg2_shared_ops,386 },387};388 389static const struct freq_tbl ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src[] = {390 F(533000000, P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 1, 0, 0),391 F(700000000, P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 1, 0, 0),392 F(806000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 1, 0, 0),393 { }394};395 396static struct clk_rcg2 ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src = {397 .cmd_rcgr = 0x8228,398 .mnd_width = 0,399 .hid_width = 5,400 .parent_map = ecpri_cc_parent_map_1,401 .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,402 .clkr.hw.init = &(const struct clk_init_data) {403 .name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src",404 .parent_data = ecpri_cc_parent_data_1,405 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),406 .ops = &clk_rcg2_shared_ops,407 },408};409 410static struct clk_rcg2 ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src = {411 .cmd_rcgr = 0x8240,412 .mnd_width = 0,413 .hid_width = 5,414 .parent_map = ecpri_cc_parent_map_1,415 .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,416 .clkr.hw.init = &(const struct clk_init_data) {417 .name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src",418 .parent_data = ecpri_cc_parent_data_1,419 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),420 .ops = &clk_rcg2_shared_ops,421 },422};423 424static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src = {425 .cmd_rcgr = 0x81e0,426 .mnd_width = 0,427 .hid_width = 5,428 .parent_map = ecpri_cc_parent_map_1,429 .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,430 .clkr.hw.init = &(const struct clk_init_data) {431 .name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src",432 .parent_data = ecpri_cc_parent_data_1,433 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),434 .ops = &clk_rcg2_shared_ops,435 },436};437 438static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src = {439 .cmd_rcgr = 0x81f8,440 .mnd_width = 0,441 .hid_width = 5,442 .parent_map = ecpri_cc_parent_map_1,443 .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,444 .clkr.hw.init = &(const struct clk_init_data) {445 .name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src",446 .parent_data = ecpri_cc_parent_data_1,447 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),448 .ops = &clk_rcg2_shared_ops,449 },450};451 452static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src = {453 .cmd_rcgr = 0x8210,454 .mnd_width = 0,455 .hid_width = 5,456 .parent_map = ecpri_cc_parent_map_1,457 .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,458 .clkr.hw.init = &(const struct clk_init_data) {459 .name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src",460 .parent_data = ecpri_cc_parent_data_1,461 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),462 .ops = &clk_rcg2_shared_ops,463 },464};465 466static const struct freq_tbl ftbl_ecpri_cc_mss_emac_clk_src[] = {467 F(403000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 2, 0, 0),468 { }469};470 471static struct clk_rcg2 ecpri_cc_mss_emac_clk_src = {472 .cmd_rcgr = 0xe00c,473 .mnd_width = 0,474 .hid_width = 5,475 .parent_map = ecpri_cc_parent_map_2,476 .freq_tbl = ftbl_ecpri_cc_mss_emac_clk_src,477 .clkr.hw.init = &(const struct clk_init_data) {478 .name = "ecpri_cc_mss_emac_clk_src",479 .parent_data = ecpri_cc_parent_data_2,480 .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),481 .ops = &clk_rcg2_shared_ops,482 },483};484 485static struct clk_regmap_div ecpri_cc_ecpri_fast_div2_clk_src = {486 .reg = 0x907c,487 .shift = 0,488 .width = 4,489 .clkr.hw.init = &(const struct clk_init_data) {490 .name = "ecpri_cc_ecpri_fast_div2_clk_src",491 .parent_hws = (const struct clk_hw*[]) {492 &ecpri_cc_ecpri_fast_clk_src.clkr.hw,493 },494 .num_parents = 1,495 .flags = CLK_SET_RATE_PARENT,496 .ops = &clk_regmap_div_ro_ops,497 },498};499 500static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src = {501 .reg = 0x8290,502 .shift = 0,503 .width = 4,504 .clkr.hw.init = &(const struct clk_init_data) {505 .name = "ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src",506 .parent_hws = (const struct clk_hw*[]) {507 &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,508 },509 .num_parents = 1,510 .flags = CLK_SET_RATE_PARENT,511 .ops = &clk_regmap_div_ro_ops,512 },513};514 515static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src = {516 .reg = 0x8294,517 .shift = 0,518 .width = 4,519 .clkr.hw.init = &(const struct clk_init_data) {520 .name = "ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src",521 .parent_hws = (const struct clk_hw*[]) {522 &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,523 },524 .num_parents = 1,525 .flags = CLK_SET_RATE_PARENT,526 .ops = &clk_regmap_div_ro_ops,527 },528};529 530static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src = {531 .reg = 0x8298,532 .shift = 0,533 .width = 4,534 .clkr.hw.init = &(const struct clk_init_data) {535 .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src",536 .parent_hws = (const struct clk_hw*[]) {537 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,538 },539 .num_parents = 1,540 .flags = CLK_SET_RATE_PARENT,541 .ops = &clk_regmap_div_ro_ops,542 },543};544 545static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src = {546 .reg = 0x829c,547 .shift = 0,548 .width = 4,549 .clkr.hw.init = &(const struct clk_init_data) {550 .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src",551 .parent_hws = (const struct clk_hw*[]) {552 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,553 },554 .num_parents = 1,555 .flags = CLK_SET_RATE_PARENT,556 .ops = &clk_regmap_div_ro_ops,557 },558};559 560static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src = {561 .reg = 0x8260,562 .shift = 0,563 .width = 4,564 .clkr.hw.init = &(const struct clk_init_data) {565 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src",566 .parent_hws = (const struct clk_hw*[]) {567 &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,568 },569 .num_parents = 1,570 .flags = CLK_SET_RATE_PARENT,571 .ops = &clk_regmap_div_ro_ops,572 },573};574 575static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src = {576 .reg = 0x8264,577 .shift = 0,578 .width = 4,579 .clkr.hw.init = &(const struct clk_init_data) {580 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src",581 .parent_hws = (const struct clk_hw*[]) {582 &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,583 },584 .num_parents = 1,585 .flags = CLK_SET_RATE_PARENT,586 .ops = &clk_regmap_div_ro_ops,587 },588};589 590static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src = {591 .reg = 0x8268,592 .shift = 0,593 .width = 4,594 .clkr.hw.init = &(const struct clk_init_data) {595 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src",596 .parent_hws = (const struct clk_hw*[]) {597 &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,598 },599 .num_parents = 1,600 .flags = CLK_SET_RATE_PARENT,601 .ops = &clk_regmap_div_ro_ops,602 },603};604 605static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src = {606 .reg = 0x826c,607 .shift = 0,608 .width = 4,609 .clkr.hw.init = &(const struct clk_init_data) {610 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src",611 .parent_hws = (const struct clk_hw*[]) {612 &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,613 },614 .num_parents = 1,615 .flags = CLK_SET_RATE_PARENT,616 .ops = &clk_regmap_div_ro_ops,617 },618};619 620static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src = {621 .reg = 0x8270,622 .shift = 0,623 .width = 4,624 .clkr.hw.init = &(const struct clk_init_data) {625 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src",626 .parent_hws = (const struct clk_hw*[]) {627 &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,628 },629 .num_parents = 1,630 .flags = CLK_SET_RATE_PARENT,631 .ops = &clk_regmap_div_ro_ops,632 },633};634 635static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src = {636 .reg = 0x8274,637 .shift = 0,638 .width = 4,639 .clkr.hw.init = &(const struct clk_init_data) {640 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src",641 .parent_hws = (const struct clk_hw*[]) {642 &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,643 },644 .num_parents = 1,645 .flags = CLK_SET_RATE_PARENT,646 .ops = &clk_regmap_div_ro_ops,647 },648};649 650static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src = {651 .reg = 0x8278,652 .shift = 0,653 .width = 4,654 .clkr.hw.init = &(const struct clk_init_data) {655 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src",656 .parent_hws = (const struct clk_hw*[]) {657 &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,658 },659 .num_parents = 1,660 .flags = CLK_SET_RATE_PARENT,661 .ops = &clk_regmap_div_ro_ops,662 },663};664 665static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src = {666 .reg = 0x827c,667 .shift = 0,668 .width = 4,669 .clkr.hw.init = &(const struct clk_init_data) {670 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src",671 .parent_hws = (const struct clk_hw*[]) {672 &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,673 },674 .num_parents = 1,675 .flags = CLK_SET_RATE_PARENT,676 .ops = &clk_regmap_div_ro_ops,677 },678};679 680static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src = {681 .reg = 0x8280,682 .shift = 0,683 .width = 4,684 .clkr.hw.init = &(const struct clk_init_data) {685 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src",686 .parent_hws = (const struct clk_hw*[]) {687 &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,688 },689 .num_parents = 1,690 .flags = CLK_SET_RATE_PARENT,691 .ops = &clk_regmap_div_ro_ops,692 },693};694 695static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src = {696 .reg = 0x8284,697 .shift = 0,698 .width = 4,699 .clkr.hw.init = &(const struct clk_init_data) {700 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src",701 .parent_hws = (const struct clk_hw*[]) {702 &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,703 },704 .num_parents = 1,705 .flags = CLK_SET_RATE_PARENT,706 .ops = &clk_regmap_div_ro_ops,707 },708};709 710static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src = {711 .reg = 0x8288,712 .shift = 0,713 .width = 4,714 .clkr.hw.init = &(const struct clk_init_data) {715 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src",716 .parent_hws = (const struct clk_hw*[]) {717 &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,718 },719 .num_parents = 1,720 .flags = CLK_SET_RATE_PARENT,721 .ops = &clk_regmap_div_ro_ops,722 },723};724 725static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src = {726 .reg = 0x828c,727 .shift = 0,728 .width = 4,729 .clkr.hw.init = &(const struct clk_init_data) {730 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src",731 .parent_hws = (const struct clk_hw*[]) {732 &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,733 },734 .num_parents = 1,735 .flags = CLK_SET_RATE_PARENT,736 .ops = &clk_regmap_div_ro_ops,737 },738};739 740static struct clk_branch ecpri_cc_ecpri_cg_clk = {741 .halt_reg = 0x900c,742 .halt_check = BRANCH_HALT,743 .clkr = {744 .enable_reg = 0x900c,745 .enable_mask = BIT(0),746 .hw.init = &(const struct clk_init_data) {747 .name = "ecpri_cc_ecpri_cg_clk",748 .parent_hws = (const struct clk_hw*[]) {749 &ecpri_cc_ecpri_clk_src.clkr.hw,750 },751 .num_parents = 1,752 .flags = CLK_SET_RATE_PARENT,753 .ops = &clk_branch2_ops,754 },755 },756};757 758static struct clk_branch ecpri_cc_ecpri_dma_clk = {759 .halt_reg = 0x902c,760 .halt_check = BRANCH_HALT,761 .clkr = {762 .enable_reg = 0x902c,763 .enable_mask = BIT(0),764 .hw.init = &(const struct clk_init_data) {765 .name = "ecpri_cc_ecpri_dma_clk",766 .parent_hws = (const struct clk_hw*[]) {767 &ecpri_cc_ecpri_dma_clk_src.clkr.hw,768 },769 .num_parents = 1,770 .flags = CLK_SET_RATE_PARENT,771 .ops = &clk_branch2_ops,772 },773 },774};775 776static struct clk_branch ecpri_cc_ecpri_dma_noc_clk = {777 .halt_reg = 0xf004,778 .halt_check = BRANCH_HALT,779 .clkr = {780 .enable_reg = 0xf004,781 .enable_mask = BIT(0),782 .hw.init = &(const struct clk_init_data) {783 .name = "ecpri_cc_ecpri_dma_noc_clk",784 .parent_hws = (const struct clk_hw*[]) {785 &ecpri_cc_ecpri_dma_clk_src.clkr.hw,786 },787 .num_parents = 1,788 .flags = CLK_SET_RATE_PARENT,789 .ops = &clk_branch2_ops,790 },791 },792};793 794static struct clk_branch ecpri_cc_ecpri_fast_clk = {795 .halt_reg = 0x9014,796 .halt_check = BRANCH_HALT,797 .clkr = {798 .enable_reg = 0x9014,799 .enable_mask = BIT(0),800 .hw.init = &(const struct clk_init_data) {801 .name = "ecpri_cc_ecpri_fast_clk",802 .parent_hws = (const struct clk_hw*[]) {803 &ecpri_cc_ecpri_fast_clk_src.clkr.hw,804 },805 .num_parents = 1,806 .flags = CLK_SET_RATE_PARENT,807 .ops = &clk_branch2_ops,808 },809 },810};811 812static struct clk_branch ecpri_cc_ecpri_fast_div2_clk = {813 .halt_reg = 0x901c,814 .halt_check = BRANCH_HALT,815 .clkr = {816 .enable_reg = 0x901c,817 .enable_mask = BIT(0),818 .hw.init = &(const struct clk_init_data) {819 .name = "ecpri_cc_ecpri_fast_div2_clk",820 .parent_hws = (const struct clk_hw*[]) {821 &ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,822 },823 .num_parents = 1,824 .flags = CLK_SET_RATE_PARENT,825 .ops = &clk_branch2_ops,826 },827 },828};829 830static struct clk_branch ecpri_cc_ecpri_fast_div2_noc_clk = {831 .halt_reg = 0xf008,832 .halt_check = BRANCH_HALT,833 .clkr = {834 .enable_reg = 0xf008,835 .enable_mask = BIT(0),836 .hw.init = &(const struct clk_init_data) {837 .name = "ecpri_cc_ecpri_fast_div2_noc_clk",838 .parent_hws = (const struct clk_hw*[]) {839 &ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,840 },841 .num_parents = 1,842 .flags = CLK_SET_RATE_PARENT,843 .ops = &clk_branch2_ops,844 },845 },846};847 848static struct clk_branch ecpri_cc_ecpri_fr_clk = {849 .halt_reg = 0x9004,850 .halt_check = BRANCH_HALT,851 .clkr = {852 .enable_reg = 0x9004,853 .enable_mask = BIT(0),854 .hw.init = &(const struct clk_init_data) {855 .name = "ecpri_cc_ecpri_fr_clk",856 .parent_hws = (const struct clk_hw*[]) {857 &ecpri_cc_ecpri_clk_src.clkr.hw,858 },859 .num_parents = 1,860 .flags = CLK_SET_RATE_PARENT,861 .ops = &clk_branch2_ops,862 },863 },864};865 866static struct clk_branch ecpri_cc_ecpri_oran_div2_clk = {867 .halt_reg = 0x9024,868 .halt_check = BRANCH_HALT,869 .clkr = {870 .enable_reg = 0x9024,871 .enable_mask = BIT(0),872 .hw.init = &(const struct clk_init_data) {873 .name = "ecpri_cc_ecpri_oran_div2_clk",874 .parent_hws = (const struct clk_hw*[]) {875 &ecpri_cc_ecpri_oran_clk_src.clkr.hw,876 },877 .num_parents = 1,878 .flags = CLK_SET_RATE_PARENT,879 .ops = &clk_branch2_ops,880 },881 },882};883 884static struct clk_branch ecpri_cc_eth_100g_c2c0_udp_fifo_clk = {885 .halt_reg = 0x80cc,886 .halt_check = BRANCH_HALT,887 .clkr = {888 .enable_reg = 0x80cc,889 .enable_mask = BIT(0),890 .hw.init = &(const struct clk_init_data) {891 .name = "ecpri_cc_eth_100g_c2c0_udp_fifo_clk",892 .parent_hws = (const struct clk_hw*[]) {893 &ecpri_cc_ecpri_clk_src.clkr.hw,894 },895 .num_parents = 1,896 .flags = CLK_SET_RATE_PARENT,897 .ops = &clk_branch2_ops,898 },899 },900};901 902static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = {903 .halt_reg = 0x80d0,904 .halt_check = BRANCH_HALT,905 .clkr = {906 .enable_reg = 0x80d0,907 .enable_mask = BIT(0),908 .hw.init = &(const struct clk_init_data) {909 .name = "ecpri_cc_eth_100g_c2c1_udp_fifo_clk",910 .parent_hws = (const struct clk_hw*[]) {911 &ecpri_cc_ecpri_clk_src.clkr.hw,912 },913 .num_parents = 1,914 .flags = CLK_SET_RATE_PARENT,915 .ops = &clk_branch2_ops,916 },917 },918};919 920static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {921 .mem_enable_reg = 0x8410,922 .mem_ack_reg = 0x8424,923 .mem_enable_ack_mask = BIT(0),924 .branch = {925 .halt_reg = 0x80b4,926 .halt_check = BRANCH_HALT,927 .clkr = {928 .enable_reg = 0x80b4,929 .enable_mask = BIT(0),930 .hw.init = &(const struct clk_init_data) {931 .name = "ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk",932 .parent_hws = (const struct clk_hw*[]) {933 &ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr.hw,934 },935 .num_parents = 1,936 .flags = CLK_SET_RATE_PARENT,937 .ops = &clk_branch2_mem_ops,938 },939 },940 },941};942 943static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {944 .mem_enable_reg = 0x8410,945 .mem_ack_reg = 0x8424,946 .mem_enable_ack_mask = BIT(1),947 .branch = {948 .halt_reg = 0x80bc,949 .halt_check = BRANCH_HALT,950 .clkr = {951 .enable_reg = 0x80bc,952 .enable_mask = BIT(0),953 .hw.init = &(const struct clk_init_data) {954 .name = "ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk",955 .parent_hws = (const struct clk_hw*[]) {956 &ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr.hw,957 },958 .num_parents = 1,959 .flags = CLK_SET_RATE_PARENT,960 .ops = &clk_branch2_mem_ops,961 },962 },963 },964};965 966static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {967 .mem_enable_reg = 0x8410,968 .mem_ack_reg = 0x8424,969 .mem_enable_ack_mask = BIT(4),970 .branch = {971 .halt_reg = 0x80ac,972 .halt_check = BRANCH_HALT,973 .clkr = {974 .enable_reg = 0x80ac,975 .enable_mask = BIT(0),976 .hw.init = &(const struct clk_init_data) {977 .name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk",978 .parent_hws = (const struct clk_hw*[]) {979 &ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr.hw,980 },981 .num_parents = 1,982 .flags = CLK_SET_RATE_PARENT,983 .ops = &clk_branch2_mem_ops,984 },985 },986 },987};988 989static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {990 .mem_enable_reg = 0x8414,991 .mem_ack_reg = 0x8428,992 .mem_enable_ack_mask = BIT(0),993 .branch = {994 .halt_reg = 0x80d8,995 .halt_check = BRANCH_HALT,996 .clkr = {997 .enable_reg = 0x80d8,998 .enable_mask = BIT(0),999 .hw.init = &(const struct clk_init_data) {1000 .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk",1001 .parent_hws = (const struct clk_hw*[]) {1002 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr.hw,1003 },1004 .num_parents = 1,1005 .flags = CLK_SET_RATE_PARENT,1006 .ops = &clk_branch2_mem_ops,1007 },1008 },1009 },1010};1011 1012static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {1013 .mem_enable_reg = 0x8414,1014 .mem_ack_reg = 0x8428,1015 .mem_enable_ack_mask = BIT(1),1016 .branch = {1017 .halt_reg = 0x80e0,1018 .halt_check = BRANCH_HALT,1019 .clkr = {1020 .enable_reg = 0x80e0,1021 .enable_mask = BIT(0),1022 .hw.init = &(const struct clk_init_data) {1023 .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk",1024 .parent_hws = (const struct clk_hw*[]) {1025 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr.hw,1026 },1027 .num_parents = 1,1028 .flags = CLK_SET_RATE_PARENT,1029 .ops = &clk_branch2_mem_ops,1030 },1031 },1032 },1033};1034 1035static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = {1036 .halt_reg = 0x80f0,1037 .halt_check = BRANCH_HALT,1038 .clkr = {1039 .enable_reg = 0x80f0,1040 .enable_mask = BIT(0),1041 .hw.init = &(const struct clk_init_data) {1042 .name = "ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk",1043 .parent_hws = (const struct clk_hw*[]) {1044 &ecpri_cc_ecpri_clk_src.clkr.hw,1045 },1046 .num_parents = 1,1047 .flags = CLK_SET_RATE_PARENT,1048 .ops = &clk_branch2_ops,1049 },1050 },1051};1052 1053static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {1054 .mem_enable_reg = 0x8404,1055 .mem_ack_reg = 0x8418,1056 .mem_enable_ack_mask = BIT(0),1057 .branch = {1058 .halt_reg = 0x800c,1059 .halt_check = BRANCH_HALT,1060 .clkr = {1061 .enable_reg = 0x800c,1062 .enable_mask = BIT(0),1063 .hw.init = &(const struct clk_init_data) {1064 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_clk",1065 .parent_hws = (const struct clk_hw*[]) {1066 &ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr.hw,1067 },1068 .num_parents = 1,1069 .flags = CLK_SET_RATE_PARENT,1070 .ops = &clk_branch2_mem_ops,1071 },1072 },1073 },1074};1075 1076static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {1077 .mem_enable_reg = 0x8404,1078 .mem_ack_reg = 0x8418,1079 .mem_enable_ack_mask = BIT(1),1080 .branch = {1081 .halt_reg = 0x8014,1082 .halt_check = BRANCH_HALT,1083 .clkr = {1084 .enable_reg = 0x8014,1085 .enable_mask = BIT(0),1086 .hw.init = &(const struct clk_init_data) {1087 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_clk",1088 .parent_hws = (const struct clk_hw*[]) {1089 &ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr.hw,1090 },1091 .num_parents = 1,1092 .flags = CLK_SET_RATE_PARENT,1093 .ops = &clk_branch2_mem_ops,1094 },1095 },1096 },1097};1098 1099static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {1100 .mem_enable_reg = 0x8404,1101 .mem_ack_reg = 0x8418,1102 .mem_enable_ack_mask = BIT(2),1103 .branch = {1104 .halt_reg = 0x801c,1105 .halt_check = BRANCH_HALT,1106 .clkr = {1107 .enable_reg = 0x801c,1108 .enable_mask = BIT(0),1109 .hw.init = &(const struct clk_init_data) {1110 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_clk",1111 .parent_hws = (const struct clk_hw*[]) {1112 &ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr.hw,1113 },1114 .num_parents = 1,1115 .flags = CLK_SET_RATE_PARENT,1116 .ops = &clk_branch2_mem_ops,1117 },1118 },1119 },1120};1121 1122static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {1123 .mem_enable_reg = 0x8404,1124 .mem_ack_reg = 0x8418,1125 .mem_enable_ack_mask = BIT(3),1126 .branch = {1127 .halt_reg = 0x8024,1128 .halt_check = BRANCH_HALT,1129 .clkr = {1130 .enable_reg = 0x8024,1131 .enable_mask = BIT(0),1132 .hw.init = &(const struct clk_init_data) {1133 .name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_clk",1134 .parent_hws = (const struct clk_hw*[]) {1135 &ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr.hw,1136 },1137 .num_parents = 1,1138 .flags = CLK_SET_RATE_PARENT,1139 .ops = &clk_branch2_mem_ops,1140 },1141 },1142 },1143};1144 1145static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = {1146 .halt_reg = 0x8034,1147 .halt_check = BRANCH_HALT,1148 .clkr = {1149 .enable_reg = 0x8034,1150 .enable_mask = BIT(0),1151 .hw.init = &(const struct clk_init_data) {1152 .name = "ecpri_cc_eth_100g_fh_0_udp_fifo_clk",1153 .parent_hws = (const struct clk_hw*[]) {1154 &ecpri_cc_ecpri_clk_src.clkr.hw,1155 },1156 .num_parents = 1,1157 .flags = CLK_SET_RATE_PARENT,1158 .ops = &clk_branch2_ops,1159 },1160 },1161};1162 1163static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {1164 .mem_enable_reg = 0x8408,1165 .mem_ack_reg = 0x841c,1166 .mem_enable_ack_mask = BIT(0),1167 .branch = {1168 .halt_reg = 0x8044,1169 .halt_check = BRANCH_HALT,1170 .clkr = {1171 .enable_reg = 0x8044,1172 .enable_mask = BIT(0),1173 .hw.init = &(const struct clk_init_data) {1174 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_clk",1175 .parent_hws = (const struct clk_hw*[]) {1176 &ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr.hw,1177 },1178 .num_parents = 1,1179 .flags = CLK_SET_RATE_PARENT,1180 .ops = &clk_branch2_mem_ops,1181 },1182 },1183 },1184};1185 1186static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {1187 .mem_enable_reg = 0x8408,1188 .mem_ack_reg = 0x841c,1189 .mem_enable_ack_mask = BIT(1),1190 .branch = {1191 .halt_reg = 0x804c,1192 .halt_check = BRANCH_HALT,1193 .clkr = {1194 .enable_reg = 0x804c,1195 .enable_mask = BIT(0),1196 .hw.init = &(const struct clk_init_data) {1197 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_clk",1198 .parent_hws = (const struct clk_hw*[]) {1199 &ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr.hw,1200 },1201 .num_parents = 1,1202 .flags = CLK_SET_RATE_PARENT,1203 .ops = &clk_branch2_mem_ops,1204 },1205 },1206 },1207};1208 1209static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {1210 .mem_enable_reg = 0x8408,1211 .mem_ack_reg = 0x841c,1212 .mem_enable_ack_mask = BIT(2),1213 .branch = {1214 .halt_reg = 0x8054,1215 .halt_check = BRANCH_HALT,1216 .clkr = {1217 .enable_reg = 0x8054,1218 .enable_mask = BIT(0),1219 .hw.init = &(const struct clk_init_data) {1220 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_clk",1221 .parent_hws = (const struct clk_hw*[]) {1222 &ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr.hw,1223 },1224 .num_parents = 1,1225 .flags = CLK_SET_RATE_PARENT,1226 .ops = &clk_branch2_mem_ops,1227 },1228 },1229 },1230};1231 1232static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {1233 .mem_enable_reg = 0x8408,1234 .mem_ack_reg = 0x841c,1235 .mem_enable_ack_mask = BIT(3),1236 .branch = {1237 .halt_reg = 0x805c,1238 .halt_check = BRANCH_HALT,1239 .clkr = {1240 .enable_reg = 0x805c,1241 .enable_mask = BIT(0),1242 .hw.init = &(const struct clk_init_data) {1243 .name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_clk",1244 .parent_hws = (const struct clk_hw*[]) {1245 &ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr.hw,1246 },1247 .num_parents = 1,1248 .flags = CLK_SET_RATE_PARENT,1249 .ops = &clk_branch2_mem_ops,1250 },1251 },1252 },1253};1254 1255static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = {1256 .halt_reg = 0x806c,1257 .halt_check = BRANCH_HALT,1258 .clkr = {1259 .enable_reg = 0x806c,1260 .enable_mask = BIT(0),1261 .hw.init = &(const struct clk_init_data) {1262 .name = "ecpri_cc_eth_100g_fh_1_udp_fifo_clk",1263 .parent_hws = (const struct clk_hw*[]) {1264 &ecpri_cc_ecpri_clk_src.clkr.hw,1265 },1266 .num_parents = 1,1267 .flags = CLK_SET_RATE_PARENT,1268 .ops = &clk_branch2_ops,1269 },1270 },1271};1272 1273static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {1274 .mem_enable_reg = 0x840c,1275 .mem_ack_reg = 0x8420,1276 .mem_enable_ack_mask = BIT(0),1277 .branch = {1278 .halt_reg = 0x807c,1279 .halt_check = BRANCH_HALT,1280 .clkr = {1281 .enable_reg = 0x807c,1282 .enable_mask = BIT(0),1283 .hw.init = &(const struct clk_init_data) {1284 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_clk",1285 .parent_hws = (const struct clk_hw*[]) {1286 &ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr.hw,1287 },1288 .num_parents = 1,1289 .flags = CLK_SET_RATE_PARENT,1290 .ops = &clk_branch2_mem_ops,1291 },1292 },1293 },1294};1295 1296static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {1297 .mem_enable_reg = 0x840c,1298 .mem_ack_reg = 0x8420,1299 .mem_enable_ack_mask = BIT(1),1300 .branch = {1301 .halt_reg = 0x8084,1302 .halt_check = BRANCH_HALT,1303 .clkr = {1304 .enable_reg = 0x8084,1305 .enable_mask = BIT(0),1306 .hw.init = &(const struct clk_init_data) {1307 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_clk",1308 .parent_hws = (const struct clk_hw*[]) {1309 &ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr.hw,1310 },1311 .num_parents = 1,1312 .flags = CLK_SET_RATE_PARENT,1313 .ops = &clk_branch2_mem_ops,1314 },1315 },1316 },1317};1318 1319static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {1320 .mem_enable_reg = 0x840c,1321 .mem_ack_reg = 0x8420,1322 .mem_enable_ack_mask = BIT(2),1323 .branch = {1324 .halt_reg = 0x808c,1325 .halt_check = BRANCH_HALT,1326 .clkr = {1327 .enable_reg = 0x808c,1328 .enable_mask = BIT(0),1329 .hw.init = &(const struct clk_init_data) {1330 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_clk",1331 .parent_hws = (const struct clk_hw*[]) {1332 &ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr.hw,1333 },1334 .num_parents = 1,1335 .flags = CLK_SET_RATE_PARENT,1336 .ops = &clk_branch2_mem_ops,1337 },1338 },1339 },1340};1341 1342static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {1343 .mem_enable_reg = 0x840c,1344 .mem_ack_reg = 0x8420,1345 .mem_enable_ack_mask = BIT(3),1346 .branch = {1347 .halt_reg = 0x8094,1348 .halt_check = BRANCH_HALT,1349 .clkr = {1350 .enable_reg = 0x8094,1351 .enable_mask = BIT(0),1352 .hw.init = &(const struct clk_init_data) {1353 .name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_clk",1354 .parent_hws = (const struct clk_hw*[]) {1355 &ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr.hw,1356 },1357 .num_parents = 1,1358 .flags = CLK_SET_RATE_PARENT,1359 .ops = &clk_branch2_mem_ops,1360 },1361 },1362 },1363};1364 1365static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = {1366 .halt_reg = 0x80a4,1367 .halt_check = BRANCH_HALT,1368 .clkr = {1369 .enable_reg = 0x80a4,1370 .enable_mask = BIT(0),1371 .hw.init = &(const struct clk_init_data) {1372 .name = "ecpri_cc_eth_100g_fh_2_udp_fifo_clk",1373 .parent_hws = (const struct clk_hw*[]) {1374 &ecpri_cc_ecpri_clk_src.clkr.hw,1375 },1376 .num_parents = 1,1377 .flags = CLK_SET_RATE_PARENT,1378 .ops = &clk_branch2_ops,1379 },1380 },1381};1382 1383static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {1384 .mem_enable_reg = 0x8404,1385 .mem_ack_reg = 0x8418,1386 .mem_enable_ack_mask = BIT(4),1387 .branch = {1388 .halt_reg = 0x8004,1389 .halt_check = BRANCH_HALT,1390 .clkr = {1391 .enable_reg = 0x8004,1392 .enable_mask = BIT(0),1393 .hw.init = &(const struct clk_init_data) {1394 .name = "ecpri_cc_eth_100g_fh_macsec_0_clk",1395 .parent_hws = (const struct clk_hw*[]) {1396 &ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr.hw,1397 },1398 .num_parents = 1,1399 .flags = CLK_SET_RATE_PARENT,1400 .ops = &clk_branch2_mem_ops,1401 },1402 },1403 },1404};1405 1406static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {1407 .mem_enable_reg = 0x8408,1408 .mem_ack_reg = 0x841c,1409 .mem_enable_ack_mask = BIT(4),1410 .branch = {1411 .halt_reg = 0x803c,1412 .halt_check = BRANCH_HALT,1413 .clkr = {1414 .enable_reg = 0x803c,1415 .enable_mask = BIT(0),1416 .hw.init = &(const struct clk_init_data) {1417 .name = "ecpri_cc_eth_100g_fh_macsec_1_clk",1418 .parent_hws = (const struct clk_hw*[]) {1419 &ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr.hw,1420 },1421 .num_parents = 1,1422 .flags = CLK_SET_RATE_PARENT,1423 .ops = &clk_branch2_mem_ops,1424 },1425 },1426 },1427};1428 1429static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {1430 .mem_enable_reg = 0x840c,1431 .mem_ack_reg = 0x8420,1432 .mem_enable_ack_mask = BIT(4),1433 .branch = {1434 .halt_reg = 0x8074,1435 .halt_check = BRANCH_HALT,1436 .clkr = {1437 .enable_reg = 0x8074,1438 .enable_mask = BIT(0),1439 .hw.init = &(const struct clk_init_data) {1440 .name = "ecpri_cc_eth_100g_fh_macsec_2_clk",1441 .parent_hws = (const struct clk_hw*[]) {1442 &ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr.hw,1443 },1444 .num_parents = 1,1445 .flags = CLK_SET_RATE_PARENT,1446 .ops = &clk_branch2_mem_ops,1447 },1448 },1449 },1450};1451 1452static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {1453 .mem_enable_reg = 0x8410,1454 .mem_ack_reg = 0x8424,1455 .mem_enable_ack_mask = BIT(5),1456 .branch = {1457 .halt_reg = 0x80c4,1458 .halt_check = BRANCH_HALT,1459 .clkr = {1460 .enable_reg = 0x80c4,1461 .enable_mask = BIT(0),1462 .hw.init = &(const struct clk_init_data) {1463 .name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk",1464 .parent_hws = (const struct clk_hw*[]) {1465 &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr.hw,1466 },1467 .num_parents = 1,1468 .flags = CLK_SET_RATE_PARENT,1469 .ops = &clk_branch2_mem_ops,1470 },1471 },1472 },1473};1474 1475static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {1476 .mem_enable_reg = 0x8414,1477 .mem_ack_reg = 0x8428,1478 .mem_enable_ack_mask = BIT(5),1479 .branch = {1480 .halt_reg = 0x80e8,1481 .halt_check = BRANCH_HALT,1482 .clkr = {1483 .enable_reg = 0x80e8,1484 .enable_mask = BIT(0),1485 .hw.init = &(const struct clk_init_data) {1486 .name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk",1487 .parent_hws = (const struct clk_hw*[]) {1488 &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr.hw,1489 },1490 .num_parents = 1,1491 .flags = CLK_SET_RATE_PARENT,1492 .ops = &clk_branch2_mem_ops,1493 },1494 },1495 },1496};1497 1498static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {1499 .mem_enable_reg = 0x8404,1500 .mem_ack_reg = 0x8418,1501 .mem_enable_ack_mask = BIT(5),1502 .branch = {1503 .halt_reg = 0x802c,1504 .halt_check = BRANCH_HALT,1505 .clkr = {1506 .enable_reg = 0x802c,1507 .enable_mask = BIT(0),1508 .hw.init = &(const struct clk_init_data) {1509 .name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk",1510 .parent_hws = (const struct clk_hw*[]) {1511 &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr.hw,1512 },1513 .num_parents = 1,1514 .flags = CLK_SET_RATE_PARENT,1515 .ops = &clk_branch2_mem_ops,1516 },1517 },1518 },1519};1520 1521static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {1522 .mem_enable_reg = 0x8408,1523 .mem_ack_reg = 0x841c,1524 .mem_enable_ack_mask = BIT(5),1525 .branch = {1526 .halt_reg = 0x8064,1527 .halt_check = BRANCH_HALT,1528 .clkr = {1529 .enable_reg = 0x8064,1530 .enable_mask = BIT(0),1531 .hw.init = &(const struct clk_init_data) {1532 .name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk",1533 .parent_hws = (const struct clk_hw*[]) {1534 &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr.hw,1535 },1536 .num_parents = 1,1537 .flags = CLK_SET_RATE_PARENT,1538 .ops = &clk_branch2_mem_ops,1539 },1540 },1541 },1542};1543 1544static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {1545 .mem_enable_reg = 0x840c,1546 .mem_ack_reg = 0x8420,1547 .mem_enable_ack_mask = BIT(5),1548 .branch = {1549 .halt_reg = 0x809c,1550 .halt_check = BRANCH_HALT,1551 .clkr = {1552 .enable_reg = 0x809c,1553 .enable_mask = BIT(0),1554 .hw.init = &(const struct clk_init_data) {1555 .name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk",1556 .parent_hws = (const struct clk_hw*[]) {1557 &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr.hw,1558 },1559 .num_parents = 1,1560 .flags = CLK_SET_RATE_PARENT,1561 .ops = &clk_branch2_mem_ops,1562 },1563 },1564 },1565};1566 1567static struct clk_branch ecpri_cc_eth_dbg_nfapi_axi_clk = {1568 .halt_reg = 0x80f4,1569 .halt_check = BRANCH_HALT,1570 .clkr = {1571 .enable_reg = 0x80f4,1572 .enable_mask = BIT(0),1573 .hw.init = &(const struct clk_init_data) {1574 .name = "ecpri_cc_eth_dbg_nfapi_axi_clk",1575 .parent_hws = (const struct clk_hw*[]) {1576 &ecpri_cc_ecpri_dma_clk_src.clkr.hw,1577 },1578 .num_parents = 1,1579 .flags = CLK_SET_RATE_PARENT,1580 .ops = &clk_branch2_ops,1581 },1582 },1583};1584 1585static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = {1586 .halt_reg = 0x80fc,1587 .halt_check = BRANCH_HALT,1588 .clkr = {1589 .enable_reg = 0x80fc,1590 .enable_mask = BIT(0),1591 .hw.init = &(const struct clk_init_data) {1592 .name = "ecpri_cc_eth_dbg_noc_axi_clk",1593 .parent_hws = (const struct clk_hw*[]) {1594 &ecpri_cc_mss_emac_clk_src.clkr.hw,1595 },1596 .num_parents = 1,1597 .flags = CLK_SET_RATE_PARENT,1598 .ops = &clk_branch2_ops,1599 },1600 },1601};1602 1603static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {1604 .mem_enable_reg = 0x8404,1605 .mem_ack_reg = 0x8418,1606 .mem_enable_ack_mask = BIT(6),1607 .branch = {1608 .halt_reg = 0xd140,1609 .halt_check = BRANCH_HALT,1610 .clkr = {1611 .enable_reg = 0xd140,1612 .enable_mask = BIT(0),1613 .hw.init = &(const struct clk_init_data) {1614 .name = "ecpri_cc_eth_phy_0_ock_sram_clk",1615 .ops = &clk_branch2_mem_ops,1616 },1617 },1618 },1619};1620 1621static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {1622 .mem_enable_reg = 0x8408,1623 .mem_ack_reg = 0x841C,1624 .mem_enable_ack_mask = BIT(6),1625 .branch = {1626 .halt_reg = 0xd148,1627 .halt_check = BRANCH_HALT,1628 .clkr = {1629 .enable_reg = 0xd148,1630 .enable_mask = BIT(0),1631 .hw.init = &(const struct clk_init_data) {1632 .name = "ecpri_cc_eth_phy_1_ock_sram_clk",1633 .ops = &clk_branch2_mem_ops,1634 },1635 },1636 },1637};1638 1639static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {1640 .mem_enable_reg = 0x840c,1641 .mem_ack_reg = 0x8420,1642 .mem_enable_ack_mask = BIT(6),1643 .branch = {1644 .halt_reg = 0xd150,1645 .halt_check = BRANCH_HALT,1646 .clkr = {1647 .enable_reg = 0xd150,1648 .enable_mask = BIT(0),1649 .hw.init = &(const struct clk_init_data) {1650 .name = "ecpri_cc_eth_phy_2_ock_sram_clk",1651 .ops = &clk_branch2_mem_ops,1652 },1653 },1654 },1655};1656 1657static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {1658 .mem_enable_reg = 0x8410,1659 .mem_ack_reg = 0x8424,1660 .mem_enable_ack_mask = BIT(6),1661 .branch = {1662 .halt_reg = 0xd158,1663 .halt_check = BRANCH_HALT,1664 .clkr = {1665 .enable_reg = 0xd158,1666 .enable_mask = BIT(0),1667 .hw.init = &(const struct clk_init_data) {1668 .name = "ecpri_cc_eth_phy_3_ock_sram_clk",1669 .ops = &clk_branch2_mem_ops,1670 },1671 },1672 },1673};1674 1675static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {1676 .mem_enable_reg = 0x8414,1677 .mem_ack_reg = 0x8428,1678 .mem_enable_ack_mask = BIT(6),1679 .branch = {1680 .halt_reg = 0xd160,1681 .halt_check = BRANCH_HALT,1682 .clkr = {1683 .enable_reg = 0xd160,1684 .enable_mask = BIT(0),1685 .hw.init = &(const struct clk_init_data) {1686 .name = "ecpri_cc_eth_phy_4_ock_sram_clk",1687 .ops = &clk_branch2_mem_ops,1688 },1689 },1690 },1691};1692 1693static struct clk_branch ecpri_cc_mss_emac_clk = {1694 .halt_reg = 0xe008,1695 .halt_check = BRANCH_HALT,1696 .clkr = {1697 .enable_reg = 0xe008,1698 .enable_mask = BIT(0),1699 .hw.init = &(const struct clk_init_data) {1700 .name = "ecpri_cc_mss_emac_clk",1701 .parent_hws = (const struct clk_hw*[]) {1702 &ecpri_cc_mss_emac_clk_src.clkr.hw,1703 },1704 .num_parents = 1,1705 .flags = CLK_SET_RATE_PARENT,1706 .ops = &clk_branch2_ops,1707 },1708 },1709};1710 1711static struct clk_branch ecpri_cc_mss_oran_clk = {1712 .halt_reg = 0xe004,1713 .halt_check = BRANCH_HALT,1714 .clkr = {1715 .enable_reg = 0xe004,1716 .enable_mask = BIT(0),1717 .hw.init = &(const struct clk_init_data) {1718 .name = "ecpri_cc_mss_oran_clk",1719 .parent_hws = (const struct clk_hw*[]) {1720 &ecpri_cc_ecpri_oran_clk_src.clkr.hw,1721 },1722 .num_parents = 1,1723 .flags = CLK_SET_RATE_PARENT,1724 .ops = &clk_branch2_ops,1725 },1726 },1727};1728 1729static struct clk_branch ecpri_cc_phy0_lane0_rx_clk = {1730 .halt_reg = 0xd000,1731 .halt_check = BRANCH_HALT,1732 .clkr = {1733 .enable_reg = 0xd000,1734 .enable_mask = BIT(0),1735 .hw.init = &(const struct clk_init_data) {1736 .name = "ecpri_cc_phy0_lane0_rx_clk",1737 .ops = &clk_branch2_ops,1738 },1739 },1740};1741 1742static struct clk_branch ecpri_cc_phy0_lane0_tx_clk = {1743 .halt_reg = 0xd050,1744 .halt_check = BRANCH_HALT,1745 .clkr = {1746 .enable_reg = 0xd050,1747 .enable_mask = BIT(0),1748 .hw.init = &(const struct clk_init_data) {1749 .name = "ecpri_cc_phy0_lane0_tx_clk",1750 .ops = &clk_branch2_ops,1751 },1752 },1753};1754 1755static struct clk_branch ecpri_cc_phy0_lane1_rx_clk = {1756 .halt_reg = 0xd004,1757 .halt_check = BRANCH_HALT,1758 .clkr = {1759 .enable_reg = 0xd004,1760 .enable_mask = BIT(0),1761 .hw.init = &(const struct clk_init_data) {1762 .name = "ecpri_cc_phy0_lane1_rx_clk",1763 .ops = &clk_branch2_ops,1764 },1765 },1766};1767 1768static struct clk_branch ecpri_cc_phy0_lane1_tx_clk = {1769 .halt_reg = 0xd054,1770 .halt_check = BRANCH_HALT,1771 .clkr = {1772 .enable_reg = 0xd054,1773 .enable_mask = BIT(0),1774 .hw.init = &(const struct clk_init_data) {1775 .name = "ecpri_cc_phy0_lane1_tx_clk",1776 .ops = &clk_branch2_ops,1777 },1778 },1779};1780 1781static struct clk_branch ecpri_cc_phy0_lane2_rx_clk = {1782 .halt_reg = 0xd008,1783 .halt_check = BRANCH_HALT,1784 .clkr = {1785 .enable_reg = 0xd008,1786 .enable_mask = BIT(0),1787 .hw.init = &(const struct clk_init_data) {1788 .name = "ecpri_cc_phy0_lane2_rx_clk",1789 .ops = &clk_branch2_ops,1790 },1791 },1792};1793 1794static struct clk_branch ecpri_cc_phy0_lane2_tx_clk = {1795 .halt_reg = 0xd058,1796 .halt_check = BRANCH_HALT,1797 .clkr = {1798 .enable_reg = 0xd058,1799 .enable_mask = BIT(0),1800 .hw.init = &(const struct clk_init_data) {1801 .name = "ecpri_cc_phy0_lane2_tx_clk",1802 .ops = &clk_branch2_ops,1803 },1804 },1805};1806 1807static struct clk_branch ecpri_cc_phy0_lane3_rx_clk = {1808 .halt_reg = 0xd00c,1809 .halt_check = BRANCH_HALT,1810 .clkr = {1811 .enable_reg = 0xd00c,1812 .enable_mask = BIT(0),1813 .hw.init = &(const struct clk_init_data) {1814 .name = "ecpri_cc_phy0_lane3_rx_clk",1815 .ops = &clk_branch2_ops,1816 },1817 },1818};1819 1820static struct clk_branch ecpri_cc_phy0_lane3_tx_clk = {1821 .halt_reg = 0xd05c,1822 .halt_check = BRANCH_HALT,1823 .clkr = {1824 .enable_reg = 0xd05c,1825 .enable_mask = BIT(0),1826 .hw.init = &(const struct clk_init_data) {1827 .name = "ecpri_cc_phy0_lane3_tx_clk",1828 .ops = &clk_branch2_ops,1829 },1830 },1831};1832 1833static struct clk_branch ecpri_cc_phy1_lane0_rx_clk = {1834 .halt_reg = 0xd010,1835 .halt_check = BRANCH_HALT,1836 .clkr = {1837 .enable_reg = 0xd010,1838 .enable_mask = BIT(0),1839 .hw.init = &(const struct clk_init_data) {1840 .name = "ecpri_cc_phy1_lane0_rx_clk",1841 .ops = &clk_branch2_ops,1842 },1843 },1844};1845 1846static struct clk_branch ecpri_cc_phy1_lane0_tx_clk = {1847 .halt_reg = 0xd060,1848 .halt_check = BRANCH_HALT,1849 .clkr = {1850 .enable_reg = 0xd060,1851 .enable_mask = BIT(0),1852 .hw.init = &(const struct clk_init_data) {1853 .name = "ecpri_cc_phy1_lane0_tx_clk",1854 .ops = &clk_branch2_ops,1855 },1856 },1857};1858 1859static struct clk_branch ecpri_cc_phy1_lane1_rx_clk = {1860 .halt_reg = 0xd014,1861 .halt_check = BRANCH_HALT,1862 .clkr = {1863 .enable_reg = 0xd014,1864 .enable_mask = BIT(0),1865 .hw.init = &(const struct clk_init_data) {1866 .name = "ecpri_cc_phy1_lane1_rx_clk",1867 .ops = &clk_branch2_ops,1868 },1869 },1870};1871 1872static struct clk_branch ecpri_cc_phy1_lane1_tx_clk = {1873 .halt_reg = 0xd064,1874 .halt_check = BRANCH_HALT,1875 .clkr = {1876 .enable_reg = 0xd064,1877 .enable_mask = BIT(0),1878 .hw.init = &(const struct clk_init_data) {1879 .name = "ecpri_cc_phy1_lane1_tx_clk",1880 .ops = &clk_branch2_ops,1881 },1882 },1883};1884 1885static struct clk_branch ecpri_cc_phy1_lane2_rx_clk = {1886 .halt_reg = 0xd018,1887 .halt_check = BRANCH_HALT,1888 .clkr = {1889 .enable_reg = 0xd018,1890 .enable_mask = BIT(0),1891 .hw.init = &(const struct clk_init_data) {1892 .name = "ecpri_cc_phy1_lane2_rx_clk",1893 .ops = &clk_branch2_ops,1894 },1895 },1896};1897 1898static struct clk_branch ecpri_cc_phy1_lane2_tx_clk = {1899 .halt_reg = 0xd068,1900 .halt_check = BRANCH_HALT,1901 .clkr = {1902 .enable_reg = 0xd068,1903 .enable_mask = BIT(0),1904 .hw.init = &(const struct clk_init_data) {1905 .name = "ecpri_cc_phy1_lane2_tx_clk",1906 .ops = &clk_branch2_ops,1907 },1908 },1909};1910 1911static struct clk_branch ecpri_cc_phy1_lane3_rx_clk = {1912 .halt_reg = 0xd01c,1913 .halt_check = BRANCH_HALT,1914 .clkr = {1915 .enable_reg = 0xd01c,1916 .enable_mask = BIT(0),1917 .hw.init = &(const struct clk_init_data) {1918 .name = "ecpri_cc_phy1_lane3_rx_clk",1919 .ops = &clk_branch2_ops,1920 },1921 },1922};1923 1924static struct clk_branch ecpri_cc_phy1_lane3_tx_clk = {1925 .halt_reg = 0xd06c,1926 .halt_check = BRANCH_HALT,1927 .clkr = {1928 .enable_reg = 0xd06c,1929 .enable_mask = BIT(0),1930 .hw.init = &(const struct clk_init_data) {1931 .name = "ecpri_cc_phy1_lane3_tx_clk",1932 .ops = &clk_branch2_ops,1933 },1934 },1935};1936 1937static struct clk_branch ecpri_cc_phy2_lane0_rx_clk = {1938 .halt_reg = 0xd020,1939 .halt_check = BRANCH_HALT,1940 .clkr = {1941 .enable_reg = 0xd020,1942 .enable_mask = BIT(0),1943 .hw.init = &(const struct clk_init_data) {1944 .name = "ecpri_cc_phy2_lane0_rx_clk",1945 .ops = &clk_branch2_ops,1946 },1947 },1948};1949 1950static struct clk_branch ecpri_cc_phy2_lane0_tx_clk = {1951 .halt_reg = 0xd070,1952 .halt_check = BRANCH_HALT,1953 .clkr = {1954 .enable_reg = 0xd070,1955 .enable_mask = BIT(0),1956 .hw.init = &(const struct clk_init_data) {1957 .name = "ecpri_cc_phy2_lane0_tx_clk",1958 .ops = &clk_branch2_ops,1959 },1960 },1961};1962 1963static struct clk_branch ecpri_cc_phy2_lane1_rx_clk = {1964 .halt_reg = 0xd024,1965 .halt_check = BRANCH_HALT,1966 .clkr = {1967 .enable_reg = 0xd024,1968 .enable_mask = BIT(0),1969 .hw.init = &(const struct clk_init_data) {1970 .name = "ecpri_cc_phy2_lane1_rx_clk",1971 .ops = &clk_branch2_ops,1972 },1973 },1974};1975 1976static struct clk_branch ecpri_cc_phy2_lane1_tx_clk = {1977 .halt_reg = 0xd074,1978 .halt_check = BRANCH_HALT,1979 .clkr = {1980 .enable_reg = 0xd074,1981 .enable_mask = BIT(0),1982 .hw.init = &(const struct clk_init_data) {1983 .name = "ecpri_cc_phy2_lane1_tx_clk",1984 .ops = &clk_branch2_ops,1985 },1986 },1987};1988 1989static struct clk_branch ecpri_cc_phy2_lane2_rx_clk = {1990 .halt_reg = 0xd028,1991 .halt_check = BRANCH_HALT,1992 .clkr = {1993 .enable_reg = 0xd028,1994 .enable_mask = BIT(0),1995 .hw.init = &(const struct clk_init_data) {1996 .name = "ecpri_cc_phy2_lane2_rx_clk",1997 .ops = &clk_branch2_ops,1998 },1999 },2000};2001 2002static struct clk_branch ecpri_cc_phy2_lane2_tx_clk = {2003 .halt_reg = 0xd078,2004 .halt_check = BRANCH_HALT,2005 .clkr = {2006 .enable_reg = 0xd078,2007 .enable_mask = BIT(0),2008 .hw.init = &(const struct clk_init_data) {2009 .name = "ecpri_cc_phy2_lane2_tx_clk",2010 .ops = &clk_branch2_ops,2011 },2012 },2013};2014 2015static struct clk_branch ecpri_cc_phy2_lane3_rx_clk = {2016 .halt_reg = 0xd02c,2017 .halt_check = BRANCH_HALT,2018 .clkr = {2019 .enable_reg = 0xd02c,2020 .enable_mask = BIT(0),2021 .hw.init = &(const struct clk_init_data) {2022 .name = "ecpri_cc_phy2_lane3_rx_clk",2023 .ops = &clk_branch2_ops,2024 },2025 },2026};2027 2028static struct clk_branch ecpri_cc_phy2_lane3_tx_clk = {2029 .halt_reg = 0xd07c,2030 .halt_check = BRANCH_HALT,2031 .clkr = {2032 .enable_reg = 0xd07c,2033 .enable_mask = BIT(0),2034 .hw.init = &(const struct clk_init_data) {2035 .name = "ecpri_cc_phy2_lane3_tx_clk",2036 .ops = &clk_branch2_ops,2037 },2038 },2039};2040 2041static struct clk_branch ecpri_cc_phy3_lane0_rx_clk = {2042 .halt_reg = 0xd030,2043 .halt_check = BRANCH_HALT,2044 .clkr = {2045 .enable_reg = 0xd030,2046 .enable_mask = BIT(0),2047 .hw.init = &(const struct clk_init_data) {2048 .name = "ecpri_cc_phy3_lane0_rx_clk",2049 .ops = &clk_branch2_ops,2050 },2051 },2052};2053 2054static struct clk_branch ecpri_cc_phy3_lane0_tx_clk = {2055 .halt_reg = 0xd080,2056 .halt_check = BRANCH_HALT,2057 .clkr = {2058 .enable_reg = 0xd080,2059 .enable_mask = BIT(0),2060 .hw.init = &(const struct clk_init_data) {2061 .name = "ecpri_cc_phy3_lane0_tx_clk",2062 .ops = &clk_branch2_ops,2063 },2064 },2065};2066 2067static struct clk_branch ecpri_cc_phy3_lane1_rx_clk = {2068 .halt_reg = 0xd034,2069 .halt_check = BRANCH_HALT,2070 .clkr = {2071 .enable_reg = 0xd034,2072 .enable_mask = BIT(0),2073 .hw.init = &(const struct clk_init_data) {2074 .name = "ecpri_cc_phy3_lane1_rx_clk",2075 .ops = &clk_branch2_ops,2076 },2077 },2078};2079 2080static struct clk_branch ecpri_cc_phy3_lane1_tx_clk = {2081 .halt_reg = 0xd084,2082 .halt_check = BRANCH_HALT,2083 .clkr = {2084 .enable_reg = 0xd084,2085 .enable_mask = BIT(0),2086 .hw.init = &(const struct clk_init_data) {2087 .name = "ecpri_cc_phy3_lane1_tx_clk",2088 .ops = &clk_branch2_ops,2089 },2090 },2091};2092 2093static struct clk_branch ecpri_cc_phy3_lane2_rx_clk = {2094 .halt_reg = 0xd038,2095 .halt_check = BRANCH_HALT,2096 .clkr = {2097 .enable_reg = 0xd038,2098 .enable_mask = BIT(0),2099 .hw.init = &(const struct clk_init_data) {2100 .name = "ecpri_cc_phy3_lane2_rx_clk",2101 .ops = &clk_branch2_ops,2102 },2103 },2104};2105 2106static struct clk_branch ecpri_cc_phy3_lane2_tx_clk = {2107 .halt_reg = 0xd088,2108 .halt_check = BRANCH_HALT,2109 .clkr = {2110 .enable_reg = 0xd088,2111 .enable_mask = BIT(0),2112 .hw.init = &(const struct clk_init_data) {2113 .name = "ecpri_cc_phy3_lane2_tx_clk",2114 .ops = &clk_branch2_ops,2115 },2116 },2117};2118 2119static struct clk_branch ecpri_cc_phy3_lane3_rx_clk = {2120 .halt_reg = 0xd03c,2121 .halt_check = BRANCH_HALT,2122 .clkr = {2123 .enable_reg = 0xd03c,2124 .enable_mask = BIT(0),2125 .hw.init = &(const struct clk_init_data) {2126 .name = "ecpri_cc_phy3_lane3_rx_clk",2127 .ops = &clk_branch2_ops,2128 },2129 },2130};2131 2132static struct clk_branch ecpri_cc_phy3_lane3_tx_clk = {2133 .halt_reg = 0xd08c,2134 .halt_check = BRANCH_HALT,2135 .clkr = {2136 .enable_reg = 0xd08c,2137 .enable_mask = BIT(0),2138 .hw.init = &(const struct clk_init_data) {2139 .name = "ecpri_cc_phy3_lane3_tx_clk",2140 .ops = &clk_branch2_ops,2141 },2142 },2143};2144 2145static struct clk_branch ecpri_cc_phy4_lane0_rx_clk = {2146 .halt_reg = 0xd040,2147 .halt_check = BRANCH_HALT,2148 .clkr = {2149 .enable_reg = 0xd040,2150 .enable_mask = BIT(0),2151 .hw.init = &(const struct clk_init_data) {2152 .name = "ecpri_cc_phy4_lane0_rx_clk",2153 .ops = &clk_branch2_ops,2154 },2155 },2156};2157 2158static struct clk_branch ecpri_cc_phy4_lane0_tx_clk = {2159 .halt_reg = 0xd090,2160 .halt_check = BRANCH_HALT,2161 .clkr = {2162 .enable_reg = 0xd090,2163 .enable_mask = BIT(0),2164 .hw.init = &(const struct clk_init_data) {2165 .name = "ecpri_cc_phy4_lane0_tx_clk",2166 .ops = &clk_branch2_ops,2167 },2168 },2169};2170 2171static struct clk_branch ecpri_cc_phy4_lane1_rx_clk = {2172 .halt_reg = 0xd044,2173 .halt_check = BRANCH_HALT,2174 .clkr = {2175 .enable_reg = 0xd044,2176 .enable_mask = BIT(0),2177 .hw.init = &(const struct clk_init_data) {2178 .name = "ecpri_cc_phy4_lane1_rx_clk",2179 .ops = &clk_branch2_ops,2180 },2181 },2182};2183 2184static struct clk_branch ecpri_cc_phy4_lane1_tx_clk = {2185 .halt_reg = 0xd094,2186 .halt_check = BRANCH_HALT,2187 .clkr = {2188 .enable_reg = 0xd094,2189 .enable_mask = BIT(0),2190 .hw.init = &(const struct clk_init_data) {2191 .name = "ecpri_cc_phy4_lane1_tx_clk",2192 .ops = &clk_branch2_ops,2193 },2194 },2195};2196 2197static struct clk_branch ecpri_cc_phy4_lane2_rx_clk = {2198 .halt_reg = 0xd048,2199 .halt_check = BRANCH_HALT,2200 .clkr = {2201 .enable_reg = 0xd048,2202 .enable_mask = BIT(0),2203 .hw.init = &(const struct clk_init_data) {2204 .name = "ecpri_cc_phy4_lane2_rx_clk",2205 .ops = &clk_branch2_ops,2206 },2207 },2208};2209 2210static struct clk_branch ecpri_cc_phy4_lane2_tx_clk = {2211 .halt_reg = 0xd098,2212 .halt_check = BRANCH_HALT,2213 .clkr = {2214 .enable_reg = 0xd098,2215 .enable_mask = BIT(0),2216 .hw.init = &(const struct clk_init_data) {2217 .name = "ecpri_cc_phy4_lane2_tx_clk",2218 .ops = &clk_branch2_ops,2219 },2220 },2221};2222 2223static struct clk_branch ecpri_cc_phy4_lane3_rx_clk = {2224 .halt_reg = 0xd04c,2225 .halt_check = BRANCH_HALT,2226 .clkr = {2227 .enable_reg = 0xd04c,2228 .enable_mask = BIT(0),2229 .hw.init = &(const struct clk_init_data) {2230 .name = "ecpri_cc_phy4_lane3_rx_clk",2231 .ops = &clk_branch2_ops,2232 },2233 },2234};2235 2236static struct clk_branch ecpri_cc_phy4_lane3_tx_clk = {2237 .halt_reg = 0xd09c,2238 .halt_check = BRANCH_HALT,2239 .clkr = {2240 .enable_reg = 0xd09c,2241 .enable_mask = BIT(0),2242 .hw.init = &(const struct clk_init_data) {2243 .name = "ecpri_cc_phy4_lane3_tx_clk",2244 .ops = &clk_branch2_ops,2245 },2246 },2247};2248 2249static struct clk_regmap *ecpri_cc_qdu1000_clocks[] = {2250 [ECPRI_CC_ECPRI_CG_CLK] = &ecpri_cc_ecpri_cg_clk.clkr,2251 [ECPRI_CC_ECPRI_CLK_SRC] = &ecpri_cc_ecpri_clk_src.clkr,2252 [ECPRI_CC_ECPRI_DMA_CLK] = &ecpri_cc_ecpri_dma_clk.clkr,2253 [ECPRI_CC_ECPRI_DMA_CLK_SRC] = &ecpri_cc_ecpri_dma_clk_src.clkr,2254 [ECPRI_CC_ECPRI_DMA_NOC_CLK] = &ecpri_cc_ecpri_dma_noc_clk.clkr,2255 [ECPRI_CC_ECPRI_FAST_CLK] = &ecpri_cc_ecpri_fast_clk.clkr,2256 [ECPRI_CC_ECPRI_FAST_CLK_SRC] = &ecpri_cc_ecpri_fast_clk_src.clkr,2257 [ECPRI_CC_ECPRI_FAST_DIV2_CLK] = &ecpri_cc_ecpri_fast_div2_clk.clkr,2258 [ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC] = &ecpri_cc_ecpri_fast_div2_clk_src.clkr,2259 [ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK] = &ecpri_cc_ecpri_fast_div2_noc_clk.clkr,2260 [ECPRI_CC_ECPRI_FR_CLK] = &ecpri_cc_ecpri_fr_clk.clkr,2261 [ECPRI_CC_ECPRI_ORAN_CLK_SRC] = &ecpri_cc_ecpri_oran_clk_src.clkr,2262 [ECPRI_CC_ECPRI_ORAN_DIV2_CLK] = &ecpri_cc_ecpri_oran_div2_clk.clkr,2263 [ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr,2264 [ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c0_udp_fifo_clk.clkr,2265 [ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c1_udp_fifo_clk.clkr,2266 [ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk.branch.clkr,2267 [ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk.branch.clkr,2268 [ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC] =2269 &ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr,2270 [ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC] =2271 &ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr,2272 [ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk.branch.clkr,2273 [ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr,2274 [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK] =2275 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk.branch.clkr,2276 [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC] =2277 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr,2278 [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK] =2279 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk.branch.clkr,2280 [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC] =2281 &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr,2282 [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr,2283 [ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk.clkr,2284 [ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr,2285 [ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr,2286 [ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr,2287 [ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr,2288 [ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr,2289 [ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr,2290 [ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_0_clk.branch.clkr,2291 [ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC] =2292 &ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr,2293 [ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_1_clk.branch.clkr,2294 [ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC] =2295 &ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr,2296 [ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_2_clk.branch.clkr,2297 [ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC] =2298 &ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr,2299 [ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_3_clk.branch.clkr,2300 [ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC] =2301 &ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr,2302 [ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_0_udp_fifo_clk.clkr,2303 [ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_0_clk.branch.clkr,2304 [ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC] =2305 &ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr,2306 [ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_1_clk.branch.clkr,2307 [ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC] =2308 &ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr,2309 [ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_2_clk.branch.clkr,2310 [ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC] =2311 &ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr,2312 [ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_3_clk.branch.clkr,2313 [ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC] =2314 &ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr,2315 [ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_1_udp_fifo_clk.clkr,2316 [ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_0_clk.branch.clkr,2317 [ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC] =2318 &ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr,2319 [ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_1_clk.branch.clkr,2320 [ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC] =2321 &ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr,2322 [ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_2_clk.branch.clkr,2323 [ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC] =2324 &ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr,2325 [ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_3_clk.branch.clkr,2326 [ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC] =2327 &ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr,2328 [ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_2_udp_fifo_clk.clkr,2329 [ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK] = &ecpri_cc_eth_100g_fh_macsec_0_clk.branch.clkr,2330 [ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK] = &ecpri_cc_eth_100g_fh_macsec_1_clk.branch.clkr,2331 [ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK] = &ecpri_cc_eth_100g_fh_macsec_2_clk.branch.clkr,2332 [ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk.branch.clkr,2333 [ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr,2334 [ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK] =2335 &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk.branch.clkr,2336 [ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC] =2337 &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr,2338 [ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk.branch.clkr,2339 [ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr,2340 [ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk.branch.clkr,2341 [ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr,2342 [ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk.branch.clkr,2343 [ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr,2344 [ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK] = &ecpri_cc_eth_dbg_nfapi_axi_clk.clkr,2345 [ECPRI_CC_ETH_DBG_NOC_AXI_CLK] = &ecpri_cc_eth_dbg_noc_axi_clk.clkr,2346 [ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_0_ock_sram_clk.branch.clkr,2347 [ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_1_ock_sram_clk.branch.clkr,2348 [ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_2_ock_sram_clk.branch.clkr,2349 [ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_3_ock_sram_clk.branch.clkr,2350 [ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_4_ock_sram_clk.branch.clkr,2351 [ECPRI_CC_MSS_EMAC_CLK] = &ecpri_cc_mss_emac_clk.clkr,2352 [ECPRI_CC_MSS_EMAC_CLK_SRC] = &ecpri_cc_mss_emac_clk_src.clkr,2353 [ECPRI_CC_MSS_ORAN_CLK] = &ecpri_cc_mss_oran_clk.clkr,2354 [ECPRI_CC_PHY0_LANE0_RX_CLK] = &ecpri_cc_phy0_lane0_rx_clk.clkr,2355 [ECPRI_CC_PHY0_LANE0_TX_CLK] = &ecpri_cc_phy0_lane0_tx_clk.clkr,2356 [ECPRI_CC_PHY0_LANE1_RX_CLK] = &ecpri_cc_phy0_lane1_rx_clk.clkr,2357 [ECPRI_CC_PHY0_LANE1_TX_CLK] = &ecpri_cc_phy0_lane1_tx_clk.clkr,2358 [ECPRI_CC_PHY0_LANE2_RX_CLK] = &ecpri_cc_phy0_lane2_rx_clk.clkr,2359 [ECPRI_CC_PHY0_LANE2_TX_CLK] = &ecpri_cc_phy0_lane2_tx_clk.clkr,2360 [ECPRI_CC_PHY0_LANE3_RX_CLK] = &ecpri_cc_phy0_lane3_rx_clk.clkr,2361 [ECPRI_CC_PHY0_LANE3_TX_CLK] = &ecpri_cc_phy0_lane3_tx_clk.clkr,2362 [ECPRI_CC_PHY1_LANE0_RX_CLK] = &ecpri_cc_phy1_lane0_rx_clk.clkr,2363 [ECPRI_CC_PHY1_LANE0_TX_CLK] = &ecpri_cc_phy1_lane0_tx_clk.clkr,2364 [ECPRI_CC_PHY1_LANE1_RX_CLK] = &ecpri_cc_phy1_lane1_rx_clk.clkr,2365 [ECPRI_CC_PHY1_LANE1_TX_CLK] = &ecpri_cc_phy1_lane1_tx_clk.clkr,2366 [ECPRI_CC_PHY1_LANE2_RX_CLK] = &ecpri_cc_phy1_lane2_rx_clk.clkr,2367 [ECPRI_CC_PHY1_LANE2_TX_CLK] = &ecpri_cc_phy1_lane2_tx_clk.clkr,2368 [ECPRI_CC_PHY1_LANE3_RX_CLK] = &ecpri_cc_phy1_lane3_rx_clk.clkr,2369 [ECPRI_CC_PHY1_LANE3_TX_CLK] = &ecpri_cc_phy1_lane3_tx_clk.clkr,2370 [ECPRI_CC_PHY2_LANE0_RX_CLK] = &ecpri_cc_phy2_lane0_rx_clk.clkr,2371 [ECPRI_CC_PHY2_LANE0_TX_CLK] = &ecpri_cc_phy2_lane0_tx_clk.clkr,2372 [ECPRI_CC_PHY2_LANE1_RX_CLK] = &ecpri_cc_phy2_lane1_rx_clk.clkr,2373 [ECPRI_CC_PHY2_LANE1_TX_CLK] = &ecpri_cc_phy2_lane1_tx_clk.clkr,2374 [ECPRI_CC_PHY2_LANE2_RX_CLK] = &ecpri_cc_phy2_lane2_rx_clk.clkr,2375 [ECPRI_CC_PHY2_LANE2_TX_CLK] = &ecpri_cc_phy2_lane2_tx_clk.clkr,2376 [ECPRI_CC_PHY2_LANE3_RX_CLK] = &ecpri_cc_phy2_lane3_rx_clk.clkr,2377 [ECPRI_CC_PHY2_LANE3_TX_CLK] = &ecpri_cc_phy2_lane3_tx_clk.clkr,2378 [ECPRI_CC_PHY3_LANE0_RX_CLK] = &ecpri_cc_phy3_lane0_rx_clk.clkr,2379 [ECPRI_CC_PHY3_LANE0_TX_CLK] = &ecpri_cc_phy3_lane0_tx_clk.clkr,2380 [ECPRI_CC_PHY3_LANE1_RX_CLK] = &ecpri_cc_phy3_lane1_rx_clk.clkr,2381 [ECPRI_CC_PHY3_LANE1_TX_CLK] = &ecpri_cc_phy3_lane1_tx_clk.clkr,2382 [ECPRI_CC_PHY3_LANE2_RX_CLK] = &ecpri_cc_phy3_lane2_rx_clk.clkr,2383 [ECPRI_CC_PHY3_LANE2_TX_CLK] = &ecpri_cc_phy3_lane2_tx_clk.clkr,2384 [ECPRI_CC_PHY3_LANE3_RX_CLK] = &ecpri_cc_phy3_lane3_rx_clk.clkr,2385 [ECPRI_CC_PHY3_LANE3_TX_CLK] = &ecpri_cc_phy3_lane3_tx_clk.clkr,2386 [ECPRI_CC_PHY4_LANE0_RX_CLK] = &ecpri_cc_phy4_lane0_rx_clk.clkr,2387 [ECPRI_CC_PHY4_LANE0_TX_CLK] = &ecpri_cc_phy4_lane0_tx_clk.clkr,2388 [ECPRI_CC_PHY4_LANE1_RX_CLK] = &ecpri_cc_phy4_lane1_rx_clk.clkr,2389 [ECPRI_CC_PHY4_LANE1_TX_CLK] = &ecpri_cc_phy4_lane1_tx_clk.clkr,2390 [ECPRI_CC_PHY4_LANE2_RX_CLK] = &ecpri_cc_phy4_lane2_rx_clk.clkr,2391 [ECPRI_CC_PHY4_LANE2_TX_CLK] = &ecpri_cc_phy4_lane2_tx_clk.clkr,2392 [ECPRI_CC_PHY4_LANE3_RX_CLK] = &ecpri_cc_phy4_lane3_rx_clk.clkr,2393 [ECPRI_CC_PHY4_LANE3_TX_CLK] = &ecpri_cc_phy4_lane3_tx_clk.clkr,2394 [ECPRI_CC_PLL0] = &ecpri_cc_pll0.clkr,2395 [ECPRI_CC_PLL1] = &ecpri_cc_pll1.clkr,2396};2397 2398static const struct qcom_reset_map ecpri_cc_qdu1000_resets[] = {2399 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR] = { 0x9000 },2400 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR] = { 0x80a8 },2401 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR] = { 0x8000 },2402 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR] = { 0x8038 },2403 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR] = { 0x8070 },2404 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR] = { 0x8104 },2405 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR] = { 0xe000 },2406 [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR] = { 0xf000 },2407};2408 2409static const struct regmap_config ecpri_cc_qdu1000_regmap_config = {2410 .reg_bits = 32,2411 .reg_stride = 4,2412 .val_bits = 32,2413 .max_register = 0x31bf0,2414 .fast_io = true,2415};2416 2417static const struct qcom_cc_desc ecpri_cc_qdu1000_desc = {2418 .config = &ecpri_cc_qdu1000_regmap_config,2419 .clks = ecpri_cc_qdu1000_clocks,2420 .num_clks = ARRAY_SIZE(ecpri_cc_qdu1000_clocks),2421 .resets = ecpri_cc_qdu1000_resets,2422 .num_resets = ARRAY_SIZE(ecpri_cc_qdu1000_resets),2423};2424 2425static const struct of_device_id ecpri_cc_qdu1000_match_table[] = {2426 { .compatible = "qcom,qdu1000-ecpricc" },2427 { }2428};2429MODULE_DEVICE_TABLE(of, ecpri_cc_qdu1000_match_table);2430 2431static int ecpri_cc_qdu1000_probe(struct platform_device *pdev)2432{2433 struct regmap *regmap;2434 2435 regmap = qcom_cc_map(pdev, &ecpri_cc_qdu1000_desc);2436 if (IS_ERR(regmap))2437 return PTR_ERR(regmap);2438 2439 clk_lucid_evo_pll_configure(&ecpri_cc_pll0, regmap, &ecpri_cc_pll0_config);2440 clk_lucid_evo_pll_configure(&ecpri_cc_pll1, regmap, &ecpri_cc_pll1_config);2441 2442 return qcom_cc_really_probe(&pdev->dev, &ecpri_cc_qdu1000_desc, regmap);2443}2444 2445static struct platform_driver ecpri_cc_qdu1000_driver = {2446 .probe = ecpri_cc_qdu1000_probe,2447 .driver = {2448 .name = "ecpri_cc-qdu1000",2449 .of_match_table = ecpri_cc_qdu1000_match_table,2450 },2451};2452 2453module_platform_driver(ecpri_cc_qdu1000_driver);2454 2455MODULE_DESCRIPTION("QTI ECPRICC QDU1000 Driver");2456MODULE_LICENSE("GPL");2457