1765 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.4 * Copyright (c) BayLibre, SAS.5 * Author : Neil Armstrong <narmstrong@baylibre.com>6 */7 8#include <linux/kernel.h>9#include <linux/bitops.h>10#include <linux/err.h>11#include <linux/platform_device.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/clk-provider.h>15#include <linux/regmap.h>16#include <linux/reset-controller.h>17 18#include <dt-bindings/clock/qcom,gcc-mdm9615.h>19#include <dt-bindings/reset/qcom,gcc-mdm9615.h>20 21#include "common.h"22#include "clk-regmap.h"23#include "clk-pll.h"24#include "clk-rcg.h"25#include "clk-branch.h"26#include "reset.h"27 28enum {29 DT_CXO,30 DT_PLL4,31};32 33enum {34 P_CXO,35 P_PLL8,36 P_PLL14,37};38 39static const struct parent_map gcc_cxo_map[] = {40 { P_CXO, 0 },41};42 43static const struct clk_parent_data gcc_cxo[] = {44 { .index = DT_CXO, .name = "cxo_board" },45};46 47static struct clk_pll pll0 = {48 .l_reg = 0x30c4,49 .m_reg = 0x30c8,50 .n_reg = 0x30cc,51 .config_reg = 0x30d4,52 .mode_reg = 0x30c0,53 .status_reg = 0x30d8,54 .status_bit = 16,55 .clkr.hw.init = &(struct clk_init_data){56 .name = "pll0",57 .parent_data = gcc_cxo,58 .num_parents = ARRAY_SIZE(gcc_cxo),59 .ops = &clk_pll_ops,60 },61};62 63static struct clk_regmap pll0_vote = {64 .enable_reg = 0x34c0,65 .enable_mask = BIT(0),66 .hw.init = &(struct clk_init_data){67 .name = "pll0_vote",68 .parent_hws = (const struct clk_hw*[]) {69 &pll0.clkr.hw,70 },71 .num_parents = 1,72 .ops = &clk_pll_vote_ops,73 },74};75 76static struct clk_regmap pll4_vote = {77 .enable_reg = 0x34c0,78 .enable_mask = BIT(4),79 .hw.init = &(struct clk_init_data){80 .name = "pll4_vote",81 .parent_data = &(const struct clk_parent_data) {82 .index = DT_PLL4, .name = "pll4",83 },84 .num_parents = 1,85 .ops = &clk_pll_vote_ops,86 },87};88 89static struct clk_pll pll8 = {90 .l_reg = 0x3144,91 .m_reg = 0x3148,92 .n_reg = 0x314c,93 .config_reg = 0x3154,94 .mode_reg = 0x3140,95 .status_reg = 0x3158,96 .status_bit = 16,97 .clkr.hw.init = &(struct clk_init_data){98 .name = "pll8",99 .parent_data = gcc_cxo,100 .num_parents = ARRAY_SIZE(gcc_cxo),101 .ops = &clk_pll_ops,102 },103};104 105static struct clk_regmap pll8_vote = {106 .enable_reg = 0x34c0,107 .enable_mask = BIT(8),108 .hw.init = &(struct clk_init_data){109 .name = "pll8_vote",110 .parent_hws = (const struct clk_hw*[]) {111 &pll8.clkr.hw,112 },113 .num_parents = 1,114 .ops = &clk_pll_vote_ops,115 },116};117 118static struct clk_pll pll14 = {119 .l_reg = 0x31c4,120 .m_reg = 0x31c8,121 .n_reg = 0x31cc,122 .config_reg = 0x31d4,123 .mode_reg = 0x31c0,124 .status_reg = 0x31d8,125 .status_bit = 16,126 .clkr.hw.init = &(struct clk_init_data){127 .name = "pll14",128 .parent_data = gcc_cxo,129 .num_parents = ARRAY_SIZE(gcc_cxo),130 .ops = &clk_pll_ops,131 },132};133 134static struct clk_regmap pll14_vote = {135 .enable_reg = 0x34c0,136 .enable_mask = BIT(11),137 .hw.init = &(struct clk_init_data){138 .name = "pll14_vote",139 .parent_hws = (const struct clk_hw*[]) {140 &pll14.clkr.hw,141 },142 .num_parents = 1,143 .ops = &clk_pll_vote_ops,144 },145};146 147static const struct parent_map gcc_cxo_pll8_map[] = {148 { P_CXO, 0 },149 { P_PLL8, 3 }150};151 152static const struct clk_parent_data gcc_cxo_pll8[] = {153 { .index = DT_CXO, .name = "cxo_board" },154 { .hw = &pll8_vote.hw },155};156 157static const struct parent_map gcc_cxo_pll14_map[] = {158 { P_CXO, 0 },159 { P_PLL14, 4 }160};161 162static const struct clk_parent_data gcc_cxo_pll14[] = {163 { .index = DT_CXO, .name = "cxo_board" },164 { .hw = &pll14_vote.hw },165};166 167static const struct freq_tbl clk_tbl_gsbi_uart[] = {168 { 1843200, P_PLL8, 2, 6, 625 },169 { 3686400, P_PLL8, 2, 12, 625 },170 { 7372800, P_PLL8, 2, 24, 625 },171 { 14745600, P_PLL8, 2, 48, 625 },172 { 16000000, P_PLL8, 4, 1, 6 },173 { 24000000, P_PLL8, 4, 1, 4 },174 { 32000000, P_PLL8, 4, 1, 3 },175 { 40000000, P_PLL8, 1, 5, 48 },176 { 46400000, P_PLL8, 1, 29, 240 },177 { 48000000, P_PLL8, 4, 1, 2 },178 { 51200000, P_PLL8, 1, 2, 15 },179 { 56000000, P_PLL8, 1, 7, 48 },180 { 58982400, P_PLL8, 1, 96, 625 },181 { 64000000, P_PLL8, 2, 1, 3 },182 { }183};184 185static struct clk_rcg gsbi1_uart_src = {186 .ns_reg = 0x29d4,187 .md_reg = 0x29d0,188 .mn = {189 .mnctr_en_bit = 8,190 .mnctr_reset_bit = 7,191 .mnctr_mode_shift = 5,192 .n_val_shift = 16,193 .m_val_shift = 16,194 .width = 16,195 },196 .p = {197 .pre_div_shift = 3,198 .pre_div_width = 2,199 },200 .s = {201 .src_sel_shift = 0,202 .parent_map = gcc_cxo_pll8_map,203 },204 .freq_tbl = clk_tbl_gsbi_uart,205 .clkr = {206 .enable_reg = 0x29d4,207 .enable_mask = BIT(11),208 .hw.init = &(struct clk_init_data){209 .name = "gsbi1_uart_src",210 .parent_data = gcc_cxo_pll8,211 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),212 .ops = &clk_rcg_ops,213 .flags = CLK_SET_PARENT_GATE,214 },215 },216};217 218static struct clk_branch gsbi1_uart_clk = {219 .halt_reg = 0x2fcc,220 .halt_bit = 10,221 .clkr = {222 .enable_reg = 0x29d4,223 .enable_mask = BIT(9),224 .hw.init = &(struct clk_init_data){225 .name = "gsbi1_uart_clk",226 .parent_hws = (const struct clk_hw*[]) {227 &gsbi1_uart_src.clkr.hw,228 },229 .num_parents = 1,230 .ops = &clk_branch_ops,231 .flags = CLK_SET_RATE_PARENT,232 },233 },234};235 236static struct clk_rcg gsbi2_uart_src = {237 .ns_reg = 0x29f4,238 .md_reg = 0x29f0,239 .mn = {240 .mnctr_en_bit = 8,241 .mnctr_reset_bit = 7,242 .mnctr_mode_shift = 5,243 .n_val_shift = 16,244 .m_val_shift = 16,245 .width = 16,246 },247 .p = {248 .pre_div_shift = 3,249 .pre_div_width = 2,250 },251 .s = {252 .src_sel_shift = 0,253 .parent_map = gcc_cxo_pll8_map,254 },255 .freq_tbl = clk_tbl_gsbi_uart,256 .clkr = {257 .enable_reg = 0x29f4,258 .enable_mask = BIT(11),259 .hw.init = &(struct clk_init_data){260 .name = "gsbi2_uart_src",261 .parent_data = gcc_cxo_pll8,262 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),263 .ops = &clk_rcg_ops,264 .flags = CLK_SET_PARENT_GATE,265 },266 },267};268 269static struct clk_branch gsbi2_uart_clk = {270 .halt_reg = 0x2fcc,271 .halt_bit = 6,272 .clkr = {273 .enable_reg = 0x29f4,274 .enable_mask = BIT(9),275 .hw.init = &(struct clk_init_data){276 .name = "gsbi2_uart_clk",277 .parent_hws = (const struct clk_hw*[]) {278 &gsbi2_uart_src.clkr.hw,279 },280 .num_parents = 1,281 .ops = &clk_branch_ops,282 .flags = CLK_SET_RATE_PARENT,283 },284 },285};286 287static struct clk_rcg gsbi3_uart_src = {288 .ns_reg = 0x2a14,289 .md_reg = 0x2a10,290 .mn = {291 .mnctr_en_bit = 8,292 .mnctr_reset_bit = 7,293 .mnctr_mode_shift = 5,294 .n_val_shift = 16,295 .m_val_shift = 16,296 .width = 16,297 },298 .p = {299 .pre_div_shift = 3,300 .pre_div_width = 2,301 },302 .s = {303 .src_sel_shift = 0,304 .parent_map = gcc_cxo_pll8_map,305 },306 .freq_tbl = clk_tbl_gsbi_uart,307 .clkr = {308 .enable_reg = 0x2a14,309 .enable_mask = BIT(11),310 .hw.init = &(struct clk_init_data){311 .name = "gsbi3_uart_src",312 .parent_data = gcc_cxo_pll8,313 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),314 .ops = &clk_rcg_ops,315 .flags = CLK_SET_PARENT_GATE,316 },317 },318};319 320static struct clk_branch gsbi3_uart_clk = {321 .halt_reg = 0x2fcc,322 .halt_bit = 2,323 .clkr = {324 .enable_reg = 0x2a14,325 .enable_mask = BIT(9),326 .hw.init = &(struct clk_init_data){327 .name = "gsbi3_uart_clk",328 .parent_hws = (const struct clk_hw*[]) {329 &gsbi3_uart_src.clkr.hw,330 },331 .num_parents = 1,332 .ops = &clk_branch_ops,333 .flags = CLK_SET_RATE_PARENT,334 },335 },336};337 338static struct clk_rcg gsbi4_uart_src = {339 .ns_reg = 0x2a34,340 .md_reg = 0x2a30,341 .mn = {342 .mnctr_en_bit = 8,343 .mnctr_reset_bit = 7,344 .mnctr_mode_shift = 5,345 .n_val_shift = 16,346 .m_val_shift = 16,347 .width = 16,348 },349 .p = {350 .pre_div_shift = 3,351 .pre_div_width = 2,352 },353 .s = {354 .src_sel_shift = 0,355 .parent_map = gcc_cxo_pll8_map,356 },357 .freq_tbl = clk_tbl_gsbi_uart,358 .clkr = {359 .enable_reg = 0x2a34,360 .enable_mask = BIT(11),361 .hw.init = &(struct clk_init_data){362 .name = "gsbi4_uart_src",363 .parent_data = gcc_cxo_pll8,364 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),365 .ops = &clk_rcg_ops,366 .flags = CLK_SET_PARENT_GATE,367 },368 },369};370 371static struct clk_branch gsbi4_uart_clk = {372 .halt_reg = 0x2fd0,373 .halt_bit = 26,374 .clkr = {375 .enable_reg = 0x2a34,376 .enable_mask = BIT(9),377 .hw.init = &(struct clk_init_data){378 .name = "gsbi4_uart_clk",379 .parent_hws = (const struct clk_hw*[]) {380 &gsbi4_uart_src.clkr.hw,381 },382 .num_parents = 1,383 .ops = &clk_branch_ops,384 .flags = CLK_SET_RATE_PARENT,385 },386 },387};388 389static struct clk_rcg gsbi5_uart_src = {390 .ns_reg = 0x2a54,391 .md_reg = 0x2a50,392 .mn = {393 .mnctr_en_bit = 8,394 .mnctr_reset_bit = 7,395 .mnctr_mode_shift = 5,396 .n_val_shift = 16,397 .m_val_shift = 16,398 .width = 16,399 },400 .p = {401 .pre_div_shift = 3,402 .pre_div_width = 2,403 },404 .s = {405 .src_sel_shift = 0,406 .parent_map = gcc_cxo_pll8_map,407 },408 .freq_tbl = clk_tbl_gsbi_uart,409 .clkr = {410 .enable_reg = 0x2a54,411 .enable_mask = BIT(11),412 .hw.init = &(struct clk_init_data){413 .name = "gsbi5_uart_src",414 .parent_data = gcc_cxo_pll8,415 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),416 .ops = &clk_rcg_ops,417 .flags = CLK_SET_PARENT_GATE,418 },419 },420};421 422static struct clk_branch gsbi5_uart_clk = {423 .halt_reg = 0x2fd0,424 .halt_bit = 22,425 .clkr = {426 .enable_reg = 0x2a54,427 .enable_mask = BIT(9),428 .hw.init = &(struct clk_init_data){429 .name = "gsbi5_uart_clk",430 .parent_hws = (const struct clk_hw*[]) {431 &gsbi5_uart_src.clkr.hw,432 },433 .num_parents = 1,434 .ops = &clk_branch_ops,435 .flags = CLK_SET_RATE_PARENT,436 },437 },438};439 440static const struct freq_tbl clk_tbl_gsbi_qup[] = {441 { 960000, P_CXO, 4, 1, 5 },442 { 4800000, P_CXO, 4, 0, 1 },443 { 9600000, P_CXO, 2, 0, 1 },444 { 15060000, P_PLL8, 1, 2, 51 },445 { 24000000, P_PLL8, 4, 1, 4 },446 { 25600000, P_PLL8, 1, 1, 15 },447 { 48000000, P_PLL8, 4, 1, 2 },448 { 51200000, P_PLL8, 1, 2, 15 },449 { }450};451 452static struct clk_rcg gsbi1_qup_src = {453 .ns_reg = 0x29cc,454 .md_reg = 0x29c8,455 .mn = {456 .mnctr_en_bit = 8,457 .mnctr_reset_bit = 7,458 .mnctr_mode_shift = 5,459 .n_val_shift = 16,460 .m_val_shift = 16,461 .width = 8,462 },463 .p = {464 .pre_div_shift = 3,465 .pre_div_width = 2,466 },467 .s = {468 .src_sel_shift = 0,469 .parent_map = gcc_cxo_pll8_map,470 },471 .freq_tbl = clk_tbl_gsbi_qup,472 .clkr = {473 .enable_reg = 0x29cc,474 .enable_mask = BIT(11),475 .hw.init = &(struct clk_init_data){476 .name = "gsbi1_qup_src",477 .parent_data = gcc_cxo_pll8,478 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),479 .ops = &clk_rcg_ops,480 .flags = CLK_SET_PARENT_GATE,481 },482 },483};484 485static struct clk_branch gsbi1_qup_clk = {486 .halt_reg = 0x2fcc,487 .halt_bit = 9,488 .clkr = {489 .enable_reg = 0x29cc,490 .enable_mask = BIT(9),491 .hw.init = &(struct clk_init_data){492 .name = "gsbi1_qup_clk",493 .parent_hws = (const struct clk_hw*[]) {494 &gsbi1_qup_src.clkr.hw,495 },496 .num_parents = 1,497 .ops = &clk_branch_ops,498 .flags = CLK_SET_RATE_PARENT,499 },500 },501};502 503static struct clk_rcg gsbi2_qup_src = {504 .ns_reg = 0x29ec,505 .md_reg = 0x29e8,506 .mn = {507 .mnctr_en_bit = 8,508 .mnctr_reset_bit = 7,509 .mnctr_mode_shift = 5,510 .n_val_shift = 16,511 .m_val_shift = 16,512 .width = 8,513 },514 .p = {515 .pre_div_shift = 3,516 .pre_div_width = 2,517 },518 .s = {519 .src_sel_shift = 0,520 .parent_map = gcc_cxo_pll8_map,521 },522 .freq_tbl = clk_tbl_gsbi_qup,523 .clkr = {524 .enable_reg = 0x29ec,525 .enable_mask = BIT(11),526 .hw.init = &(struct clk_init_data){527 .name = "gsbi2_qup_src",528 .parent_data = gcc_cxo_pll8,529 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),530 .ops = &clk_rcg_ops,531 .flags = CLK_SET_PARENT_GATE,532 },533 },534};535 536static struct clk_branch gsbi2_qup_clk = {537 .halt_reg = 0x2fcc,538 .halt_bit = 4,539 .clkr = {540 .enable_reg = 0x29ec,541 .enable_mask = BIT(9),542 .hw.init = &(struct clk_init_data){543 .name = "gsbi2_qup_clk",544 .parent_hws = (const struct clk_hw*[]) {545 &gsbi2_qup_src.clkr.hw,546 },547 .num_parents = 1,548 .ops = &clk_branch_ops,549 .flags = CLK_SET_RATE_PARENT,550 },551 },552};553 554static struct clk_rcg gsbi3_qup_src = {555 .ns_reg = 0x2a0c,556 .md_reg = 0x2a08,557 .mn = {558 .mnctr_en_bit = 8,559 .mnctr_reset_bit = 7,560 .mnctr_mode_shift = 5,561 .n_val_shift = 16,562 .m_val_shift = 16,563 .width = 8,564 },565 .p = {566 .pre_div_shift = 3,567 .pre_div_width = 2,568 },569 .s = {570 .src_sel_shift = 0,571 .parent_map = gcc_cxo_pll8_map,572 },573 .freq_tbl = clk_tbl_gsbi_qup,574 .clkr = {575 .enable_reg = 0x2a0c,576 .enable_mask = BIT(11),577 .hw.init = &(struct clk_init_data){578 .name = "gsbi3_qup_src",579 .parent_data = gcc_cxo_pll8,580 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),581 .ops = &clk_rcg_ops,582 .flags = CLK_SET_PARENT_GATE,583 },584 },585};586 587static struct clk_branch gsbi3_qup_clk = {588 .halt_reg = 0x2fcc,589 .halt_bit = 0,590 .clkr = {591 .enable_reg = 0x2a0c,592 .enable_mask = BIT(9),593 .hw.init = &(struct clk_init_data){594 .name = "gsbi3_qup_clk",595 .parent_hws = (const struct clk_hw*[]) {596 &gsbi3_qup_src.clkr.hw,597 },598 .num_parents = 1,599 .ops = &clk_branch_ops,600 .flags = CLK_SET_RATE_PARENT,601 },602 },603};604 605static struct clk_rcg gsbi4_qup_src = {606 .ns_reg = 0x2a2c,607 .md_reg = 0x2a28,608 .mn = {609 .mnctr_en_bit = 8,610 .mnctr_reset_bit = 7,611 .mnctr_mode_shift = 5,612 .n_val_shift = 16,613 .m_val_shift = 16,614 .width = 8,615 },616 .p = {617 .pre_div_shift = 3,618 .pre_div_width = 2,619 },620 .s = {621 .src_sel_shift = 0,622 .parent_map = gcc_cxo_pll8_map,623 },624 .freq_tbl = clk_tbl_gsbi_qup,625 .clkr = {626 .enable_reg = 0x2a2c,627 .enable_mask = BIT(11),628 .hw.init = &(struct clk_init_data){629 .name = "gsbi4_qup_src",630 .parent_data = gcc_cxo_pll8,631 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),632 .ops = &clk_rcg_ops,633 .flags = CLK_SET_PARENT_GATE,634 },635 },636};637 638static struct clk_branch gsbi4_qup_clk = {639 .halt_reg = 0x2fd0,640 .halt_bit = 24,641 .clkr = {642 .enable_reg = 0x2a2c,643 .enable_mask = BIT(9),644 .hw.init = &(struct clk_init_data){645 .name = "gsbi4_qup_clk",646 .parent_hws = (const struct clk_hw*[]) {647 &gsbi4_qup_src.clkr.hw,648 },649 .num_parents = 1,650 .ops = &clk_branch_ops,651 .flags = CLK_SET_RATE_PARENT,652 },653 },654};655 656static struct clk_rcg gsbi5_qup_src = {657 .ns_reg = 0x2a4c,658 .md_reg = 0x2a48,659 .mn = {660 .mnctr_en_bit = 8,661 .mnctr_reset_bit = 7,662 .mnctr_mode_shift = 5,663 .n_val_shift = 16,664 .m_val_shift = 16,665 .width = 8,666 },667 .p = {668 .pre_div_shift = 3,669 .pre_div_width = 2,670 },671 .s = {672 .src_sel_shift = 0,673 .parent_map = gcc_cxo_pll8_map,674 },675 .freq_tbl = clk_tbl_gsbi_qup,676 .clkr = {677 .enable_reg = 0x2a4c,678 .enable_mask = BIT(11),679 .hw.init = &(struct clk_init_data){680 .name = "gsbi5_qup_src",681 .parent_data = gcc_cxo_pll8,682 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),683 .ops = &clk_rcg_ops,684 .flags = CLK_SET_PARENT_GATE,685 },686 },687};688 689static struct clk_branch gsbi5_qup_clk = {690 .halt_reg = 0x2fd0,691 .halt_bit = 20,692 .clkr = {693 .enable_reg = 0x2a4c,694 .enable_mask = BIT(9),695 .hw.init = &(struct clk_init_data){696 .name = "gsbi5_qup_clk",697 .parent_hws = (const struct clk_hw*[]) {698 &gsbi5_qup_src.clkr.hw,699 },700 .num_parents = 1,701 .ops = &clk_branch_ops,702 .flags = CLK_SET_RATE_PARENT,703 },704 },705};706 707static const struct freq_tbl clk_tbl_gp[] = {708 { 9600000, P_CXO, 2, 0, 0 },709 { 19200000, P_CXO, 1, 0, 0 },710 { }711};712 713static struct clk_rcg gp0_src = {714 .ns_reg = 0x2d24,715 .md_reg = 0x2d00,716 .mn = {717 .mnctr_en_bit = 8,718 .mnctr_reset_bit = 7,719 .mnctr_mode_shift = 5,720 .n_val_shift = 16,721 .m_val_shift = 16,722 .width = 8,723 },724 .p = {725 .pre_div_shift = 3,726 .pre_div_width = 2,727 },728 .s = {729 .src_sel_shift = 0,730 .parent_map = gcc_cxo_map,731 },732 .freq_tbl = clk_tbl_gp,733 .clkr = {734 .enable_reg = 0x2d24,735 .enable_mask = BIT(11),736 .hw.init = &(struct clk_init_data){737 .name = "gp0_src",738 .parent_data = gcc_cxo,739 .num_parents = ARRAY_SIZE(gcc_cxo),740 .ops = &clk_rcg_ops,741 .flags = CLK_SET_PARENT_GATE,742 },743 }744};745 746static struct clk_branch gp0_clk = {747 .halt_reg = 0x2fd8,748 .halt_bit = 7,749 .clkr = {750 .enable_reg = 0x2d24,751 .enable_mask = BIT(9),752 .hw.init = &(struct clk_init_data){753 .name = "gp0_clk",754 .parent_hws = (const struct clk_hw*[]) {755 &gp0_src.clkr.hw,756 },757 .num_parents = 1,758 .ops = &clk_branch_ops,759 .flags = CLK_SET_RATE_PARENT,760 },761 },762};763 764static struct clk_rcg gp1_src = {765 .ns_reg = 0x2d44,766 .md_reg = 0x2d40,767 .mn = {768 .mnctr_en_bit = 8,769 .mnctr_reset_bit = 7,770 .mnctr_mode_shift = 5,771 .n_val_shift = 16,772 .m_val_shift = 16,773 .width = 8,774 },775 .p = {776 .pre_div_shift = 3,777 .pre_div_width = 2,778 },779 .s = {780 .src_sel_shift = 0,781 .parent_map = gcc_cxo_map,782 },783 .freq_tbl = clk_tbl_gp,784 .clkr = {785 .enable_reg = 0x2d44,786 .enable_mask = BIT(11),787 .hw.init = &(struct clk_init_data){788 .name = "gp1_src",789 .parent_data = gcc_cxo,790 .num_parents = ARRAY_SIZE(gcc_cxo),791 .ops = &clk_rcg_ops,792 .flags = CLK_SET_RATE_GATE,793 },794 }795};796 797static struct clk_branch gp1_clk = {798 .halt_reg = 0x2fd8,799 .halt_bit = 6,800 .clkr = {801 .enable_reg = 0x2d44,802 .enable_mask = BIT(9),803 .hw.init = &(struct clk_init_data){804 .name = "gp1_clk",805 .parent_hws = (const struct clk_hw*[]) {806 &gp1_src.clkr.hw,807 },808 .num_parents = 1,809 .ops = &clk_branch_ops,810 .flags = CLK_SET_RATE_PARENT,811 },812 },813};814 815static struct clk_rcg gp2_src = {816 .ns_reg = 0x2d64,817 .md_reg = 0x2d60,818 .mn = {819 .mnctr_en_bit = 8,820 .mnctr_reset_bit = 7,821 .mnctr_mode_shift = 5,822 .n_val_shift = 16,823 .m_val_shift = 16,824 .width = 8,825 },826 .p = {827 .pre_div_shift = 3,828 .pre_div_width = 2,829 },830 .s = {831 .src_sel_shift = 0,832 .parent_map = gcc_cxo_map,833 },834 .freq_tbl = clk_tbl_gp,835 .clkr = {836 .enable_reg = 0x2d64,837 .enable_mask = BIT(11),838 .hw.init = &(struct clk_init_data){839 .name = "gp2_src",840 .parent_data = gcc_cxo,841 .num_parents = ARRAY_SIZE(gcc_cxo),842 .ops = &clk_rcg_ops,843 .flags = CLK_SET_RATE_GATE,844 },845 }846};847 848static struct clk_branch gp2_clk = {849 .halt_reg = 0x2fd8,850 .halt_bit = 5,851 .clkr = {852 .enable_reg = 0x2d64,853 .enable_mask = BIT(9),854 .hw.init = &(struct clk_init_data){855 .name = "gp2_clk",856 .parent_hws = (const struct clk_hw*[]) {857 &gp2_src.clkr.hw,858 },859 .num_parents = 1,860 .ops = &clk_branch_ops,861 .flags = CLK_SET_RATE_PARENT,862 },863 },864};865 866static struct clk_branch pmem_clk = {867 .hwcg_reg = 0x25a0,868 .hwcg_bit = 6,869 .halt_reg = 0x2fc8,870 .halt_bit = 20,871 .clkr = {872 .enable_reg = 0x25a0,873 .enable_mask = BIT(4),874 .hw.init = &(struct clk_init_data){875 .name = "pmem_clk",876 .ops = &clk_branch_ops,877 },878 },879};880 881static struct clk_rcg prng_src = {882 .ns_reg = 0x2e80,883 .p = {884 .pre_div_shift = 3,885 .pre_div_width = 4,886 },887 .s = {888 .src_sel_shift = 0,889 .parent_map = gcc_cxo_pll8_map,890 },891 .clkr = {892 .hw.init = &(struct clk_init_data){893 .name = "prng_src",894 .parent_data = gcc_cxo_pll8,895 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),896 .ops = &clk_rcg_ops,897 },898 },899};900 901static struct clk_branch prng_clk = {902 .halt_reg = 0x2fd8,903 .halt_check = BRANCH_HALT_VOTED,904 .halt_bit = 10,905 .clkr = {906 .enable_reg = 0x3080,907 .enable_mask = BIT(10),908 .hw.init = &(struct clk_init_data){909 .name = "prng_clk",910 .parent_hws = (const struct clk_hw*[]) {911 &prng_src.clkr.hw,912 },913 .num_parents = 1,914 .ops = &clk_branch_ops,915 },916 },917};918 919static const struct freq_tbl clk_tbl_sdc[] = {920 { 144000, P_CXO, 1, 1, 133 },921 { 400000, P_PLL8, 4, 1, 240 },922 { 16000000, P_PLL8, 4, 1, 6 },923 { 17070000, P_PLL8, 1, 2, 45 },924 { 20210000, P_PLL8, 1, 1, 19 },925 { 24000000, P_PLL8, 4, 1, 4 },926 { 38400000, P_PLL8, 2, 1, 5 },927 { 48000000, P_PLL8, 4, 1, 2 },928 { 64000000, P_PLL8, 3, 1, 2 },929 { 76800000, P_PLL8, 1, 1, 5 },930 { }931};932 933static struct clk_rcg sdc1_src = {934 .ns_reg = 0x282c,935 .md_reg = 0x2828,936 .mn = {937 .mnctr_en_bit = 8,938 .mnctr_reset_bit = 7,939 .mnctr_mode_shift = 5,940 .n_val_shift = 16,941 .m_val_shift = 16,942 .width = 8,943 },944 .p = {945 .pre_div_shift = 3,946 .pre_div_width = 2,947 },948 .s = {949 .src_sel_shift = 0,950 .parent_map = gcc_cxo_pll8_map,951 },952 .freq_tbl = clk_tbl_sdc,953 .clkr = {954 .enable_reg = 0x282c,955 .enable_mask = BIT(11),956 .hw.init = &(struct clk_init_data){957 .name = "sdc1_src",958 .parent_data = gcc_cxo_pll8,959 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),960 .ops = &clk_rcg_ops,961 },962 }963};964 965static struct clk_branch sdc1_clk = {966 .halt_reg = 0x2fc8,967 .halt_bit = 6,968 .clkr = {969 .enable_reg = 0x282c,970 .enable_mask = BIT(9),971 .hw.init = &(struct clk_init_data){972 .name = "sdc1_clk",973 .parent_hws = (const struct clk_hw*[]) {974 &sdc1_src.clkr.hw,975 },976 .num_parents = 1,977 .ops = &clk_branch_ops,978 .flags = CLK_SET_RATE_PARENT,979 },980 },981};982 983static struct clk_rcg sdc2_src = {984 .ns_reg = 0x284c,985 .md_reg = 0x2848,986 .mn = {987 .mnctr_en_bit = 8,988 .mnctr_reset_bit = 7,989 .mnctr_mode_shift = 5,990 .n_val_shift = 16,991 .m_val_shift = 16,992 .width = 8,993 },994 .p = {995 .pre_div_shift = 3,996 .pre_div_width = 2,997 },998 .s = {999 .src_sel_shift = 0,1000 .parent_map = gcc_cxo_pll8_map,1001 },1002 .freq_tbl = clk_tbl_sdc,1003 .clkr = {1004 .enable_reg = 0x284c,1005 .enable_mask = BIT(11),1006 .hw.init = &(struct clk_init_data){1007 .name = "sdc2_src",1008 .parent_data = gcc_cxo_pll8,1009 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),1010 .ops = &clk_rcg_ops,1011 },1012 }1013};1014 1015static struct clk_branch sdc2_clk = {1016 .halt_reg = 0x2fc8,1017 .halt_bit = 5,1018 .clkr = {1019 .enable_reg = 0x284c,1020 .enable_mask = BIT(9),1021 .hw.init = &(struct clk_init_data){1022 .name = "sdc2_clk",1023 .parent_hws = (const struct clk_hw*[]) {1024 &sdc2_src.clkr.hw,1025 },1026 .num_parents = 1,1027 .ops = &clk_branch_ops,1028 .flags = CLK_SET_RATE_PARENT,1029 },1030 },1031};1032 1033static const struct freq_tbl clk_tbl_usb[] = {1034 { 60000000, P_PLL8, 1, 5, 32 },1035 { }1036};1037 1038static struct clk_rcg usb_hs1_xcvr_src = {1039 .ns_reg = 0x290c,1040 .md_reg = 0x2908,1041 .mn = {1042 .mnctr_en_bit = 8,1043 .mnctr_reset_bit = 7,1044 .mnctr_mode_shift = 5,1045 .n_val_shift = 16,1046 .m_val_shift = 16,1047 .width = 8,1048 },1049 .p = {1050 .pre_div_shift = 3,1051 .pre_div_width = 2,1052 },1053 .s = {1054 .src_sel_shift = 0,1055 .parent_map = gcc_cxo_pll8_map,1056 },1057 .freq_tbl = clk_tbl_usb,1058 .clkr = {1059 .enable_reg = 0x290c,1060 .enable_mask = BIT(11),1061 .hw.init = &(struct clk_init_data){1062 .name = "usb_hs1_xcvr_src",1063 .parent_data = gcc_cxo_pll8,1064 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),1065 .ops = &clk_rcg_ops,1066 .flags = CLK_SET_RATE_GATE,1067 },1068 }1069};1070 1071static struct clk_branch usb_hs1_xcvr_clk = {1072 .halt_reg = 0x2fc8,1073 .halt_bit = 0,1074 .clkr = {1075 .enable_reg = 0x290c,1076 .enable_mask = BIT(9),1077 .hw.init = &(struct clk_init_data){1078 .name = "usb_hs1_xcvr_clk",1079 .parent_hws = (const struct clk_hw*[]) {1080 &usb_hs1_xcvr_src.clkr.hw,1081 },1082 .num_parents = 1,1083 .ops = &clk_branch_ops,1084 .flags = CLK_SET_RATE_PARENT,1085 },1086 },1087};1088 1089static struct clk_rcg usb_hsic_xcvr_fs_src = {1090 .ns_reg = 0x2928,1091 .md_reg = 0x2924,1092 .mn = {1093 .mnctr_en_bit = 8,1094 .mnctr_reset_bit = 7,1095 .mnctr_mode_shift = 5,1096 .n_val_shift = 16,1097 .m_val_shift = 16,1098 .width = 8,1099 },1100 .p = {1101 .pre_div_shift = 3,1102 .pre_div_width = 2,1103 },1104 .s = {1105 .src_sel_shift = 0,1106 .parent_map = gcc_cxo_pll8_map,1107 },1108 .freq_tbl = clk_tbl_usb,1109 .clkr = {1110 .enable_reg = 0x2928,1111 .enable_mask = BIT(11),1112 .hw.init = &(struct clk_init_data){1113 .name = "usb_hsic_xcvr_fs_src",1114 .parent_data = gcc_cxo_pll8,1115 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),1116 .ops = &clk_rcg_ops,1117 .flags = CLK_SET_RATE_GATE,1118 },1119 }1120};1121 1122static struct clk_branch usb_hsic_xcvr_fs_clk = {1123 .halt_reg = 0x2fc8,1124 .halt_bit = 9,1125 .clkr = {1126 .enable_reg = 0x2928,1127 .enable_mask = BIT(9),1128 .hw.init = &(struct clk_init_data){1129 .name = "usb_hsic_xcvr_fs_clk",1130 .parent_hws = (const struct clk_hw*[]) {1131 &usb_hsic_xcvr_fs_src.clkr.hw,1132 },1133 .num_parents = 1,1134 .ops = &clk_branch_ops,1135 .flags = CLK_SET_RATE_PARENT,1136 },1137 },1138};1139 1140static const struct freq_tbl clk_tbl_usb_hs1_system[] = {1141 { 60000000, P_PLL8, 1, 5, 32 },1142 { }1143};1144 1145static struct clk_rcg usb_hs1_system_src = {1146 .ns_reg = 0x36a4,1147 .md_reg = 0x36a0,1148 .mn = {1149 .mnctr_en_bit = 8,1150 .mnctr_reset_bit = 7,1151 .mnctr_mode_shift = 5,1152 .n_val_shift = 16,1153 .m_val_shift = 16,1154 .width = 8,1155 },1156 .p = {1157 .pre_div_shift = 3,1158 .pre_div_width = 2,1159 },1160 .s = {1161 .src_sel_shift = 0,1162 .parent_map = gcc_cxo_pll8_map,1163 },1164 .freq_tbl = clk_tbl_usb_hs1_system,1165 .clkr = {1166 .enable_reg = 0x36a4,1167 .enable_mask = BIT(11),1168 .hw.init = &(struct clk_init_data){1169 .name = "usb_hs1_system_src",1170 .parent_data = gcc_cxo_pll8,1171 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),1172 .ops = &clk_rcg_ops,1173 .flags = CLK_SET_RATE_GATE,1174 },1175 }1176};1177 1178static struct clk_branch usb_hs1_system_clk = {1179 .halt_reg = 0x2fc8,1180 .halt_bit = 4,1181 .clkr = {1182 .enable_reg = 0x36a4,1183 .enable_mask = BIT(9),1184 .hw.init = &(struct clk_init_data){1185 .parent_hws = (const struct clk_hw*[]) {1186 &usb_hs1_system_src.clkr.hw,1187 },1188 .num_parents = 1,1189 .name = "usb_hs1_system_clk",1190 .ops = &clk_branch_ops,1191 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,1192 },1193 },1194};1195 1196static const struct freq_tbl clk_tbl_usb_hsic_system[] = {1197 { 64000000, P_PLL8, 1, 1, 6 },1198 { }1199};1200 1201static struct clk_rcg usb_hsic_system_src = {1202 .ns_reg = 0x2b58,1203 .md_reg = 0x2b54,1204 .mn = {1205 .mnctr_en_bit = 8,1206 .mnctr_reset_bit = 7,1207 .mnctr_mode_shift = 5,1208 .n_val_shift = 16,1209 .m_val_shift = 16,1210 .width = 8,1211 },1212 .p = {1213 .pre_div_shift = 3,1214 .pre_div_width = 2,1215 },1216 .s = {1217 .src_sel_shift = 0,1218 .parent_map = gcc_cxo_pll8_map,1219 },1220 .freq_tbl = clk_tbl_usb_hsic_system,1221 .clkr = {1222 .enable_reg = 0x2b58,1223 .enable_mask = BIT(11),1224 .hw.init = &(struct clk_init_data){1225 .name = "usb_hsic_system_src",1226 .parent_data = gcc_cxo_pll8,1227 .num_parents = ARRAY_SIZE(gcc_cxo_pll8),1228 .ops = &clk_rcg_ops,1229 .flags = CLK_SET_RATE_GATE,1230 },1231 }1232};1233 1234static struct clk_branch usb_hsic_system_clk = {1235 .halt_reg = 0x2fc8,1236 .halt_bit = 7,1237 .clkr = {1238 .enable_reg = 0x2b58,1239 .enable_mask = BIT(9),1240 .hw.init = &(struct clk_init_data){1241 .parent_hws = (const struct clk_hw*[]) {1242 &usb_hsic_system_src.clkr.hw,1243 },1244 .num_parents = 1,1245 .name = "usb_hsic_system_clk",1246 .ops = &clk_branch_ops,1247 .flags = CLK_SET_RATE_PARENT,1248 },1249 },1250};1251 1252static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {1253 { 48000000, P_PLL14, 1, 0, 0 },1254 { }1255};1256 1257static struct clk_rcg usb_hsic_hsic_src = {1258 .ns_reg = 0x2b50,1259 .md_reg = 0x2b4c,1260 .mn = {1261 .mnctr_en_bit = 8,1262 .mnctr_reset_bit = 7,1263 .mnctr_mode_shift = 5,1264 .n_val_shift = 16,1265 .m_val_shift = 16,1266 .width = 8,1267 },1268 .p = {1269 .pre_div_shift = 3,1270 .pre_div_width = 2,1271 },1272 .s = {1273 .src_sel_shift = 0,1274 .parent_map = gcc_cxo_pll14_map,1275 },1276 .freq_tbl = clk_tbl_usb_hsic_hsic,1277 .clkr = {1278 .enable_reg = 0x2b50,1279 .enable_mask = BIT(11),1280 .hw.init = &(struct clk_init_data){1281 .name = "usb_hsic_hsic_src",1282 .parent_data = gcc_cxo_pll14,1283 .num_parents = ARRAY_SIZE(gcc_cxo_pll14),1284 .ops = &clk_rcg_ops,1285 .flags = CLK_SET_RATE_GATE,1286 },1287 }1288};1289 1290static struct clk_branch usb_hsic_hsic_clk = {1291 .halt_check = BRANCH_HALT_DELAY,1292 .clkr = {1293 .enable_reg = 0x2b50,1294 .enable_mask = BIT(9),1295 .hw.init = &(struct clk_init_data){1296 .parent_hws = (const struct clk_hw*[]) {1297 &usb_hsic_hsic_src.clkr.hw,1298 },1299 .num_parents = 1,1300 .name = "usb_hsic_hsic_clk",1301 .ops = &clk_branch_ops,1302 .flags = CLK_SET_RATE_PARENT,1303 },1304 },1305};1306 1307static struct clk_branch usb_hsic_hsio_cal_clk = {1308 .halt_reg = 0x2fc8,1309 .halt_bit = 8,1310 .clkr = {1311 .enable_reg = 0x2b48,1312 .enable_mask = BIT(0),1313 .hw.init = &(struct clk_init_data){1314 .parent_data = gcc_cxo,1315 .num_parents = ARRAY_SIZE(gcc_cxo),1316 .name = "usb_hsic_hsio_cal_clk",1317 .ops = &clk_branch_ops,1318 },1319 },1320};1321 1322static struct clk_branch ce1_core_clk = {1323 .hwcg_reg = 0x2724,1324 .hwcg_bit = 6,1325 .halt_reg = 0x2fd4,1326 .halt_bit = 27,1327 .clkr = {1328 .enable_reg = 0x2724,1329 .enable_mask = BIT(4),1330 .hw.init = &(struct clk_init_data){1331 .name = "ce1_core_clk",1332 .ops = &clk_branch_ops,1333 },1334 },1335};1336 1337static struct clk_branch ce1_h_clk = {1338 .halt_reg = 0x2fd4,1339 .halt_bit = 1,1340 .clkr = {1341 .enable_reg = 0x2720,1342 .enable_mask = BIT(4),1343 .hw.init = &(struct clk_init_data){1344 .name = "ce1_h_clk",1345 .ops = &clk_branch_ops,1346 },1347 },1348};1349 1350static struct clk_branch dma_bam_h_clk = {1351 .hwcg_reg = 0x25c0,1352 .hwcg_bit = 6,1353 .halt_reg = 0x2fc8,1354 .halt_bit = 12,1355 .clkr = {1356 .enable_reg = 0x25c0,1357 .enable_mask = BIT(4),1358 .hw.init = &(struct clk_init_data){1359 .name = "dma_bam_h_clk",1360 .ops = &clk_branch_ops,1361 },1362 },1363};1364 1365static struct clk_branch gsbi1_h_clk = {1366 .hwcg_reg = 0x29c0,1367 .hwcg_bit = 6,1368 .halt_reg = 0x2fcc,1369 .halt_bit = 11,1370 .clkr = {1371 .enable_reg = 0x29c0,1372 .enable_mask = BIT(4),1373 .hw.init = &(struct clk_init_data){1374 .name = "gsbi1_h_clk",1375 .ops = &clk_branch_ops,1376 },1377 },1378};1379 1380static struct clk_branch gsbi2_h_clk = {1381 .hwcg_reg = 0x29e0,1382 .hwcg_bit = 6,1383 .halt_reg = 0x2fcc,1384 .halt_bit = 7,1385 .clkr = {1386 .enable_reg = 0x29e0,1387 .enable_mask = BIT(4),1388 .hw.init = &(struct clk_init_data){1389 .name = "gsbi2_h_clk",1390 .ops = &clk_branch_ops,1391 },1392 },1393};1394 1395static struct clk_branch gsbi3_h_clk = {1396 .hwcg_reg = 0x2a00,1397 .hwcg_bit = 6,1398 .halt_reg = 0x2fcc,1399 .halt_bit = 3,1400 .clkr = {1401 .enable_reg = 0x2a00,1402 .enable_mask = BIT(4),1403 .hw.init = &(struct clk_init_data){1404 .name = "gsbi3_h_clk",1405 .ops = &clk_branch_ops,1406 },1407 },1408};1409 1410static struct clk_branch gsbi4_h_clk = {1411 .hwcg_reg = 0x2a20,1412 .hwcg_bit = 6,1413 .halt_reg = 0x2fd0,1414 .halt_bit = 27,1415 .clkr = {1416 .enable_reg = 0x2a20,1417 .enable_mask = BIT(4),1418 .hw.init = &(struct clk_init_data){1419 .name = "gsbi4_h_clk",1420 .ops = &clk_branch_ops,1421 },1422 },1423};1424 1425static struct clk_branch gsbi5_h_clk = {1426 .hwcg_reg = 0x2a40,1427 .hwcg_bit = 6,1428 .halt_reg = 0x2fd0,1429 .halt_bit = 23,1430 .clkr = {1431 .enable_reg = 0x2a40,1432 .enable_mask = BIT(4),1433 .hw.init = &(struct clk_init_data){1434 .name = "gsbi5_h_clk",1435 .ops = &clk_branch_ops,1436 },1437 },1438};1439 1440static struct clk_branch usb_hs1_h_clk = {1441 .hwcg_reg = 0x2900,1442 .hwcg_bit = 6,1443 .halt_reg = 0x2fc8,1444 .halt_bit = 1,1445 .clkr = {1446 .enable_reg = 0x2900,1447 .enable_mask = BIT(4),1448 .hw.init = &(struct clk_init_data){1449 .name = "usb_hs1_h_clk",1450 .ops = &clk_branch_ops,1451 },1452 },1453};1454 1455static struct clk_branch usb_hsic_h_clk = {1456 .halt_reg = 0x2fcc,1457 .halt_bit = 28,1458 .clkr = {1459 .enable_reg = 0x2920,1460 .enable_mask = BIT(4),1461 .hw.init = &(struct clk_init_data){1462 .name = "usb_hsic_h_clk",1463 .ops = &clk_branch_ops,1464 },1465 },1466};1467 1468static struct clk_branch sdc1_h_clk = {1469 .hwcg_reg = 0x2820,1470 .hwcg_bit = 6,1471 .halt_reg = 0x2fc8,1472 .halt_bit = 11,1473 .clkr = {1474 .enable_reg = 0x2820,1475 .enable_mask = BIT(4),1476 .hw.init = &(struct clk_init_data){1477 .name = "sdc1_h_clk",1478 .ops = &clk_branch_ops,1479 },1480 },1481};1482 1483static struct clk_branch sdc2_h_clk = {1484 .hwcg_reg = 0x2840,1485 .hwcg_bit = 6,1486 .halt_reg = 0x2fc8,1487 .halt_bit = 10,1488 .clkr = {1489 .enable_reg = 0x2840,1490 .enable_mask = BIT(4),1491 .hw.init = &(struct clk_init_data){1492 .name = "sdc2_h_clk",1493 .ops = &clk_branch_ops,1494 },1495 },1496};1497 1498static struct clk_branch adm0_clk = {1499 .halt_reg = 0x2fdc,1500 .halt_check = BRANCH_HALT_VOTED,1501 .halt_bit = 14,1502 .clkr = {1503 .enable_reg = 0x3080,1504 .enable_mask = BIT(2),1505 .hw.init = &(struct clk_init_data){1506 .name = "adm0_clk",1507 .ops = &clk_branch_ops,1508 },1509 },1510};1511 1512static struct clk_branch adm0_pbus_clk = {1513 .hwcg_reg = 0x2208,1514 .hwcg_bit = 6,1515 .halt_reg = 0x2fdc,1516 .halt_check = BRANCH_HALT_VOTED,1517 .halt_bit = 13,1518 .clkr = {1519 .enable_reg = 0x3080,1520 .enable_mask = BIT(3),1521 .hw.init = &(struct clk_init_data){1522 .name = "adm0_pbus_clk",1523 .ops = &clk_branch_ops,1524 },1525 },1526};1527 1528static struct clk_branch pmic_arb0_h_clk = {1529 .halt_reg = 0x2fd8,1530 .halt_check = BRANCH_HALT_VOTED,1531 .halt_bit = 22,1532 .clkr = {1533 .enable_reg = 0x3080,1534 .enable_mask = BIT(8),1535 .hw.init = &(struct clk_init_data){1536 .name = "pmic_arb0_h_clk",1537 .ops = &clk_branch_ops,1538 },1539 },1540};1541 1542static struct clk_branch pmic_arb1_h_clk = {1543 .halt_reg = 0x2fd8,1544 .halt_check = BRANCH_HALT_VOTED,1545 .halt_bit = 21,1546 .clkr = {1547 .enable_reg = 0x3080,1548 .enable_mask = BIT(9),1549 .hw.init = &(struct clk_init_data){1550 .name = "pmic_arb1_h_clk",1551 .ops = &clk_branch_ops,1552 },1553 },1554};1555 1556static struct clk_branch pmic_ssbi2_clk = {1557 .halt_reg = 0x2fd8,1558 .halt_check = BRANCH_HALT_VOTED,1559 .halt_bit = 23,1560 .clkr = {1561 .enable_reg = 0x3080,1562 .enable_mask = BIT(7),1563 .hw.init = &(struct clk_init_data){1564 .name = "pmic_ssbi2_clk",1565 .ops = &clk_branch_ops,1566 },1567 },1568};1569 1570static struct clk_branch rpm_msg_ram_h_clk = {1571 .hwcg_reg = 0x27e0,1572 .hwcg_bit = 6,1573 .halt_reg = 0x2fd8,1574 .halt_check = BRANCH_HALT_VOTED,1575 .halt_bit = 12,1576 .clkr = {1577 .enable_reg = 0x3080,1578 .enable_mask = BIT(6),1579 .hw.init = &(struct clk_init_data){1580 .name = "rpm_msg_ram_h_clk",1581 .ops = &clk_branch_ops,1582 },1583 },1584};1585 1586static struct clk_branch ebi2_clk = {1587 .hwcg_reg = 0x2664,1588 .hwcg_bit = 6,1589 .halt_reg = 0x2fcc,1590 .halt_bit = 24,1591 .clkr = {1592 .enable_reg = 0x2664,1593 .enable_mask = BIT(6) | BIT(4),1594 .hw.init = &(struct clk_init_data){1595 .name = "ebi2_clk",1596 .ops = &clk_branch_ops,1597 },1598 },1599};1600 1601static struct clk_branch ebi2_aon_clk = {1602 .halt_reg = 0x2fcc,1603 .halt_bit = 23,1604 .clkr = {1605 .enable_reg = 0x2664,1606 .enable_mask = BIT(8),1607 .hw.init = &(struct clk_init_data){1608 .name = "ebi2_aon_clk",1609 .ops = &clk_branch_ops,1610 },1611 },1612};1613 1614static struct clk_regmap *gcc_mdm9615_clks[] = {1615 [PLL0] = &pll0.clkr,1616 [PLL0_VOTE] = &pll0_vote,1617 [PLL4_VOTE] = &pll4_vote,1618 [PLL8] = &pll8.clkr,1619 [PLL8_VOTE] = &pll8_vote,1620 [PLL14] = &pll14.clkr,1621 [PLL14_VOTE] = &pll14_vote,1622 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,1623 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,1624 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,1625 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,1626 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,1627 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,1628 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,1629 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,1630 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,1631 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,1632 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,1633 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,1634 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,1635 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,1636 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,1637 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,1638 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,1639 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,1640 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,1641 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,1642 [GP0_SRC] = &gp0_src.clkr,1643 [GP0_CLK] = &gp0_clk.clkr,1644 [GP1_SRC] = &gp1_src.clkr,1645 [GP1_CLK] = &gp1_clk.clkr,1646 [GP2_SRC] = &gp2_src.clkr,1647 [GP2_CLK] = &gp2_clk.clkr,1648 [PMEM_A_CLK] = &pmem_clk.clkr,1649 [PRNG_SRC] = &prng_src.clkr,1650 [PRNG_CLK] = &prng_clk.clkr,1651 [SDC1_SRC] = &sdc1_src.clkr,1652 [SDC1_CLK] = &sdc1_clk.clkr,1653 [SDC2_SRC] = &sdc2_src.clkr,1654 [SDC2_CLK] = &sdc2_clk.clkr,1655 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,1656 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,1657 [USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,1658 [USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,1659 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,1660 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,1661 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,1662 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,1663 [USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,1664 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,1665 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,1666 [CE1_CORE_CLK] = &ce1_core_clk.clkr,1667 [CE1_H_CLK] = &ce1_h_clk.clkr,1668 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,1669 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,1670 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,1671 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,1672 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,1673 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,1674 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,1675 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,1676 [SDC1_H_CLK] = &sdc1_h_clk.clkr,1677 [SDC2_H_CLK] = &sdc2_h_clk.clkr,1678 [ADM0_CLK] = &adm0_clk.clkr,1679 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,1680 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,1681 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,1682 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,1683 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,1684 [EBI2_CLK] = &ebi2_clk.clkr,1685 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,1686};1687 1688static const struct qcom_reset_map gcc_mdm9615_resets[] = {1689 [DMA_BAM_RESET] = { 0x25c0, 7 },1690 [CE1_H_RESET] = { 0x2720, 7 },1691 [CE1_CORE_RESET] = { 0x2724, 7 },1692 [SDC1_RESET] = { 0x2830 },1693 [SDC2_RESET] = { 0x2850 },1694 [ADM0_C2_RESET] = { 0x220c, 4 },1695 [ADM0_C1_RESET] = { 0x220c, 3 },1696 [ADM0_C0_RESET] = { 0x220c, 2 },1697 [ADM0_PBUS_RESET] = { 0x220c, 1 },1698 [ADM0_RESET] = { 0x220c },1699 [USB_HS1_RESET] = { 0x2910 },1700 [USB_HSIC_RESET] = { 0x2934 },1701 [GSBI1_RESET] = { 0x29dc },1702 [GSBI2_RESET] = { 0x29fc },1703 [GSBI3_RESET] = { 0x2a1c },1704 [GSBI4_RESET] = { 0x2a3c },1705 [GSBI5_RESET] = { 0x2a5c },1706 [PDM_RESET] = { 0x2CC0, 12 },1707};1708 1709static const struct regmap_config gcc_mdm9615_regmap_config = {1710 .reg_bits = 32,1711 .reg_stride = 4,1712 .val_bits = 32,1713 .max_register = 0x3660,1714 .fast_io = true,1715};1716 1717static const struct qcom_cc_desc gcc_mdm9615_desc = {1718 .config = &gcc_mdm9615_regmap_config,1719 .clks = gcc_mdm9615_clks,1720 .num_clks = ARRAY_SIZE(gcc_mdm9615_clks),1721 .resets = gcc_mdm9615_resets,1722 .num_resets = ARRAY_SIZE(gcc_mdm9615_resets),1723};1724 1725static const struct of_device_id gcc_mdm9615_match_table[] = {1726 { .compatible = "qcom,gcc-mdm9615" },1727 { }1728};1729MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);1730 1731static int gcc_mdm9615_probe(struct platform_device *pdev)1732{1733 struct regmap *regmap;1734 1735 regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);1736 if (IS_ERR(regmap))1737 return PTR_ERR(regmap);1738 1739 return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9615_desc, regmap);1740}1741 1742static struct platform_driver gcc_mdm9615_driver = {1743 .probe = gcc_mdm9615_probe,1744 .driver = {1745 .name = "gcc-mdm9615",1746 .of_match_table = gcc_mdm9615_match_table,1747 },1748};1749 1750static int __init gcc_mdm9615_init(void)1751{1752 return platform_driver_register(&gcc_mdm9615_driver);1753}1754core_initcall(gcc_mdm9615_init);1755 1756static void __exit gcc_mdm9615_exit(void)1757{1758 platform_driver_unregister(&gcc_mdm9615_driver);1759}1760module_exit(gcc_mdm9615_exit);1761 1762MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");1763MODULE_LICENSE("GPL v2");1764MODULE_ALIAS("platform:gcc-mdm9615");1765