2731 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2022 Kernkonzept GmbH.4 *5 * Based on gcc-msm8916.c:6 * Copyright 2015 Linaro Limited7 * adapted with data from clock-gcc-8909.c in Qualcomm's msm-3.18 release:8 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.9 */10 11#include <linux/bitops.h>12#include <linux/clk-provider.h>13#include <linux/err.h>14#include <linux/kernel.h>15#include <linux/module.h>16#include <linux/of.h>17#include <linux/platform_device.h>18#include <linux/regmap.h>19#include <linux/reset-controller.h>20 21#include <dt-bindings/clock/qcom,gcc-msm8909.h>22 23#include "clk-alpha-pll.h"24#include "clk-branch.h"25#include "clk-pll.h"26#include "clk-rcg.h"27#include "clk-regmap.h"28#include "common.h"29#include "gdsc.h"30#include "reset.h"31 32/* Need to match the order of clocks in DT binding */33enum {34 DT_XO,35 DT_SLEEP_CLK,36 DT_DSI0PLL,37 DT_DSI0PLL_BYTE,38};39 40enum {41 P_XO,42 P_SLEEP_CLK,43 P_GPLL0,44 P_GPLL1,45 P_GPLL2,46 P_BIMC,47 P_DSI0PLL,48 P_DSI0PLL_BYTE,49};50 51static const struct parent_map gcc_xo_map[] = {52 { P_XO, 0 },53};54 55static const struct clk_parent_data gcc_xo_data[] = {56 { .index = DT_XO },57};58 59static const struct clk_parent_data gcc_sleep_clk_data[] = {60 { .index = DT_SLEEP_CLK },61};62 63static struct clk_alpha_pll gpll0_early = {64 .offset = 0x21000,65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],66 .clkr = {67 .enable_reg = 0x45000,68 .enable_mask = BIT(0),69 .hw.init = &(struct clk_init_data) {70 .name = "gpll0_early",71 .parent_data = gcc_xo_data,72 .num_parents = ARRAY_SIZE(gcc_xo_data),73 /* Avoid rate changes for shared clock */74 .ops = &clk_alpha_pll_fixed_ops,75 },76 },77};78 79static struct clk_alpha_pll_postdiv gpll0 = {80 .offset = 0x21000,81 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],82 .clkr.hw.init = &(struct clk_init_data) {83 .name = "gpll0",84 .parent_hws = (const struct clk_hw*[]) {85 &gpll0_early.clkr.hw,86 },87 .num_parents = 1,88 /* Avoid rate changes for shared clock */89 .ops = &clk_alpha_pll_postdiv_ro_ops,90 },91};92 93static struct clk_pll gpll1 = {94 .l_reg = 0x20004,95 .m_reg = 0x20008,96 .n_reg = 0x2000c,97 .config_reg = 0x20010,98 .mode_reg = 0x20000,99 .status_reg = 0x2001c,100 .status_bit = 17,101 .clkr.hw.init = &(struct clk_init_data) {102 .name = "gpll1",103 .parent_data = gcc_xo_data,104 .num_parents = ARRAY_SIZE(gcc_xo_data),105 .ops = &clk_pll_ops,106 },107};108 109static struct clk_regmap gpll1_vote = {110 .enable_reg = 0x45000,111 .enable_mask = BIT(1),112 .hw.init = &(struct clk_init_data) {113 .name = "gpll1_vote",114 .parent_hws = (const struct clk_hw*[]) {115 &gpll1.clkr.hw,116 },117 .num_parents = 1,118 .ops = &clk_pll_vote_ops,119 },120};121 122static struct clk_alpha_pll gpll2_early = {123 .offset = 0x25000,124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],125 .clkr = {126 .enable_reg = 0x45000,127 .enable_mask = BIT(3),128 .hw.init = &(struct clk_init_data) {129 .name = "gpll2_early",130 .parent_data = gcc_xo_data,131 .num_parents = ARRAY_SIZE(gcc_xo_data),132 /* Avoid rate changes for shared clock */133 .ops = &clk_alpha_pll_fixed_ops,134 },135 },136};137 138static struct clk_alpha_pll_postdiv gpll2 = {139 .offset = 0x25000,140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],141 .clkr.hw.init = &(struct clk_init_data) {142 .name = "gpll2",143 .parent_hws = (const struct clk_hw*[]) {144 &gpll2_early.clkr.hw,145 },146 .num_parents = 1,147 /* Avoid rate changes for shared clock */148 .ops = &clk_alpha_pll_postdiv_ro_ops,149 },150};151 152static struct clk_alpha_pll bimc_pll_early = {153 .offset = 0x23000,154 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],155 .clkr = {156 .enable_reg = 0x45000,157 .enable_mask = BIT(2),158 .hw.init = &(struct clk_init_data) {159 .name = "bimc_pll_early",160 .parent_data = gcc_xo_data,161 .num_parents = ARRAY_SIZE(gcc_xo_data),162 /* Avoid rate changes for shared clock */163 .ops = &clk_alpha_pll_fixed_ops,164 },165 },166};167 168static struct clk_alpha_pll_postdiv bimc_pll = {169 .offset = 0x23000,170 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],171 .clkr.hw.init = &(struct clk_init_data) {172 .name = "bimc_pll",173 .parent_hws = (const struct clk_hw*[]) {174 &bimc_pll_early.clkr.hw,175 },176 .num_parents = 1,177 /* Avoid rate changes for shared clock */178 .ops = &clk_alpha_pll_postdiv_ro_ops,179 },180};181 182static const struct parent_map gcc_xo_gpll0_map[] = {183 { P_XO, 0 },184 { P_GPLL0, 1 },185};186 187static const struct clk_parent_data gcc_xo_gpll0_data[] = {188 { .index = DT_XO },189 { .hw = &gpll0.clkr.hw },190};191 192static const struct parent_map gcc_xo_gpll0_bimc_map[] = {193 { P_XO, 0 },194 { P_GPLL0, 1 },195 { P_BIMC, 2 },196};197 198static const struct clk_parent_data gcc_xo_gpll0_bimc_data[] = {199 { .index = DT_XO },200 { .hw = &gpll0.clkr.hw },201 { .hw = &bimc_pll.clkr.hw },202};203 204static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {205 F(19200000, P_XO, 1, 0, 0),206 F(50000000, P_GPLL0, 16, 0, 0),207 F(100000000, P_GPLL0, 8, 0, 0),208 { }209};210 211static struct clk_rcg2 apss_ahb_clk_src = {212 .cmd_rcgr = 0x46000,213 .hid_width = 5,214 .freq_tbl = ftbl_apss_ahb_clk_src,215 .parent_map = gcc_xo_gpll0_map,216 .clkr.hw.init = &(struct clk_init_data) {217 .name = "apss_ahb_clk_src",218 .parent_data = gcc_xo_gpll0_data,219 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),220 .ops = &clk_rcg2_ops,221 }222};223 224static struct clk_rcg2 bimc_ddr_clk_src = {225 .cmd_rcgr = 0x32004,226 .hid_width = 5,227 .parent_map = gcc_xo_gpll0_bimc_map,228 .clkr.hw.init = &(struct clk_init_data) {229 .name = "bimc_ddr_clk_src",230 .parent_data = gcc_xo_gpll0_bimc_data,231 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),232 .ops = &clk_rcg2_ops,233 .flags = CLK_GET_RATE_NOCACHE,234 },235};236 237static struct clk_rcg2 bimc_gpu_clk_src = {238 .cmd_rcgr = 0x31028,239 .hid_width = 5,240 .parent_map = gcc_xo_gpll0_bimc_map,241 .clkr.hw.init = &(struct clk_init_data) {242 .name = "bimc_gpu_clk_src",243 .parent_data = gcc_xo_gpll0_bimc_data,244 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),245 .ops = &clk_rcg2_ops,246 .flags = CLK_GET_RATE_NOCACHE,247 },248};249 250static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {251 F(19200000, P_XO, 1, 0, 0),252 F(50000000, P_GPLL0, 16, 0, 0),253 { }254};255 256static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {257 .cmd_rcgr = 0x0200c,258 .hid_width = 5,259 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,260 .parent_map = gcc_xo_gpll0_map,261 .clkr.hw.init = &(struct clk_init_data) {262 .name = "blsp1_qup1_i2c_apps_clk_src",263 .parent_data = gcc_xo_gpll0_data,264 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),265 .ops = &clk_rcg2_ops,266 }267};268 269static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {270 .cmd_rcgr = 0x03000,271 .hid_width = 5,272 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,273 .parent_map = gcc_xo_gpll0_map,274 .clkr.hw.init = &(struct clk_init_data) {275 .name = "blsp1_qup2_i2c_apps_clk_src",276 .parent_data = gcc_xo_gpll0_data,277 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),278 .ops = &clk_rcg2_ops,279 }280};281 282static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {283 .cmd_rcgr = 0x04000,284 .hid_width = 5,285 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,286 .parent_map = gcc_xo_gpll0_map,287 .clkr.hw.init = &(struct clk_init_data) {288 .name = "blsp1_qup3_i2c_apps_clk_src",289 .parent_data = gcc_xo_gpll0_data,290 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),291 .ops = &clk_rcg2_ops,292 }293};294 295static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {296 .cmd_rcgr = 0x05000,297 .hid_width = 5,298 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,299 .parent_map = gcc_xo_gpll0_map,300 .clkr.hw.init = &(struct clk_init_data) {301 .name = "blsp1_qup4_i2c_apps_clk_src",302 .parent_data = gcc_xo_gpll0_data,303 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),304 .ops = &clk_rcg2_ops,305 }306};307 308static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {309 .cmd_rcgr = 0x06000,310 .hid_width = 5,311 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,312 .parent_map = gcc_xo_gpll0_map,313 .clkr.hw.init = &(struct clk_init_data) {314 .name = "blsp1_qup5_i2c_apps_clk_src",315 .parent_data = gcc_xo_gpll0_data,316 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),317 .ops = &clk_rcg2_ops,318 }319};320 321static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {322 .cmd_rcgr = 0x07000,323 .hid_width = 5,324 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,325 .parent_map = gcc_xo_gpll0_map,326 .clkr.hw.init = &(struct clk_init_data) {327 .name = "blsp1_qup6_i2c_apps_clk_src",328 .parent_data = gcc_xo_gpll0_data,329 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),330 .ops = &clk_rcg2_ops,331 }332};333 334static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {335 F(960000, P_XO, 10, 1, 2),336 F(4800000, P_XO, 4, 0, 0),337 F(9600000, P_XO, 2, 0, 0),338 F(16000000, P_GPLL0, 10, 1, 5),339 F(19200000, P_XO, 1, 0, 0),340 F(25000000, P_GPLL0, 16, 1, 2),341 F(50000000, P_GPLL0, 16, 0, 0),342 { }343};344 345static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {346 .cmd_rcgr = 0x02024,347 .hid_width = 5,348 .mnd_width = 8,349 .freq_tbl = ftbl_blsp_spi_apps_clk_src,350 .parent_map = gcc_xo_gpll0_map,351 .clkr.hw.init = &(struct clk_init_data) {352 .name = "blsp1_qup1_spi_apps_clk_src",353 .parent_data = gcc_xo_gpll0_data,354 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),355 .ops = &clk_rcg2_ops,356 }357};358 359static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {360 .cmd_rcgr = 0x03014,361 .hid_width = 5,362 .mnd_width = 8,363 .freq_tbl = ftbl_blsp_spi_apps_clk_src,364 .parent_map = gcc_xo_gpll0_map,365 .clkr.hw.init = &(struct clk_init_data) {366 .name = "blsp1_qup2_spi_apps_clk_src",367 .parent_data = gcc_xo_gpll0_data,368 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),369 .ops = &clk_rcg2_ops,370 }371};372 373static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {374 .cmd_rcgr = 0x04024,375 .hid_width = 5,376 .mnd_width = 8,377 .freq_tbl = ftbl_blsp_spi_apps_clk_src,378 .parent_map = gcc_xo_gpll0_map,379 .clkr.hw.init = &(struct clk_init_data) {380 .name = "blsp1_qup3_spi_apps_clk_src",381 .parent_data = gcc_xo_gpll0_data,382 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),383 .ops = &clk_rcg2_ops,384 }385};386 387static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {388 .cmd_rcgr = 0x05024,389 .hid_width = 5,390 .mnd_width = 8,391 .freq_tbl = ftbl_blsp_spi_apps_clk_src,392 .parent_map = gcc_xo_gpll0_map,393 .clkr.hw.init = &(struct clk_init_data) {394 .name = "blsp1_qup4_spi_apps_clk_src",395 .parent_data = gcc_xo_gpll0_data,396 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),397 .ops = &clk_rcg2_ops,398 }399};400 401static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {402 .cmd_rcgr = 0x06024,403 .hid_width = 5,404 .mnd_width = 8,405 .freq_tbl = ftbl_blsp_spi_apps_clk_src,406 .parent_map = gcc_xo_gpll0_map,407 .clkr.hw.init = &(struct clk_init_data) {408 .name = "blsp1_qup5_spi_apps_clk_src",409 .parent_data = gcc_xo_gpll0_data,410 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),411 .ops = &clk_rcg2_ops,412 }413};414 415static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {416 .cmd_rcgr = 0x07024,417 .hid_width = 5,418 .mnd_width = 8,419 .freq_tbl = ftbl_blsp_spi_apps_clk_src,420 .parent_map = gcc_xo_gpll0_map,421 .clkr.hw.init = &(struct clk_init_data) {422 .name = "blsp1_qup6_spi_apps_clk_src",423 .parent_data = gcc_xo_gpll0_data,424 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),425 .ops = &clk_rcg2_ops,426 }427};428 429static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {430 F(3686400, P_GPLL0, 1, 72, 15625),431 F(7372800, P_GPLL0, 1, 144, 15625),432 F(14745600, P_GPLL0, 1, 288, 15625),433 F(16000000, P_GPLL0, 10, 1, 5),434 F(19200000, P_XO, 1, 0, 0),435 F(24000000, P_GPLL0, 1, 3, 100),436 F(25000000, P_GPLL0, 16, 1, 2),437 F(32000000, P_GPLL0, 1, 1, 25),438 F(40000000, P_GPLL0, 1, 1, 20),439 F(46400000, P_GPLL0, 1, 29, 500),440 F(48000000, P_GPLL0, 1, 3, 50),441 F(51200000, P_GPLL0, 1, 8, 125),442 F(56000000, P_GPLL0, 1, 7, 100),443 F(58982400, P_GPLL0, 1, 1152, 15625),444 F(60000000, P_GPLL0, 1, 3, 40),445 { }446};447 448static struct clk_rcg2 blsp1_uart1_apps_clk_src = {449 .cmd_rcgr = 0x02044,450 .hid_width = 5,451 .mnd_width = 16,452 .freq_tbl = ftbl_blsp_uart_apps_clk_src,453 .parent_map = gcc_xo_gpll0_map,454 .clkr.hw.init = &(struct clk_init_data) {455 .name = "blsp1_uart1_apps_clk_src",456 .parent_data = gcc_xo_gpll0_data,457 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),458 .ops = &clk_rcg2_ops,459 }460};461 462static struct clk_rcg2 blsp1_uart2_apps_clk_src = {463 .cmd_rcgr = 0x03034,464 .hid_width = 5,465 .mnd_width = 16,466 .freq_tbl = ftbl_blsp_uart_apps_clk_src,467 .parent_map = gcc_xo_gpll0_map,468 .clkr.hw.init = &(struct clk_init_data) {469 .name = "blsp1_uart2_apps_clk_src",470 .parent_data = gcc_xo_gpll0_data,471 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),472 .ops = &clk_rcg2_ops,473 }474};475 476static const struct parent_map gcc_byte0_map[] = {477 { P_XO, 0 },478 { P_DSI0PLL_BYTE, 1 },479};480 481static const struct clk_parent_data gcc_byte_data[] = {482 { .index = DT_XO },483 { .index = DT_DSI0PLL_BYTE },484};485 486static struct clk_rcg2 byte0_clk_src = {487 .cmd_rcgr = 0x4d044,488 .hid_width = 5,489 .parent_map = gcc_byte0_map,490 .clkr.hw.init = &(struct clk_init_data) {491 .name = "byte0_clk_src",492 .parent_data = gcc_byte_data,493 .num_parents = ARRAY_SIZE(gcc_byte_data),494 .ops = &clk_byte2_ops,495 .flags = CLK_SET_RATE_PARENT,496 }497};498 499static const struct freq_tbl ftbl_camss_gp_clk_src[] = {500 F(100000000, P_GPLL0, 8, 0, 0),501 F(200000000, P_GPLL0, 4, 0, 0),502 { }503};504 505static struct clk_rcg2 camss_gp0_clk_src = {506 .cmd_rcgr = 0x54000,507 .hid_width = 5,508 .mnd_width = 8,509 .freq_tbl = ftbl_camss_gp_clk_src,510 .parent_map = gcc_xo_gpll0_map,511 .clkr.hw.init = &(struct clk_init_data) {512 .name = "camss_gp0_clk_src",513 .parent_data = gcc_xo_gpll0_data,514 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),515 .ops = &clk_rcg2_ops,516 }517};518 519static struct clk_rcg2 camss_gp1_clk_src = {520 .cmd_rcgr = 0x55000,521 .hid_width = 5,522 .mnd_width = 8,523 .freq_tbl = ftbl_camss_gp_clk_src,524 .parent_map = gcc_xo_gpll0_map,525 .clkr.hw.init = &(struct clk_init_data) {526 .name = "camss_gp1_clk_src",527 .parent_data = gcc_xo_gpll0_data,528 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),529 .ops = &clk_rcg2_ops,530 }531};532 533static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {534 F(40000000, P_GPLL0, 10, 1, 2),535 F(80000000, P_GPLL0, 10, 0, 0),536 { }537};538 539static struct clk_rcg2 camss_top_ahb_clk_src = {540 .cmd_rcgr = 0x5a000,541 .hid_width = 5,542 .mnd_width = 8,543 .freq_tbl = ftbl_camss_top_ahb_clk_src,544 .parent_map = gcc_xo_gpll0_map,545 .clkr.hw.init = &(struct clk_init_data) {546 .name = "camss_top_ahb_clk_src",547 .parent_data = gcc_xo_gpll0_data,548 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),549 .ops = &clk_rcg2_ops,550 }551};552 553static const struct freq_tbl ftbl_crypto_clk_src[] = {554 F(50000000, P_GPLL0, 16, 0, 0),555 F(80000000, P_GPLL0, 10, 0, 0),556 F(100000000, P_GPLL0, 8, 0, 0),557 F(160000000, P_GPLL0, 5, 0, 0),558 { }559};560 561static struct clk_rcg2 crypto_clk_src = {562 .cmd_rcgr = 0x16004,563 .hid_width = 5,564 .freq_tbl = ftbl_crypto_clk_src,565 .parent_map = gcc_xo_gpll0_map,566 .clkr.hw.init = &(struct clk_init_data) {567 .name = "crypto_clk_src",568 .parent_data = gcc_xo_gpll0_data,569 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),570 .ops = &clk_rcg2_ops,571 }572};573 574static const struct freq_tbl ftbl_csi_clk_src[] = {575 F(100000000, P_GPLL0, 8, 0, 0),576 F(200000000, P_GPLL0, 4, 0, 0),577 { }578};579 580static struct clk_rcg2 csi0_clk_src = {581 .cmd_rcgr = 0x4e020,582 .hid_width = 5,583 .freq_tbl = ftbl_csi_clk_src,584 .parent_map = gcc_xo_gpll0_map,585 .clkr.hw.init = &(struct clk_init_data) {586 .name = "csi0_clk_src",587 .parent_data = gcc_xo_gpll0_data,588 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_map),589 .ops = &clk_rcg2_ops,590 }591};592 593static struct clk_rcg2 csi1_clk_src = {594 .cmd_rcgr = 0x4f020,595 .hid_width = 5,596 .freq_tbl = ftbl_csi_clk_src,597 .parent_map = gcc_xo_gpll0_map,598 .clkr.hw.init = &(struct clk_init_data) {599 .name = "csi1_clk_src",600 .parent_data = gcc_xo_gpll0_data,601 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),602 .ops = &clk_rcg2_ops,603 }604};605 606static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {607 F(100000000, P_GPLL0, 8, 0, 0),608 F(200000000, P_GPLL0, 4, 0, 0),609 { }610};611 612static struct clk_rcg2 csi0phytimer_clk_src = {613 .cmd_rcgr = 0x4e000,614 .hid_width = 5,615 .freq_tbl = ftbl_csi_phytimer_clk_src,616 .parent_map = gcc_xo_gpll0_map,617 .clkr.hw.init = &(struct clk_init_data) {618 .name = "csi0phytimer_clk_src",619 .parent_data = gcc_xo_gpll0_data,620 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),621 .ops = &clk_rcg2_ops,622 }623};624 625static const struct freq_tbl ftbl_esc0_clk_src[] = {626 F(19200000, P_XO, 1, 0, 0),627 { }628};629 630static struct clk_rcg2 esc0_clk_src = {631 .cmd_rcgr = 0x4d05c,632 .hid_width = 5,633 .freq_tbl = ftbl_esc0_clk_src,634 .parent_map = gcc_xo_map,635 .clkr.hw.init = &(struct clk_init_data) {636 .name = "esc0_clk_src",637 .parent_data = gcc_xo_data,638 .num_parents = ARRAY_SIZE(gcc_xo_data),639 .ops = &clk_rcg2_ops,640 }641};642 643static const struct parent_map gcc_gfx3d_map[] = {644 { P_XO, 0 },645 { P_GPLL0, 1 },646 { P_GPLL1, 2 },647};648 649static const struct clk_parent_data gcc_gfx3d_data[] = {650 { .index = DT_XO },651 { .hw = &gpll0.clkr.hw },652 { .hw = &gpll1_vote.hw },653};654 655static const struct freq_tbl ftbl_gfx3d_clk_src[] = {656 F(19200000, P_XO, 1, 0, 0),657 F(50000000, P_GPLL0, 16, 0, 0),658 F(80000000, P_GPLL0, 10, 0, 0),659 F(100000000, P_GPLL0, 8, 0, 0),660 F(160000000, P_GPLL0, 5, 0, 0),661 F(177780000, P_GPLL0, 4.5, 0, 0),662 F(200000000, P_GPLL0, 4, 0, 0),663 F(266670000, P_GPLL0, 3, 0, 0),664 F(307200000, P_GPLL1, 4, 0, 0),665 F(409600000, P_GPLL1, 3, 0, 0),666 { }667};668 669static struct clk_rcg2 gfx3d_clk_src = {670 .cmd_rcgr = 0x59000,671 .hid_width = 5,672 .freq_tbl = ftbl_gfx3d_clk_src,673 .parent_map = gcc_gfx3d_map,674 .clkr.hw.init = &(struct clk_init_data) {675 .name = "gfx3d_clk_src",676 .parent_data = gcc_gfx3d_data,677 .num_parents = ARRAY_SIZE(gcc_gfx3d_data),678 .ops = &clk_rcg2_ops,679 }680};681 682static const struct freq_tbl ftbl_gp_clk_src[] = {683 F(150000, P_XO, 1, 1, 128),684 F(19200000, P_XO, 1, 0, 0),685 { }686};687 688static struct clk_rcg2 gp1_clk_src = {689 .cmd_rcgr = 0x08004,690 .hid_width = 5,691 .mnd_width = 8,692 .freq_tbl = ftbl_gp_clk_src,693 .parent_map = gcc_xo_map,694 .clkr.hw.init = &(struct clk_init_data) {695 .name = "gp1_clk_src",696 .parent_data = gcc_xo_data,697 .num_parents = ARRAY_SIZE(gcc_xo_data),698 .ops = &clk_rcg2_ops,699 }700};701 702static struct clk_rcg2 gp2_clk_src = {703 .cmd_rcgr = 0x09004,704 .hid_width = 5,705 .mnd_width = 8,706 .freq_tbl = ftbl_gp_clk_src,707 .parent_map = gcc_xo_map,708 .clkr.hw.init = &(struct clk_init_data) {709 .name = "gp2_clk_src",710 .parent_data = gcc_xo_data,711 .num_parents = ARRAY_SIZE(gcc_xo_data),712 .ops = &clk_rcg2_ops,713 }714};715 716static struct clk_rcg2 gp3_clk_src = {717 .cmd_rcgr = 0x0a004,718 .hid_width = 5,719 .mnd_width = 8,720 .freq_tbl = ftbl_gp_clk_src,721 .parent_map = gcc_xo_map,722 .clkr.hw.init = &(struct clk_init_data) {723 .name = "gp3_clk_src",724 .parent_data = gcc_xo_data,725 .num_parents = ARRAY_SIZE(gcc_xo_data),726 .ops = &clk_rcg2_ops,727 }728};729 730static const struct parent_map gcc_mclk_map[] = {731 { P_XO, 0 },732 { P_GPLL0, 1 },733 { P_GPLL2, 3 },734};735 736static const struct clk_parent_data gcc_mclk_data[] = {737 { .index = DT_XO },738 { .hw = &gpll0.clkr.hw },739 { .hw = &gpll2.clkr.hw },740};741 742static const struct freq_tbl ftbl_mclk_clk_src[] = {743 F(24000000, P_GPLL2, 1, 1, 33),744 F(66667000, P_GPLL0, 12, 0, 0),745 { }746};747 748static struct clk_rcg2 mclk0_clk_src = {749 .cmd_rcgr = 0x52000,750 .hid_width = 5,751 .mnd_width = 8,752 .freq_tbl = ftbl_mclk_clk_src,753 .parent_map = gcc_mclk_map,754 .clkr.hw.init = &(struct clk_init_data) {755 .name = "mclk0_clk_src",756 .parent_data = gcc_mclk_data,757 .num_parents = ARRAY_SIZE(gcc_mclk_data),758 .ops = &clk_rcg2_ops,759 }760};761 762static struct clk_rcg2 mclk1_clk_src = {763 .cmd_rcgr = 0x53000,764 .hid_width = 5,765 .mnd_width = 8,766 .freq_tbl = ftbl_mclk_clk_src,767 .parent_map = gcc_mclk_map,768 .clkr.hw.init = &(struct clk_init_data) {769 .name = "mclk1_clk_src",770 .parent_data = gcc_mclk_data,771 .num_parents = ARRAY_SIZE(gcc_mclk_data),772 .ops = &clk_rcg2_ops,773 }774};775 776static const struct parent_map gcc_mdp_map[] = {777 { P_XO, 0 },778 { P_GPLL0, 1 },779 { P_GPLL1, 3 },780};781 782static const struct clk_parent_data gcc_mdp_data[] = {783 { .index = DT_XO },784 { .hw = &gpll0.clkr.hw },785 { .hw = &gpll1_vote.hw },786};787 788static const struct freq_tbl ftbl_mdp_clk_src[] = {789 F(50000000, P_GPLL0, 16, 0, 0),790 F(80000000, P_GPLL0, 10, 0, 0),791 F(100000000, P_GPLL0, 8, 0, 0),792 F(160000000, P_GPLL0, 5, 0, 0),793 F(177780000, P_GPLL0, 4.5, 0, 0),794 F(200000000, P_GPLL0, 4, 0, 0),795 F(266670000, P_GPLL0, 3, 0, 0),796 F(307200000, P_GPLL1, 4, 0, 0),797 { }798};799 800static struct clk_rcg2 mdp_clk_src = {801 .cmd_rcgr = 0x4d014,802 .hid_width = 5,803 .freq_tbl = ftbl_mdp_clk_src,804 .parent_map = gcc_mdp_map,805 .clkr.hw.init = &(struct clk_init_data) {806 .name = "mdp_clk_src",807 .parent_data = gcc_mdp_data,808 .num_parents = ARRAY_SIZE(gcc_mdp_data),809 .ops = &clk_rcg2_ops,810 }811};812 813static const struct parent_map gcc_pclk0_map[] = {814 { P_XO, 0 },815 { P_DSI0PLL, 1 },816};817 818static const struct clk_parent_data gcc_pclk_data[] = {819 { .index = DT_XO },820 { .index = DT_DSI0PLL },821};822 823static struct clk_rcg2 pclk0_clk_src = {824 .cmd_rcgr = 0x4d000,825 .hid_width = 5,826 .mnd_width = 8,827 .parent_map = gcc_pclk0_map,828 .clkr.hw.init = &(struct clk_init_data) {829 .name = "pclk0_clk_src",830 .parent_data = gcc_pclk_data,831 .num_parents = ARRAY_SIZE(gcc_pclk_data),832 .ops = &clk_pixel_ops,833 .flags = CLK_SET_RATE_PARENT,834 }835};836 837static struct clk_rcg2 pcnoc_bfdcd_clk_src = {838 .cmd_rcgr = 0x27000,839 .hid_width = 5,840 .parent_map = gcc_xo_gpll0_bimc_map,841 .clkr.hw.init = &(struct clk_init_data) {842 .name = "pcnoc_bfdcd_clk_src",843 .parent_data = gcc_xo_gpll0_bimc_data,844 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),845 .ops = &clk_rcg2_ops,846 },847};848 849static const struct freq_tbl ftbl_pdm2_clk_src[] = {850 F(64000000, P_GPLL0, 12.5, 0, 0),851 { }852};853 854static struct clk_rcg2 pdm2_clk_src = {855 .cmd_rcgr = 0x44010,856 .hid_width = 5,857 .freq_tbl = ftbl_pdm2_clk_src,858 .parent_map = gcc_xo_gpll0_map,859 .clkr.hw.init = &(struct clk_init_data) {860 .name = "pdm2_clk_src",861 .parent_data = gcc_xo_gpll0_data,862 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),863 .ops = &clk_rcg2_ops,864 }865};866 867static const struct freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = {868 F(144000, P_XO, 16, 3, 25),869 F(400000, P_XO, 12, 1, 4),870 F(20000000, P_GPLL0, 10, 1, 4),871 F(25000000, P_GPLL0, 16, 1, 2),872 F(50000000, P_GPLL0, 16, 0, 0),873 F(100000000, P_GPLL0, 8, 0, 0),874 F(177770000, P_GPLL0, 4.5, 0, 0),875 F(200000000, P_GPLL0, 4, 0, 0),876 { }877};878 879static struct clk_rcg2 sdcc1_apps_clk_src = {880 .cmd_rcgr = 0x42004,881 .hid_width = 5,882 .mnd_width = 8,883 .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,884 .parent_map = gcc_xo_gpll0_map,885 .clkr.hw.init = &(struct clk_init_data) {886 .name = "sdcc1_apps_clk_src",887 .parent_data = gcc_xo_gpll0_data,888 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),889 .ops = &clk_rcg2_floor_ops,890 }891};892 893static struct clk_rcg2 sdcc2_apps_clk_src = {894 .cmd_rcgr = 0x43004,895 .hid_width = 5,896 .mnd_width = 8,897 .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk,898 .parent_map = gcc_xo_gpll0_map,899 .clkr.hw.init = &(struct clk_init_data) {900 .name = "sdcc2_apps_clk_src",901 .parent_data = gcc_xo_gpll0_data,902 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),903 .ops = &clk_rcg2_floor_ops,904 }905};906 907static struct clk_rcg2 system_noc_bfdcd_clk_src = {908 .cmd_rcgr = 0x26004,909 .hid_width = 5,910 .parent_map = gcc_xo_gpll0_bimc_map,911 .clkr.hw.init = &(struct clk_init_data) {912 .name = "system_noc_bfdcd_clk_src",913 .parent_data = gcc_xo_gpll0_bimc_data,914 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data),915 .ops = &clk_rcg2_ops,916 },917};918 919static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {920 F(57140000, P_GPLL0, 14, 0, 0),921 F(80000000, P_GPLL0, 10, 0, 0),922 F(100000000, P_GPLL0, 8, 0, 0),923 { }924};925 926static struct clk_rcg2 usb_hs_system_clk_src = {927 .cmd_rcgr = 0x41010,928 .hid_width = 5,929 .freq_tbl = ftbl_gcc_usb_hs_system_clk,930 .parent_map = gcc_xo_gpll0_map,931 .clkr.hw.init = &(struct clk_init_data) {932 .name = "usb_hs_system_clk_src",933 .parent_data = gcc_xo_gpll0_data,934 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),935 .ops = &clk_rcg2_ops,936 }937};938 939static const struct parent_map gcc_vcodec0_map[] = {940 { P_XO, 0 },941 { P_GPLL0, 1 },942 { P_GPLL1, 3 },943};944 945static const struct clk_parent_data gcc_vcodec0_data[] = {946 { .index = DT_XO },947 { .hw = &gpll0.clkr.hw },948 { .hw = &gpll1_vote.hw },949};950 951static const struct freq_tbl ftbl_vcodec0_clk_src[] = {952 F(133330000, P_GPLL0, 6, 0, 0),953 F(266670000, P_GPLL0, 3, 0, 0),954 F(307200000, P_GPLL1, 4, 0, 0),955 { }956};957 958static struct clk_rcg2 vcodec0_clk_src = {959 .cmd_rcgr = 0x4c000,960 .hid_width = 5,961 .mnd_width = 8,962 .freq_tbl = ftbl_vcodec0_clk_src,963 .parent_map = gcc_vcodec0_map,964 .clkr.hw.init = &(struct clk_init_data) {965 .name = "vcodec0_clk_src",966 .parent_data = gcc_vcodec0_data,967 .num_parents = ARRAY_SIZE(gcc_vcodec0_data),968 .ops = &clk_rcg2_ops,969 }970};971 972static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {973 F(50000000, P_GPLL0, 16, 0, 0),974 F(80000000, P_GPLL0, 10, 0, 0),975 F(100000000, P_GPLL0, 8, 0, 0),976 F(133330000, P_GPLL0, 6, 0, 0),977 F(160000000, P_GPLL0, 5, 0, 0),978 F(177780000, P_GPLL0, 4.5, 0, 0),979 F(200000000, P_GPLL0, 4, 0, 0),980 F(266670000, P_GPLL0, 3, 0, 0),981 F(320000000, P_GPLL0, 2.5, 0, 0),982 { }983};984 985static struct clk_rcg2 vfe0_clk_src = {986 .cmd_rcgr = 0x58000,987 .hid_width = 5,988 .freq_tbl = ftbl_gcc_camss_vfe0_clk,989 .parent_map = gcc_xo_gpll0_map,990 .clkr.hw.init = &(struct clk_init_data) {991 .name = "vfe0_clk_src",992 .parent_data = gcc_xo_gpll0_data,993 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data),994 .ops = &clk_rcg2_ops,995 }996};997 998static const struct freq_tbl ftbl_vsync_clk_src[] = {999 F(19200000, P_XO, 1, 0, 0),1000 { }1001};1002 1003static struct clk_rcg2 vsync_clk_src = {1004 .cmd_rcgr = 0x4d02c,1005 .hid_width = 5,1006 .freq_tbl = ftbl_vsync_clk_src,1007 .parent_map = gcc_xo_map,1008 .clkr.hw.init = &(struct clk_init_data) {1009 .name = "vsync_clk_src",1010 .parent_data = gcc_xo_data,1011 .num_parents = ARRAY_SIZE(gcc_xo_data),1012 .ops = &clk_rcg2_ops,1013 }1014};1015 1016static struct clk_branch gcc_apss_tcu_clk = {1017 .halt_reg = 0x12018,1018 .halt_check = BRANCH_HALT_VOTED,1019 .clkr = {1020 .enable_reg = 0x4500c,1021 .enable_mask = BIT(1),1022 .hw.init = &(struct clk_init_data) {1023 .name = "gcc_apss_tcu_clk",1024 .parent_hws = (const struct clk_hw*[]) {1025 &bimc_ddr_clk_src.clkr.hw,1026 },1027 .num_parents = 1,1028 .ops = &clk_branch2_ops,1029 }1030 }1031};1032 1033static struct clk_branch gcc_blsp1_ahb_clk = {1034 .halt_reg = 0x01008,1035 .halt_check = BRANCH_HALT_VOTED,1036 .clkr = {1037 .enable_reg = 0x45004,1038 .enable_mask = BIT(10),1039 .hw.init = &(struct clk_init_data) {1040 .name = "gcc_blsp1_ahb_clk",1041 .parent_hws = (const struct clk_hw*[]) {1042 &pcnoc_bfdcd_clk_src.clkr.hw,1043 },1044 .num_parents = 1,1045 .ops = &clk_branch2_ops,1046 }1047 }1048};1049 1050static struct clk_branch gcc_blsp1_sleep_clk = {1051 .halt_reg = 0x01004,1052 .halt_check = BRANCH_HALT_VOTED,1053 .clkr = {1054 .enable_reg = 0x45004,1055 .enable_mask = BIT(9),1056 .hw.init = &(struct clk_init_data) {1057 .name = "gcc_blsp1_sleep_clk",1058 .parent_data = gcc_sleep_clk_data,1059 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),1060 .ops = &clk_branch2_ops,1061 }1062 }1063};1064 1065static struct clk_branch gcc_boot_rom_ahb_clk = {1066 .halt_reg = 0x1300c,1067 .halt_check = BRANCH_HALT_VOTED,1068 .clkr = {1069 .enable_reg = 0x45004,1070 .enable_mask = BIT(7),1071 .hw.init = &(struct clk_init_data) {1072 .name = "gcc_boot_rom_ahb_clk",1073 .parent_hws = (const struct clk_hw*[]) {1074 &pcnoc_bfdcd_clk_src.clkr.hw,1075 },1076 .num_parents = 1,1077 .ops = &clk_branch2_ops,1078 }1079 }1080};1081 1082static struct clk_branch gcc_crypto_clk = {1083 .halt_reg = 0x1601c,1084 .halt_check = BRANCH_HALT_VOTED,1085 .clkr = {1086 .enable_reg = 0x45004,1087 .enable_mask = BIT(2),1088 .hw.init = &(struct clk_init_data) {1089 .name = "gcc_crypto_clk",1090 .parent_hws = (const struct clk_hw*[]) {1091 &crypto_clk_src.clkr.hw,1092 },1093 .num_parents = 1,1094 .ops = &clk_branch2_ops,1095 .flags = CLK_SET_RATE_PARENT,1096 }1097 }1098};1099 1100static struct clk_branch gcc_crypto_ahb_clk = {1101 .halt_reg = 0x16024,1102 .halt_check = BRANCH_HALT_VOTED,1103 .clkr = {1104 .enable_reg = 0x45004,1105 .enable_mask = BIT(0),1106 .hw.init = &(struct clk_init_data) {1107 .name = "gcc_crypto_ahb_clk",1108 .parent_hws = (const struct clk_hw*[]) {1109 &pcnoc_bfdcd_clk_src.clkr.hw,1110 },1111 .num_parents = 1,1112 .ops = &clk_branch2_ops,1113 }1114 }1115};1116 1117static struct clk_branch gcc_crypto_axi_clk = {1118 .halt_reg = 0x16020,1119 .halt_check = BRANCH_HALT_VOTED,1120 .clkr = {1121 .enable_reg = 0x45004,1122 .enable_mask = BIT(1),1123 .hw.init = &(struct clk_init_data) {1124 .name = "gcc_crypto_axi_clk",1125 .parent_hws = (const struct clk_hw*[]) {1126 &pcnoc_bfdcd_clk_src.clkr.hw,1127 },1128 .num_parents = 1,1129 .ops = &clk_branch2_ops,1130 }1131 }1132};1133 1134static struct clk_branch gcc_gfx_tbu_clk = {1135 .halt_reg = 0x12010,1136 .halt_check = BRANCH_HALT_VOTED,1137 .clkr = {1138 .enable_reg = 0x4500c,1139 .enable_mask = BIT(3),1140 .hw.init = &(struct clk_init_data) {1141 .name = "gcc_gfx_tbu_clk",1142 .parent_hws = (const struct clk_hw*[]) {1143 &bimc_ddr_clk_src.clkr.hw,1144 },1145 .num_parents = 1,1146 .ops = &clk_branch2_ops,1147 }1148 }1149};1150 1151static struct clk_branch gcc_gfx_tcu_clk = {1152 .halt_reg = 0x12020,1153 .halt_check = BRANCH_HALT_VOTED,1154 .clkr = {1155 .enable_reg = 0x4500c,1156 .enable_mask = BIT(2),1157 .hw.init = &(struct clk_init_data) {1158 .name = "gcc_gfx_tcu_clk",1159 .parent_hws = (const struct clk_hw*[]) {1160 &bimc_ddr_clk_src.clkr.hw,1161 },1162 .num_parents = 1,1163 .ops = &clk_branch2_ops,1164 }1165 }1166};1167 1168static struct clk_branch gcc_gtcu_ahb_clk = {1169 .halt_reg = 0x12044,1170 .halt_check = BRANCH_HALT_VOTED,1171 .clkr = {1172 .enable_reg = 0x4500c,1173 .enable_mask = BIT(13),1174 .hw.init = &(struct clk_init_data) {1175 .name = "gcc_gtcu_ahb_clk",1176 .parent_hws = (const struct clk_hw*[]) {1177 &pcnoc_bfdcd_clk_src.clkr.hw,1178 },1179 .num_parents = 1,1180 .ops = &clk_branch2_ops,1181 }1182 }1183};1184 1185static struct clk_branch gcc_mdp_tbu_clk = {1186 .halt_reg = 0x1201c,1187 .halt_check = BRANCH_HALT_VOTED,1188 .clkr = {1189 .enable_reg = 0x4500c,1190 .enable_mask = BIT(4),1191 .hw.init = &(struct clk_init_data) {1192 .name = "gcc_mdp_tbu_clk",1193 .parent_hws = (const struct clk_hw*[]) {1194 &system_noc_bfdcd_clk_src.clkr.hw,1195 },1196 .num_parents = 1,1197 .ops = &clk_branch2_ops,1198 }1199 }1200};1201 1202static struct clk_branch gcc_prng_ahb_clk = {1203 .halt_reg = 0x13004,1204 .halt_check = BRANCH_HALT_VOTED,1205 .clkr = {1206 .enable_reg = 0x45004,1207 .enable_mask = BIT(8),1208 .hw.init = &(struct clk_init_data) {1209 .name = "gcc_prng_ahb_clk",1210 .parent_hws = (const struct clk_hw*[]) {1211 &pcnoc_bfdcd_clk_src.clkr.hw,1212 },1213 .num_parents = 1,1214 .ops = &clk_branch2_ops,1215 }1216 }1217};1218 1219static struct clk_branch gcc_smmu_cfg_clk = {1220 .halt_reg = 0x12038,1221 .halt_check = BRANCH_HALT_VOTED,1222 .clkr = {1223 .enable_reg = 0x4500c,1224 .enable_mask = BIT(12),1225 .hw.init = &(struct clk_init_data) {1226 .name = "gcc_smmu_cfg_clk",1227 .parent_hws = (const struct clk_hw*[]) {1228 &pcnoc_bfdcd_clk_src.clkr.hw,1229 },1230 .num_parents = 1,1231 .ops = &clk_branch2_ops,1232 }1233 }1234};1235 1236static struct clk_branch gcc_venus_tbu_clk = {1237 .halt_reg = 0x12014,1238 .halt_check = BRANCH_HALT_VOTED,1239 .clkr = {1240 .enable_reg = 0x4500c,1241 .enable_mask = BIT(5),1242 .hw.init = &(struct clk_init_data) {1243 .name = "gcc_venus_tbu_clk",1244 .parent_hws = (const struct clk_hw*[]) {1245 &system_noc_bfdcd_clk_src.clkr.hw,1246 },1247 .num_parents = 1,1248 .ops = &clk_branch2_ops,1249 }1250 }1251};1252 1253static struct clk_branch gcc_vfe_tbu_clk = {1254 .halt_reg = 0x1203c,1255 .halt_check = BRANCH_HALT_VOTED,1256 .clkr = {1257 .enable_reg = 0x4500c,1258 .enable_mask = BIT(9),1259 .hw.init = &(struct clk_init_data) {1260 .name = "gcc_vfe_tbu_clk",1261 .parent_hws = (const struct clk_hw*[]) {1262 &system_noc_bfdcd_clk_src.clkr.hw,1263 },1264 .num_parents = 1,1265 .ops = &clk_branch2_ops,1266 }1267 }1268};1269 1270static struct clk_branch gcc_bimc_gfx_clk = {1271 .halt_reg = 0x31024,1272 .halt_check = BRANCH_HALT,1273 .clkr = {1274 .enable_reg = 0x31024,1275 .enable_mask = BIT(0),1276 .hw.init = &(struct clk_init_data) {1277 .name = "gcc_bimc_gfx_clk",1278 .parent_hws = (const struct clk_hw*[]) {1279 &bimc_gpu_clk_src.clkr.hw,1280 },1281 .num_parents = 1,1282 .ops = &clk_branch2_ops,1283 }1284 }1285};1286 1287static struct clk_branch gcc_bimc_gpu_clk = {1288 .halt_reg = 0x31040,1289 .halt_check = BRANCH_HALT,1290 .clkr = {1291 .enable_reg = 0x31040,1292 .enable_mask = BIT(0),1293 .hw.init = &(struct clk_init_data) {1294 .name = "gcc_bimc_gpu_clk",1295 .parent_hws = (const struct clk_hw*[]) {1296 &bimc_gpu_clk_src.clkr.hw,1297 },1298 .num_parents = 1,1299 .ops = &clk_branch2_ops,1300 }1301 }1302};1303 1304static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {1305 .halt_reg = 0x02008,1306 .halt_check = BRANCH_HALT,1307 .clkr = {1308 .enable_reg = 0x02008,1309 .enable_mask = BIT(0),1310 .hw.init = &(struct clk_init_data) {1311 .name = "gcc_blsp1_qup1_i2c_apps_clk",1312 .parent_hws = (const struct clk_hw*[]) {1313 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,1314 },1315 .num_parents = 1,1316 .ops = &clk_branch2_ops,1317 .flags = CLK_SET_RATE_PARENT,1318 }1319 }1320};1321 1322static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {1323 .halt_reg = 0x03010,1324 .halt_check = BRANCH_HALT,1325 .clkr = {1326 .enable_reg = 0x03010,1327 .enable_mask = BIT(0),1328 .hw.init = &(struct clk_init_data) {1329 .name = "gcc_blsp1_qup2_i2c_apps_clk",1330 .parent_hws = (const struct clk_hw*[]) {1331 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,1332 },1333 .num_parents = 1,1334 .ops = &clk_branch2_ops,1335 .flags = CLK_SET_RATE_PARENT,1336 }1337 }1338};1339 1340static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {1341 .halt_reg = 0x04020,1342 .halt_check = BRANCH_HALT,1343 .clkr = {1344 .enable_reg = 0x04020,1345 .enable_mask = BIT(0),1346 .hw.init = &(struct clk_init_data) {1347 .name = "gcc_blsp1_qup3_i2c_apps_clk",1348 .parent_hws = (const struct clk_hw*[]) {1349 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,1350 },1351 .num_parents = 1,1352 .ops = &clk_branch2_ops,1353 .flags = CLK_SET_RATE_PARENT,1354 }1355 }1356};1357 1358static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {1359 .halt_reg = 0x05020,1360 .halt_check = BRANCH_HALT,1361 .clkr = {1362 .enable_reg = 0x05020,1363 .enable_mask = BIT(0),1364 .hw.init = &(struct clk_init_data) {1365 .name = "gcc_blsp1_qup4_i2c_apps_clk",1366 .parent_hws = (const struct clk_hw*[]) {1367 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,1368 },1369 .num_parents = 1,1370 .ops = &clk_branch2_ops,1371 .flags = CLK_SET_RATE_PARENT,1372 }1373 }1374};1375 1376static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {1377 .halt_reg = 0x06020,1378 .halt_check = BRANCH_HALT,1379 .clkr = {1380 .enable_reg = 0x06020,1381 .enable_mask = BIT(0),1382 .hw.init = &(struct clk_init_data) {1383 .name = "gcc_blsp1_qup5_i2c_apps_clk",1384 .parent_hws = (const struct clk_hw*[]) {1385 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,1386 },1387 .num_parents = 1,1388 .ops = &clk_branch2_ops,1389 .flags = CLK_SET_RATE_PARENT,1390 }1391 }1392};1393 1394static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {1395 .halt_reg = 0x07020,1396 .halt_check = BRANCH_HALT,1397 .clkr = {1398 .enable_reg = 0x07020,1399 .enable_mask = BIT(0),1400 .hw.init = &(struct clk_init_data) {1401 .name = "gcc_blsp1_qup6_i2c_apps_clk",1402 .parent_hws = (const struct clk_hw*[]) {1403 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,1404 },1405 .num_parents = 1,1406 .ops = &clk_branch2_ops,1407 .flags = CLK_SET_RATE_PARENT,1408 }1409 }1410};1411 1412static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {1413 .halt_reg = 0x02004,1414 .halt_check = BRANCH_HALT,1415 .clkr = {1416 .enable_reg = 0x02004,1417 .enable_mask = BIT(0),1418 .hw.init = &(struct clk_init_data) {1419 .name = "gcc_blsp1_qup1_spi_apps_clk",1420 .parent_hws = (const struct clk_hw*[]) {1421 &blsp1_qup1_spi_apps_clk_src.clkr.hw,1422 },1423 .num_parents = 1,1424 .ops = &clk_branch2_ops,1425 .flags = CLK_SET_RATE_PARENT,1426 }1427 }1428};1429 1430static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {1431 .halt_reg = 0x0300c,1432 .halt_check = BRANCH_HALT,1433 .clkr = {1434 .enable_reg = 0x0300c,1435 .enable_mask = BIT(0),1436 .hw.init = &(struct clk_init_data) {1437 .name = "gcc_blsp1_qup2_spi_apps_clk",1438 .parent_hws = (const struct clk_hw*[]) {1439 &blsp1_qup2_spi_apps_clk_src.clkr.hw,1440 },1441 .num_parents = 1,1442 .ops = &clk_branch2_ops,1443 .flags = CLK_SET_RATE_PARENT,1444 }1445 }1446};1447 1448static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {1449 .halt_reg = 0x0401c,1450 .halt_check = BRANCH_HALT,1451 .clkr = {1452 .enable_reg = 0x0401c,1453 .enable_mask = BIT(0),1454 .hw.init = &(struct clk_init_data) {1455 .name = "gcc_blsp1_qup3_spi_apps_clk",1456 .parent_hws = (const struct clk_hw*[]) {1457 &blsp1_qup3_spi_apps_clk_src.clkr.hw,1458 },1459 .num_parents = 1,1460 .ops = &clk_branch2_ops,1461 .flags = CLK_SET_RATE_PARENT,1462 }1463 }1464};1465 1466static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {1467 .halt_reg = 0x0501c,1468 .halt_check = BRANCH_HALT,1469 .clkr = {1470 .enable_reg = 0x0501c,1471 .enable_mask = BIT(0),1472 .hw.init = &(struct clk_init_data) {1473 .name = "gcc_blsp1_qup4_spi_apps_clk",1474 .parent_hws = (const struct clk_hw*[]) {1475 &blsp1_qup4_spi_apps_clk_src.clkr.hw,1476 },1477 .num_parents = 1,1478 .ops = &clk_branch2_ops,1479 .flags = CLK_SET_RATE_PARENT,1480 }1481 }1482};1483 1484static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {1485 .halt_reg = 0x0601c,1486 .halt_check = BRANCH_HALT,1487 .clkr = {1488 .enable_reg = 0x0601c,1489 .enable_mask = BIT(0),1490 .hw.init = &(struct clk_init_data) {1491 .name = "gcc_blsp1_qup5_spi_apps_clk",1492 .parent_hws = (const struct clk_hw*[]) {1493 &blsp1_qup5_spi_apps_clk_src.clkr.hw,1494 },1495 .num_parents = 1,1496 .ops = &clk_branch2_ops,1497 .flags = CLK_SET_RATE_PARENT,1498 }1499 }1500};1501 1502static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {1503 .halt_reg = 0x0701c,1504 .halt_check = BRANCH_HALT,1505 .clkr = {1506 .enable_reg = 0x0701c,1507 .enable_mask = BIT(0),1508 .hw.init = &(struct clk_init_data) {1509 .name = "gcc_blsp1_qup6_spi_apps_clk",1510 .parent_hws = (const struct clk_hw*[]) {1511 &blsp1_qup6_spi_apps_clk_src.clkr.hw,1512 },1513 .num_parents = 1,1514 .ops = &clk_branch2_ops,1515 .flags = CLK_SET_RATE_PARENT,1516 }1517 }1518};1519 1520static struct clk_branch gcc_blsp1_uart1_apps_clk = {1521 .halt_reg = 0x0203c,1522 .halt_check = BRANCH_HALT,1523 .clkr = {1524 .enable_reg = 0x0203c,1525 .enable_mask = BIT(0),1526 .hw.init = &(struct clk_init_data) {1527 .name = "gcc_blsp1_uart1_apps_clk",1528 .parent_hws = (const struct clk_hw*[]) {1529 &blsp1_uart1_apps_clk_src.clkr.hw,1530 },1531 .num_parents = 1,1532 .ops = &clk_branch2_ops,1533 .flags = CLK_SET_RATE_PARENT,1534 }1535 }1536};1537 1538static struct clk_branch gcc_blsp1_uart2_apps_clk = {1539 .halt_reg = 0x0302c,1540 .halt_check = BRANCH_HALT,1541 .clkr = {1542 .enable_reg = 0x0302c,1543 .enable_mask = BIT(0),1544 .hw.init = &(struct clk_init_data) {1545 .name = "gcc_blsp1_uart2_apps_clk",1546 .parent_hws = (const struct clk_hw*[]) {1547 &blsp1_uart2_apps_clk_src.clkr.hw,1548 },1549 .num_parents = 1,1550 .ops = &clk_branch2_ops,1551 .flags = CLK_SET_RATE_PARENT,1552 }1553 }1554};1555 1556static struct clk_branch gcc_camss_ahb_clk = {1557 .halt_reg = 0x5a014,1558 .halt_check = BRANCH_HALT,1559 .clkr = {1560 .enable_reg = 0x5a014,1561 .enable_mask = BIT(0),1562 .hw.init = &(struct clk_init_data) {1563 .name = "gcc_camss_ahb_clk",1564 .parent_hws = (const struct clk_hw*[]) {1565 &pcnoc_bfdcd_clk_src.clkr.hw,1566 },1567 .num_parents = 1,1568 .ops = &clk_branch2_ops,1569 }1570 }1571};1572 1573static struct clk_branch gcc_camss_csi0_clk = {1574 .halt_reg = 0x4e03c,1575 .halt_check = BRANCH_HALT,1576 .clkr = {1577 .enable_reg = 0x4e03c,1578 .enable_mask = BIT(0),1579 .hw.init = &(struct clk_init_data) {1580 .name = "gcc_camss_csi0_clk",1581 .parent_hws = (const struct clk_hw*[]) {1582 &csi0_clk_src.clkr.hw,1583 },1584 .num_parents = 1,1585 .ops = &clk_branch2_ops,1586 .flags = CLK_SET_RATE_PARENT,1587 }1588 }1589};1590 1591static struct clk_branch gcc_camss_csi0_ahb_clk = {1592 .halt_reg = 0x4e040,1593 .halt_check = BRANCH_HALT,1594 .clkr = {1595 .enable_reg = 0x4e040,1596 .enable_mask = BIT(0),1597 .hw.init = &(struct clk_init_data) {1598 .name = "gcc_camss_csi0_ahb_clk",1599 .parent_hws = (const struct clk_hw*[]) {1600 &camss_top_ahb_clk_src.clkr.hw,1601 },1602 .num_parents = 1,1603 .ops = &clk_branch2_ops,1604 .flags = CLK_SET_RATE_PARENT,1605 }1606 }1607};1608 1609static struct clk_branch gcc_camss_csi0phy_clk = {1610 .halt_reg = 0x4e048,1611 .halt_check = BRANCH_HALT,1612 .clkr = {1613 .enable_reg = 0x4e048,1614 .enable_mask = BIT(0),1615 .hw.init = &(struct clk_init_data) {1616 .name = "gcc_camss_csi0phy_clk",1617 .parent_hws = (const struct clk_hw*[]) {1618 &csi0_clk_src.clkr.hw,1619 },1620 .num_parents = 1,1621 .ops = &clk_branch2_ops,1622 .flags = CLK_SET_RATE_PARENT,1623 }1624 }1625};1626 1627static struct clk_branch gcc_camss_csi0phytimer_clk = {1628 .halt_reg = 0x4e01c,1629 .halt_check = BRANCH_HALT,1630 .clkr = {1631 .enable_reg = 0x4e01c,1632 .enable_mask = BIT(0),1633 .hw.init = &(struct clk_init_data) {1634 .name = "gcc_camss_csi0phytimer_clk",1635 .parent_hws = (const struct clk_hw*[]) {1636 &csi0phytimer_clk_src.clkr.hw,1637 },1638 .num_parents = 1,1639 .ops = &clk_branch2_ops,1640 .flags = CLK_SET_RATE_PARENT,1641 }1642 }1643};1644 1645static struct clk_branch gcc_camss_csi0pix_clk = {1646 .halt_reg = 0x4e058,1647 .halt_check = BRANCH_HALT,1648 .clkr = {1649 .enable_reg = 0x4e058,1650 .enable_mask = BIT(0),1651 .hw.init = &(struct clk_init_data) {1652 .name = "gcc_camss_csi0pix_clk",1653 .parent_hws = (const struct clk_hw*[]) {1654 &csi0_clk_src.clkr.hw,1655 },1656 .num_parents = 1,1657 .ops = &clk_branch2_ops,1658 .flags = CLK_SET_RATE_PARENT,1659 }1660 }1661};1662 1663static struct clk_branch gcc_camss_csi0rdi_clk = {1664 .halt_reg = 0x4e050,1665 .halt_check = BRANCH_HALT,1666 .clkr = {1667 .enable_reg = 0x4e050,1668 .enable_mask = BIT(0),1669 .hw.init = &(struct clk_init_data) {1670 .name = "gcc_camss_csi0rdi_clk",1671 .parent_hws = (const struct clk_hw*[]) {1672 &csi0_clk_src.clkr.hw,1673 },1674 .num_parents = 1,1675 .ops = &clk_branch2_ops,1676 .flags = CLK_SET_RATE_PARENT,1677 }1678 }1679};1680 1681static struct clk_branch gcc_camss_csi1_clk = {1682 .halt_reg = 0x4f03c,1683 .halt_check = BRANCH_HALT,1684 .clkr = {1685 .enable_reg = 0x4f03c,1686 .enable_mask = BIT(0),1687 .hw.init = &(struct clk_init_data) {1688 .name = "gcc_camss_csi1_clk",1689 .parent_hws = (const struct clk_hw*[]) {1690 &csi1_clk_src.clkr.hw,1691 },1692 .num_parents = 1,1693 .ops = &clk_branch2_ops,1694 .flags = CLK_SET_RATE_PARENT,1695 }1696 }1697};1698 1699static struct clk_branch gcc_camss_csi1_ahb_clk = {1700 .halt_reg = 0x4f040,1701 .halt_check = BRANCH_HALT,1702 .clkr = {1703 .enable_reg = 0x4f040,1704 .enable_mask = BIT(0),1705 .hw.init = &(struct clk_init_data) {1706 .name = "gcc_camss_csi1_ahb_clk",1707 .parent_hws = (const struct clk_hw*[]) {1708 &camss_top_ahb_clk_src.clkr.hw,1709 },1710 .num_parents = 1,1711 .ops = &clk_branch2_ops,1712 .flags = CLK_SET_RATE_PARENT,1713 }1714 }1715};1716 1717static struct clk_branch gcc_camss_csi1phy_clk = {1718 .halt_reg = 0x4f048,1719 .halt_check = BRANCH_HALT,1720 .clkr = {1721 .enable_reg = 0x4f048,1722 .enable_mask = BIT(0),1723 .hw.init = &(struct clk_init_data) {1724 .name = "gcc_camss_csi1phy_clk",1725 .parent_hws = (const struct clk_hw*[]) {1726 &csi1_clk_src.clkr.hw,1727 },1728 .num_parents = 1,1729 .ops = &clk_branch2_ops,1730 .flags = CLK_SET_RATE_PARENT,1731 }1732 }1733};1734 1735static struct clk_branch gcc_camss_csi1pix_clk = {1736 .halt_reg = 0x4f058,1737 .halt_check = BRANCH_HALT,1738 .clkr = {1739 .enable_reg = 0x4f058,1740 .enable_mask = BIT(0),1741 .hw.init = &(struct clk_init_data) {1742 .name = "gcc_camss_csi1pix_clk",1743 .parent_hws = (const struct clk_hw*[]) {1744 &csi1_clk_src.clkr.hw,1745 },1746 .num_parents = 1,1747 .ops = &clk_branch2_ops,1748 .flags = CLK_SET_RATE_PARENT,1749 }1750 }1751};1752 1753static struct clk_branch gcc_camss_csi1rdi_clk = {1754 .halt_reg = 0x4f050,1755 .halt_check = BRANCH_HALT,1756 .clkr = {1757 .enable_reg = 0x4f050,1758 .enable_mask = BIT(0),1759 .hw.init = &(struct clk_init_data) {1760 .name = "gcc_camss_csi1rdi_clk",1761 .parent_hws = (const struct clk_hw*[]) {1762 &csi1_clk_src.clkr.hw,1763 },1764 .num_parents = 1,1765 .ops = &clk_branch2_ops,1766 .flags = CLK_SET_RATE_PARENT,1767 }1768 }1769};1770 1771static struct clk_branch gcc_camss_csi_vfe0_clk = {1772 .halt_reg = 0x58050,1773 .halt_check = BRANCH_HALT,1774 .clkr = {1775 .enable_reg = 0x58050,1776 .enable_mask = BIT(0),1777 .hw.init = &(struct clk_init_data) {1778 .name = "gcc_camss_csi_vfe0_clk",1779 .parent_hws = (const struct clk_hw*[]) {1780 &vfe0_clk_src.clkr.hw,1781 },1782 .num_parents = 1,1783 .ops = &clk_branch2_ops,1784 .flags = CLK_SET_RATE_PARENT,1785 }1786 }1787};1788 1789static struct clk_branch gcc_camss_gp0_clk = {1790 .halt_reg = 0x54018,1791 .halt_check = BRANCH_HALT,1792 .clkr = {1793 .enable_reg = 0x54018,1794 .enable_mask = BIT(0),1795 .hw.init = &(struct clk_init_data) {1796 .name = "gcc_camss_gp0_clk",1797 .parent_hws = (const struct clk_hw*[]) {1798 &camss_gp0_clk_src.clkr.hw,1799 },1800 .num_parents = 1,1801 .ops = &clk_branch2_ops,1802 .flags = CLK_SET_RATE_PARENT,1803 }1804 }1805};1806 1807static struct clk_branch gcc_camss_gp1_clk = {1808 .halt_reg = 0x55018,1809 .halt_check = BRANCH_HALT,1810 .clkr = {1811 .enable_reg = 0x55018,1812 .enable_mask = BIT(0),1813 .hw.init = &(struct clk_init_data) {1814 .name = "gcc_camss_gp1_clk",1815 .parent_hws = (const struct clk_hw*[]) {1816 &camss_gp1_clk_src.clkr.hw,1817 },1818 .num_parents = 1,1819 .ops = &clk_branch2_ops,1820 .flags = CLK_SET_RATE_PARENT,1821 }1822 }1823};1824 1825static struct clk_branch gcc_camss_ispif_ahb_clk = {1826 .halt_reg = 0x50004,1827 .halt_check = BRANCH_HALT,1828 .clkr = {1829 .enable_reg = 0x50004,1830 .enable_mask = BIT(0),1831 .hw.init = &(struct clk_init_data) {1832 .name = "gcc_camss_ispif_ahb_clk",1833 .parent_hws = (const struct clk_hw*[]) {1834 &camss_top_ahb_clk_src.clkr.hw,1835 },1836 .num_parents = 1,1837 .ops = &clk_branch2_ops,1838 .flags = CLK_SET_RATE_PARENT,1839 }1840 }1841};1842 1843static struct clk_branch gcc_camss_mclk0_clk = {1844 .halt_reg = 0x52018,1845 .halt_check = BRANCH_HALT,1846 .clkr = {1847 .enable_reg = 0x52018,1848 .enable_mask = BIT(0),1849 .hw.init = &(struct clk_init_data) {1850 .name = "gcc_camss_mclk0_clk",1851 .parent_hws = (const struct clk_hw*[]) {1852 &mclk0_clk_src.clkr.hw,1853 },1854 .num_parents = 1,1855 .ops = &clk_branch2_ops,1856 .flags = CLK_SET_RATE_PARENT,1857 }1858 }1859};1860 1861static struct clk_branch gcc_camss_mclk1_clk = {1862 .halt_reg = 0x53018,1863 .halt_check = BRANCH_HALT,1864 .clkr = {1865 .enable_reg = 0x53018,1866 .enable_mask = BIT(0),1867 .hw.init = &(struct clk_init_data) {1868 .name = "gcc_camss_mclk1_clk",1869 .parent_hws = (const struct clk_hw*[]) {1870 &mclk1_clk_src.clkr.hw,1871 },1872 .num_parents = 1,1873 .ops = &clk_branch2_ops,1874 .flags = CLK_SET_RATE_PARENT,1875 }1876 }1877};1878 1879static struct clk_branch gcc_camss_top_ahb_clk = {1880 .halt_reg = 0x56004,1881 .halt_check = BRANCH_HALT,1882 .clkr = {1883 .enable_reg = 0x56004,1884 .enable_mask = BIT(0),1885 .hw.init = &(struct clk_init_data) {1886 .name = "gcc_camss_top_ahb_clk",1887 .parent_hws = (const struct clk_hw*[]) {1888 &camss_top_ahb_clk_src.clkr.hw,1889 },1890 .num_parents = 1,1891 .ops = &clk_branch2_ops,1892 .flags = CLK_SET_RATE_PARENT,1893 }1894 }1895};1896 1897static struct clk_branch gcc_camss_vfe0_clk = {1898 .halt_reg = 0x58038,1899 .halt_check = BRANCH_HALT,1900 .clkr = {1901 .enable_reg = 0x58038,1902 .enable_mask = BIT(0),1903 .hw.init = &(struct clk_init_data) {1904 .name = "gcc_camss_vfe0_clk",1905 .parent_hws = (const struct clk_hw*[]) {1906 &vfe0_clk_src.clkr.hw,1907 },1908 .num_parents = 1,1909 .ops = &clk_branch2_ops,1910 .flags = CLK_SET_RATE_PARENT,1911 }1912 }1913};1914 1915static struct clk_branch gcc_camss_vfe_ahb_clk = {1916 .halt_reg = 0x58044,1917 .halt_check = BRANCH_HALT,1918 .clkr = {1919 .enable_reg = 0x58044,1920 .enable_mask = BIT(0),1921 .hw.init = &(struct clk_init_data) {1922 .name = "gcc_camss_vfe_ahb_clk",1923 .parent_hws = (const struct clk_hw*[]) {1924 &camss_top_ahb_clk_src.clkr.hw,1925 },1926 .num_parents = 1,1927 .ops = &clk_branch2_ops,1928 .flags = CLK_SET_RATE_PARENT,1929 }1930 }1931};1932 1933static struct clk_branch gcc_camss_vfe_axi_clk = {1934 .halt_reg = 0x58048,1935 .halt_check = BRANCH_HALT,1936 .clkr = {1937 .enable_reg = 0x58048,1938 .enable_mask = BIT(0),1939 .hw.init = &(struct clk_init_data) {1940 .name = "gcc_camss_vfe_axi_clk",1941 .parent_hws = (const struct clk_hw*[]) {1942 &system_noc_bfdcd_clk_src.clkr.hw,1943 },1944 .num_parents = 1,1945 .ops = &clk_branch2_ops,1946 }1947 }1948};1949 1950static struct clk_branch gcc_gp1_clk = {1951 .halt_reg = 0x08000,1952 .halt_check = BRANCH_HALT,1953 .clkr = {1954 .enable_reg = 0x08000,1955 .enable_mask = BIT(0),1956 .hw.init = &(struct clk_init_data) {1957 .name = "gcc_gp1_clk",1958 .parent_hws = (const struct clk_hw*[]) {1959 &gp1_clk_src.clkr.hw,1960 },1961 .num_parents = 1,1962 .ops = &clk_branch2_ops,1963 .flags = CLK_SET_RATE_PARENT,1964 }1965 }1966};1967 1968static struct clk_branch gcc_gp2_clk = {1969 .halt_reg = 0x09000,1970 .halt_check = BRANCH_HALT,1971 .clkr = {1972 .enable_reg = 0x09000,1973 .enable_mask = BIT(0),1974 .hw.init = &(struct clk_init_data) {1975 .name = "gcc_gp2_clk",1976 .parent_hws = (const struct clk_hw*[]) {1977 &gp2_clk_src.clkr.hw,1978 },1979 .num_parents = 1,1980 .ops = &clk_branch2_ops,1981 .flags = CLK_SET_RATE_PARENT,1982 }1983 }1984};1985 1986static struct clk_branch gcc_gp3_clk = {1987 .halt_reg = 0x0a000,1988 .halt_check = BRANCH_HALT,1989 .clkr = {1990 .enable_reg = 0x0a000,1991 .enable_mask = BIT(0),1992 .hw.init = &(struct clk_init_data) {1993 .name = "gcc_gp3_clk",1994 .parent_hws = (const struct clk_hw*[]) {1995 &gp3_clk_src.clkr.hw,1996 },1997 .num_parents = 1,1998 .ops = &clk_branch2_ops,1999 .flags = CLK_SET_RATE_PARENT,2000 }2001 }2002};2003 2004static struct clk_branch gcc_mdss_ahb_clk = {2005 .halt_reg = 0x4d07c,2006 .halt_check = BRANCH_HALT,2007 .clkr = {2008 .enable_reg = 0x4d07c,2009 .enable_mask = BIT(0),2010 .hw.init = &(struct clk_init_data) {2011 .name = "gcc_mdss_ahb_clk",2012 .parent_hws = (const struct clk_hw*[]) {2013 &pcnoc_bfdcd_clk_src.clkr.hw,2014 },2015 .num_parents = 1,2016 .ops = &clk_branch2_ops,2017 }2018 }2019};2020 2021static struct clk_branch gcc_mdss_axi_clk = {2022 .halt_reg = 0x4d080,2023 .halt_check = BRANCH_HALT,2024 .clkr = {2025 .enable_reg = 0x4d080,2026 .enable_mask = BIT(0),2027 .hw.init = &(struct clk_init_data) {2028 .name = "gcc_mdss_axi_clk",2029 .parent_hws = (const struct clk_hw*[]) {2030 &system_noc_bfdcd_clk_src.clkr.hw,2031 },2032 .num_parents = 1,2033 .ops = &clk_branch2_ops,2034 }2035 }2036};2037 2038static struct clk_branch gcc_mdss_byte0_clk = {2039 .halt_reg = 0x4d094,2040 .halt_check = BRANCH_HALT,2041 .clkr = {2042 .enable_reg = 0x4d094,2043 .enable_mask = BIT(0),2044 .hw.init = &(struct clk_init_data) {2045 .name = "gcc_mdss_byte0_clk",2046 .parent_hws = (const struct clk_hw*[]) {2047 &byte0_clk_src.clkr.hw,2048 },2049 .num_parents = 1,2050 .ops = &clk_branch2_ops,2051 .flags = CLK_SET_RATE_PARENT,2052 }2053 }2054};2055 2056static struct clk_branch gcc_mdss_esc0_clk = {2057 .halt_reg = 0x4d098,2058 .halt_check = BRANCH_HALT,2059 .clkr = {2060 .enable_reg = 0x4d098,2061 .enable_mask = BIT(0),2062 .hw.init = &(struct clk_init_data) {2063 .name = "gcc_mdss_esc0_clk",2064 .parent_hws = (const struct clk_hw*[]) {2065 &esc0_clk_src.clkr.hw,2066 },2067 .num_parents = 1,2068 .ops = &clk_branch2_ops,2069 .flags = CLK_SET_RATE_PARENT,2070 }2071 }2072};2073 2074static struct clk_branch gcc_mdss_mdp_clk = {2075 .halt_reg = 0x4d088,2076 .halt_check = BRANCH_HALT,2077 .clkr = {2078 .enable_reg = 0x4d088,2079 .enable_mask = BIT(0),2080 .hw.init = &(struct clk_init_data) {2081 .name = "gcc_mdss_mdp_clk",2082 .parent_hws = (const struct clk_hw*[]) {2083 &mdp_clk_src.clkr.hw,2084 },2085 .num_parents = 1,2086 .ops = &clk_branch2_ops,2087 .flags = CLK_SET_RATE_PARENT,2088 }2089 }2090};2091 2092static struct clk_branch gcc_mdss_pclk0_clk = {2093 .halt_reg = 0x4d084,2094 .halt_check = BRANCH_HALT,2095 .clkr = {2096 .enable_reg = 0x4d084,2097 .enable_mask = BIT(0),2098 .hw.init = &(struct clk_init_data) {2099 .name = "gcc_mdss_pclk0_clk",2100 .parent_hws = (const struct clk_hw*[]) {2101 &pclk0_clk_src.clkr.hw,2102 },2103 .num_parents = 1,2104 .ops = &clk_branch2_ops,2105 .flags = CLK_SET_RATE_PARENT,2106 }2107 }2108};2109 2110static struct clk_branch gcc_mdss_vsync_clk = {2111 .halt_reg = 0x4d090,2112 .halt_check = BRANCH_HALT,2113 .clkr = {2114 .enable_reg = 0x4d090,2115 .enable_mask = BIT(0),2116 .hw.init = &(struct clk_init_data) {2117 .name = "gcc_mdss_vsync_clk",2118 .parent_hws = (const struct clk_hw*[]) {2119 &vsync_clk_src.clkr.hw,2120 },2121 .num_parents = 1,2122 .ops = &clk_branch2_ops,2123 .flags = CLK_SET_RATE_PARENT,2124 }2125 }2126};2127 2128static struct clk_branch gcc_mss_cfg_ahb_clk = {2129 .halt_reg = 0x49000,2130 .halt_check = BRANCH_HALT,2131 .clkr = {2132 .enable_reg = 0x49000,2133 .enable_mask = BIT(0),2134 .hw.init = &(struct clk_init_data) {2135 .name = "gcc_mss_cfg_ahb_clk",2136 .parent_hws = (const struct clk_hw*[]) {2137 &pcnoc_bfdcd_clk_src.clkr.hw,2138 },2139 .num_parents = 1,2140 .ops = &clk_branch2_ops,2141 }2142 }2143};2144 2145static struct clk_branch gcc_mss_q6_bimc_axi_clk = {2146 .halt_reg = 0x49004,2147 .halt_check = BRANCH_HALT,2148 .clkr = {2149 .enable_reg = 0x49004,2150 .enable_mask = BIT(0),2151 .hw.init = &(struct clk_init_data) {2152 .name = "gcc_mss_q6_bimc_axi_clk",2153 .parent_hws = (const struct clk_hw*[]) {2154 &bimc_ddr_clk_src.clkr.hw,2155 },2156 .num_parents = 1,2157 .ops = &clk_branch2_ops,2158 }2159 }2160};2161 2162static struct clk_branch gcc_oxili_ahb_clk = {2163 .halt_reg = 0x59028,2164 .halt_check = BRANCH_HALT,2165 .clkr = {2166 .enable_reg = 0x59028,2167 .enable_mask = BIT(0),2168 .hw.init = &(struct clk_init_data) {2169 .name = "gcc_oxili_ahb_clk",2170 .parent_hws = (const struct clk_hw*[]) {2171 &pcnoc_bfdcd_clk_src.clkr.hw,2172 },2173 .num_parents = 1,2174 .ops = &clk_branch2_ops,2175 }2176 }2177};2178 2179static struct clk_branch gcc_oxili_gfx3d_clk = {2180 .halt_reg = 0x59020,2181 .halt_check = BRANCH_HALT,2182 .clkr = {2183 .enable_reg = 0x59020,2184 .enable_mask = BIT(0),2185 .hw.init = &(struct clk_init_data) {2186 .name = "gcc_oxili_gfx3d_clk",2187 .parent_hws = (const struct clk_hw*[]) {2188 &gfx3d_clk_src.clkr.hw,2189 },2190 .num_parents = 1,2191 .ops = &clk_branch2_ops,2192 .flags = CLK_SET_RATE_PARENT,2193 }2194 }2195};2196 2197static struct clk_branch gcc_pdm2_clk = {2198 .halt_reg = 0x4400c,2199 .halt_check = BRANCH_HALT,2200 .clkr = {2201 .enable_reg = 0x4400c,2202 .enable_mask = BIT(0),2203 .hw.init = &(struct clk_init_data) {2204 .name = "gcc_pdm2_clk",2205 .parent_hws = (const struct clk_hw*[]) {2206 &pdm2_clk_src.clkr.hw,2207 },2208 .num_parents = 1,2209 .ops = &clk_branch2_ops,2210 .flags = CLK_SET_RATE_PARENT,2211 }2212 }2213};2214 2215static struct clk_branch gcc_pdm_ahb_clk = {2216 .halt_reg = 0x44004,2217 .halt_check = BRANCH_HALT,2218 .clkr = {2219 .enable_reg = 0x44004,2220 .enable_mask = BIT(0),2221 .hw.init = &(struct clk_init_data) {2222 .name = "gcc_pdm_ahb_clk",2223 .parent_hws = (const struct clk_hw*[]) {2224 &pcnoc_bfdcd_clk_src.clkr.hw,2225 },2226 .num_parents = 1,2227 .ops = &clk_branch2_ops,2228 }2229 }2230};2231 2232static struct clk_branch gcc_sdcc1_ahb_clk = {2233 .halt_reg = 0x4201c,2234 .halt_check = BRANCH_HALT,2235 .clkr = {2236 .enable_reg = 0x4201c,2237 .enable_mask = BIT(0),2238 .hw.init = &(struct clk_init_data) {2239 .name = "gcc_sdcc1_ahb_clk",2240 .parent_hws = (const struct clk_hw*[]) {2241 &pcnoc_bfdcd_clk_src.clkr.hw,2242 },2243 .num_parents = 1,2244 .ops = &clk_branch2_ops,2245 }2246 }2247};2248 2249static struct clk_branch gcc_sdcc1_apps_clk = {2250 .halt_reg = 0x42018,2251 .halt_check = BRANCH_HALT,2252 .clkr = {2253 .enable_reg = 0x42018,2254 .enable_mask = BIT(0),2255 .hw.init = &(struct clk_init_data) {2256 .name = "gcc_sdcc1_apps_clk",2257 .parent_hws = (const struct clk_hw*[]) {2258 &sdcc1_apps_clk_src.clkr.hw,2259 },2260 .num_parents = 1,2261 .ops = &clk_branch2_ops,2262 .flags = CLK_SET_RATE_PARENT,2263 }2264 }2265};2266 2267static struct clk_branch gcc_sdcc2_ahb_clk = {2268 .halt_reg = 0x4301c,2269 .halt_check = BRANCH_HALT,2270 .clkr = {2271 .enable_reg = 0x4301c,2272 .enable_mask = BIT(0),2273 .hw.init = &(struct clk_init_data) {2274 .name = "gcc_sdcc2_ahb_clk",2275 .parent_hws = (const struct clk_hw*[]) {2276 &pcnoc_bfdcd_clk_src.clkr.hw,2277 },2278 .num_parents = 1,2279 .ops = &clk_branch2_ops,2280 }2281 }2282};2283 2284static struct clk_branch gcc_sdcc2_apps_clk = {2285 .halt_reg = 0x43018,2286 .halt_check = BRANCH_HALT,2287 .clkr = {2288 .enable_reg = 0x43018,2289 .enable_mask = BIT(0),2290 .hw.init = &(struct clk_init_data) {2291 .name = "gcc_sdcc2_apps_clk",2292 .parent_hws = (const struct clk_hw*[]) {2293 &sdcc2_apps_clk_src.clkr.hw,2294 },2295 .num_parents = 1,2296 .ops = &clk_branch2_ops,2297 .flags = CLK_SET_RATE_PARENT,2298 }2299 }2300};2301 2302static struct clk_branch gcc_usb2a_phy_sleep_clk = {2303 .halt_reg = 0x4102c,2304 .halt_check = BRANCH_HALT,2305 .clkr = {2306 .enable_reg = 0x4102c,2307 .enable_mask = BIT(0),2308 .hw.init = &(struct clk_init_data) {2309 .name = "gcc_usb2a_phy_sleep_clk",2310 .parent_data = gcc_sleep_clk_data,2311 .num_parents = ARRAY_SIZE(gcc_sleep_clk_data),2312 .ops = &clk_branch2_ops,2313 }2314 }2315};2316 2317static struct clk_branch gcc_usb_hs_ahb_clk = {2318 .halt_reg = 0x41008,2319 .halt_check = BRANCH_HALT,2320 .clkr = {2321 .enable_reg = 0x41008,2322 .enable_mask = BIT(0),2323 .hw.init = &(struct clk_init_data) {2324 .name = "gcc_usb_hs_ahb_clk",2325 .parent_hws = (const struct clk_hw*[]) {2326 &pcnoc_bfdcd_clk_src.clkr.hw,2327 },2328 .num_parents = 1,2329 .ops = &clk_branch2_ops,2330 }2331 }2332};2333 2334static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {2335 .halt_reg = 0x41030,2336 .halt_check = BRANCH_HALT,2337 .clkr = {2338 .enable_reg = 0x41030,2339 .enable_mask = BIT(0),2340 .hw.init = &(struct clk_init_data) {2341 .name = "gcc_usb_hs_phy_cfg_ahb_clk",2342 .parent_hws = (const struct clk_hw*[]) {2343 &pcnoc_bfdcd_clk_src.clkr.hw,2344 },2345 .num_parents = 1,2346 .ops = &clk_branch2_ops,2347 }2348 }2349};2350 2351static struct clk_branch gcc_usb_hs_system_clk = {2352 .halt_reg = 0x41004,2353 .halt_check = BRANCH_HALT,2354 .clkr = {2355 .enable_reg = 0x41004,2356 .enable_mask = BIT(0),2357 .hw.init = &(struct clk_init_data) {2358 .name = "gcc_usb_hs_system_clk",2359 .parent_hws = (const struct clk_hw*[]) {2360 &usb_hs_system_clk_src.clkr.hw,2361 },2362 .num_parents = 1,2363 .ops = &clk_branch2_ops,2364 .flags = CLK_SET_RATE_PARENT,2365 }2366 }2367};2368 2369static struct clk_branch gcc_venus0_ahb_clk = {2370 .halt_reg = 0x4c020,2371 .halt_check = BRANCH_HALT,2372 .clkr = {2373 .enable_reg = 0x4c020,2374 .enable_mask = BIT(0),2375 .hw.init = &(struct clk_init_data) {2376 .name = "gcc_venus0_ahb_clk",2377 .parent_hws = (const struct clk_hw*[]) {2378 &pcnoc_bfdcd_clk_src.clkr.hw,2379 },2380 .num_parents = 1,2381 .ops = &clk_branch2_ops,2382 }2383 }2384};2385 2386static struct clk_branch gcc_venus0_axi_clk = {2387 .halt_reg = 0x4c024,2388 .halt_check = BRANCH_HALT,2389 .clkr = {2390 .enable_reg = 0x4c024,2391 .enable_mask = BIT(0),2392 .hw.init = &(struct clk_init_data) {2393 .name = "gcc_venus0_axi_clk",2394 .parent_hws = (const struct clk_hw*[]) {2395 &system_noc_bfdcd_clk_src.clkr.hw,2396 },2397 .num_parents = 1,2398 .ops = &clk_branch2_ops,2399 }2400 }2401};2402 2403static struct clk_branch gcc_venus0_core0_vcodec0_clk = {2404 .halt_reg = 0x4c02c,2405 .halt_check = BRANCH_HALT,2406 .clkr = {2407 .enable_reg = 0x4c02c,2408 .enable_mask = BIT(0),2409 .hw.init = &(struct clk_init_data) {2410 .name = "gcc_venus0_core0_vcodec0_clk",2411 .parent_hws = (const struct clk_hw*[]) {2412 &vcodec0_clk_src.clkr.hw,2413 },2414 .num_parents = 1,2415 .ops = &clk_branch2_ops,2416 .flags = CLK_SET_RATE_PARENT,2417 }2418 }2419};2420 2421static struct clk_branch gcc_venus0_vcodec0_clk = {2422 .halt_reg = 0x4c01c,2423 .halt_check = BRANCH_HALT,2424 .clkr = {2425 .enable_reg = 0x4c01c,2426 .enable_mask = BIT(0),2427 .hw.init = &(struct clk_init_data) {2428 .name = "gcc_venus0_vcodec0_clk",2429 .parent_hws = (const struct clk_hw*[]) {2430 &vcodec0_clk_src.clkr.hw,2431 },2432 .num_parents = 1,2433 .ops = &clk_branch2_ops,2434 .flags = CLK_SET_RATE_PARENT,2435 }2436 }2437};2438 2439static struct gdsc mdss_gdsc = {2440 .gdscr = 0x4d078,2441 .cxcs = (unsigned int []) { 0x4d080, 0x4d088 },2442 .cxc_count = 2,2443 .pd = {2444 .name = "mdss_gdsc",2445 },2446 .pwrsts = PWRSTS_OFF_ON,2447};2448 2449static struct gdsc oxili_gdsc = {2450 .gdscr = 0x5901c,2451 .cxcs = (unsigned int []) { 0x59020 },2452 .cxc_count = 1,2453 .pd = {2454 .name = "oxili_gdsc",2455 },2456 .pwrsts = PWRSTS_OFF_ON,2457};2458 2459static struct gdsc venus_gdsc = {2460 .gdscr = 0x4c018,2461 .cxcs = (unsigned int []) { 0x4c024, 0x4c01c },2462 .cxc_count = 2,2463 .pd = {2464 .name = "venus_gdsc",2465 },2466 .pwrsts = PWRSTS_OFF_ON,2467};2468 2469static struct gdsc venus_core0_gdsc = {2470 .gdscr = 0x4c028,2471 .cxcs = (unsigned int []) { 0x4c02c },2472 .cxc_count = 1,2473 .pd = {2474 .name = "venus_core0_gdsc",2475 },2476 .flags = HW_CTRL,2477 .pwrsts = PWRSTS_OFF_ON,2478};2479 2480static struct gdsc vfe_gdsc = {2481 .gdscr = 0x58034,2482 .cxcs = (unsigned int []) { 0x58038, 0x58048, 0x58050 },2483 .cxc_count = 3,2484 .pd = {2485 .name = "vfe_gdsc",2486 },2487 .pwrsts = PWRSTS_OFF_ON,2488};2489 2490static struct clk_regmap *gcc_msm8909_clocks[] = {2491 [GPLL0_EARLY] = &gpll0_early.clkr,2492 [GPLL0] = &gpll0.clkr,2493 [GPLL1] = &gpll1.clkr,2494 [GPLL1_VOTE] = &gpll1_vote,2495 [GPLL2_EARLY] = &gpll2_early.clkr,2496 [GPLL2] = &gpll2.clkr,2497 [BIMC_PLL_EARLY] = &bimc_pll_early.clkr,2498 [BIMC_PLL] = &bimc_pll.clkr,2499 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,2500 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,2501 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,2502 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,2503 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,2504 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,2505 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,2506 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,2507 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,2508 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,2509 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,2510 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,2511 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,2512 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,2513 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,2514 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,2515 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,2516 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,2517 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,2518 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,2519 [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,2520 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,2521 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,2522 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,2523 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,2524 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,2525 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,2526 [GP1_CLK_SRC] = &gp1_clk_src.clkr,2527 [GP2_CLK_SRC] = &gp2_clk_src.clkr,2528 [GP3_CLK_SRC] = &gp3_clk_src.clkr,2529 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,2530 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,2531 [MDP_CLK_SRC] = &mdp_clk_src.clkr,2532 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,2533 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,2534 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,2535 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,2536 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,2537 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,2538 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,2539 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,2540 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,2541 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,2542 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,2543 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,2544 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,2545 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,2546 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,2547 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,2548 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,2549 [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,2550 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,2551 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,2552 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,2553 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,2554 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,2555 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,2556 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,2557 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,2558 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,2559 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,2560 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,2561 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,2562 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,2563 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,2564 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,2565 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,2566 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,2567 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,2568 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,2569 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,2570 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,2571 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,2572 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,2573 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,2574 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,2575 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,2576 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,2577 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,2578 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,2579 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,2580 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,2581 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,2582 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,2583 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,2584 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,2585 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,2586 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,2587 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,2588 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,2589 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,2590 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,2591 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,2592 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,2593 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,2594 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,2595 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,2596 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,2597 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,2598 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,2599 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,2600 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,2601 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,2602 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,2603 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,2604 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,2605 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,2606 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,2607 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,2608 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,2609 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,2610 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,2611 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,2612 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,2613 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,2614 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,2615 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,2616 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,2617 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,2618 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,2619 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,2620 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,2621 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,2622 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,2623};2624 2625static struct gdsc *gcc_msm8909_gdscs[] = {2626 [MDSS_GDSC] = &mdss_gdsc,2627 [OXILI_GDSC] = &oxili_gdsc,2628 [VENUS_GDSC] = &venus_gdsc,2629 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,2630 [VFE_GDSC] = &vfe_gdsc,2631};2632 2633static const struct qcom_reset_map gcc_msm8909_resets[] = {2634 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },2635 [GCC_BLSP1_BCR] = { 0x01000 },2636 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },2637 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },2638 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },2639 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },2640 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },2641 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },2642 [GCC_BLSP1_UART1_BCR] = { 0x02038 },2643 [GCC_BLSP1_UART2_BCR] = { 0x03028 },2644 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },2645 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },2646 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },2647 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },2648 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },2649 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },2650 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },2651 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },2652 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },2653 [GCC_CAMSS_GP0_BCR] = { 0x54014 },2654 [GCC_CAMSS_GP1_BCR] = { 0x55014 },2655 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },2656 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },2657 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },2658 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },2659 [GCC_CAMSS_TOP_BCR] = { 0x56000 },2660 [GCC_CAMSS_TOP_AHB_BCR] = { 0x5a018 },2661 [GCC_CAMSS_VFE_BCR] = { 0x58030 },2662 [GCC_CRYPTO_BCR] = { 0x16000 },2663 [GCC_MDSS_BCR] = { 0x4d074 },2664 [GCC_OXILI_BCR] = { 0x59018 },2665 [GCC_PDM_BCR] = { 0x44000 },2666 [GCC_PRNG_BCR] = { 0x13000 },2667 [GCC_QUSB2_PHY_BCR] = { 0x4103c },2668 [GCC_SDCC1_BCR] = { 0x42000 },2669 [GCC_SDCC2_BCR] = { 0x43000 },2670 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },2671 [GCC_USB2A_PHY_BCR] = { 0x41028 },2672 [GCC_USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 },2673 [GCC_USB_HS_BCR] = { 0x41000 },2674 [GCC_VENUS0_BCR] = { 0x4c014 },2675 /* Subsystem Restart */2676 [GCC_MSS_RESTART] = { 0x3e000 },2677};2678 2679static const struct regmap_config gcc_msm8909_regmap_config = {2680 .reg_bits = 32,2681 .reg_stride = 4,2682 .val_bits = 32,2683 .max_register = 0x80000,2684 .fast_io = true,2685};2686 2687static const struct qcom_cc_desc gcc_msm8909_desc = {2688 .config = &gcc_msm8909_regmap_config,2689 .clks = gcc_msm8909_clocks,2690 .num_clks = ARRAY_SIZE(gcc_msm8909_clocks),2691 .resets = gcc_msm8909_resets,2692 .num_resets = ARRAY_SIZE(gcc_msm8909_resets),2693 .gdscs = gcc_msm8909_gdscs,2694 .num_gdscs = ARRAY_SIZE(gcc_msm8909_gdscs),2695};2696 2697static const struct of_device_id gcc_msm8909_match_table[] = {2698 { .compatible = "qcom,gcc-msm8909" },2699 { }2700};2701MODULE_DEVICE_TABLE(of, gcc_msm8909_match_table);2702 2703static int gcc_msm8909_probe(struct platform_device *pdev)2704{2705 return qcom_cc_probe(pdev, &gcc_msm8909_desc);2706}2707 2708static struct platform_driver gcc_msm8909_driver = {2709 .probe = gcc_msm8909_probe,2710 .driver = {2711 .name = "gcc-msm8909",2712 .of_match_table = gcc_msm8909_match_table,2713 },2714};2715 2716static int __init gcc_msm8909_init(void)2717{2718 return platform_driver_register(&gcc_msm8909_driver);2719}2720core_initcall(gcc_msm8909_init);2721 2722static void __exit gcc_msm8909_exit(void)2723{2724 platform_driver_unregister(&gcc_msm8909_driver);2725}2726module_exit(gcc_msm8909_exit);2727 2728MODULE_DESCRIPTION("Qualcomm GCC MSM8909 Driver");2729MODULE_LICENSE("GPL");2730MODULE_ALIAS("platform:gcc-msm8909");2731