4158 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Qualcomm Global Clock Controller driver for MSM8956/764 *5 * Copyright (c) 2016-2021, AngeloGioacchino Del Regno6 * <angelogioacchino.delregno@somainline.org>7 *8 * Driver cleanup and modernization9 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>10 * Marijn Suijten <marijn.suijten@somainline.org>11 *12 */13 14#include <linux/clk-provider.h>15#include <linux/err.h>16#include <linux/kernel.h>17#include <linux/module.h>18#include <linux/of.h>19#include <linux/platform_device.h>20#include <linux/regmap.h>21 22#include <dt-bindings/clock/qcom,gcc-msm8976.h>23 24#include "clk-pll.h"25#include "clk-branch.h"26#include "clk-rcg.h"27#include "common.h"28#include "gdsc.h"29#include "reset.h"30 31enum {32 P_GPLL0_OUT_MAIN,33 P_GPLL0_AUX,34 P_GPLL0_OUT,35 P_GPLL0_OUT_M,36 P_GPLL0_OUT_MDP,37 P_GPLL2_AUX,38 P_GPLL2_OUT,39 P_GPLL4_OUT_MAIN,40 P_GPLL4_AUX,41 P_GPLL4_OUT,42 P_GPLL4_GFX3D,43 P_GPLL6_OUT_MAIN,44 P_GPLL6_AUX,45 P_GPLL6_OUT,46 P_GPLL6_GFX3D,47 P_DSI0PLL,48 P_DSI1PLL,49 P_DSI0PLL_BYTE,50 P_DSI1PLL_BYTE,51 P_XO_A,52 P_XO,53};54 55static struct clk_pll gpll0 = {56 .l_reg = 0x21004,57 .m_reg = 0x21008,58 .n_reg = 0x2100c,59 .config_reg = 0x21014,60 .mode_reg = 0x21000,61 .status_reg = 0x2101c,62 .status_bit = 17,63 .clkr.hw.init = &(struct clk_init_data){64 .name = "gpll0",65 .parent_data = &(const struct clk_parent_data){66 .fw_name = "xo",67 },68 .num_parents = 1,69 .ops = &clk_pll_ops,70 },71};72 73static struct clk_regmap gpll0_vote = {74 .enable_reg = 0x45000,75 .enable_mask = BIT(0),76 .hw.init = &(struct clk_init_data){77 .name = "gpll0_vote",78 .parent_hws = (const struct clk_hw *[]) {79 &gpll0.clkr.hw,80 },81 .num_parents = 1,82 /* This clock is required for other ones to function. */83 .flags = CLK_IS_CRITICAL,84 .ops = &clk_pll_vote_ops,85 },86};87 88static struct clk_pll gpll2 = {89 .l_reg = 0x4a004,90 .m_reg = 0x4a008,91 .n_reg = 0x4a00c,92 .config_reg = 0x4a014,93 .mode_reg = 0x4a000,94 .status_reg = 0x4a01c,95 .status_bit = 17,96 .clkr.hw.init = &(struct clk_init_data){97 .name = "gpll2",98 .parent_data = &(const struct clk_parent_data){99 .fw_name = "xo",100 },101 .num_parents = 1,102 .ops = &clk_pll_ops,103 },104};105 106static struct clk_regmap gpll2_vote = {107 .enable_reg = 0x45000,108 .enable_mask = BIT(2),109 .hw.init = &(struct clk_init_data){110 .name = "gpll2_vote",111 .parent_hws = (const struct clk_hw *[]) {112 &gpll2.clkr.hw,113 },114 .num_parents = 1,115 .ops = &clk_pll_vote_ops,116 },117};118 119static const struct pll_freq_tbl gpll3_freq_tbl[] = {120 { 1100000000, 57, 7, 24, 0 },121 { }122};123 124static struct clk_pll gpll3 = {125 .l_reg = 0x22004,126 .m_reg = 0x22008,127 .n_reg = 0x2200c,128 .config_reg = 0x22010,129 .mode_reg = 0x22000,130 .status_reg = 0x22024,131 .status_bit = 17,132 .freq_tbl = gpll3_freq_tbl,133 .clkr.hw.init = &(struct clk_init_data) {134 .name = "gpll3",135 .parent_data = &(const struct clk_parent_data){136 .fw_name = "xo",137 },138 .num_parents = 1,139 .ops = &clk_pll_ops,140 },141};142 143static struct clk_regmap gpll3_vote = {144 .enable_reg = 0x45000,145 .enable_mask = BIT(4),146 .hw.init = &(struct clk_init_data){147 .name = "gpll3_vote",148 .parent_hws = (const struct clk_hw *[]) {149 &gpll3.clkr.hw,150 },151 .num_parents = 1,152 .ops = &clk_pll_vote_ops,153 },154};155 156/* GPLL3 at 1100MHz, main output enabled. */157static const struct pll_config gpll3_config = {158 .l = 57,159 .m = 7,160 .n = 24,161 .vco_val = 0x0,162 .vco_mask = 0x3 << 20,163 .pre_div_val = 0x0,164 .pre_div_mask = 0x7 << 12,165 .post_div_val = 0x0,166 .post_div_mask = 0x3 << 8,167 .mn_ena_mask = BIT(24),168 .main_output_mask = BIT(0),169 .aux_output_mask = BIT(1),170};171 172static struct clk_pll gpll4 = {173 .l_reg = 0x24004,174 .m_reg = 0x24008,175 .n_reg = 0x2400c,176 .config_reg = 0x24018,177 .mode_reg = 0x24000,178 .status_reg = 0x24024,179 .status_bit = 17,180 .clkr.hw.init = &(struct clk_init_data){181 .name = "gpll4",182 .parent_data = &(const struct clk_parent_data){183 .fw_name = "xo",184 },185 .num_parents = 1,186 .ops = &clk_pll_ops,187 },188};189 190static struct clk_regmap gpll4_vote = {191 .enable_reg = 0x45000,192 .enable_mask = BIT(5),193 .hw.init = &(struct clk_init_data){194 .name = "gpll4_vote",195 .parent_hws = (const struct clk_hw *[]) {196 &gpll4.clkr.hw,197 },198 .num_parents = 1,199 .ops = &clk_pll_vote_ops,200 },201};202 203static struct clk_pll gpll6 = {204 .mode_reg = 0x37000,205 .l_reg = 0x37004,206 .m_reg = 0x37008,207 .n_reg = 0x3700c,208 .config_reg = 0x37014,209 .status_reg = 0x3701c,210 .status_bit = 17,211 .clkr.hw.init = &(struct clk_init_data){212 .name = "gpll6",213 .parent_data = &(const struct clk_parent_data){214 .fw_name = "xo",215 },216 .num_parents = 1,217 .ops = &clk_pll_ops,218 },219};220 221static struct clk_regmap gpll6_vote = {222 .enable_reg = 0x45000,223 .enable_mask = BIT(7),224 .hw.init = &(struct clk_init_data){225 .name = "gpll6_vote",226 .parent_hws = (const struct clk_hw *[]) {227 &gpll6.clkr.hw,228 },229 .num_parents = 1,230 .ops = &clk_pll_vote_ops,231 },232};233 234static const struct parent_map gcc_parent_map_1[] = {235 { P_XO, 0 },236 { P_GPLL0_OUT_MAIN, 1 },237 { P_GPLL4_OUT, 2 },238};239 240static const struct clk_parent_data gcc_parent_data_1[] = {241 { .fw_name = "xo" },242 { .hw = &gpll0_vote.hw },243 { .hw = &gpll4_vote.hw },244};245 246static const struct parent_map gcc_parent_map_v1_1[] = {247 { P_XO, 0 },248 { P_GPLL0_OUT_MAIN, 1 },249 { P_GPLL2_OUT, 4 },250};251 252static const struct clk_parent_data gcc_parent_data_v1_1[] = {253 { .fw_name = "xo" },254 { .hw = &gpll0_vote.hw },255 { .hw = &gpll2_vote.hw },256};257 258static const struct parent_map gcc_parent_map_2[] = {259 { P_XO, 0 },260 { P_GPLL0_OUT_MAIN, 1 },261 { P_GPLL2_AUX, 3 },262 { P_GPLL4_OUT, 2 },263};264 265static const struct clk_parent_data gcc_parent_data_2[] = {266 { .fw_name = "xo" },267 { .hw = &gpll0_vote.hw },268 { .hw = &gpll2_vote.hw },269 { .hw = &gpll4_vote.hw },270};271 272static const struct parent_map gcc_parent_map_3[] = {273 { P_XO, 0 },274 { P_GPLL0_OUT_MAIN, 1 },275 { P_GPLL2_AUX, 3 },276 { P_GPLL6_AUX, 2 },277};278 279static const struct clk_parent_data gcc_parent_data_3[] = {280 { .fw_name = "xo" },281 { .hw = &gpll0_vote.hw },282 { .hw = &gpll2_vote.hw },283 { .hw = &gpll6_vote.hw },284};285 286static const struct parent_map gcc_parent_map_4[] = {287 { P_XO, 0 },288 { P_GPLL0_OUT_MAIN, 1 },289};290 291static const struct parent_map gcc_parent_map_4_fs[] = {292 { P_XO, 0 },293 { P_GPLL0_OUT, 2 },294};295 296static const struct parent_map gcc_parent_map_5[] = {297 { P_XO, 0 },298 { P_GPLL4_OUT, 2 },299 { P_GPLL6_OUT_MAIN, 1 },300};301 302static const struct clk_parent_data gcc_parent_data_5[] = {303 { .fw_name = "xo" },304 { .hw = &gpll4_vote.hw },305 { .hw = &gpll6_vote.hw },306};307 308static const struct parent_map gcc_parent_map_6[] = {309 { P_XO, 0 },310 { P_GPLL0_OUT_MAIN, 1 },311 { P_GPLL4_OUT_MAIN, 5 },312};313 314static const struct clk_parent_data gcc_parent_data_6[] = {315 { .fw_name = "xo" },316 { .hw = &gpll0_vote.hw },317 { .hw = &gpll4_vote.hw },318};319 320static const struct parent_map gcc_parent_map_7_mdp[] = {321 { P_XO, 0 },322 { P_GPLL6_OUT, 3 },323 { P_GPLL0_OUT_MDP, 6 },324};325 326static const struct clk_parent_data gcc_parent_data_7_mdp[] = {327 { .fw_name = "xo" },328 { .hw = &gpll6_vote.hw },329 { .hw = &gpll0_vote.hw },330};331 332static const struct parent_map gcc_parent_map_7[] = {333 { P_GPLL0_OUT_MAIN, 1 },334 { P_GPLL6_OUT, 3 },335};336 337static const struct clk_hw * gcc_parent_hws_7[] = {338 &gpll0_vote.hw,339 &gpll6_vote.hw,340};341 342static const struct parent_map gcc_parent_map_8[] = {343 { P_XO, 0 },344 { P_GPLL0_OUT_MAIN, 1 },345};346 347static const struct clk_parent_data gcc_parent_data_4_8[] = {348 { .fw_name = "xo" },349 { .hw = &gpll0_vote.hw },350};351 352static const struct parent_map gcc_parent_map_8_a[] = {353 { P_XO_A, 0 },354 { P_GPLL0_OUT_MAIN, 1 },355};356 357static const struct clk_parent_data gcc_parent_data_8_a[] = {358 { .fw_name = "xo_a" },359 { .hw = &gpll0_vote.hw },360};361 362static const struct parent_map gcc_parent_map_8_gp[] = {363 { P_GPLL0_OUT_MAIN, 1 },364};365 366static const struct clk_hw *gcc_parent_hws_8_gp[] = {367 &gpll0_vote.hw,368};369 370static const struct parent_map gcc_parent_map_9[] = {371 { P_XO, 0 },372 { P_GPLL6_OUT_MAIN, 6 },373};374 375static const struct clk_parent_data gcc_parent_data_9[] = {376 { .fw_name = "xo" },377 { .hw = &gpll6_vote.hw },378};379 380static const struct parent_map gcc_parent_map_10[] = {381 { P_XO, 0 },382};383 384static const struct clk_parent_data gcc_parent_data_10[] = {385 { .fw_name = "xo" },386};387 388static const struct parent_map gcc_parent_map_sdcc_ice[] = {389 { P_XO, 0 },390 { P_GPLL0_OUT_M, 3 },391};392 393static const struct parent_map gcc_parent_map_cci[] = {394 { P_XO, 0 },395 { P_GPLL0_AUX, 2 },396};397 398static const struct parent_map gcc_parent_map_cpp[] = {399 { P_XO, 0 },400 { P_GPLL0_OUT_MAIN, 1 },401 { P_GPLL4_AUX, 3 },402};403 404static const struct parent_map gcc_parent_map_mdss_pix0[] = {405 { P_XO, 0 },406 { P_DSI0PLL, 1 },407};408 409static const struct clk_parent_data gcc_parent_data_mdss_pix0[] = {410 { .fw_name = "xo" },411 { .fw_name = "dsi0pll" },412};413 414static const struct parent_map gcc_parent_map_mdss_pix1[] = {415 { P_XO, 0 },416 { P_DSI0PLL, 3 },417 { P_DSI1PLL, 1 },418};419 420static const struct clk_parent_data gcc_parent_data_mdss_pix1[] = {421 { .fw_name = "xo" },422 { .fw_name = "dsi0pll" },423 { .fw_name = "dsi1pll" },424};425 426static const struct parent_map gcc_parent_map_mdss_byte0[] = {427 { P_XO, 0 },428 { P_DSI0PLL_BYTE, 1 },429};430 431static const struct clk_parent_data gcc_parent_data_mdss_byte0[] = {432 { .fw_name = "xo" },433 { .fw_name = "dsi0pllbyte" },434};435 436static const struct parent_map gcc_parent_map_mdss_byte1[] = {437 { P_XO, 0 },438 { P_DSI0PLL_BYTE, 3 },439 { P_DSI1PLL_BYTE, 1 },440};441 442static const struct clk_parent_data gcc_parent_data_mdss_byte1[] = {443 { .fw_name = "xo" },444 { .fw_name = "dsi0pllbyte" },445 { .fw_name = "dsi1pllbyte" },446};447 448static const struct parent_map gcc_parent_map_gfx3d[] = {449 { P_XO, 0 },450 { P_GPLL0_OUT_MAIN, 1 },451 { P_GPLL4_GFX3D, 5 },452 { P_GPLL6_GFX3D, 3 },453};454 455static const struct clk_parent_data gcc_parent_data_gfx3d[] = {456 { .fw_name = "xo" },457 { .hw = &gpll0_vote.hw },458 { .hw = &gpll4_vote.hw },459 { .hw = &gpll6_vote.hw },460};461 462static const struct freq_tbl ftbl_aps_0_clk_src[] = {463 F(19200000, P_XO, 1, 0, 0),464 F(300000000, P_GPLL4_OUT, 4, 0, 0),465 F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),466 { }467};468 469static struct clk_rcg2 aps_0_clk_src = {470 .cmd_rcgr = 0x78008,471 .hid_width = 5,472 .parent_map = gcc_parent_map_5,473 .freq_tbl = ftbl_aps_0_clk_src,474 .clkr.hw.init = &(struct clk_init_data){475 .name = "aps_0_clk_src",476 .parent_data = gcc_parent_data_5,477 .num_parents = ARRAY_SIZE(gcc_parent_data_5),478 .ops = &clk_rcg2_ops,479 },480};481 482static const struct freq_tbl ftbl_aps_1_clk_src[] = {483 F(19200000, P_XO, 1, 0, 0),484 F(300000000, P_GPLL4_OUT, 4, 0, 0),485 F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),486 { }487};488 489static struct clk_rcg2 aps_1_clk_src = {490 .cmd_rcgr = 0x79008,491 .hid_width = 5,492 .parent_map = gcc_parent_map_5,493 .freq_tbl = ftbl_aps_1_clk_src,494 .clkr.hw.init = &(struct clk_init_data){495 .name = "aps_1_clk_src",496 .parent_data = gcc_parent_data_5,497 .num_parents = ARRAY_SIZE(gcc_parent_data_5),498 .ops = &clk_rcg2_ops,499 },500};501 502static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {503 F(19200000, P_XO_A, 1, 0, 0),504 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),505 F(88890000, P_GPLL0_OUT_MAIN, 9, 0, 0),506 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),507 { }508};509 510static struct clk_rcg2 apss_ahb_clk_src = {511 .cmd_rcgr = 0x46000,512 .hid_width = 5,513 .parent_map = gcc_parent_map_8_a,514 .freq_tbl = ftbl_apss_ahb_clk_src,515 .clkr.hw.init = &(struct clk_init_data){516 .name = "apss_ahb_clk_src",517 .parent_data = gcc_parent_data_8_a,518 .num_parents = ARRAY_SIZE(gcc_parent_data_8_a),519 .ops = &clk_rcg2_ops,520 /*521 * This clock allows the CPUs to communicate with522 * the rest of the SoC. Without it, the brain will523 * operate without the rest of the body.524 */525 .flags = CLK_IS_CRITICAL,526 },527};528 529static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {530 F(19200000, P_XO, 1, 0, 0),531 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),532 { }533};534 535static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {536 .cmd_rcgr = 0x200c,537 .hid_width = 5,538 .parent_map = gcc_parent_map_8,539 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,540 .clkr.hw.init = &(struct clk_init_data){541 .name = "blsp1_qup1_i2c_apps_clk_src",542 .parent_data = gcc_parent_data_4_8,543 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),544 .ops = &clk_rcg2_ops,545 },546};547 548static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {549 F(960000, P_XO, 10, 1, 2),550 F(4800000, P_XO, 4, 0, 0),551 F(9600000, P_XO, 2, 0, 0),552 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),553 F(19200000, P_XO, 1, 0, 0),554 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),555 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),556 { }557};558 559static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {560 .cmd_rcgr = 0x2024,561 .mnd_width = 8,562 .hid_width = 5,563 .parent_map = gcc_parent_map_8,564 .freq_tbl = ftbl_blsp_spi_apps_clk_src,565 .clkr.hw.init = &(struct clk_init_data){566 .name = "blsp1_qup1_spi_apps_clk_src",567 .parent_data = gcc_parent_data_4_8,568 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),569 .ops = &clk_rcg2_ops,570 },571};572 573static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {574 .cmd_rcgr = 0x3000,575 .hid_width = 5,576 .parent_map = gcc_parent_map_8,577 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,578 .clkr.hw.init = &(struct clk_init_data){579 .name = "blsp1_qup2_i2c_apps_clk_src",580 .parent_data = gcc_parent_data_4_8,581 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),582 .ops = &clk_rcg2_ops,583 },584};585 586static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {587 .cmd_rcgr = 0x3014,588 .mnd_width = 8,589 .hid_width = 5,590 .parent_map = gcc_parent_map_8,591 .freq_tbl = ftbl_blsp_spi_apps_clk_src,592 .clkr.hw.init = &(struct clk_init_data){593 .name = "blsp1_qup2_spi_apps_clk_src",594 .parent_data = gcc_parent_data_4_8,595 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),596 .ops = &clk_rcg2_ops,597 },598};599 600static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {601 .cmd_rcgr = 0x4000,602 .hid_width = 5,603 .parent_map = gcc_parent_map_8,604 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,605 .clkr.hw.init = &(struct clk_init_data){606 .name = "blsp1_qup3_i2c_apps_clk_src",607 .parent_data = gcc_parent_data_4_8,608 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),609 .ops = &clk_rcg2_ops,610 },611};612 613static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {614 .cmd_rcgr = 0x4024,615 .mnd_width = 8,616 .hid_width = 5,617 .parent_map = gcc_parent_map_8,618 .freq_tbl = ftbl_blsp_spi_apps_clk_src,619 .clkr.hw.init = &(struct clk_init_data){620 .name = "blsp1_qup3_spi_apps_clk_src",621 .parent_data = gcc_parent_data_4_8,622 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),623 .ops = &clk_rcg2_ops,624 },625};626 627static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {628 .cmd_rcgr = 0x5000,629 .hid_width = 5,630 .parent_map = gcc_parent_map_8,631 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,632 .clkr.hw.init = &(struct clk_init_data){633 .name = "blsp1_qup4_i2c_apps_clk_src",634 .parent_data = gcc_parent_data_4_8,635 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),636 .ops = &clk_rcg2_ops,637 },638};639 640static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {641 .cmd_rcgr = 0x5024,642 .mnd_width = 8,643 .hid_width = 5,644 .parent_map = gcc_parent_map_8,645 .freq_tbl = ftbl_blsp_spi_apps_clk_src,646 .clkr.hw.init = &(struct clk_init_data){647 .name = "blsp1_qup4_spi_apps_clk_src",648 .parent_data = gcc_parent_data_4_8,649 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),650 .ops = &clk_rcg2_ops,651 },652};653 654static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {655 F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),656 F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),657 F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),658 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),659 F(19200000, P_XO, 1, 0, 0),660 F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),661 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),662 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),663 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),664 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),665 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),666 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),667 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),668 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),669 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),670 F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),671 { }672};673 674static struct clk_rcg2 blsp1_uart1_apps_clk_src = {675 .cmd_rcgr = 0x2044,676 .mnd_width = 16,677 .hid_width = 5,678 .parent_map = gcc_parent_map_8,679 .freq_tbl = ftbl_blsp_uart_apps_clk_src,680 .clkr.hw.init = &(struct clk_init_data){681 .name = "blsp1_uart1_apps_clk_src",682 .parent_data = gcc_parent_data_4_8,683 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),684 .ops = &clk_rcg2_ops,685 },686};687 688static struct clk_rcg2 blsp1_uart2_apps_clk_src = {689 .cmd_rcgr = 0x3034,690 .mnd_width = 16,691 .hid_width = 5,692 .parent_map = gcc_parent_map_8,693 .freq_tbl = ftbl_blsp_uart_apps_clk_src,694 .clkr.hw.init = &(struct clk_init_data){695 .name = "blsp1_uart2_apps_clk_src",696 .parent_data = gcc_parent_data_4_8,697 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),698 .ops = &clk_rcg2_ops,699 },700};701 702static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {703 .cmd_rcgr = 0xc00c,704 .hid_width = 5,705 .parent_map = gcc_parent_map_8,706 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,707 .clkr.hw.init = &(struct clk_init_data){708 .name = "blsp2_qup1_i2c_apps_clk_src",709 .parent_data = gcc_parent_data_4_8,710 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),711 .ops = &clk_rcg2_ops,712 },713};714 715static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {716 .cmd_rcgr = 0xc024,717 .mnd_width = 8,718 .hid_width = 5,719 .parent_map = gcc_parent_map_8,720 .freq_tbl = ftbl_blsp_spi_apps_clk_src,721 .clkr.hw.init = &(struct clk_init_data){722 .name = "blsp2_qup1_spi_apps_clk_src",723 .parent_data = gcc_parent_data_4_8,724 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),725 .ops = &clk_rcg2_ops,726 },727};728 729static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {730 .cmd_rcgr = 0xd000,731 .hid_width = 5,732 .parent_map = gcc_parent_map_8,733 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,734 .clkr.hw.init = &(struct clk_init_data){735 .name = "blsp2_qup2_i2c_apps_clk_src",736 .parent_data = gcc_parent_data_4_8,737 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),738 .ops = &clk_rcg2_ops,739 },740};741 742static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {743 .cmd_rcgr = 0xd014,744 .mnd_width = 8,745 .hid_width = 5,746 .parent_map = gcc_parent_map_8,747 .freq_tbl = ftbl_blsp_spi_apps_clk_src,748 .clkr.hw.init = &(struct clk_init_data){749 .name = "blsp2_qup2_spi_apps_clk_src",750 .parent_data = gcc_parent_data_4_8,751 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),752 .ops = &clk_rcg2_ops,753 },754};755 756static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {757 .cmd_rcgr = 0xf000,758 .hid_width = 5,759 .parent_map = gcc_parent_map_8,760 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,761 .clkr.hw.init = &(struct clk_init_data){762 .name = "blsp2_qup3_i2c_apps_clk_src",763 .parent_data = gcc_parent_data_4_8,764 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),765 .ops = &clk_rcg2_ops,766 },767};768 769static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {770 .cmd_rcgr = 0xf024,771 .mnd_width = 8,772 .hid_width = 5,773 .parent_map = gcc_parent_map_8,774 .freq_tbl = ftbl_blsp_spi_apps_clk_src,775 .clkr.hw.init = &(struct clk_init_data){776 .name = "blsp2_qup3_spi_apps_clk_src",777 .parent_data = gcc_parent_data_4_8,778 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),779 .ops = &clk_rcg2_ops,780 },781};782 783static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {784 .cmd_rcgr = 0x18000,785 .hid_width = 5,786 .parent_map = gcc_parent_map_8,787 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,788 .clkr.hw.init = &(struct clk_init_data){789 .name = "blsp2_qup4_i2c_apps_clk_src",790 .parent_data = gcc_parent_data_4_8,791 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),792 .ops = &clk_rcg2_ops,793 },794};795 796static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {797 .cmd_rcgr = 0x18024,798 .mnd_width = 8,799 .hid_width = 5,800 .parent_map = gcc_parent_map_8,801 .freq_tbl = ftbl_blsp_spi_apps_clk_src,802 .clkr.hw.init = &(struct clk_init_data){803 .name = "blsp2_qup4_spi_apps_clk_src",804 .parent_data = gcc_parent_data_4_8,805 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),806 .ops = &clk_rcg2_ops,807 },808};809 810static struct clk_rcg2 blsp2_uart1_apps_clk_src = {811 .cmd_rcgr = 0xc044,812 .mnd_width = 16,813 .hid_width = 5,814 .parent_map = gcc_parent_map_8,815 .freq_tbl = ftbl_blsp_uart_apps_clk_src,816 .clkr.hw.init = &(struct clk_init_data){817 .name = "blsp2_uart1_apps_clk_src",818 .parent_data = gcc_parent_data_4_8,819 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),820 .ops = &clk_rcg2_ops,821 },822};823 824static struct clk_rcg2 blsp2_uart2_apps_clk_src = {825 .cmd_rcgr = 0xd034,826 .mnd_width = 16,827 .hid_width = 5,828 .parent_map = gcc_parent_map_8,829 .freq_tbl = ftbl_blsp_uart_apps_clk_src,830 .clkr.hw.init = &(struct clk_init_data){831 .name = "blsp2_uart2_apps_clk_src",832 .parent_data = gcc_parent_data_4_8,833 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),834 .ops = &clk_rcg2_ops,835 },836};837 838static const struct freq_tbl ftbl_cci_clk_src[] = {839 F(19200000, P_XO, 1, 0, 0),840 F(37500000, P_GPLL0_AUX, 1, 3, 64),841 { }842};843 844static struct clk_rcg2 cci_clk_src = {845 .cmd_rcgr = 0x51000,846 .mnd_width = 8,847 .hid_width = 5,848 .parent_map = gcc_parent_map_cci,849 .freq_tbl = ftbl_cci_clk_src,850 .clkr.hw.init = &(struct clk_init_data){851 .name = "cci_clk_src",852 .parent_data = gcc_parent_data_4_8,853 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),854 .ops = &clk_rcg2_ops,855 },856};857 858static const struct freq_tbl ftbl_cpp_clk_src[] = {859 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),860 F(240000000, P_GPLL4_AUX, 5, 0, 0),861 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),862 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),863 F(480000000, P_GPLL4_AUX, 2.5, 0, 0),864 { }865};866 867static struct clk_rcg2 cpp_clk_src = {868 .cmd_rcgr = 0x58018,869 .hid_width = 5,870 .parent_map = gcc_parent_map_cpp,871 .freq_tbl = ftbl_cpp_clk_src,872 .clkr.hw.init = &(struct clk_init_data){873 .name = "cpp_clk_src",874 .parent_data = gcc_parent_data_6,875 .num_parents = ARRAY_SIZE(gcc_parent_data_6),876 .ops = &clk_rcg2_ops,877 },878};879 880static const struct freq_tbl ftbl_csi0_clk_src[] = {881 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),882 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),883 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),884 { }885};886 887static struct clk_rcg2 csi0_clk_src = {888 .cmd_rcgr = 0x4e020,889 .hid_width = 5,890 .parent_map = gcc_parent_map_8,891 .freq_tbl = ftbl_csi0_clk_src,892 .clkr.hw.init = &(struct clk_init_data){893 .name = "csi0_clk_src",894 .parent_data = gcc_parent_data_4_8,895 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),896 .ops = &clk_rcg2_ops,897 },898};899 900static const struct freq_tbl ftbl_csi1_clk_src[] = {901 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),902 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),903 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),904 { }905};906 907static struct clk_rcg2 csi1_clk_src = {908 .cmd_rcgr = 0x4f020,909 .hid_width = 5,910 .parent_map = gcc_parent_map_8,911 .freq_tbl = ftbl_csi1_clk_src,912 .clkr.hw.init = &(struct clk_init_data){913 .name = "csi1_clk_src",914 .parent_data = gcc_parent_data_4_8,915 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),916 .ops = &clk_rcg2_ops,917 },918};919 920static const struct freq_tbl ftbl_csi2_clk_src[] = {921 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),922 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),923 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),924 { }925};926 927static struct clk_rcg2 csi2_clk_src = {928 .cmd_rcgr = 0x3c020,929 .hid_width = 5,930 .parent_map = gcc_parent_map_8,931 .freq_tbl = ftbl_csi2_clk_src,932 .clkr.hw.init = &(struct clk_init_data){933 .name = "csi2_clk_src",934 .parent_data = gcc_parent_data_4_8,935 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),936 .ops = &clk_rcg2_ops,937 },938};939 940static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {941 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),942 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),943 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),944 { }945};946 947static struct clk_rcg2 camss_gp0_clk_src = {948 .cmd_rcgr = 0x54000,949 .mnd_width = 8,950 .hid_width = 5,951 .parent_map = gcc_parent_map_8_gp,952 .freq_tbl = ftbl_camss_gp0_clk_src,953 .clkr.hw.init = &(struct clk_init_data){954 .name = "camss_gp0_clk_src",955 .parent_hws = gcc_parent_hws_8_gp,956 .num_parents = ARRAY_SIZE(gcc_parent_hws_8_gp),957 .ops = &clk_rcg2_ops,958 },959};960 961static const struct freq_tbl ftbl_camss_gp1_clk_src[] = {962 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),963 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),964 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),965 { }966};967 968static struct clk_rcg2 camss_gp1_clk_src = {969 .cmd_rcgr = 0x55000,970 .mnd_width = 8,971 .hid_width = 5,972 .parent_map = gcc_parent_map_8_gp,973 .freq_tbl = ftbl_camss_gp1_clk_src,974 .clkr.hw.init = &(struct clk_init_data){975 .name = "camss_gp1_clk_src",976 .parent_hws = gcc_parent_hws_8_gp,977 .num_parents = ARRAY_SIZE(gcc_parent_hws_8_gp),978 .ops = &clk_rcg2_ops,979 },980};981 982static const struct freq_tbl ftbl_jpeg0_clk_src[] = {983 F(133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),984 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),985 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),986 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),987 { }988};989 990static struct clk_rcg2 jpeg0_clk_src = {991 .cmd_rcgr = 0x57000,992 .hid_width = 5,993 .parent_map = gcc_parent_map_6,994 .freq_tbl = ftbl_jpeg0_clk_src,995 .clkr.hw.init = &(struct clk_init_data){996 .name = "jpeg0_clk_src",997 .parent_data = gcc_parent_data_6,998 .num_parents = ARRAY_SIZE(gcc_parent_data_6),999 .ops = &clk_rcg2_ops,1000 },1001};1002 1003static const struct freq_tbl ftbl_mclk_clk_src[] = {1004 F(8000000, P_GPLL0_OUT_MAIN, 1, 1, 100),1005 F(24000000, P_GPLL6_OUT, 1, 1, 45),1006 F(66670000, P_GPLL0_OUT_MAIN, 12, 0, 0),1007 { }1008};1009 1010static struct clk_rcg2 mclk0_clk_src = {1011 .cmd_rcgr = 0x52000,1012 .mnd_width = 8,1013 .hid_width = 5,1014 .parent_map = gcc_parent_map_7,1015 .freq_tbl = ftbl_mclk_clk_src,1016 .clkr.hw.init = &(struct clk_init_data){1017 .name = "mclk0_clk_src",1018 .parent_hws = gcc_parent_hws_7,1019 .num_parents = ARRAY_SIZE(gcc_parent_hws_7),1020 .ops = &clk_rcg2_ops,1021 },1022};1023 1024static struct clk_rcg2 mclk1_clk_src = {1025 .cmd_rcgr = 0x53000,1026 .mnd_width = 8,1027 .hid_width = 5,1028 .parent_map = gcc_parent_map_7,1029 .freq_tbl = ftbl_mclk_clk_src,1030 .clkr.hw.init = &(struct clk_init_data){1031 .name = "mclk1_clk_src",1032 .parent_hws = gcc_parent_hws_7,1033 .num_parents = ARRAY_SIZE(gcc_parent_hws_7),1034 .ops = &clk_rcg2_ops,1035 },1036};1037 1038static struct clk_rcg2 mclk2_clk_src = {1039 .cmd_rcgr = 0x5c000,1040 .mnd_width = 8,1041 .hid_width = 5,1042 .parent_map = gcc_parent_map_7,1043 .freq_tbl = ftbl_mclk_clk_src,1044 .clkr.hw.init = &(struct clk_init_data){1045 .name = "mclk2_clk_src",1046 .parent_hws = gcc_parent_hws_7,1047 .num_parents = ARRAY_SIZE(gcc_parent_hws_7),1048 .ops = &clk_rcg2_ops,1049 },1050};1051 1052static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {1053 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1054 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1055 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),1056 { }1057};1058 1059static struct clk_rcg2 csi0phytimer_clk_src = {1060 .cmd_rcgr = 0x4e000,1061 .hid_width = 5,1062 .parent_map = gcc_parent_map_8,1063 .freq_tbl = ftbl_csi0phytimer_clk_src,1064 .clkr.hw.init = &(struct clk_init_data){1065 .name = "csi0phytimer_clk_src",1066 .parent_data = gcc_parent_data_4_8,1067 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1068 .ops = &clk_rcg2_ops,1069 },1070};1071 1072static const struct freq_tbl ftbl_csi1phytimer_clk_src[] = {1073 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1074 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1075 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),1076 { }1077};1078 1079static struct clk_rcg2 csi1phytimer_clk_src = {1080 .cmd_rcgr = 0x4f000,1081 .hid_width = 5,1082 .parent_map = gcc_parent_map_8,1083 .freq_tbl = ftbl_csi1phytimer_clk_src,1084 .clkr.hw.init = &(struct clk_init_data){1085 .name = "csi1phytimer_clk_src",1086 .parent_data = gcc_parent_data_4_8,1087 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1088 .ops = &clk_rcg2_ops,1089 },1090};1091 1092static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {1093 F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),1094 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1095 { }1096};1097 1098static struct clk_rcg2 camss_top_ahb_clk_src = {1099 .cmd_rcgr = 0x5a000,1100 .mnd_width = 8,1101 .hid_width = 5,1102 .parent_map = gcc_parent_map_8,1103 .freq_tbl = ftbl_camss_top_ahb_clk_src,1104 .clkr.hw.init = &(struct clk_init_data){1105 .name = "camss_top_ahb_clk_src",1106 .parent_data = gcc_parent_data_4_8,1107 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1108 .ops = &clk_rcg2_ops,1109 },1110};1111 1112static const struct freq_tbl ftbl_vfe0_clk_src[] = {1113 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1114 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1115 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1116 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),1117 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),1118 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1119 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1120 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),1121 F(300000000, P_GPLL4_OUT, 4, 0, 0),1122 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1123 F(466000000, P_GPLL2_AUX, 2, 0, 0),1124 { }1125};1126 1127static struct clk_rcg2 vfe0_clk_src = {1128 .cmd_rcgr = 0x58000,1129 .hid_width = 5,1130 .parent_map = gcc_parent_map_2,1131 .freq_tbl = ftbl_vfe0_clk_src,1132 .clkr.hw.init = &(struct clk_init_data){1133 .name = "vfe0_clk_src",1134 .parent_data = gcc_parent_data_2,1135 .num_parents = ARRAY_SIZE(gcc_parent_data_2),1136 .ops = &clk_rcg2_ops,1137 },1138};1139 1140static const struct freq_tbl ftbl_vfe1_clk_src[] = {1141 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1142 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1143 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1144 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),1145 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),1146 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1147 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1148 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),1149 F(300000000, P_GPLL4_OUT, 4, 0, 0),1150 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1151 F(466000000, P_GPLL2_AUX, 2, 0, 0),1152 { }1153};1154 1155static struct clk_rcg2 vfe1_clk_src = {1156 .cmd_rcgr = 0x58054,1157 .hid_width = 5,1158 .parent_map = gcc_parent_map_2,1159 .freq_tbl = ftbl_vfe1_clk_src,1160 .clkr.hw.init = &(struct clk_init_data){1161 .name = "vfe1_clk_src",1162 .parent_data = gcc_parent_data_2,1163 .num_parents = ARRAY_SIZE(gcc_parent_data_2),1164 .ops = &clk_rcg2_ops,1165 },1166};1167 1168static const struct freq_tbl ftbl_crypto_clk_src[] = {1169 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1170 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1171 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1172 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),1173 { }1174};1175 1176static struct clk_rcg2 crypto_clk_src = {1177 .cmd_rcgr = 0x16004,1178 .hid_width = 5,1179 .parent_map = gcc_parent_map_8,1180 .freq_tbl = ftbl_crypto_clk_src,1181 .clkr.hw.init = &(struct clk_init_data){1182 .name = "crypto_clk_src",1183 .parent_data = gcc_parent_data_4_8,1184 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1185 .ops = &clk_rcg2_ops,1186 },1187};1188 1189static const struct freq_tbl ftbl_gp1_clk_src[] = {1190 F(19200000, P_XO, 1, 0, 0),1191 { }1192};1193 1194static struct clk_rcg2 gp1_clk_src = {1195 .cmd_rcgr = 0x8004,1196 .mnd_width = 8,1197 .hid_width = 5,1198 .parent_map = gcc_parent_map_8_gp,1199 .freq_tbl = ftbl_gp1_clk_src,1200 .clkr.hw.init = &(struct clk_init_data){1201 .name = "gp1_clk_src",1202 .parent_hws = (const struct clk_hw *[]) {1203 &gpll0_vote.hw,1204 },1205 .num_parents = 1,1206 .ops = &clk_rcg2_ops,1207 },1208};1209 1210static const struct freq_tbl ftbl_gp2_clk_src[] = {1211 F(19200000, P_XO, 1, 0, 0),1212 { }1213};1214 1215static struct clk_rcg2 gp2_clk_src = {1216 .cmd_rcgr = 0x9004,1217 .mnd_width = 8,1218 .hid_width = 5,1219 .parent_map = gcc_parent_map_8_gp,1220 .freq_tbl = ftbl_gp2_clk_src,1221 .clkr.hw.init = &(struct clk_init_data){1222 .name = "gp2_clk_src",1223 .parent_hws = (const struct clk_hw *[]) {1224 &gpll0_vote.hw,1225 },1226 .num_parents = 1,1227 .ops = &clk_rcg2_ops,1228 },1229};1230 1231static const struct freq_tbl ftbl_gp3_clk_src[] = {1232 F(19200000, P_XO, 1, 0, 0),1233 { }1234};1235 1236static struct clk_rcg2 gp3_clk_src = {1237 .cmd_rcgr = 0xa004,1238 .mnd_width = 8,1239 .hid_width = 5,1240 .parent_map = gcc_parent_map_8_gp,1241 .freq_tbl = ftbl_gp3_clk_src,1242 .clkr.hw.init = &(struct clk_init_data){1243 .name = "gp3_clk_src",1244 .parent_hws = (const struct clk_hw *[]) {1245 &gpll0_vote.hw,1246 },1247 .num_parents = 1,1248 .ops = &clk_rcg2_ops,1249 },1250};1251 1252static struct clk_rcg2 byte0_clk_src = {1253 .cmd_rcgr = 0x4d044,1254 .mnd_width = 0,1255 .hid_width = 5,1256 .parent_map = gcc_parent_map_mdss_byte0,1257 .clkr.hw.init = &(struct clk_init_data){1258 .name = "byte0_clk_src",1259 .parent_data = gcc_parent_data_mdss_byte0,1260 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),1261 .ops = &clk_byte2_ops,1262 .flags = CLK_SET_RATE_PARENT,1263 },1264};1265 1266static struct clk_rcg2 byte1_clk_src = {1267 .cmd_rcgr = 0x4d0b0,1268 .mnd_width = 0,1269 .hid_width = 5,1270 .parent_map = gcc_parent_map_mdss_byte1,1271 .clkr.hw.init = &(struct clk_init_data){1272 .name = "byte1_clk_src",1273 .parent_data = gcc_parent_data_mdss_byte1,1274 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),1275 .ops = &clk_byte2_ops,1276 .flags = CLK_SET_RATE_PARENT,1277 },1278};1279 1280static const struct freq_tbl ftbl_esc0_1_clk_src[] = {1281 F(19200000, P_XO, 1, 0, 0),1282 { }1283};1284 1285static struct clk_rcg2 esc0_clk_src = {1286 .cmd_rcgr = 0x4d05c,1287 .hid_width = 5,1288 .freq_tbl = ftbl_esc0_1_clk_src,1289 .parent_map = gcc_parent_map_mdss_byte0,1290 .clkr.hw.init = &(struct clk_init_data){1291 .name = "esc0_clk_src",1292 .parent_data = gcc_parent_data_mdss_byte0,1293 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),1294 .ops = &clk_rcg2_ops,1295 },1296};1297 1298static struct clk_rcg2 esc1_clk_src = {1299 .cmd_rcgr = 0x4d0a8,1300 .hid_width = 5,1301 .freq_tbl = ftbl_esc0_1_clk_src,1302 .parent_map = gcc_parent_map_mdss_byte1,1303 .clkr.hw.init = &(struct clk_init_data){1304 .name = "esc1_clk_src",1305 .parent_data = gcc_parent_data_mdss_byte1,1306 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte1),1307 .ops = &clk_rcg2_ops,1308 },1309};1310 1311static const struct freq_tbl ftbl_mdp_clk_src[] = {1312 F(50000000, P_GPLL0_OUT_MDP, 16, 0, 0),1313 F(80000000, P_GPLL0_OUT_MDP, 10, 0, 0),1314 F(100000000, P_GPLL0_OUT_MDP, 8, 0, 0),1315 F(145454545, P_GPLL0_OUT_MDP, 5.5, 0, 0),1316 F(160000000, P_GPLL0_OUT_MDP, 5, 0, 0),1317 F(177777778, P_GPLL0_OUT_MDP, 4.5, 0, 0),1318 F(200000000, P_GPLL0_OUT_MDP, 4, 0, 0),1319 F(270000000, P_GPLL6_OUT, 4, 0, 0),1320 F(320000000, P_GPLL0_OUT_MDP, 2.5, 0, 0),1321 F(360000000, P_GPLL6_OUT, 3, 0, 0),1322 { }1323};1324 1325static struct clk_rcg2 mdp_clk_src = {1326 .cmd_rcgr = 0x4d014,1327 .hid_width = 5,1328 .parent_map = gcc_parent_map_7_mdp,1329 .freq_tbl = ftbl_mdp_clk_src,1330 .clkr.hw.init = &(struct clk_init_data){1331 .name = "mdp_clk_src",1332 .parent_data = gcc_parent_data_7_mdp,1333 .num_parents = ARRAY_SIZE(gcc_parent_data_7_mdp),1334 .ops = &clk_rcg2_ops,1335 },1336};1337 1338static struct clk_rcg2 pclk0_clk_src = {1339 .cmd_rcgr = 0x4d000,1340 .mnd_width = 8,1341 .hid_width = 5,1342 .parent_map = gcc_parent_map_mdss_pix0,1343 .clkr.hw.init = &(struct clk_init_data){1344 .name = "pclk0_clk_src",1345 .parent_data = gcc_parent_data_mdss_pix0,1346 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix0),1347 .ops = &clk_pixel_ops,1348 .flags = CLK_SET_RATE_PARENT,1349 },1350};1351 1352static struct clk_rcg2 pclk1_clk_src = {1353 .cmd_rcgr = 0x4d0b8,1354 .mnd_width = 8,1355 .hid_width = 5,1356 .parent_map = gcc_parent_map_mdss_pix1,1357 .clkr.hw.init = &(struct clk_init_data){1358 .name = "pclk1_clk_src",1359 .parent_data = gcc_parent_data_mdss_pix1,1360 .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_pix1),1361 .ops = &clk_pixel_ops,1362 .flags = CLK_SET_RATE_PARENT,1363 },1364};1365 1366static const struct freq_tbl ftbl_vsync_clk_src[] = {1367 F(19200000, P_XO, 1, 0, 0),1368 { }1369};1370 1371static struct clk_rcg2 vsync_clk_src = {1372 .cmd_rcgr = 0x4d02c,1373 .hid_width = 5,1374 .parent_map = gcc_parent_map_10,1375 .freq_tbl = ftbl_vsync_clk_src,1376 .clkr.hw.init = &(struct clk_init_data){1377 .name = "vsync_clk_src",1378 .parent_data = gcc_parent_data_10,1379 .num_parents = ARRAY_SIZE(gcc_parent_data_10),1380 .ops = &clk_rcg2_ops,1381 },1382};1383 1384static const struct freq_tbl ftbl_gfx3d_clk_src[] = {1385 F(19200000, P_XO, 1, 0, 0),1386 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1387 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1388 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1389 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),1390 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),1391 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1392 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),1393 F(240000000, P_GPLL6_GFX3D, 4.5, 0, 0),1394 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),1395 F(300000000, P_GPLL4_GFX3D, 4, 0, 0),1396 F(360000000, P_GPLL6_GFX3D, 3, 0, 0),1397 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),1398 F(432000000, P_GPLL6_GFX3D, 2.5, 0, 0),1399 F(480000000, P_GPLL4_GFX3D, 2.5, 0, 0),1400 F(540000000, P_GPLL6_GFX3D, 2, 0, 0),1401 F(600000000, P_GPLL4_GFX3D, 2, 0, 0),1402 { }1403};1404 1405static const struct clk_init_data gfx3d_clk_params = {1406 .name = "gfx3d_clk_src",1407 .parent_data = gcc_parent_data_gfx3d,1408 .num_parents = ARRAY_SIZE(gcc_parent_data_gfx3d),1409 .ops = &clk_rcg2_ops,1410};1411 1412static struct clk_rcg2 gfx3d_clk_src = {1413 .cmd_rcgr = 0x59000,1414 .hid_width = 5,1415 .parent_map = gcc_parent_map_gfx3d,1416 .freq_tbl = ftbl_gfx3d_clk_src,1417 .clkr.hw.init = &gfx3d_clk_params,1418};1419 1420static const struct freq_tbl ftbl_pdm2_clk_src[] = {1421 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),1422 { }1423};1424 1425static struct clk_rcg2 pdm2_clk_src = {1426 .cmd_rcgr = 0x44010,1427 .hid_width = 5,1428 .parent_map = gcc_parent_map_8,1429 .freq_tbl = ftbl_pdm2_clk_src,1430 .clkr.hw.init = &(struct clk_init_data){1431 .name = "pdm2_clk_src",1432 .parent_data = gcc_parent_data_4_8,1433 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1434 .ops = &clk_rcg2_ops,1435 },1436};1437 1438static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {1439 F(19200000, P_XO, 1, 0, 0),1440 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1441 { }1442};1443 1444static struct clk_rcg2 rbcpr_gfx_clk_src = {1445 .cmd_rcgr = 0x3a00c,1446 .hid_width = 5,1447 .parent_map = gcc_parent_map_8,1448 .freq_tbl = ftbl_rbcpr_gfx_clk_src,1449 .clkr.hw.init = &(struct clk_init_data){1450 .name = "rbcpr_gfx_clk_src",1451 .parent_data = gcc_parent_data_4_8,1452 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1453 .ops = &clk_rcg2_ops,1454 },1455};1456 1457static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {1458 F(144000, P_XO, 16, 3, 25),1459 F(400000, P_XO, 12, 1, 4),1460 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),1461 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),1462 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1463 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1464 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1465 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1466 F(342850000, P_GPLL4_OUT, 3.5, 0, 0),1467 F(400000000, P_GPLL4_OUT, 3, 0, 0),1468 { }1469};1470 1471static const struct freq_tbl ftbl_sdcc1_8976_v1_1_apps_clk_src[] = {1472 F(144000, P_XO, 16, 3, 25),1473 F(400000, P_XO, 12, 1, 4),1474 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),1475 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),1476 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1477 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1478 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1479 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1480 F(186400000, P_GPLL2_OUT, 5, 0, 0),1481 F(372800000, P_GPLL2_OUT, 2.5, 0, 0),1482 { }1483};1484 1485static const struct clk_init_data sdcc1_apps_clk_src_8976v1_1_init = {1486 .name = "sdcc1_apps_clk_src",1487 .parent_data = gcc_parent_data_v1_1,1488 .num_parents = ARRAY_SIZE(gcc_parent_data_v1_1),1489 .ops = &clk_rcg2_floor_ops,1490};1491 1492static struct clk_rcg2 sdcc1_apps_clk_src = {1493 .cmd_rcgr = 0x42004,1494 .mnd_width = 8,1495 .hid_width = 5,1496 .parent_map = gcc_parent_map_1,1497 .freq_tbl = ftbl_sdcc1_apps_clk_src,1498 .clkr.hw.init = &(struct clk_init_data){1499 .name = "sdcc1_apps_clk_src",1500 .parent_data = gcc_parent_data_1,1501 .num_parents = ARRAY_SIZE(gcc_parent_data_1),1502 .ops = &clk_rcg2_floor_ops,1503 },1504};1505 1506static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {1507 F(100000000, P_GPLL0_OUT_M, 8, 0, 0),1508 F(200000000, P_GPLL0_OUT_M, 4, 0, 0),1509 { }1510};1511 1512static struct clk_rcg2 sdcc1_ice_core_clk_src = {1513 .cmd_rcgr = 0x5d000,1514 .mnd_width = 8,1515 .hid_width = 5,1516 .parent_map = gcc_parent_map_sdcc_ice,1517 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,1518 .clkr.hw.init = &(struct clk_init_data){1519 .name = "sdcc1_ice_core_clk_src",1520 .parent_data = gcc_parent_data_4_8,1521 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1522 .ops = &clk_rcg2_ops,1523 },1524};1525 1526static const struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {1527 F(144000, P_XO, 16, 3, 25),1528 F(400000, P_XO, 12, 1, 4),1529 F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),1530 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),1531 F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),1532 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),1533 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1534 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1535 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1536 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1537 { }1538};1539 1540static struct clk_rcg2 sdcc2_apps_clk_src = {1541 .cmd_rcgr = 0x43004,1542 .mnd_width = 8,1543 .hid_width = 5,1544 .parent_map = gcc_parent_map_4,1545 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,1546 .clkr.hw.init = &(struct clk_init_data){1547 .name = "sdcc2_apps_clk_src",1548 .parent_data = gcc_parent_data_4_8,1549 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1550 .ops = &clk_rcg2_floor_ops,1551 },1552};1553 1554static struct clk_rcg2 sdcc3_apps_clk_src = {1555 .cmd_rcgr = 0x39004,1556 .mnd_width = 8,1557 .hid_width = 5,1558 .parent_map = gcc_parent_map_4,1559 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,1560 .clkr.hw.init = &(struct clk_init_data){1561 .name = "sdcc3_apps_clk_src",1562 .parent_data = gcc_parent_data_4_8,1563 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1564 .ops = &clk_rcg2_ops,1565 },1566};1567 1568static const struct freq_tbl ftbl_usb_fs_ic_clk_src[] = {1569 F(60000000, P_GPLL6_OUT_MAIN, 6, 1, 3),1570 { }1571};1572 1573static struct clk_rcg2 usb_fs_ic_clk_src = {1574 .cmd_rcgr = 0x3f034,1575 .mnd_width = 8,1576 .hid_width = 5,1577 .parent_map = gcc_parent_map_9,1578 .freq_tbl = ftbl_usb_fs_ic_clk_src,1579 .clkr.hw.init = &(struct clk_init_data){1580 .name = "usb_fs_ic_clk_src",1581 .parent_data = gcc_parent_data_9,1582 .num_parents = ARRAY_SIZE(gcc_parent_data_9),1583 .ops = &clk_rcg2_ops,1584 },1585};1586 1587static const struct freq_tbl ftbl_usb_fs_system_clk_src[] = {1588 F(64000000, P_GPLL0_OUT, 12.5, 0, 0),1589 { }1590};1591 1592static struct clk_rcg2 usb_fs_system_clk_src = {1593 .cmd_rcgr = 0x3f010,1594 .mnd_width = 8,1595 .hid_width = 5,1596 .parent_map = gcc_parent_map_4_fs,1597 .freq_tbl = ftbl_usb_fs_system_clk_src,1598 .clkr.hw.init = &(struct clk_init_data){1599 .name = "usb_fs_system_clk_src",1600 .parent_data = gcc_parent_data_4_8,1601 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1602 .ops = &clk_rcg2_ops,1603 },1604};1605 1606static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {1607 F(57140000, P_GPLL0_OUT_MAIN, 14, 0, 0),1608 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1609 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),1610 F(177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1611 { }1612};1613 1614static struct clk_rcg2 usb_hs_system_clk_src = {1615 .cmd_rcgr = 0x41010,1616 .hid_width = 5,1617 .parent_map = gcc_parent_map_4,1618 .freq_tbl = ftbl_usb_hs_system_clk_src,1619 .clkr.hw.init = &(struct clk_init_data){1620 .name = "usb_hs_system_clk_src",1621 .parent_data = gcc_parent_data_4_8,1622 .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),1623 .ops = &clk_rcg2_ops,1624 },1625};1626 1627static const struct freq_tbl ftbl_vcodec0_clk_src[] = {1628 F(72727200, P_GPLL0_OUT_MAIN, 11, 0, 0),1629 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1630 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1631 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),1632 F(228570000, P_GPLL0_OUT_MAIN, 3.5, 0, 0),1633 F(310667000, P_GPLL2_AUX, 3, 0, 0),1634 F(360000000, P_GPLL6_AUX, 3, 0, 0),1635 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),1636 F(466000000, P_GPLL2_AUX, 2, 0, 0),1637 { }1638};1639 1640static struct clk_rcg2 vcodec0_clk_src = {1641 .cmd_rcgr = 0x4c000,1642 .mnd_width = 8,1643 .hid_width = 5,1644 .parent_map = gcc_parent_map_3,1645 .freq_tbl = ftbl_vcodec0_clk_src,1646 .clkr.hw.init = &(struct clk_init_data){1647 .name = "vcodec0_clk_src",1648 .parent_data = gcc_parent_data_3,1649 .num_parents = ARRAY_SIZE(gcc_parent_data_3),1650 .ops = &clk_rcg2_ops,1651 },1652};1653 1654static struct clk_branch gcc_aps_0_clk = {1655 .halt_reg = 0x78004,1656 .clkr = {1657 .enable_reg = 0x78004,1658 .enable_mask = BIT(0),1659 .hw.init = &(struct clk_init_data) {1660 .name = "gcc_aps_0_clk",1661 .parent_hws = (const struct clk_hw *[]) {1662 &aps_0_clk_src.clkr.hw,1663 },1664 .num_parents = 1,1665 .flags = CLK_SET_RATE_PARENT,1666 .ops = &clk_branch2_ops,1667 },1668 },1669};1670 1671static struct clk_branch gcc_aps_1_clk = {1672 .halt_reg = 0x79004,1673 .clkr = {1674 .enable_reg = 0x79004,1675 .enable_mask = BIT(0),1676 .hw.init = &(struct clk_init_data) {1677 .name = "gcc_aps_1_clk",1678 .parent_hws = (const struct clk_hw *[]) {1679 &aps_1_clk_src.clkr.hw,1680 },1681 .num_parents = 1,1682 .flags = CLK_SET_RATE_PARENT,1683 .ops = &clk_branch2_ops,1684 },1685 },1686};1687 1688static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {1689 .halt_reg = 0x2008,1690 .halt_check = BRANCH_HALT,1691 .clkr = {1692 .enable_reg = 0x2008,1693 .enable_mask = BIT(0),1694 .hw.init = &(struct clk_init_data) {1695 .name = "gcc_blsp1_qup1_i2c_apps_clk",1696 .parent_hws = (const struct clk_hw *[]) {1697 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,1698 },1699 .num_parents = 1,1700 .flags = CLK_SET_RATE_PARENT,1701 .ops = &clk_branch2_ops,1702 },1703 },1704};1705 1706static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {1707 .halt_reg = 0x2004,1708 .halt_check = BRANCH_HALT,1709 .clkr = {1710 .enable_reg = 0x2004,1711 .enable_mask = BIT(0),1712 .hw.init = &(struct clk_init_data) {1713 .name = "gcc_blsp1_qup1_spi_apps_clk",1714 .parent_hws = (const struct clk_hw *[]) {1715 &blsp1_qup1_spi_apps_clk_src.clkr.hw,1716 },1717 .num_parents = 1,1718 .flags = CLK_SET_RATE_PARENT,1719 .ops = &clk_branch2_ops,1720 },1721 },1722};1723 1724static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {1725 .halt_reg = 0x3010,1726 .halt_check = BRANCH_HALT,1727 .clkr = {1728 .enable_reg = 0x3010,1729 .enable_mask = BIT(0),1730 .hw.init = &(struct clk_init_data) {1731 .name = "gcc_blsp1_qup2_i2c_apps_clk",1732 .parent_hws = (const struct clk_hw *[]) {1733 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,1734 },1735 .num_parents = 1,1736 .flags = CLK_SET_RATE_PARENT,1737 .ops = &clk_branch2_ops,1738 },1739 },1740};1741 1742static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {1743 .halt_reg = 0x300c,1744 .halt_check = BRANCH_HALT,1745 .clkr = {1746 .enable_reg = 0x300c,1747 .enable_mask = BIT(0),1748 .hw.init = &(struct clk_init_data) {1749 .name = "gcc_blsp1_qup2_spi_apps_clk",1750 .parent_hws = (const struct clk_hw *[]) {1751 &blsp1_qup2_spi_apps_clk_src.clkr.hw,1752 },1753 .num_parents = 1,1754 .flags = CLK_SET_RATE_PARENT,1755 .ops = &clk_branch2_ops,1756 },1757 },1758};1759 1760static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {1761 .halt_reg = 0x4020,1762 .halt_check = BRANCH_HALT,1763 .clkr = {1764 .enable_reg = 0x4020,1765 .enable_mask = BIT(0),1766 .hw.init = &(struct clk_init_data) {1767 .name = "gcc_blsp1_qup3_i2c_apps_clk",1768 .parent_hws = (const struct clk_hw *[]) {1769 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,1770 },1771 .num_parents = 1,1772 .flags = CLK_SET_RATE_PARENT,1773 .ops = &clk_branch2_ops,1774 },1775 },1776};1777 1778static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {1779 .halt_reg = 0x401c,1780 .halt_check = BRANCH_HALT,1781 .clkr = {1782 .enable_reg = 0x401c,1783 .enable_mask = BIT(0),1784 .hw.init = &(struct clk_init_data) {1785 .name = "gcc_blsp1_qup3_spi_apps_clk",1786 .parent_hws = (const struct clk_hw *[]) {1787 &blsp1_qup3_spi_apps_clk_src.clkr.hw,1788 },1789 .num_parents = 1,1790 .flags = CLK_SET_RATE_PARENT,1791 .ops = &clk_branch2_ops,1792 },1793 },1794};1795 1796static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {1797 .halt_reg = 0x5020,1798 .halt_check = BRANCH_HALT,1799 .clkr = {1800 .enable_reg = 0x5020,1801 .enable_mask = BIT(0),1802 .hw.init = &(struct clk_init_data) {1803 .name = "gcc_blsp1_qup4_i2c_apps_clk",1804 .parent_hws = (const struct clk_hw *[]) {1805 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,1806 },1807 .num_parents = 1,1808 .flags = CLK_SET_RATE_PARENT,1809 .ops = &clk_branch2_ops,1810 },1811 },1812};1813 1814static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {1815 .halt_reg = 0x501c,1816 .halt_check = BRANCH_HALT,1817 .clkr = {1818 .enable_reg = 0x501c,1819 .enable_mask = BIT(0),1820 .hw.init = &(struct clk_init_data) {1821 .name = "gcc_blsp1_qup4_spi_apps_clk",1822 .parent_hws = (const struct clk_hw *[]) {1823 &blsp1_qup4_spi_apps_clk_src.clkr.hw,1824 },1825 .num_parents = 1,1826 .flags = CLK_SET_RATE_PARENT,1827 .ops = &clk_branch2_ops,1828 },1829 },1830};1831 1832static struct clk_branch gcc_blsp1_uart1_apps_clk = {1833 .halt_reg = 0x203c,1834 .halt_check = BRANCH_HALT,1835 .clkr = {1836 .enable_reg = 0x203c,1837 .enable_mask = BIT(0),1838 .hw.init = &(struct clk_init_data) {1839 .name = "gcc_blsp1_uart1_apps_clk",1840 .parent_hws = (const struct clk_hw *[]) {1841 &blsp1_uart1_apps_clk_src.clkr.hw,1842 },1843 .num_parents = 1,1844 .flags = CLK_SET_RATE_PARENT,1845 .ops = &clk_branch2_ops,1846 },1847 },1848};1849 1850static struct clk_branch gcc_blsp1_uart2_apps_clk = {1851 .halt_reg = 0x302c,1852 .halt_check = BRANCH_HALT,1853 .clkr = {1854 .enable_reg = 0x302c,1855 .enable_mask = BIT(0),1856 .hw.init = &(struct clk_init_data) {1857 .name = "gcc_blsp1_uart2_apps_clk",1858 .parent_hws = (const struct clk_hw *[]) {1859 &blsp1_uart2_apps_clk_src.clkr.hw,1860 },1861 .num_parents = 1,1862 .flags = CLK_SET_RATE_PARENT,1863 .ops = &clk_branch2_ops,1864 },1865 },1866};1867 1868static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {1869 .halt_reg = 0xc008,1870 .halt_check = BRANCH_HALT,1871 .clkr = {1872 .enable_reg = 0xc008,1873 .enable_mask = BIT(0),1874 .hw.init = &(struct clk_init_data) {1875 .name = "gcc_blsp2_qup1_i2c_apps_clk",1876 .parent_hws = (const struct clk_hw *[]) {1877 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,1878 },1879 .num_parents = 1,1880 .flags = CLK_SET_RATE_PARENT,1881 .ops = &clk_branch2_ops,1882 },1883 },1884};1885 1886static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {1887 .halt_reg = 0xc004,1888 .halt_check = BRANCH_HALT,1889 .clkr = {1890 .enable_reg = 0xc004,1891 .enable_mask = BIT(0),1892 .hw.init = &(struct clk_init_data) {1893 .name = "gcc_blsp2_qup1_spi_apps_clk",1894 .parent_hws = (const struct clk_hw *[]) {1895 &blsp2_qup1_spi_apps_clk_src.clkr.hw,1896 },1897 .num_parents = 1,1898 .flags = CLK_SET_RATE_PARENT,1899 .ops = &clk_branch2_ops,1900 },1901 },1902};1903 1904static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {1905 .halt_reg = 0xd010,1906 .halt_check = BRANCH_HALT,1907 .clkr = {1908 .enable_reg = 0xd010,1909 .enable_mask = BIT(0),1910 .hw.init = &(struct clk_init_data) {1911 .name = "gcc_blsp2_qup2_i2c_apps_clk",1912 .parent_hws = (const struct clk_hw *[]) {1913 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,1914 },1915 .num_parents = 1,1916 .flags = CLK_SET_RATE_PARENT,1917 .ops = &clk_branch2_ops,1918 },1919 },1920};1921 1922static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {1923 .halt_reg = 0xd00c,1924 .halt_check = BRANCH_HALT,1925 .clkr = {1926 .enable_reg = 0xd00c,1927 .enable_mask = BIT(0),1928 .hw.init = &(struct clk_init_data) {1929 .name = "gcc_blsp2_qup2_spi_apps_clk",1930 .parent_hws = (const struct clk_hw *[]) {1931 &blsp2_qup2_spi_apps_clk_src.clkr.hw,1932 },1933 .num_parents = 1,1934 .flags = CLK_SET_RATE_PARENT,1935 .ops = &clk_branch2_ops,1936 },1937 },1938};1939 1940static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {1941 .halt_reg = 0xf020,1942 .halt_check = BRANCH_HALT,1943 .clkr = {1944 .enable_reg = 0xf020,1945 .enable_mask = BIT(0),1946 .hw.init = &(struct clk_init_data) {1947 .name = "gcc_blsp2_qup3_i2c_apps_clk",1948 .parent_hws = (const struct clk_hw *[]) {1949 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,1950 },1951 .num_parents = 1,1952 .flags = CLK_SET_RATE_PARENT,1953 .ops = &clk_branch2_ops,1954 },1955 },1956};1957 1958static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {1959 .halt_reg = 0xf01c,1960 .halt_check = BRANCH_HALT,1961 .clkr = {1962 .enable_reg = 0xf01c,1963 .enable_mask = BIT(0),1964 .hw.init = &(struct clk_init_data) {1965 .name = "gcc_blsp2_qup3_spi_apps_clk",1966 .parent_hws = (const struct clk_hw *[]) {1967 &blsp2_qup3_spi_apps_clk_src.clkr.hw,1968 },1969 .num_parents = 1,1970 .flags = CLK_SET_RATE_PARENT,1971 .ops = &clk_branch2_ops,1972 },1973 },1974};1975 1976static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {1977 .halt_reg = 0x18020,1978 .halt_check = BRANCH_HALT,1979 .clkr = {1980 .enable_reg = 0x18020,1981 .enable_mask = BIT(0),1982 .hw.init = &(struct clk_init_data) {1983 .name = "gcc_blsp2_qup4_i2c_apps_clk",1984 .parent_hws = (const struct clk_hw *[]) {1985 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,1986 },1987 .num_parents = 1,1988 .flags = CLK_SET_RATE_PARENT,1989 .ops = &clk_branch2_ops,1990 },1991 },1992};1993 1994static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {1995 .halt_reg = 0x1801c,1996 .halt_check = BRANCH_HALT,1997 .clkr = {1998 .enable_reg = 0x1801c,1999 .enable_mask = BIT(0),2000 .hw.init = &(struct clk_init_data) {2001 .name = "gcc_blsp2_qup4_spi_apps_clk",2002 .parent_hws = (const struct clk_hw *[]) {2003 &blsp2_qup4_spi_apps_clk_src.clkr.hw,2004 },2005 .num_parents = 1,2006 .flags = CLK_SET_RATE_PARENT,2007 .ops = &clk_branch2_ops,2008 },2009 },2010};2011 2012static struct clk_branch gcc_blsp2_uart1_apps_clk = {2013 .halt_reg = 0xc03c,2014 .halt_check = BRANCH_HALT,2015 .clkr = {2016 .enable_reg = 0xc03c,2017 .enable_mask = BIT(0),2018 .hw.init = &(struct clk_init_data) {2019 .name = "gcc_blsp2_uart1_apps_clk",2020 .parent_hws = (const struct clk_hw *[]) {2021 &blsp2_uart1_apps_clk_src.clkr.hw,2022 },2023 .num_parents = 1,2024 .flags = CLK_SET_RATE_PARENT,2025 .ops = &clk_branch2_ops,2026 },2027 },2028};2029 2030static struct clk_branch gcc_blsp2_uart2_apps_clk = {2031 .halt_reg = 0xd02c,2032 .halt_check = BRANCH_HALT,2033 .clkr = {2034 .enable_reg = 0xd02c,2035 .enable_mask = BIT(0),2036 .hw.init = &(struct clk_init_data) {2037 .name = "gcc_blsp2_uart2_apps_clk",2038 .parent_hws = (const struct clk_hw *[]) {2039 &blsp2_uart2_apps_clk_src.clkr.hw,2040 },2041 .num_parents = 1,2042 .flags = CLK_SET_RATE_PARENT,2043 .ops = &clk_branch2_ops,2044 },2045 },2046};2047 2048static struct clk_branch gcc_camss_cci_ahb_clk = {2049 .halt_reg = 0x5101c,2050 .clkr = {2051 .enable_reg = 0x5101c,2052 .enable_mask = BIT(0),2053 .hw.init = &(struct clk_init_data) {2054 .name = "gcc_camss_cci_ahb_clk",2055 .parent_hws = (const struct clk_hw *[]) {2056 &camss_top_ahb_clk_src.clkr.hw,2057 },2058 .num_parents = 1,2059 .flags = CLK_SET_RATE_PARENT,2060 .ops = &clk_branch2_ops,2061 },2062 },2063};2064 2065static struct clk_branch gcc_camss_cci_clk = {2066 .halt_reg = 0x51018,2067 .clkr = {2068 .enable_reg = 0x51018,2069 .enable_mask = BIT(0),2070 .hw.init = &(struct clk_init_data) {2071 .name = "gcc_camss_cci_clk",2072 .parent_hws = (const struct clk_hw *[]) {2073 &cci_clk_src.clkr.hw,2074 },2075 .num_parents = 1,2076 .flags = CLK_SET_RATE_PARENT,2077 .ops = &clk_branch2_ops,2078 },2079 },2080};2081 2082static struct clk_branch gcc_camss_cpp_ahb_clk = {2083 .halt_reg = 0x58040,2084 .clkr = {2085 .enable_reg = 0x58040,2086 .enable_mask = BIT(0),2087 .hw.init = &(struct clk_init_data) {2088 .name = "gcc_camss_cpp_ahb_clk",2089 .parent_hws = (const struct clk_hw *[]) {2090 &camss_top_ahb_clk_src.clkr.hw,2091 },2092 .num_parents = 1,2093 .flags = CLK_SET_RATE_PARENT,2094 .ops = &clk_branch2_ops,2095 },2096 },2097};2098 2099static struct clk_branch gcc_camss_cpp_axi_clk = {2100 .halt_reg = 0x58064,2101 .clkr = {2102 .enable_reg = 0x58064,2103 .enable_mask = BIT(0),2104 .hw.init = &(struct clk_init_data) {2105 .name = "gcc_camss_cpp_axi_clk",2106 .ops = &clk_branch2_ops,2107 },2108 },2109};2110 2111static struct clk_branch gcc_camss_cpp_clk = {2112 .halt_reg = 0x5803c,2113 .clkr = {2114 .enable_reg = 0x5803c,2115 .enable_mask = BIT(0),2116 .hw.init = &(struct clk_init_data) {2117 .name = "gcc_camss_cpp_clk",2118 .parent_hws = (const struct clk_hw *[]) {2119 &cpp_clk_src.clkr.hw,2120 },2121 .num_parents = 1,2122 .flags = CLK_SET_RATE_PARENT,2123 .ops = &clk_branch2_ops,2124 },2125 },2126};2127 2128static struct clk_branch gcc_camss_csi0_ahb_clk = {2129 .halt_reg = 0x4e040,2130 .clkr = {2131 .enable_reg = 0x4e040,2132 .enable_mask = BIT(0),2133 .hw.init = &(struct clk_init_data) {2134 .name = "gcc_camss_csi0_ahb_clk",2135 .parent_hws = (const struct clk_hw *[]) {2136 &camss_top_ahb_clk_src.clkr.hw,2137 },2138 .num_parents = 1,2139 .flags = CLK_SET_RATE_PARENT,2140 .ops = &clk_branch2_ops,2141 },2142 },2143};2144 2145static struct clk_branch gcc_camss_csi0_clk = {2146 .halt_reg = 0x4e03c,2147 .clkr = {2148 .enable_reg = 0x4e03c,2149 .enable_mask = BIT(0),2150 .hw.init = &(struct clk_init_data) {2151 .name = "gcc_camss_csi0_clk",2152 .parent_hws = (const struct clk_hw *[]) {2153 &csi0_clk_src.clkr.hw,2154 },2155 .num_parents = 1,2156 .flags = CLK_SET_RATE_PARENT,2157 .ops = &clk_branch2_ops,2158 },2159 },2160};2161 2162static struct clk_branch gcc_camss_csi0phy_clk = {2163 .halt_reg = 0x4e048,2164 .clkr = {2165 .enable_reg = 0x4e048,2166 .enable_mask = BIT(0),2167 .hw.init = &(struct clk_init_data) {2168 .name = "gcc_camss_csi0phy_clk",2169 .parent_hws = (const struct clk_hw *[]) {2170 &csi0_clk_src.clkr.hw,2171 },2172 .num_parents = 1,2173 .flags = CLK_SET_RATE_PARENT,2174 .ops = &clk_branch2_ops,2175 },2176 },2177};2178 2179static struct clk_branch gcc_camss_csi0pix_clk = {2180 .halt_reg = 0x4e058,2181 .clkr = {2182 .enable_reg = 0x4e058,2183 .enable_mask = BIT(0),2184 .hw.init = &(struct clk_init_data) {2185 .name = "gcc_camss_csi0pix_clk",2186 .parent_hws = (const struct clk_hw *[]) {2187 &csi0_clk_src.clkr.hw,2188 },2189 .num_parents = 1,2190 .flags = CLK_SET_RATE_PARENT,2191 .ops = &clk_branch2_ops,2192 },2193 },2194};2195 2196static struct clk_branch gcc_camss_csi0rdi_clk = {2197 .halt_reg = 0x4e050,2198 .clkr = {2199 .enable_reg = 0x4e050,2200 .enable_mask = BIT(0),2201 .hw.init = &(struct clk_init_data) {2202 .name = "gcc_camss_csi0rdi_clk",2203 .parent_hws = (const struct clk_hw *[]) {2204 &csi0_clk_src.clkr.hw,2205 },2206 .num_parents = 1,2207 .flags = CLK_SET_RATE_PARENT,2208 .ops = &clk_branch2_ops,2209 },2210 },2211};2212 2213static struct clk_branch gcc_camss_csi1_ahb_clk = {2214 .halt_reg = 0x4f040,2215 .clkr = {2216 .enable_reg = 0x4f040,2217 .enable_mask = BIT(0),2218 .hw.init = &(struct clk_init_data) {2219 .name = "gcc_camss_csi1_ahb_clk",2220 .parent_hws = (const struct clk_hw *[]) {2221 &camss_top_ahb_clk_src.clkr.hw,2222 },2223 .num_parents = 1,2224 .flags = CLK_SET_RATE_PARENT,2225 .ops = &clk_branch2_ops,2226 },2227 },2228};2229 2230static struct clk_branch gcc_camss_csi1_clk = {2231 .halt_reg = 0x4f03c,2232 .clkr = {2233 .enable_reg = 0x4f03c,2234 .enable_mask = BIT(0),2235 .hw.init = &(struct clk_init_data) {2236 .name = "gcc_camss_csi1_clk",2237 .parent_hws = (const struct clk_hw *[]) {2238 &csi1_clk_src.clkr.hw,2239 },2240 .num_parents = 1,2241 .flags = CLK_SET_RATE_PARENT,2242 .ops = &clk_branch2_ops,2243 },2244 },2245};2246 2247static struct clk_branch gcc_camss_csi1phy_clk = {2248 .halt_reg = 0x4f048,2249 .clkr = {2250 .enable_reg = 0x4f048,2251 .enable_mask = BIT(0),2252 .hw.init = &(struct clk_init_data) {2253 .name = "gcc_camss_csi1phy_clk",2254 .parent_hws = (const struct clk_hw *[]) {2255 &csi1_clk_src.clkr.hw,2256 },2257 .num_parents = 1,2258 .flags = CLK_SET_RATE_PARENT,2259 .ops = &clk_branch2_ops,2260 },2261 },2262};2263 2264static struct clk_branch gcc_camss_csi1pix_clk = {2265 .halt_reg = 0x4f058,2266 .clkr = {2267 .enable_reg = 0x4f058,2268 .enable_mask = BIT(0),2269 .hw.init = &(struct clk_init_data) {2270 .name = "gcc_camss_csi1pix_clk",2271 .parent_hws = (const struct clk_hw *[]) {2272 &csi1_clk_src.clkr.hw,2273 },2274 .num_parents = 1,2275 .flags = CLK_SET_RATE_PARENT,2276 .ops = &clk_branch2_ops,2277 },2278 },2279};2280 2281static struct clk_branch gcc_camss_csi1rdi_clk = {2282 .halt_reg = 0x4f050,2283 .clkr = {2284 .enable_reg = 0x4f050,2285 .enable_mask = BIT(0),2286 .hw.init = &(struct clk_init_data) {2287 .name = "gcc_camss_csi1rdi_clk",2288 .parent_hws = (const struct clk_hw *[]) {2289 &csi1_clk_src.clkr.hw,2290 },2291 .num_parents = 1,2292 .flags = CLK_SET_RATE_PARENT,2293 .ops = &clk_branch2_ops,2294 },2295 },2296};2297 2298static struct clk_branch gcc_camss_csi2_ahb_clk = {2299 .halt_reg = 0x3c040,2300 .clkr = {2301 .enable_reg = 0x3c040,2302 .enable_mask = BIT(0),2303 .hw.init = &(struct clk_init_data) {2304 .name = "gcc_camss_csi2_ahb_clk",2305 .parent_hws = (const struct clk_hw *[]) {2306 &camss_top_ahb_clk_src.clkr.hw,2307 },2308 .num_parents = 1,2309 .flags = CLK_SET_RATE_PARENT,2310 .ops = &clk_branch2_ops,2311 },2312 },2313};2314 2315static struct clk_branch gcc_camss_csi2_clk = {2316 .halt_reg = 0x3c03c,2317 .clkr = {2318 .enable_reg = 0x3c03c,2319 .enable_mask = BIT(0),2320 .hw.init = &(struct clk_init_data) {2321 .name = "gcc_camss_csi2_clk",2322 .parent_hws = (const struct clk_hw *[]) {2323 &csi2_clk_src.clkr.hw,2324 },2325 .num_parents = 1,2326 .flags = CLK_SET_RATE_PARENT,2327 .ops = &clk_branch2_ops,2328 },2329 },2330};2331 2332static struct clk_branch gcc_camss_csi2phy_clk = {2333 .halt_reg = 0x3c048,2334 .clkr = {2335 .enable_reg = 0x3c048,2336 .enable_mask = BIT(0),2337 .hw.init = &(struct clk_init_data) {2338 .name = "gcc_camss_csi2phy_clk",2339 .parent_hws = (const struct clk_hw *[]) {2340 &csi2_clk_src.clkr.hw,2341 },2342 .num_parents = 1,2343 .flags = CLK_SET_RATE_PARENT,2344 .ops = &clk_branch2_ops,2345 },2346 },2347};2348 2349static struct clk_branch gcc_camss_csi2pix_clk = {2350 .halt_reg = 0x3c058,2351 .clkr = {2352 .enable_reg = 0x3c058,2353 .enable_mask = BIT(0),2354 .hw.init = &(struct clk_init_data) {2355 .name = "gcc_camss_csi2pix_clk",2356 .parent_hws = (const struct clk_hw *[]) {2357 &csi2_clk_src.clkr.hw,2358 },2359 .num_parents = 1,2360 .flags = CLK_SET_RATE_PARENT,2361 .ops = &clk_branch2_ops,2362 },2363 },2364};2365 2366static struct clk_branch gcc_camss_csi2rdi_clk = {2367 .halt_reg = 0x3c050,2368 .clkr = {2369 .enable_reg = 0x3c050,2370 .enable_mask = BIT(0),2371 .hw.init = &(struct clk_init_data) {2372 .name = "gcc_camss_csi2rdi_clk",2373 .parent_hws = (const struct clk_hw *[]) {2374 &csi2_clk_src.clkr.hw,2375 },2376 .num_parents = 1,2377 .flags = CLK_SET_RATE_PARENT,2378 .ops = &clk_branch2_ops,2379 },2380 },2381};2382 2383static struct clk_branch gcc_camss_csi_vfe0_clk = {2384 .halt_reg = 0x58050,2385 .clkr = {2386 .enable_reg = 0x58050,2387 .enable_mask = BIT(0),2388 .hw.init = &(struct clk_init_data) {2389 .name = "gcc_camss_csi_vfe0_clk",2390 .parent_hws = (const struct clk_hw *[]) {2391 &vfe0_clk_src.clkr.hw,2392 },2393 .num_parents = 1,2394 .flags = CLK_SET_RATE_PARENT,2395 .ops = &clk_branch2_ops,2396 },2397 },2398};2399 2400static struct clk_branch gcc_camss_csi_vfe1_clk = {2401 .halt_reg = 0x58074,2402 .clkr = {2403 .enable_reg = 0x58074,2404 .enable_mask = BIT(0),2405 .hw.init = &(struct clk_init_data) {2406 .name = "gcc_camss_csi_vfe1_clk",2407 .parent_hws = (const struct clk_hw *[]) {2408 &vfe1_clk_src.clkr.hw,2409 },2410 .num_parents = 1,2411 .flags = CLK_SET_RATE_PARENT,2412 .ops = &clk_branch2_ops,2413 },2414 },2415};2416 2417static struct clk_branch gcc_camss_gp0_clk = {2418 .halt_reg = 0x54018,2419 .clkr = {2420 .enable_reg = 0x54018,2421 .enable_mask = BIT(0),2422 .hw.init = &(struct clk_init_data) {2423 .name = "gcc_camss_gp0_clk",2424 .parent_hws = (const struct clk_hw *[]) {2425 &camss_gp0_clk_src.clkr.hw,2426 },2427 .num_parents = 1,2428 .flags = CLK_SET_RATE_PARENT,2429 .ops = &clk_branch2_ops,2430 },2431 },2432};2433 2434static struct clk_branch gcc_camss_gp1_clk = {2435 .halt_reg = 0x55018,2436 .clkr = {2437 .enable_reg = 0x55018,2438 .enable_mask = BIT(0),2439 .hw.init = &(struct clk_init_data) {2440 .name = "gcc_camss_gp1_clk",2441 .parent_hws = (const struct clk_hw *[]) {2442 &camss_gp1_clk_src.clkr.hw,2443 },2444 .num_parents = 1,2445 .flags = CLK_SET_RATE_PARENT,2446 .ops = &clk_branch2_ops,2447 },2448 },2449};2450 2451static struct clk_branch gcc_camss_ispif_ahb_clk = {2452 .halt_reg = 0x50004,2453 .clkr = {2454 .enable_reg = 0x50004,2455 .enable_mask = BIT(0),2456 .hw.init = &(struct clk_init_data) {2457 .name = "gcc_camss_ispif_ahb_clk",2458 .parent_hws = (const struct clk_hw *[]) {2459 &camss_top_ahb_clk_src.clkr.hw,2460 },2461 .num_parents = 1,2462 .flags = CLK_SET_RATE_PARENT,2463 .ops = &clk_branch2_ops,2464 },2465 },2466};2467 2468static struct clk_branch gcc_camss_jpeg0_clk = {2469 .halt_reg = 0x57020,2470 .halt_check = BRANCH_HALT,2471 .clkr = {2472 .enable_reg = 0x57020,2473 .enable_mask = BIT(0),2474 .hw.init = &(struct clk_init_data) {2475 .name = "gcc_camss_jpeg0_clk",2476 .parent_hws = (const struct clk_hw *[]) {2477 &jpeg0_clk_src.clkr.hw,2478 },2479 .num_parents = 1,2480 .flags = CLK_SET_RATE_PARENT,2481 .ops = &clk_branch2_ops,2482 },2483 },2484};2485 2486static struct clk_branch gcc_camss_jpeg_ahb_clk = {2487 .halt_reg = 0x57024,2488 .clkr = {2489 .enable_reg = 0x57024,2490 .enable_mask = BIT(0),2491 .hw.init = &(struct clk_init_data) {2492 .name = "gcc_camss_jpeg_ahb_clk",2493 .parent_hws = (const struct clk_hw *[]) {2494 &camss_top_ahb_clk_src.clkr.hw,2495 },2496 .num_parents = 1,2497 .flags = CLK_SET_RATE_PARENT,2498 .ops = &clk_branch2_ops,2499 },2500 },2501};2502 2503static struct clk_branch gcc_camss_jpeg_axi_clk = {2504 .halt_reg = 0x57028,2505 .clkr = {2506 .enable_reg = 0x57028,2507 .enable_mask = BIT(0),2508 .hw.init = &(struct clk_init_data) {2509 .name = "gcc_camss_jpeg_axi_clk",2510 .ops = &clk_branch2_ops,2511 },2512 },2513};2514 2515static struct clk_branch gcc_camss_mclk0_clk = {2516 .halt_reg = 0x52018,2517 .clkr = {2518 .enable_reg = 0x52018,2519 .enable_mask = BIT(0),2520 .hw.init = &(struct clk_init_data) {2521 .name = "gcc_camss_mclk0_clk",2522 .parent_hws = (const struct clk_hw *[]) {2523 &mclk0_clk_src.clkr.hw,2524 },2525 .num_parents = 1,2526 .flags = CLK_SET_RATE_PARENT,2527 .ops = &clk_branch2_ops,2528 },2529 },2530};2531 2532static struct clk_branch gcc_camss_mclk1_clk = {2533 .halt_reg = 0x53018,2534 .clkr = {2535 .enable_reg = 0x53018,2536 .enable_mask = BIT(0),2537 .hw.init = &(struct clk_init_data) {2538 .name = "gcc_camss_mclk1_clk",2539 .parent_hws = (const struct clk_hw *[]) {2540 &mclk1_clk_src.clkr.hw,2541 },2542 .num_parents = 1,2543 .flags = CLK_SET_RATE_PARENT,2544 .ops = &clk_branch2_ops,2545 },2546 },2547};2548 2549static struct clk_branch gcc_camss_mclk2_clk = {2550 .halt_reg = 0x5c018,2551 .clkr = {2552 .enable_reg = 0x5c018,2553 .enable_mask = BIT(0),2554 .hw.init = &(struct clk_init_data) {2555 .name = "gcc_camss_mclk2_clk",2556 .parent_hws = (const struct clk_hw *[]) {2557 &mclk2_clk_src.clkr.hw,2558 },2559 .num_parents = 1,2560 .ops = &clk_branch2_ops,2561 },2562 },2563};2564 2565static struct clk_branch gcc_camss_micro_ahb_clk = {2566 .halt_reg = 0x5600c,2567 .clkr = {2568 .enable_reg = 0x5600c,2569 .enable_mask = BIT(0),2570 .hw.init = &(struct clk_init_data) {2571 .name = "gcc_camss_micro_ahb_clk",2572 .parent_hws = (const struct clk_hw *[]) {2573 &camss_top_ahb_clk_src.clkr.hw,2574 },2575 .num_parents = 1,2576 .flags = CLK_SET_RATE_PARENT,2577 .ops = &clk_branch2_ops,2578 },2579 },2580};2581 2582static struct clk_branch gcc_camss_csi0phytimer_clk = {2583 .halt_reg = 0x4e01c,2584 .clkr = {2585 .enable_reg = 0x4e01c,2586 .enable_mask = BIT(0),2587 .hw.init = &(struct clk_init_data) {2588 .name = "gcc_camss_csi0phytimer_clk",2589 .parent_hws = (const struct clk_hw *[]) {2590 &csi0phytimer_clk_src.clkr.hw,2591 },2592 .num_parents = 1,2593 .flags = CLK_SET_RATE_PARENT,2594 .ops = &clk_branch2_ops,2595 },2596 },2597};2598 2599static struct clk_branch gcc_camss_csi1phytimer_clk = {2600 .halt_reg = 0x4f01c,2601 .clkr = {2602 .enable_reg = 0x4f01c,2603 .enable_mask = BIT(0),2604 .hw.init = &(struct clk_init_data) {2605 .name = "gcc_camss_csi1phytimer_clk",2606 .parent_hws = (const struct clk_hw *[]) {2607 &csi1phytimer_clk_src.clkr.hw,2608 },2609 .num_parents = 1,2610 .flags = CLK_SET_RATE_PARENT,2611 .ops = &clk_branch2_ops,2612 },2613 },2614};2615 2616static struct clk_branch gcc_camss_ahb_clk = {2617 .halt_reg = 0x56004,2618 .clkr = {2619 .enable_reg = 0x56004,2620 .enable_mask = BIT(0),2621 .hw.init = &(struct clk_init_data) {2622 .name = "gcc_camss_ahb_clk",2623 .ops = &clk_branch2_ops,2624 },2625 },2626};2627 2628static struct clk_branch gcc_camss_top_ahb_clk = {2629 .halt_reg = 0x5a014,2630 .clkr = {2631 .enable_reg = 0x5a014,2632 .enable_mask = BIT(0),2633 .hw.init = &(struct clk_init_data) {2634 .name = "gcc_camss_top_ahb_clk",2635 .parent_hws = (const struct clk_hw *[]) {2636 &camss_top_ahb_clk_src.clkr.hw,2637 },2638 .num_parents = 1,2639 .flags = CLK_SET_RATE_PARENT,2640 .ops = &clk_branch2_ops,2641 },2642 },2643};2644 2645static struct clk_branch gcc_camss_vfe0_clk = {2646 .halt_reg = 0x58038,2647 .clkr = {2648 .enable_reg = 0x58038,2649 .enable_mask = BIT(0),2650 .hw.init = &(struct clk_init_data) {2651 .name = "gcc_camss_vfe0_clk",2652 .parent_hws = (const struct clk_hw *[]) {2653 &vfe0_clk_src.clkr.hw,2654 },2655 .num_parents = 1,2656 .flags = CLK_SET_RATE_PARENT,2657 .ops = &clk_branch2_ops,2658 },2659 },2660};2661 2662static struct clk_branch gcc_camss_vfe_ahb_clk = {2663 .halt_reg = 0x58044,2664 .clkr = {2665 .enable_reg = 0x58044,2666 .enable_mask = BIT(0),2667 .hw.init = &(struct clk_init_data) {2668 .name = "gcc_camss_vfe_ahb_clk",2669 .parent_hws = (const struct clk_hw *[]) {2670 &camss_top_ahb_clk_src.clkr.hw,2671 },2672 .num_parents = 1,2673 .flags = CLK_SET_RATE_PARENT,2674 .ops = &clk_branch2_ops,2675 },2676 },2677};2678 2679static struct clk_branch gcc_camss_vfe_axi_clk = {2680 .halt_reg = 0x58048,2681 .clkr = {2682 .enable_reg = 0x58048,2683 .enable_mask = BIT(0),2684 .hw.init = &(struct clk_init_data) {2685 .name = "gcc_camss_vfe_axi_clk",2686 .ops = &clk_branch2_ops,2687 },2688 },2689};2690 2691static struct clk_branch gcc_camss_vfe1_ahb_clk = {2692 .halt_reg = 0x58060,2693 .clkr = {2694 .enable_reg = 0x58060,2695 .enable_mask = BIT(0),2696 .hw.init = &(struct clk_init_data) {2697 .name = "gcc_camss_vfe1_ahb_clk",2698 .parent_hws = (const struct clk_hw *[]) {2699 &camss_top_ahb_clk_src.clkr.hw,2700 },2701 .num_parents = 1,2702 .flags = CLK_SET_RATE_PARENT,2703 .ops = &clk_branch2_ops,2704 },2705 },2706};2707 2708static struct clk_branch gcc_camss_vfe1_axi_clk = {2709 .halt_reg = 0x58068,2710 .clkr = {2711 .enable_reg = 0x58068,2712 .enable_mask = BIT(0),2713 .hw.init = &(struct clk_init_data) {2714 .name = "gcc_camss_vfe1_axi_clk",2715 .ops = &clk_branch2_ops,2716 },2717 },2718};2719 2720static struct clk_branch gcc_camss_vfe1_clk = {2721 .halt_reg = 0x5805c,2722 .clkr = {2723 .enable_reg = 0x5805c,2724 .enable_mask = BIT(0),2725 .hw.init = &(struct clk_init_data) {2726 .name = "gcc_camss_vfe1_clk",2727 .parent_hws = (const struct clk_hw *[]) {2728 &vfe1_clk_src.clkr.hw,2729 },2730 .num_parents = 1,2731 .flags = CLK_SET_RATE_PARENT,2732 .ops = &clk_branch2_ops,2733 },2734 },2735};2736 2737static struct clk_branch gcc_dcc_clk = {2738 .halt_reg = 0x77004,2739 .clkr = {2740 .enable_reg = 0x77004,2741 .enable_mask = BIT(0),2742 .hw.init = &(struct clk_init_data) {2743 .name = "gcc_dcc_clk",2744 .ops = &clk_branch2_ops,2745 },2746 },2747};2748 2749static struct clk_branch gcc_oxili_gmem_clk = {2750 .halt_reg = 0x59024,2751 .clkr = {2752 .enable_reg = 0x59024,2753 .enable_mask = BIT(0),2754 .hw.init = &(struct clk_init_data) {2755 .name = "gcc_oxili_gmem_clk",2756 .parent_hws = (const struct clk_hw *[]) {2757 &gfx3d_clk_src.clkr.hw,2758 },2759 .num_parents = 1,2760 .flags = CLK_SET_RATE_PARENT,2761 .ops = &clk_branch2_ops,2762 },2763 },2764};2765 2766static struct clk_branch gcc_gp1_clk = {2767 .halt_reg = 0x8000,2768 .halt_check = BRANCH_HALT,2769 .clkr = {2770 .enable_reg = 0x8000,2771 .enable_mask = BIT(0),2772 .hw.init = &(struct clk_init_data) {2773 .name = "gcc_gp1_clk",2774 .parent_hws = (const struct clk_hw *[]) {2775 &gp1_clk_src.clkr.hw,2776 },2777 .num_parents = 1,2778 .flags = CLK_SET_RATE_PARENT,2779 .ops = &clk_branch2_ops,2780 },2781 },2782};2783 2784static struct clk_branch gcc_gp2_clk = {2785 .halt_reg = 0x9000,2786 .halt_check = BRANCH_HALT,2787 .clkr = {2788 .enable_reg = 0x9000,2789 .enable_mask = BIT(0),2790 .hw.init = &(struct clk_init_data) {2791 .name = "gcc_gp2_clk",2792 .parent_hws = (const struct clk_hw *[]) {2793 &gp2_clk_src.clkr.hw,2794 },2795 .num_parents = 1,2796 .flags = CLK_SET_RATE_PARENT,2797 .ops = &clk_branch2_ops,2798 },2799 },2800};2801 2802static struct clk_branch gcc_gp3_clk = {2803 .halt_reg = 0xa000,2804 .halt_check = BRANCH_HALT,2805 .clkr = {2806 .enable_reg = 0xa000,2807 .enable_mask = BIT(0),2808 .hw.init = &(struct clk_init_data) {2809 .name = "gcc_gp3_clk",2810 .parent_hws = (const struct clk_hw *[]) {2811 &gp3_clk_src.clkr.hw,2812 },2813 .num_parents = 1,2814 .flags = CLK_SET_RATE_PARENT,2815 .ops = &clk_branch2_ops,2816 },2817 },2818};2819 2820static struct clk_branch gcc_mdss_ahb_clk = {2821 .halt_reg = 0x4d07c,2822 .halt_check = BRANCH_HALT,2823 .clkr = {2824 .enable_reg = 0x4d07c,2825 .enable_mask = BIT(0),2826 .hw.init = &(struct clk_init_data) {2827 .name = "gcc_mdss_ahb_clk",2828 .ops = &clk_branch2_ops,2829 },2830 },2831};2832 2833static struct clk_branch gcc_mdss_axi_clk = {2834 .halt_reg = 0x4d080,2835 .halt_check = BRANCH_HALT,2836 .clkr = {2837 .enable_reg = 0x4d080,2838 .enable_mask = BIT(0),2839 .hw.init = &(struct clk_init_data) {2840 .name = "gcc_mdss_axi_clk",2841 .ops = &clk_branch2_ops,2842 },2843 },2844};2845 2846static struct clk_branch gcc_mdss_byte0_clk = {2847 .halt_reg = 0x4d094,2848 .halt_check = BRANCH_HALT,2849 .clkr = {2850 .enable_reg = 0x4d094,2851 .enable_mask = BIT(0),2852 .hw.init = &(struct clk_init_data) {2853 .name = "gcc_mdss_byte0_clk",2854 .parent_hws = (const struct clk_hw *[]) {2855 &byte0_clk_src.clkr.hw,2856 },2857 .num_parents = 1,2858 .flags = CLK_SET_RATE_PARENT,2859 .ops = &clk_branch2_ops,2860 },2861 },2862};2863 2864static struct clk_branch gcc_mdss_byte1_clk = {2865 .halt_reg = 0x4d0a0,2866 .halt_check = BRANCH_HALT,2867 .clkr = {2868 .enable_reg = 0x4d0a0,2869 .enable_mask = BIT(0),2870 .hw.init = &(struct clk_init_data) {2871 .name = "gcc_mdss_byte1_clk",2872 .parent_hws = (const struct clk_hw *[]) {2873 &byte1_clk_src.clkr.hw,2874 },2875 .num_parents = 1,2876 .flags = CLK_SET_RATE_PARENT,2877 .ops = &clk_branch2_ops,2878 },2879 },2880};2881 2882static struct clk_branch gcc_mdss_esc0_clk = {2883 .halt_reg = 0x4d098,2884 .halt_check = BRANCH_HALT,2885 .clkr = {2886 .enable_reg = 0x4d098,2887 .enable_mask = BIT(0),2888 .hw.init = &(struct clk_init_data) {2889 .name = "gcc_mdss_esc0_clk",2890 .parent_hws = (const struct clk_hw *[]) {2891 &esc0_clk_src.clkr.hw,2892 },2893 .num_parents = 1,2894 .flags = CLK_SET_RATE_PARENT,2895 .ops = &clk_branch2_ops,2896 },2897 },2898};2899 2900static struct clk_branch gcc_mdss_esc1_clk = {2901 .halt_reg = 0x4d09c,2902 .halt_check = BRANCH_HALT,2903 .clkr = {2904 .enable_reg = 0x4d09c,2905 .enable_mask = BIT(0),2906 .hw.init = &(struct clk_init_data) {2907 .name = "gcc_mdss_esc1_clk",2908 .parent_hws = (const struct clk_hw *[]) {2909 &esc1_clk_src.clkr.hw,2910 },2911 .num_parents = 1,2912 .flags = CLK_SET_RATE_PARENT,2913 .ops = &clk_branch2_ops,2914 },2915 },2916};2917 2918static struct clk_branch gcc_mdss_mdp_clk = {2919 .halt_reg = 0x4d088,2920 .halt_check = BRANCH_HALT,2921 .clkr = {2922 .enable_reg = 0x4d088,2923 .enable_mask = BIT(0),2924 .hw.init = &(struct clk_init_data) {2925 .name = "gcc_mdss_mdp_clk",2926 .parent_hws = (const struct clk_hw *[]) {2927 &mdp_clk_src.clkr.hw,2928 },2929 .num_parents = 1,2930 .flags = CLK_SET_RATE_PARENT,2931 .ops = &clk_branch2_ops,2932 },2933 },2934};2935 2936static struct clk_branch gcc_mdss_pclk0_clk = {2937 .halt_reg = 0x4d084,2938 .halt_check = BRANCH_HALT,2939 .clkr = {2940 .enable_reg = 0x4d084,2941 .enable_mask = BIT(0),2942 .hw.init = &(struct clk_init_data) {2943 .name = "gcc_mdss_pclk0_clk",2944 .parent_hws = (const struct clk_hw *[]) {2945 &pclk0_clk_src.clkr.hw,2946 },2947 .num_parents = 1,2948 .flags = CLK_SET_RATE_PARENT,2949 .ops = &clk_branch2_ops,2950 },2951 },2952};2953 2954static struct clk_branch gcc_mdss_pclk1_clk = {2955 .halt_reg = 0x4d0a4,2956 .halt_check = BRANCH_HALT,2957 .clkr = {2958 .enable_reg = 0x4d0a4,2959 .enable_mask = BIT(0),2960 .hw.init = &(struct clk_init_data) {2961 .name = "gcc_mdss_pclk1_clk",2962 .parent_hws = (const struct clk_hw *[]) {2963 &pclk1_clk_src.clkr.hw,2964 },2965 .num_parents = 1,2966 .flags = CLK_SET_RATE_PARENT,2967 .ops = &clk_branch2_ops,2968 },2969 },2970};2971 2972static struct clk_branch gcc_mdss_vsync_clk = {2973 .halt_reg = 0x4d090,2974 .halt_check = BRANCH_HALT,2975 .clkr = {2976 .enable_reg = 0x4d090,2977 .enable_mask = BIT(0),2978 .hw.init = &(struct clk_init_data) {2979 .name = "gcc_mdss_vsync_clk",2980 .parent_hws = (const struct clk_hw *[]) {2981 &vsync_clk_src.clkr.hw,2982 },2983 .num_parents = 1,2984 .flags = CLK_SET_RATE_PARENT,2985 .ops = &clk_branch2_ops,2986 },2987 },2988};2989 2990static struct clk_branch gcc_mss_cfg_ahb_clk = {2991 .halt_reg = 0x49000,2992 .clkr = {2993 .enable_reg = 0x49000,2994 .enable_mask = BIT(0),2995 .hw.init = &(struct clk_init_data) {2996 .name = "gcc_mss_cfg_ahb_clk",2997 .ops = &clk_branch2_ops,2998 },2999 },3000};3001 3002static struct clk_branch gcc_mss_q6_bimc_axi_clk = {3003 .halt_reg = 0x49004,3004 .halt_check = BRANCH_HALT,3005 .clkr = {3006 .enable_reg = 0x49004,3007 .enable_mask = BIT(0),3008 .hw.init = &(struct clk_init_data) {3009 .name = "gcc_mss_q6_bimc_axi_clk",3010 .ops = &clk_branch2_ops,3011 },3012 },3013};3014 3015static struct clk_branch gcc_bimc_gfx_clk = {3016 .halt_reg = 0x59048,3017 .clkr = {3018 .enable_reg = 0x59048,3019 .enable_mask = BIT(0),3020 .hw.init = &(struct clk_init_data) {3021 .name = "gcc_bimc_gfx_clk",3022 .ops = &clk_branch2_ops,3023 },3024 },3025};3026 3027static struct clk_branch gcc_oxili_ahb_clk = {3028 .halt_reg = 0x59028,3029 .clkr = {3030 .enable_reg = 0x59028,3031 .enable_mask = BIT(0),3032 .hw.init = &(struct clk_init_data) {3033 .name = "gcc_oxili_ahb_clk",3034 .ops = &clk_branch2_ops,3035 },3036 },3037};3038 3039static struct clk_branch gcc_oxili_aon_clk = {3040 .halt_reg = 0x59044,3041 .clkr = {3042 .enable_reg = 0x59044,3043 .enable_mask = BIT(0),3044 .hw.init = &(struct clk_init_data) {3045 .name = "gcc_oxili_aon_clk",3046 .parent_hws = (const struct clk_hw *[]) {3047 &gfx3d_clk_src.clkr.hw,3048 },3049 .num_parents = 1,3050 .flags = CLK_SET_RATE_PARENT,3051 .ops = &clk_branch2_ops,3052 },3053 },3054};3055 3056static struct clk_branch gcc_oxili_gfx3d_clk = {3057 .halt_reg = 0x59020,3058 .clkr = {3059 .enable_reg = 0x59020,3060 .enable_mask = BIT(0),3061 .hw.init = &(struct clk_init_data) {3062 .name = "gcc_oxili_gfx3d_clk",3063 .parent_hws = (const struct clk_hw *[]) {3064 &gfx3d_clk_src.clkr.hw,3065 },3066 .num_parents = 1,3067 .flags = CLK_SET_RATE_PARENT,3068 .ops = &clk_branch2_ops,3069 },3070 },3071};3072 3073static struct clk_branch gcc_oxili_timer_clk = {3074 .halt_reg = 0x59040,3075 .clkr = {3076 .enable_reg = 0x59040,3077 .enable_mask = BIT(0),3078 .hw.init = &(struct clk_init_data) {3079 .name = "gcc_oxili_timer_clk",3080 .parent_data = &(const struct clk_parent_data){3081 .fw_name = "xo",3082 },3083 .num_parents = 1,3084 .ops = &clk_branch2_ops,3085 },3086 },3087};3088 3089static struct clk_branch gcc_pdm2_clk = {3090 .halt_reg = 0x4400c,3091 .halt_check = BRANCH_HALT,3092 .clkr = {3093 .enable_reg = 0x4400c,3094 .enable_mask = BIT(0),3095 .hw.init = &(struct clk_init_data) {3096 .name = "gcc_pdm2_clk",3097 .parent_hws = (const struct clk_hw *[]) {3098 &pdm2_clk_src.clkr.hw,3099 },3100 .num_parents = 1,3101 .flags = CLK_SET_RATE_PARENT,3102 .ops = &clk_branch2_ops,3103 },3104 },3105};3106 3107static struct clk_branch gcc_pdm_ahb_clk = {3108 .halt_reg = 0x44004,3109 .halt_check = BRANCH_HALT,3110 .clkr = {3111 .enable_reg = 0x44004,3112 .enable_mask = BIT(0),3113 .hw.init = &(struct clk_init_data) {3114 .name = "gcc_pdm_ahb_clk",3115 .ops = &clk_branch2_ops,3116 },3117 },3118};3119 3120static struct clk_branch gcc_rbcpr_gfx_ahb_clk = {3121 .halt_reg = 0x3a008,3122 .clkr = {3123 .enable_reg = 0x3a008,3124 .enable_mask = BIT(0),3125 .hw.init = &(struct clk_init_data) {3126 .name = "gcc_rbcpr_gfx_ahb_clk",3127 .ops = &clk_branch2_ops,3128 },3129 },3130};3131 3132static struct clk_branch gcc_rbcpr_gfx_clk = {3133 .halt_reg = 0x3a004,3134 .clkr = {3135 .enable_reg = 0x3a004,3136 .enable_mask = BIT(0),3137 .hw.init = &(struct clk_init_data) {3138 .name = "gcc_rbcpr_gfx_clk",3139 .parent_hws = (const struct clk_hw *[]) {3140 &rbcpr_gfx_clk_src.clkr.hw,3141 },3142 .num_parents = 1,3143 .flags = CLK_SET_RATE_PARENT,3144 .ops = &clk_branch2_ops,3145 },3146 },3147};3148 3149static struct clk_branch gcc_sdcc1_ahb_clk = {3150 .halt_reg = 0x4201c,3151 .halt_check = BRANCH_HALT,3152 .clkr = {3153 .enable_reg = 0x4201c,3154 .enable_mask = BIT(0),3155 .hw.init = &(struct clk_init_data) {3156 .name = "gcc_sdcc1_ahb_clk",3157 .ops = &clk_branch2_ops,3158 },3159 },3160};3161 3162static struct clk_branch gcc_sdcc1_apps_clk = {3163 .halt_reg = 0x42018,3164 .halt_check = BRANCH_HALT,3165 .clkr = {3166 .enable_reg = 0x42018,3167 .enable_mask = BIT(0),3168 .hw.init = &(struct clk_init_data) {3169 .name = "gcc_sdcc1_apps_clk",3170 .parent_hws = (const struct clk_hw *[]) {3171 &sdcc1_apps_clk_src.clkr.hw,3172 },3173 .num_parents = 1,3174 .flags = CLK_SET_RATE_PARENT,3175 .ops = &clk_branch2_ops,3176 },3177 },3178};3179 3180static struct clk_branch gcc_sdcc1_ice_core_clk = {3181 .halt_reg = 0x5d014,3182 .halt_check = BRANCH_HALT,3183 .clkr = {3184 .enable_reg = 0x5d014,3185 .enable_mask = BIT(0),3186 .hw.init = &(struct clk_init_data) {3187 .name = "gcc_sdcc1_ice_core_clk",3188 .parent_hws = (const struct clk_hw *[]) {3189 &sdcc1_ice_core_clk_src.clkr.hw,3190 },3191 .num_parents = 1,3192 .flags = CLK_SET_RATE_PARENT,3193 .ops = &clk_branch2_ops,3194 },3195 },3196};3197 3198static struct clk_branch gcc_sdcc2_ahb_clk = {3199 .halt_reg = 0x4301c,3200 .halt_check = BRANCH_HALT,3201 .clkr = {3202 .enable_reg = 0x4301c,3203 .enable_mask = BIT(0),3204 .hw.init = &(struct clk_init_data) {3205 .name = "gcc_sdcc2_ahb_clk",3206 .ops = &clk_branch2_ops,3207 },3208 },3209};3210 3211static struct clk_branch gcc_sdcc2_apps_clk = {3212 .halt_reg = 0x43018,3213 .halt_check = BRANCH_HALT,3214 .clkr = {3215 .enable_reg = 0x43018,3216 .enable_mask = BIT(0),3217 .hw.init = &(struct clk_init_data) {3218 .name = "gcc_sdcc2_apps_clk",3219 .parent_hws = (const struct clk_hw *[]) {3220 &sdcc2_apps_clk_src.clkr.hw,3221 },3222 .num_parents = 1,3223 .flags = CLK_SET_RATE_PARENT,3224 .ops = &clk_branch2_ops,3225 },3226 },3227};3228 3229static struct clk_branch gcc_sdcc3_ahb_clk = {3230 .halt_reg = 0x3901c,3231 .halt_check = BRANCH_HALT,3232 .clkr = {3233 .enable_reg = 0x3901c,3234 .enable_mask = BIT(0),3235 .hw.init = &(struct clk_init_data) {3236 .name = "gcc_sdcc3_ahb_clk",3237 .ops = &clk_branch2_ops,3238 },3239 },3240};3241 3242static struct clk_branch gcc_sdcc3_apps_clk = {3243 .halt_reg = 0x39018,3244 .halt_check = BRANCH_HALT,3245 .clkr = {3246 .enable_reg = 0x39018,3247 .enable_mask = BIT(0),3248 .hw.init = &(struct clk_init_data) {3249 .name = "gcc_sdcc3_apps_clk",3250 .parent_hws = (const struct clk_hw *[]) {3251 &sdcc3_apps_clk_src.clkr.hw,3252 },3253 .num_parents = 1,3254 .flags = CLK_SET_RATE_PARENT,3255 .ops = &clk_branch2_ops,3256 },3257 },3258};3259 3260static struct clk_branch gcc_usb2a_phy_sleep_clk = {3261 .halt_reg = 0x4102c,3262 .clkr = {3263 .enable_reg = 0x4102c,3264 .enable_mask = BIT(0),3265 .hw.init = &(struct clk_init_data) {3266 .name = "gcc_usb2a_phy_sleep_clk",3267 .ops = &clk_branch2_ops,3268 },3269 },3270};3271 3272static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {3273 .halt_reg = 0x41030,3274 .clkr = {3275 .enable_reg = 0x41030,3276 .enable_mask = BIT(0),3277 .hw.init = &(struct clk_init_data) {3278 .name = "gcc_usb_hs_phy_cfg_ahb_clk",3279 .ops = &clk_branch2_ops,3280 },3281 },3282};3283 3284static struct clk_branch gcc_usb_fs_ahb_clk = {3285 .halt_reg = 0x3f008,3286 .clkr = {3287 .enable_reg = 0x3f008,3288 .enable_mask = BIT(0),3289 .hw.init = &(struct clk_init_data) {3290 .name = "gcc_usb_fs_ahb_clk",3291 .ops = &clk_branch2_ops,3292 },3293 },3294};3295 3296static struct clk_branch gcc_usb_fs_ic_clk = {3297 .halt_reg = 0x3f030,3298 .clkr = {3299 .enable_reg = 0x3f030,3300 .enable_mask = BIT(0),3301 .hw.init = &(struct clk_init_data) {3302 .name = "gcc_usb_fs_ic_clk",3303 .parent_hws = (const struct clk_hw *[]) {3304 &usb_fs_ic_clk_src.clkr.hw,3305 },3306 .num_parents = 1,3307 .flags = CLK_SET_RATE_PARENT,3308 .ops = &clk_branch2_ops,3309 },3310 },3311};3312 3313static struct clk_branch gcc_usb_fs_system_clk = {3314 .halt_reg = 0x3f004,3315 .clkr = {3316 .enable_reg = 0x3f004,3317 .enable_mask = BIT(0),3318 .hw.init = &(struct clk_init_data) {3319 .name = "gcc_usb_fs_system_clk",3320 .parent_hws = (const struct clk_hw *[]) {3321 &usb_fs_system_clk_src.clkr.hw,3322 },3323 .num_parents = 1,3324 .flags = CLK_SET_RATE_PARENT,3325 .ops = &clk_branch2_ops,3326 },3327 },3328};3329 3330static struct clk_branch gcc_usb_hs_ahb_clk = {3331 .halt_reg = 0x41008,3332 .clkr = {3333 .enable_reg = 0x41008,3334 .enable_mask = BIT(0),3335 .hw.init = &(struct clk_init_data) {3336 .name = "gcc_usb_hs_ahb_clk",3337 .ops = &clk_branch2_ops,3338 },3339 },3340};3341 3342static struct clk_branch gcc_usb_hs_system_clk = {3343 .halt_reg = 0x41004,3344 .clkr = {3345 .enable_reg = 0x41004,3346 .enable_mask = BIT(0),3347 .hw.init = &(struct clk_init_data) {3348 .name = "gcc_usb_hs_system_clk",3349 .parent_hws = (const struct clk_hw *[]) {3350 &usb_hs_system_clk_src.clkr.hw,3351 },3352 .num_parents = 1,3353 .flags = CLK_SET_RATE_PARENT,3354 .ops = &clk_branch2_ops,3355 },3356 },3357};3358 3359static struct clk_branch gcc_venus0_ahb_clk = {3360 .halt_reg = 0x4c020,3361 .clkr = {3362 .enable_reg = 0x4c020,3363 .enable_mask = BIT(0),3364 .hw.init = &(struct clk_init_data) {3365 .name = "gcc_venus0_ahb_clk",3366 .ops = &clk_branch2_ops,3367 },3368 },3369};3370 3371static struct clk_branch gcc_venus0_axi_clk = {3372 .halt_reg = 0x4c024,3373 .clkr = {3374 .enable_reg = 0x4c024,3375 .enable_mask = BIT(0),3376 .hw.init = &(struct clk_init_data) {3377 .name = "gcc_venus0_axi_clk",3378 .ops = &clk_branch2_ops,3379 },3380 },3381};3382 3383static struct clk_branch gcc_venus0_core0_vcodec0_clk = {3384 .halt_reg = 0x4c02c,3385 .clkr = {3386 .enable_reg = 0x4c02c,3387 .enable_mask = BIT(0),3388 .hw.init = &(struct clk_init_data) {3389 .name = "gcc_venus0_core0_vcodec0_clk",3390 .parent_hws = (const struct clk_hw *[]) {3391 &vcodec0_clk_src.clkr.hw,3392 },3393 .num_parents = 1,3394 .flags = CLK_SET_RATE_PARENT,3395 .ops = &clk_branch2_ops,3396 },3397 },3398};3399 3400static struct clk_branch gcc_venus0_core1_vcodec0_clk = {3401 .halt_reg = 0x4c034,3402 .clkr = {3403 .enable_reg = 0x4c034,3404 .enable_mask = BIT(0),3405 .hw.init = &(struct clk_init_data) {3406 .name = "gcc_venus0_core1_vcodec0_clk",3407 .parent_hws = (const struct clk_hw *[]) {3408 &vcodec0_clk_src.clkr.hw,3409 },3410 .num_parents = 1,3411 .flags = CLK_SET_RATE_PARENT,3412 .ops = &clk_branch2_ops,3413 },3414 },3415};3416 3417static struct clk_branch gcc_venus0_vcodec0_clk = {3418 .halt_reg = 0x4c01c,3419 .clkr = {3420 .enable_reg = 0x4c01c,3421 .enable_mask = BIT(0),3422 .hw.init = &(struct clk_init_data) {3423 .name = "gcc_venus0_vcodec0_clk",3424 .parent_hws = (const struct clk_hw *[]) {3425 &vcodec0_clk_src.clkr.hw,3426 },3427 .num_parents = 1,3428 .flags = CLK_SET_RATE_PARENT,3429 .ops = &clk_branch2_ops,3430 },3431 },3432};3433 3434/* Vote clocks */3435static struct clk_branch gcc_apss_ahb_clk = {3436 .halt_reg = 0x4601c,3437 .halt_check = BRANCH_HALT_VOTED,3438 .clkr = {3439 .enable_reg = 0x45004,3440 .enable_mask = BIT(14),3441 .hw.init = &(struct clk_init_data){3442 .name = "gcc_apss_ahb_clk",3443 .ops = &clk_branch2_ops,3444 },3445 },3446};3447 3448static struct clk_branch gcc_apss_axi_clk = {3449 .halt_reg = 0x46020,3450 .halt_check = BRANCH_HALT_VOTED,3451 .clkr = {3452 .enable_reg = 0x45004,3453 .enable_mask = BIT(13),3454 .hw.init = &(struct clk_init_data){3455 .name = "gcc_apss_axi_clk",3456 .ops = &clk_branch2_ops,3457 },3458 },3459};3460 3461static struct clk_branch gcc_blsp1_ahb_clk = {3462 .halt_reg = 0x1008,3463 .halt_check = BRANCH_HALT_VOTED,3464 .clkr = {3465 .enable_reg = 0x45004,3466 .enable_mask = BIT(10),3467 .hw.init = &(struct clk_init_data){3468 .name = "gcc_blsp1_ahb_clk",3469 .ops = &clk_branch2_ops,3470 },3471 },3472};3473 3474static struct clk_branch gcc_blsp2_ahb_clk = {3475 .halt_reg = 0xb008,3476 .halt_check = BRANCH_HALT_VOTED,3477 .clkr = {3478 .enable_reg = 0x45004,3479 .enable_mask = BIT(20),3480 .hw.init = &(struct clk_init_data){3481 .name = "gcc_blsp2_ahb_clk",3482 .ops = &clk_branch2_ops,3483 },3484 },3485};3486 3487static struct clk_branch gcc_prng_ahb_clk = {3488 .halt_reg = 0x13004,3489 .halt_check = BRANCH_HALT_VOTED,3490 .clkr = {3491 .enable_reg = 0x45004,3492 .enable_mask = BIT(8),3493 .hw.init = &(struct clk_init_data){3494 .name = "gcc_prng_ahb_clk",3495 .ops = &clk_branch2_ops,3496 },3497 },3498};3499 3500static struct clk_branch gcc_boot_rom_ahb_clk = {3501 .halt_reg = 0x1300c,3502 .halt_check = BRANCH_HALT_VOTED,3503 .clkr = {3504 .enable_reg = 0x45004,3505 .enable_mask = BIT(7),3506 .hw.init = &(struct clk_init_data){3507 .name = "gcc_boot_rom_ahb_clk",3508 .ops = &clk_branch2_ops,3509 },3510 },3511};3512 3513static struct clk_branch gcc_crypto_ahb_clk = {3514 .halt_reg = 0x16024,3515 .halt_check = BRANCH_HALT_VOTED,3516 .clkr = {3517 .enable_reg = 0x45004,3518 .enable_mask = BIT(0),3519 .hw.init = &(struct clk_init_data){3520 .name = "gcc_crypto_ahb_clk",3521 .ops = &clk_branch2_ops,3522 },3523 },3524};3525 3526static struct clk_branch gcc_crypto_axi_clk = {3527 .halt_reg = 0x16020,3528 .halt_check = BRANCH_HALT_VOTED,3529 .clkr = {3530 .enable_reg = 0x45004,3531 .enable_mask = BIT(1),3532 .hw.init = &(struct clk_init_data){3533 .name = "gcc_crypto_axi_clk",3534 .ops = &clk_branch2_ops,3535 },3536 },3537};3538 3539static struct clk_branch gcc_crypto_clk = {3540 .halt_reg = 0x1601c,3541 .halt_check = BRANCH_HALT_VOTED,3542 .clkr = {3543 .enable_reg = 0x45004,3544 .enable_mask = BIT(2),3545 .hw.init = &(struct clk_init_data){3546 .name = "gcc_crypto_clk",3547 .parent_hws = (const struct clk_hw *[]) {3548 &crypto_clk_src.clkr.hw,3549 },3550 .num_parents = 1,3551 .flags = CLK_SET_RATE_PARENT,3552 .ops = &clk_branch2_ops,3553 },3554 },3555};3556 3557static struct clk_branch gcc_cpp_tbu_clk = {3558 .halt_reg = 0x12040,3559 .halt_check = BRANCH_HALT_VOTED,3560 .clkr = {3561 .enable_reg = 0x4500c,3562 .enable_mask = BIT(14),3563 .hw.init = &(struct clk_init_data){3564 .name = "gcc_cpp_tbu_clk",3565 .ops = &clk_branch2_ops,3566 },3567 },3568};3569 3570static struct clk_branch gcc_gfx_1_tbu_clk = {3571 .halt_reg = 0x12098,3572 .halt_check = BRANCH_HALT_VOTED,3573 .clkr = {3574 .enable_reg = 0x4500c,3575 .enable_mask = BIT(19),3576 .hw.init = &(struct clk_init_data){3577 .name = "gcc_gfx_1_tbu_clk",3578 .ops = &clk_branch2_ops,3579 },3580 },3581};3582 3583static struct clk_branch gcc_gfx_tbu_clk = {3584 .halt_reg = 0x12010,3585 .halt_check = BRANCH_HALT_VOTED,3586 .clkr = {3587 .enable_reg = 0x4500c,3588 .enable_mask = BIT(3),3589 .hw.init = &(struct clk_init_data){3590 .name = "gcc_gfx_tbu_clk",3591 .ops = &clk_branch2_ops,3592 },3593 },3594};3595 3596static struct clk_branch gcc_gfx_tcu_clk = {3597 .halt_reg = 0x12020,3598 .halt_check = BRANCH_HALT_VOTED,3599 .clkr = {3600 .enable_reg = 0x4500c,3601 .enable_mask = BIT(2),3602 .hw.init = &(struct clk_init_data){3603 .name = "gcc_gfx_tcu_clk",3604 .ops = &clk_branch2_ops,3605 },3606 },3607};3608 3609static struct clk_branch gcc_apss_tcu_clk = {3610 .halt_reg = 0x12018,3611 .halt_check = BRANCH_HALT_VOTED,3612 .clkr = {3613 .enable_reg = 0x4500c,3614 .enable_mask = BIT(1),3615 .hw.init = &(struct clk_init_data){3616 .name = "gcc_apss_tcu_clk",3617 .ops = &clk_branch2_ops,3618 },3619 },3620};3621 3622static struct clk_branch gcc_gtcu_ahb_clk = {3623 .halt_reg = 0x12044,3624 .halt_check = BRANCH_HALT_VOTED,3625 .clkr = {3626 .enable_reg = 0x4500c,3627 .enable_mask = BIT(13),3628 .hw.init = &(struct clk_init_data){3629 .name = "gcc_gtcu_ahb_clk",3630 .ops = &clk_branch2_ops,3631 },3632 },3633};3634 3635static struct clk_branch gcc_jpeg_tbu_clk = {3636 .halt_reg = 0x12034,3637 .halt_check = BRANCH_HALT_VOTED,3638 .clkr = {3639 .enable_reg = 0x4500c,3640 .enable_mask = BIT(10),3641 .hw.init = &(struct clk_init_data){3642 .name = "gcc_jpeg_tbu_clk",3643 .ops = &clk_branch2_ops,3644 },3645 },3646};3647 3648static struct clk_branch gcc_mdp_rt_tbu_clk = {3649 .halt_reg = 0x1204c,3650 .halt_check = BRANCH_HALT_VOTED,3651 .clkr = {3652 .enable_reg = 0x4500c,3653 .enable_mask = BIT(15),3654 .hw.init = &(struct clk_init_data){3655 .name = "gcc_mdp_rt_tbu_clk",3656 .ops = &clk_branch2_ops,3657 },3658 },3659};3660 3661static struct clk_branch gcc_mdp_tbu_clk = {3662 .halt_reg = 0x1201c,3663 .halt_check = BRANCH_HALT_VOTED,3664 .clkr = {3665 .enable_reg = 0x4500c,3666 .enable_mask = BIT(4),3667 .hw.init = &(struct clk_init_data){3668 .name = "gcc_mdp_tbu_clk",3669 .ops = &clk_branch2_ops,3670 },3671 },3672};3673 3674static struct clk_branch gcc_smmu_cfg_clk = {3675 .halt_reg = 0x12038,3676 .halt_check = BRANCH_HALT_VOTED,3677 .clkr = {3678 .enable_reg = 0x4500c,3679 .enable_mask = BIT(12),3680 .hw.init = &(struct clk_init_data){3681 .name = "gcc_smmu_cfg_clk",3682 .ops = &clk_branch2_ops,3683 },3684 },3685};3686 3687static struct clk_branch gcc_venus_1_tbu_clk = {3688 .halt_reg = 0x1209c,3689 .halt_check = BRANCH_HALT_VOTED,3690 .clkr = {3691 .enable_reg = 0x4500c,3692 .enable_mask = BIT(20),3693 .hw.init = &(struct clk_init_data){3694 .name = "gcc_venus_1_tbu_clk",3695 .ops = &clk_branch2_ops,3696 },3697 },3698};3699 3700static struct clk_branch gcc_venus_tbu_clk = {3701 .halt_reg = 0x12014,3702 .halt_check = BRANCH_HALT_VOTED,3703 .clkr = {3704 .enable_reg = 0x4500c,3705 .enable_mask = BIT(5),3706 .hw.init = &(struct clk_init_data){3707 .name = "gcc_venus_tbu_clk",3708 .ops = &clk_branch2_ops,3709 },3710 },3711};3712 3713static struct clk_branch gcc_vfe1_tbu_clk = {3714 .halt_reg = 0x12090,3715 .halt_check = BRANCH_HALT_VOTED,3716 .clkr = {3717 .enable_reg = 0x4500c,3718 .enable_mask = BIT(17),3719 .hw.init = &(struct clk_init_data){3720 .name = "gcc_vfe1_tbu_clk",3721 .ops = &clk_branch2_ops,3722 },3723 },3724};3725 3726static struct clk_branch gcc_vfe_tbu_clk = {3727 .halt_reg = 0x1203c,3728 .halt_check = BRANCH_HALT_VOTED,3729 .clkr = {3730 .enable_reg = 0x4500c,3731 .enable_mask = BIT(9),3732 .hw.init = &(struct clk_init_data){3733 .name = "gcc_vfe_tbu_clk",3734 .ops = &clk_branch2_ops,3735 },3736 },3737};3738 3739static struct gdsc venus_gdsc = {3740 .gdscr = 0x4c018,3741 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },3742 .cxc_count = 2,3743 .pd = {3744 .name = "venus_gdsc",3745 },3746 .pwrsts = PWRSTS_OFF_ON,3747};3748 3749static struct gdsc venus_core0_gdsc = {3750 .gdscr = 0x4c028,3751 .cxcs = (unsigned int []){ 0x4c02c },3752 .cxc_count = 1,3753 .pd = {3754 .name = "venus_core0_gdsc",3755 },3756 .pwrsts = PWRSTS_OFF_ON,3757};3758 3759static struct gdsc venus_core1_gdsc = {3760 .gdscr = 0x4c030,3761 .pd = {3762 .name = "venus_core1_gdsc",3763 },3764 .pwrsts = PWRSTS_OFF_ON,3765};3766 3767static struct gdsc mdss_gdsc = {3768 .gdscr = 0x4d078,3769 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },3770 .cxc_count = 2,3771 .pd = {3772 .name = "mdss_gdsc",3773 },3774 .pwrsts = PWRSTS_OFF_ON,3775};3776 3777static struct gdsc jpeg_gdsc = {3778 .gdscr = 0x5701c,3779 .cxcs = (unsigned int []){ 0x57020, 0x57028 },3780 .cxc_count = 2,3781 .pd = {3782 .name = "jpeg_gdsc",3783 },3784 .pwrsts = PWRSTS_OFF_ON,3785};3786 3787static struct gdsc vfe0_gdsc = {3788 .gdscr = 0x58034,3789 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },3790 .cxc_count = 4,3791 .pd = {3792 .name = "vfe0_gdsc",3793 },3794 .pwrsts = PWRSTS_OFF_ON,3795};3796 3797static struct gdsc vfe1_gdsc = {3798 .gdscr = 0x5806c,3799 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },3800 .cxc_count = 4,3801 .pd = {3802 .name = "vfe1_gdsc",3803 },3804 .pwrsts = PWRSTS_OFF_ON,3805};3806 3807static struct gdsc cpp_gdsc = {3808 .gdscr = 0x58078,3809 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },3810 .cxc_count = 2,3811 .pd = {3812 .name = "cpp_gdsc",3813 },3814 .pwrsts = PWRSTS_OFF_ON,3815};3816 3817static struct gdsc oxili_cx_gdsc = {3818 .gdscr = 0x5904c,3819 .cxcs = (unsigned int []){ 0x59020 },3820 .cxc_count = 1,3821 .pd = {3822 .name = "oxili_cx_gdsc",3823 },3824 .pwrsts = PWRSTS_OFF_ON,3825 .flags = VOTABLE,3826};3827 3828static struct gdsc oxili_gx_gdsc = {3829 .gdscr = 0x5901c,3830 .clamp_io_ctrl = 0x5b00c,3831 .cxcs = (unsigned int []){ 0x59000, 0x59024 },3832 .cxc_count = 2,3833 .pd = {3834 .name = "oxili_gx_gdsc",3835 },3836 .pwrsts = PWRSTS_OFF_ON,3837 .supply = "vdd_gfx",3838 .flags = CLAMP_IO,3839};3840 3841static struct clk_regmap *gcc_msm8976_clocks[] = {3842 [GPLL0] = &gpll0.clkr,3843 [GPLL2] = &gpll2.clkr,3844 [GPLL3] = &gpll3.clkr,3845 [GPLL4] = &gpll4.clkr,3846 [GPLL6] = &gpll6.clkr,3847 [GPLL0_CLK_SRC] = &gpll0_vote,3848 [GPLL2_CLK_SRC] = &gpll2_vote,3849 [GPLL3_CLK_SRC] = &gpll3_vote,3850 [GPLL4_CLK_SRC] = &gpll4_vote,3851 [GPLL6_CLK_SRC] = &gpll6_vote,3852 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,3853 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,3854 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,3855 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,3856 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,3857 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,3858 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,3859 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,3860 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,3861 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,3862 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,3863 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,3864 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,3865 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,3866 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,3867 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,3868 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,3869 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,3870 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,3871 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,3872 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,3873 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,3874 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,3875 [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,3876 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,3877 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,3878 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,3879 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,3880 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,3881 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,3882 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,3883 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,3884 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,3885 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,3886 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,3887 [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,3888 [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,3889 [GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,3890 [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,3891 [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,3892 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,3893 [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,3894 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,3895 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,3896 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,3897 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,3898 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,3899 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,3900 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,3901 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,3902 [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,3903 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,3904 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,3905 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,3906 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,3907 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,3908 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,3909 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,3910 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,3911 [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,3912 [GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,3913 [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,3914 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,3915 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,3916 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,3917 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,3918 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,3919 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,3920 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,3921 [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,3922 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,3923 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,3924 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,3925 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,3926 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,3927 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,3928 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,3929 [GCC_RBCPR_GFX_AHB_CLK] = &gcc_rbcpr_gfx_ahb_clk.clkr,3930 [GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,3931 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,3932 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,3933 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,3934 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,3935 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,3936 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,3937 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,3938 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,3939 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,3940 [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,3941 [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,3942 [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,3943 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,3944 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,3945 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,3946 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,3947 [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,3948 [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,3949 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,3950 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,3951 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,3952 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,3953 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,3954 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,3955 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,3956 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,3957 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,3958 [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,3959 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,3960 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,3961 [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,3962 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,3963 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,3964 [GCC_VENUS_1_TBU_CLK] = &gcc_venus_1_tbu_clk.clkr,3965 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,3966 [GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,3967 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,3968 [GCC_APS_0_CLK] = &gcc_aps_0_clk.clkr,3969 [GCC_APS_1_CLK] = &gcc_aps_1_clk.clkr,3970 [APS_0_CLK_SRC] = &aps_0_clk_src.clkr,3971 [APS_1_CLK_SRC] = &aps_1_clk_src.clkr,3972 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,3973 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,3974 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,3975 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,3976 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,3977 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,3978 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,3979 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,3980 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,3981 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,3982 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,3983 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,3984 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,3985 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,3986 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,3987 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,3988 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,3989 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,3990 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,3991 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,3992 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,3993 [CCI_CLK_SRC] = &cci_clk_src.clkr,3994 [CPP_CLK_SRC] = &cpp_clk_src.clkr,3995 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,3996 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,3997 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,3998 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,3999 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,4000 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,4001 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,4002 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,4003 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,4004 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,4005 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,4006 [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,4007 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,4008 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,4009 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,4010 [GP1_CLK_SRC] = &gp1_clk_src.clkr,4011 [GP2_CLK_SRC] = &gp2_clk_src.clkr,4012 [GP3_CLK_SRC] = &gp3_clk_src.clkr,4013 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,4014 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,4015 [MDP_CLK_SRC] = &mdp_clk_src.clkr,4016 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,4017 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,4018 [RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,4019 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,4020 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,4021 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,4022 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,4023 [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,4024 [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,4025 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,4026 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,4027 [GCC_MDSS_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,4028 [GCC_MDSS_BYTE1_CLK_SRC] = &byte1_clk_src.clkr,4029 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,4030 [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,4031 [GCC_MDSS_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,4032 [GCC_MDSS_PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,4033 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,4034 [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,4035 [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,4036 [GCC_GFX3D_OXILI_CLK] = &gcc_oxili_gfx3d_clk.clkr,4037 [GCC_GFX3D_BIMC_CLK] = &gcc_bimc_gfx_clk.clkr,4038 [GCC_GFX3D_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,4039 [GCC_GFX3D_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,4040 [GCC_GFX3D_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,4041 [GCC_GFX3D_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,4042 [GCC_GFX3D_TBU0_CLK] = &gcc_gfx_tbu_clk.clkr,4043 [GCC_GFX3D_TBU1_CLK] = &gcc_gfx_1_tbu_clk.clkr,4044 [GCC_GFX3D_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,4045 [GCC_GFX3D_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,4046};4047 4048static const struct qcom_reset_map gcc_msm8976_resets[] = {4049 [RST_CAMSS_MICRO_BCR] = { 0x56008 },4050 [RST_USB_HS_BCR] = { 0x41000 },4051 [RST_QUSB2_PHY_BCR] = { 0x4103c },4052 [RST_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },4053 [RST_USB_HS_PHY_CFG_AHB_BCR] = { 0x41038 },4054 [RST_USB_FS_BCR] = { 0x3f000 },4055 [RST_CAMSS_CSI1PIX_BCR] = { 0x4f054 },4056 [RST_CAMSS_CSI_VFE1_BCR] = { 0x58070 },4057 [RST_CAMSS_VFE1_BCR] = { 0x5807c },4058 [RST_CAMSS_CPP_BCR] = { 0x58080 },4059 [RST_MSS_BCR] = { 0x71000 },4060};4061 4062static struct gdsc *gcc_msm8976_gdscs[] = {4063 [VENUS_GDSC] = &venus_gdsc,4064 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,4065 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,4066 [MDSS_GDSC] = &mdss_gdsc,4067 [JPEG_GDSC] = &jpeg_gdsc,4068 [VFE0_GDSC] = &vfe0_gdsc,4069 [VFE1_GDSC] = &vfe1_gdsc,4070 [CPP_GDSC] = &cpp_gdsc,4071 [OXILI_GX_GDSC] = &oxili_gx_gdsc,4072 [OXILI_CX_GDSC] = &oxili_cx_gdsc,4073};4074 4075static const struct regmap_config gcc_msm8976_regmap_config = {4076 .reg_bits = 32,4077 .reg_stride = 4,4078 .val_bits = 32,4079 .max_register = 0x7fffc,4080 .fast_io = true,4081};4082 4083static const struct qcom_cc_desc gcc_msm8976_desc = {4084 .config = &gcc_msm8976_regmap_config,4085 .clks = gcc_msm8976_clocks,4086 .num_clks = ARRAY_SIZE(gcc_msm8976_clocks),4087 .resets = gcc_msm8976_resets,4088 .num_resets = ARRAY_SIZE(gcc_msm8976_resets),4089 .gdscs = gcc_msm8976_gdscs,4090 .num_gdscs = ARRAY_SIZE(gcc_msm8976_gdscs),4091};4092 4093static const struct of_device_id gcc_msm8976_match_table[] = {4094 { .compatible = "qcom,gcc-msm8976" }, /* Also valid for 8x56 */4095 { .compatible = "qcom,gcc-msm8976-v1.1" },4096 { }4097};4098MODULE_DEVICE_TABLE(of, gcc_msm8976_match_table);4099 4100static int gcc_msm8976_probe(struct platform_device *pdev)4101{4102 struct regmap *regmap;4103 int ret;4104 4105 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8976-v1.1")) {4106 sdcc1_apps_clk_src.parent_map = gcc_parent_map_v1_1;4107 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_8976_v1_1_apps_clk_src;4108 sdcc1_apps_clk_src.clkr.hw.init = &sdcc1_apps_clk_src_8976v1_1_init;4109 }4110 4111 regmap = qcom_cc_map(pdev, &gcc_msm8976_desc);4112 if (IS_ERR(regmap))4113 return PTR_ERR(regmap);4114 4115 /* Set Sleep and Wakeup cycles to 0 for GMEM clock */4116 ret = regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0xff0, 0);4117 if (ret)4118 return ret;4119 4120 clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);4121 4122 /* Enable AUX2 clock for APSS */4123 ret = regmap_update_bits(regmap, 0x60000, BIT(2), BIT(2));4124 if (ret)4125 return ret;4126 4127 /* Set Sleep cycles to 0 for OXILI clock */4128 ret = regmap_update_bits(regmap, gcc_oxili_gfx3d_clk.clkr.enable_reg, 0xf0, 0);4129 if (ret)4130 return ret;4131 4132 return qcom_cc_really_probe(&pdev->dev, &gcc_msm8976_desc, regmap);4133}4134 4135static struct platform_driver gcc_msm8976_driver = {4136 .probe = gcc_msm8976_probe,4137 .driver = {4138 .name = "qcom,gcc-msm8976",4139 .of_match_table = gcc_msm8976_match_table,4140 },4141};4142 4143static int __init gcc_msm8976_init(void)4144{4145 return platform_driver_register(&gcc_msm8976_driver);4146}4147core_initcall(gcc_msm8976_init);4148 4149static void __exit gcc_msm8976_exit(void)4150{4151 platform_driver_unregister(&gcc_msm8976_driver);4152}4153module_exit(gcc_msm8976_exit);4154 4155MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>");4156MODULE_LICENSE("GPL v2");4157MODULE_DESCRIPTION("QTI MSM8996 Global Clock Controller");4158