3649 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.4 */5 6#include <linux/kernel.h>7#include <linux/bitops.h>8#include <linux/err.h>9#include <linux/platform_device.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/clk-provider.h>13#include <linux/regmap.h>14#include <linux/reset-controller.h>15 16#include <dt-bindings/clock/qcom,gcc-msm8996.h>17 18#include "common.h"19#include "clk-regmap.h"20#include "clk-alpha-pll.h"21#include "clk-rcg.h"22#include "clk-branch.h"23#include "reset.h"24#include "gdsc.h"25 26enum {27 P_XO,28 P_GPLL0,29 P_GPLL0_EARLY_DIV,30 P_SLEEP_CLK,31 P_GPLL4,32 P_AUD_REF_CLK,33};34 35static struct clk_fixed_factor xo = {36 .mult = 1,37 .div = 1,38 .hw.init = &(struct clk_init_data){39 .name = "xo",40 .parent_data = &(const struct clk_parent_data){41 .fw_name = "cxo", .name = "xo_board",42 },43 .num_parents = 1,44 .ops = &clk_fixed_factor_ops,45 },46};47 48static struct clk_alpha_pll gpll0_early = {49 .offset = 0x00000,50 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],51 .clkr = {52 .enable_reg = 0x52000,53 .enable_mask = BIT(0),54 .hw.init = &(struct clk_init_data){55 .name = "gpll0_early",56 .parent_data = &(const struct clk_parent_data){57 .fw_name = "cxo", .name = "xo_board",58 },59 .num_parents = 1,60 .ops = &clk_alpha_pll_ops,61 },62 },63};64 65static struct clk_fixed_factor gpll0_early_div = {66 .mult = 1,67 .div = 2,68 .hw.init = &(struct clk_init_data){69 .name = "gpll0_early_div",70 .parent_hws = (const struct clk_hw*[]){71 &gpll0_early.clkr.hw,72 },73 .num_parents = 1,74 .ops = &clk_fixed_factor_ops,75 },76};77 78static struct clk_alpha_pll_postdiv gpll0 = {79 .offset = 0x00000,80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],81 .clkr.hw.init = &(struct clk_init_data){82 .name = "gpll0",83 .parent_hws = (const struct clk_hw*[]){84 &gpll0_early.clkr.hw,85 },86 .num_parents = 1,87 .ops = &clk_alpha_pll_postdiv_ops,88 },89};90 91static struct clk_branch gcc_mmss_gpll0_div_clk = {92 .halt_check = BRANCH_HALT_DELAY,93 .clkr = {94 .enable_reg = 0x5200c,95 .enable_mask = BIT(0),96 .hw.init = &(struct clk_init_data){97 .name = "gcc_mmss_gpll0_div_clk",98 .parent_hws = (const struct clk_hw*[]){99 &gpll0.clkr.hw,100 },101 .num_parents = 1,102 .flags = CLK_SET_RATE_PARENT,103 .ops = &clk_branch2_ops,104 },105 },106};107 108static struct clk_branch gcc_mss_gpll0_div_clk = {109 .halt_check = BRANCH_HALT_DELAY,110 .clkr = {111 .enable_reg = 0x5200c,112 .enable_mask = BIT(2),113 .hw.init = &(struct clk_init_data){114 .name = "gcc_mss_gpll0_div_clk",115 .parent_hws = (const struct clk_hw*[]){116 &gpll0.clkr.hw,117 },118 .num_parents = 1,119 .flags = CLK_SET_RATE_PARENT,120 .ops = &clk_branch2_ops121 },122 },123};124 125static struct clk_alpha_pll gpll4_early = {126 .offset = 0x77000,127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],128 .clkr = {129 .enable_reg = 0x52000,130 .enable_mask = BIT(4),131 .hw.init = &(struct clk_init_data){132 .name = "gpll4_early",133 .parent_data = &(const struct clk_parent_data){134 .fw_name = "cxo", .name = "xo_board",135 },136 .num_parents = 1,137 .ops = &clk_alpha_pll_ops,138 },139 },140};141 142static struct clk_alpha_pll_postdiv gpll4 = {143 .offset = 0x77000,144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],145 .clkr.hw.init = &(struct clk_init_data){146 .name = "gpll4",147 .parent_hws = (const struct clk_hw*[]){148 &gpll4_early.clkr.hw,149 },150 .num_parents = 1,151 .ops = &clk_alpha_pll_postdiv_ops,152 },153};154 155static const struct parent_map gcc_sleep_clk_map[] = {156 { P_SLEEP_CLK, 5 }157};158 159static const struct clk_parent_data gcc_sleep_clk[] = {160 { .fw_name = "sleep_clk", .name = "sleep_clk" }161};162 163static const struct parent_map gcc_xo_gpll0_map[] = {164 { P_XO, 0 },165 { P_GPLL0, 1 }166};167 168static const struct clk_parent_data gcc_xo_gpll0[] = {169 { .fw_name = "cxo", .name = "xo_board" },170 { .hw = &gpll0.clkr.hw }171};172 173static const struct parent_map gcc_xo_sleep_clk_map[] = {174 { P_XO, 0 },175 { P_SLEEP_CLK, 5 }176};177 178static const struct clk_parent_data gcc_xo_sleep_clk[] = {179 { .fw_name = "cxo", .name = "xo_board" },180 { .fw_name = "sleep_clk", .name = "sleep_clk" }181};182 183static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {184 { P_XO, 0 },185 { P_GPLL0, 1 },186 { P_GPLL0_EARLY_DIV, 6 }187};188 189static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {190 { .fw_name = "cxo", .name = "xo_board" },191 { .hw = &gpll0.clkr.hw },192 { .hw = &gpll0_early_div.hw }193};194 195static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {196 { P_XO, 0 },197 { P_GPLL0, 1 },198 { P_GPLL4, 5 }199};200 201static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {202 { .fw_name = "cxo", .name = "xo_board" },203 { .hw = &gpll0.clkr.hw },204 { .hw = &gpll4.clkr.hw }205};206 207static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {208 { P_XO, 0 },209 { P_GPLL0, 1 },210 { P_AUD_REF_CLK, 2 }211};212 213static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {214 { .fw_name = "cxo", .name = "xo_board" },215 { .hw = &gpll0.clkr.hw },216 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }217};218 219static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {220 { P_XO, 0 },221 { P_GPLL0, 1 },222 { P_SLEEP_CLK, 5 },223 { P_GPLL0_EARLY_DIV, 6 }224};225 226static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {227 { .fw_name = "cxo", .name = "xo_board" },228 { .hw = &gpll0.clkr.hw },229 { .fw_name = "sleep_clk", .name = "sleep_clk" },230 { .hw = &gpll0_early_div.hw }231};232 233static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {234 { P_XO, 0 },235 { P_GPLL0, 1 },236 { P_GPLL4, 5 },237 { P_GPLL0_EARLY_DIV, 6 }238};239 240static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {241 { .fw_name = "cxo", .name = "xo_board" },242 { .hw = &gpll0.clkr.hw },243 { .hw = &gpll4.clkr.hw },244 { .hw = &gpll0_early_div.hw }245};246 247static const struct freq_tbl ftbl_usb30_master_clk_src[] = {248 F(19200000, P_XO, 1, 0, 0),249 F(120000000, P_GPLL0, 5, 0, 0),250 F(150000000, P_GPLL0, 4, 0, 0),251 { }252};253 254static struct clk_rcg2 usb30_master_clk_src = {255 .cmd_rcgr = 0x0f014,256 .mnd_width = 8,257 .hid_width = 5,258 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,259 .freq_tbl = ftbl_usb30_master_clk_src,260 .clkr.hw.init = &(struct clk_init_data){261 .name = "usb30_master_clk_src",262 .parent_data = gcc_xo_gpll0_gpll0_early_div,263 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),264 .ops = &clk_rcg2_ops,265 },266};267 268static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {269 F(19200000, P_XO, 1, 0, 0),270 { }271};272 273static struct clk_rcg2 usb30_mock_utmi_clk_src = {274 .cmd_rcgr = 0x0f028,275 .hid_width = 5,276 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,277 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,278 .clkr.hw.init = &(struct clk_init_data){279 .name = "usb30_mock_utmi_clk_src",280 .parent_data = gcc_xo_gpll0_gpll0_early_div,281 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),282 .ops = &clk_rcg2_ops,283 },284};285 286static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {287 F(1200000, P_XO, 16, 0, 0),288 { }289};290 291static struct clk_rcg2 usb3_phy_aux_clk_src = {292 .cmd_rcgr = 0x5000c,293 .hid_width = 5,294 .parent_map = gcc_xo_sleep_clk_map,295 .freq_tbl = ftbl_usb3_phy_aux_clk_src,296 .clkr.hw.init = &(struct clk_init_data){297 .name = "usb3_phy_aux_clk_src",298 .parent_data = gcc_xo_sleep_clk,299 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),300 .ops = &clk_rcg2_ops,301 },302};303 304static const struct freq_tbl ftbl_usb20_master_clk_src[] = {305 F(120000000, P_GPLL0, 5, 0, 0),306 { }307};308 309static struct clk_rcg2 usb20_master_clk_src = {310 .cmd_rcgr = 0x12010,311 .mnd_width = 8,312 .hid_width = 5,313 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,314 .freq_tbl = ftbl_usb20_master_clk_src,315 .clkr.hw.init = &(struct clk_init_data){316 .name = "usb20_master_clk_src",317 .parent_data = gcc_xo_gpll0_gpll0_early_div,318 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),319 .ops = &clk_rcg2_ops,320 },321};322 323static struct clk_rcg2 usb20_mock_utmi_clk_src = {324 .cmd_rcgr = 0x12024,325 .hid_width = 5,326 .parent_map = gcc_xo_gpll0_gpll0_early_div_map,327 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,328 .clkr.hw.init = &(struct clk_init_data){329 .name = "usb20_mock_utmi_clk_src",330 .parent_data = gcc_xo_gpll0_gpll0_early_div,331 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),332 .ops = &clk_rcg2_ops,333 },334};335 336static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {337 F(144000, P_XO, 16, 3, 25),338 F(400000, P_XO, 12, 1, 4),339 F(20000000, P_GPLL0, 15, 1, 2),340 F(25000000, P_GPLL0, 12, 1, 2),341 F(50000000, P_GPLL0, 12, 0, 0),342 F(96000000, P_GPLL4, 4, 0, 0),343 F(192000000, P_GPLL4, 2, 0, 0),344 F(384000000, P_GPLL4, 1, 0, 0),345 { }346};347 348static struct clk_rcg2 sdcc1_apps_clk_src = {349 .cmd_rcgr = 0x13010,350 .mnd_width = 8,351 .hid_width = 5,352 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,353 .freq_tbl = ftbl_sdcc1_apps_clk_src,354 .clkr.hw.init = &(struct clk_init_data){355 .name = "sdcc1_apps_clk_src",356 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,357 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),358 .ops = &clk_rcg2_floor_ops,359 },360};361 362static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {363 F(19200000, P_XO, 1, 0, 0),364 F(150000000, P_GPLL0, 4, 0, 0),365 F(300000000, P_GPLL0, 2, 0, 0),366 { }367};368 369static struct clk_rcg2 sdcc1_ice_core_clk_src = {370 .cmd_rcgr = 0x13024,371 .hid_width = 5,372 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,373 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,374 .clkr.hw.init = &(struct clk_init_data){375 .name = "sdcc1_ice_core_clk_src",376 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,377 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),378 .ops = &clk_rcg2_ops,379 },380};381 382static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {383 F(144000, P_XO, 16, 3, 25),384 F(400000, P_XO, 12, 1, 4),385 F(20000000, P_GPLL0, 15, 1, 2),386 F(25000000, P_GPLL0, 12, 1, 2),387 F(50000000, P_GPLL0, 12, 0, 0),388 F(100000000, P_GPLL0, 6, 0, 0),389 F(200000000, P_GPLL0, 3, 0, 0),390 { }391};392 393static struct clk_rcg2 sdcc2_apps_clk_src = {394 .cmd_rcgr = 0x14010,395 .mnd_width = 8,396 .hid_width = 5,397 .parent_map = gcc_xo_gpll0_gpll4_map,398 .freq_tbl = ftbl_sdcc2_apps_clk_src,399 .clkr.hw.init = &(struct clk_init_data){400 .name = "sdcc2_apps_clk_src",401 .parent_data = gcc_xo_gpll0_gpll4,402 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),403 .ops = &clk_rcg2_floor_ops,404 },405};406 407static struct clk_rcg2 sdcc3_apps_clk_src = {408 .cmd_rcgr = 0x15010,409 .mnd_width = 8,410 .hid_width = 5,411 .parent_map = gcc_xo_gpll0_gpll4_map,412 .freq_tbl = ftbl_sdcc2_apps_clk_src,413 .clkr.hw.init = &(struct clk_init_data){414 .name = "sdcc3_apps_clk_src",415 .parent_data = gcc_xo_gpll0_gpll4,416 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),417 .ops = &clk_rcg2_floor_ops,418 },419};420 421static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {422 F(144000, P_XO, 16, 3, 25),423 F(400000, P_XO, 12, 1, 4),424 F(20000000, P_GPLL0, 15, 1, 2),425 F(25000000, P_GPLL0, 12, 1, 2),426 F(50000000, P_GPLL0, 12, 0, 0),427 F(100000000, P_GPLL0, 6, 0, 0),428 { }429};430 431static struct clk_rcg2 sdcc4_apps_clk_src = {432 .cmd_rcgr = 0x16010,433 .mnd_width = 8,434 .hid_width = 5,435 .parent_map = gcc_xo_gpll0_map,436 .freq_tbl = ftbl_sdcc4_apps_clk_src,437 .clkr.hw.init = &(struct clk_init_data){438 .name = "sdcc4_apps_clk_src",439 .parent_data = gcc_xo_gpll0,440 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),441 .ops = &clk_rcg2_floor_ops,442 },443};444 445static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {446 F(960000, P_XO, 10, 1, 2),447 F(4800000, P_XO, 4, 0, 0),448 F(9600000, P_XO, 2, 0, 0),449 F(15000000, P_GPLL0, 10, 1, 4),450 F(19200000, P_XO, 1, 0, 0),451 F(25000000, P_GPLL0, 12, 1, 2),452 F(50000000, P_GPLL0, 12, 0, 0),453 { }454};455 456static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {457 .cmd_rcgr = 0x1900c,458 .mnd_width = 8,459 .hid_width = 5,460 .parent_map = gcc_xo_gpll0_map,461 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,462 .clkr.hw.init = &(struct clk_init_data){463 .name = "blsp1_qup1_spi_apps_clk_src",464 .parent_data = gcc_xo_gpll0,465 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),466 .ops = &clk_rcg2_ops,467 },468};469 470static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {471 F(19200000, P_XO, 1, 0, 0),472 F(50000000, P_GPLL0, 12, 0, 0),473 { }474};475 476static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {477 .cmd_rcgr = 0x19020,478 .hid_width = 5,479 .parent_map = gcc_xo_gpll0_map,480 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,481 .clkr.hw.init = &(struct clk_init_data){482 .name = "blsp1_qup1_i2c_apps_clk_src",483 .parent_data = gcc_xo_gpll0,484 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),485 .ops = &clk_rcg2_ops,486 },487};488 489static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {490 F(3686400, P_GPLL0, 1, 96, 15625),491 F(7372800, P_GPLL0, 1, 192, 15625),492 F(14745600, P_GPLL0, 1, 384, 15625),493 F(16000000, P_GPLL0, 5, 2, 15),494 F(19200000, P_XO, 1, 0, 0),495 F(24000000, P_GPLL0, 5, 1, 5),496 F(32000000, P_GPLL0, 1, 4, 75),497 F(40000000, P_GPLL0, 15, 0, 0),498 F(46400000, P_GPLL0, 1, 29, 375),499 F(48000000, P_GPLL0, 12.5, 0, 0),500 F(51200000, P_GPLL0, 1, 32, 375),501 F(56000000, P_GPLL0, 1, 7, 75),502 F(58982400, P_GPLL0, 1, 1536, 15625),503 F(60000000, P_GPLL0, 10, 0, 0),504 F(63157895, P_GPLL0, 9.5, 0, 0),505 { }506};507 508static struct clk_rcg2 blsp1_uart1_apps_clk_src = {509 .cmd_rcgr = 0x1a00c,510 .mnd_width = 16,511 .hid_width = 5,512 .parent_map = gcc_xo_gpll0_map,513 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,514 .clkr.hw.init = &(struct clk_init_data){515 .name = "blsp1_uart1_apps_clk_src",516 .parent_data = gcc_xo_gpll0,517 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),518 .ops = &clk_rcg2_ops,519 },520};521 522static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {523 .cmd_rcgr = 0x1b00c,524 .mnd_width = 8,525 .hid_width = 5,526 .parent_map = gcc_xo_gpll0_map,527 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,528 .clkr.hw.init = &(struct clk_init_data){529 .name = "blsp1_qup2_spi_apps_clk_src",530 .parent_data = gcc_xo_gpll0,531 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),532 .ops = &clk_rcg2_ops,533 },534};535 536static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {537 .cmd_rcgr = 0x1b020,538 .hid_width = 5,539 .parent_map = gcc_xo_gpll0_map,540 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,541 .clkr.hw.init = &(struct clk_init_data){542 .name = "blsp1_qup2_i2c_apps_clk_src",543 .parent_data = gcc_xo_gpll0,544 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),545 .ops = &clk_rcg2_ops,546 },547};548 549static struct clk_rcg2 blsp1_uart2_apps_clk_src = {550 .cmd_rcgr = 0x1c00c,551 .mnd_width = 16,552 .hid_width = 5,553 .parent_map = gcc_xo_gpll0_map,554 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,555 .clkr.hw.init = &(struct clk_init_data){556 .name = "blsp1_uart2_apps_clk_src",557 .parent_data = gcc_xo_gpll0,558 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),559 .ops = &clk_rcg2_ops,560 },561};562 563static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {564 .cmd_rcgr = 0x1d00c,565 .mnd_width = 8,566 .hid_width = 5,567 .parent_map = gcc_xo_gpll0_map,568 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,569 .clkr.hw.init = &(struct clk_init_data){570 .name = "blsp1_qup3_spi_apps_clk_src",571 .parent_data = gcc_xo_gpll0,572 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),573 .ops = &clk_rcg2_ops,574 },575};576 577static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {578 .cmd_rcgr = 0x1d020,579 .hid_width = 5,580 .parent_map = gcc_xo_gpll0_map,581 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,582 .clkr.hw.init = &(struct clk_init_data){583 .name = "blsp1_qup3_i2c_apps_clk_src",584 .parent_data = gcc_xo_gpll0,585 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),586 .ops = &clk_rcg2_ops,587 },588};589 590static struct clk_rcg2 blsp1_uart3_apps_clk_src = {591 .cmd_rcgr = 0x1e00c,592 .mnd_width = 16,593 .hid_width = 5,594 .parent_map = gcc_xo_gpll0_map,595 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,596 .clkr.hw.init = &(struct clk_init_data){597 .name = "blsp1_uart3_apps_clk_src",598 .parent_data = gcc_xo_gpll0,599 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),600 .ops = &clk_rcg2_ops,601 },602};603 604static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {605 .cmd_rcgr = 0x1f00c,606 .mnd_width = 8,607 .hid_width = 5,608 .parent_map = gcc_xo_gpll0_map,609 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,610 .clkr.hw.init = &(struct clk_init_data){611 .name = "blsp1_qup4_spi_apps_clk_src",612 .parent_data = gcc_xo_gpll0,613 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),614 .ops = &clk_rcg2_ops,615 },616};617 618static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {619 .cmd_rcgr = 0x1f020,620 .hid_width = 5,621 .parent_map = gcc_xo_gpll0_map,622 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,623 .clkr.hw.init = &(struct clk_init_data){624 .name = "blsp1_qup4_i2c_apps_clk_src",625 .parent_data = gcc_xo_gpll0,626 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),627 .ops = &clk_rcg2_ops,628 },629};630 631static struct clk_rcg2 blsp1_uart4_apps_clk_src = {632 .cmd_rcgr = 0x2000c,633 .mnd_width = 16,634 .hid_width = 5,635 .parent_map = gcc_xo_gpll0_map,636 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,637 .clkr.hw.init = &(struct clk_init_data){638 .name = "blsp1_uart4_apps_clk_src",639 .parent_data = gcc_xo_gpll0,640 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),641 .ops = &clk_rcg2_ops,642 },643};644 645static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {646 .cmd_rcgr = 0x2100c,647 .mnd_width = 8,648 .hid_width = 5,649 .parent_map = gcc_xo_gpll0_map,650 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,651 .clkr.hw.init = &(struct clk_init_data){652 .name = "blsp1_qup5_spi_apps_clk_src",653 .parent_data = gcc_xo_gpll0,654 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),655 .ops = &clk_rcg2_ops,656 },657};658 659static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {660 .cmd_rcgr = 0x21020,661 .hid_width = 5,662 .parent_map = gcc_xo_gpll0_map,663 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,664 .clkr.hw.init = &(struct clk_init_data){665 .name = "blsp1_qup5_i2c_apps_clk_src",666 .parent_data = gcc_xo_gpll0,667 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),668 .ops = &clk_rcg2_ops,669 },670};671 672static struct clk_rcg2 blsp1_uart5_apps_clk_src = {673 .cmd_rcgr = 0x2200c,674 .mnd_width = 16,675 .hid_width = 5,676 .parent_map = gcc_xo_gpll0_map,677 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,678 .clkr.hw.init = &(struct clk_init_data){679 .name = "blsp1_uart5_apps_clk_src",680 .parent_data = gcc_xo_gpll0,681 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),682 .ops = &clk_rcg2_ops,683 },684};685 686static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {687 .cmd_rcgr = 0x2300c,688 .mnd_width = 8,689 .hid_width = 5,690 .parent_map = gcc_xo_gpll0_map,691 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,692 .clkr.hw.init = &(struct clk_init_data){693 .name = "blsp1_qup6_spi_apps_clk_src",694 .parent_data = gcc_xo_gpll0,695 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),696 .ops = &clk_rcg2_ops,697 },698};699 700static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {701 .cmd_rcgr = 0x23020,702 .hid_width = 5,703 .parent_map = gcc_xo_gpll0_map,704 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,705 .clkr.hw.init = &(struct clk_init_data){706 .name = "blsp1_qup6_i2c_apps_clk_src",707 .parent_data = gcc_xo_gpll0,708 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),709 .ops = &clk_rcg2_ops,710 },711};712 713static struct clk_rcg2 blsp1_uart6_apps_clk_src = {714 .cmd_rcgr = 0x2400c,715 .mnd_width = 16,716 .hid_width = 5,717 .parent_map = gcc_xo_gpll0_map,718 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,719 .clkr.hw.init = &(struct clk_init_data){720 .name = "blsp1_uart6_apps_clk_src",721 .parent_data = gcc_xo_gpll0,722 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),723 .ops = &clk_rcg2_ops,724 },725};726 727static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {728 .cmd_rcgr = 0x2600c,729 .mnd_width = 8,730 .hid_width = 5,731 .parent_map = gcc_xo_gpll0_map,732 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,733 .clkr.hw.init = &(struct clk_init_data){734 .name = "blsp2_qup1_spi_apps_clk_src",735 .parent_data = gcc_xo_gpll0,736 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),737 .ops = &clk_rcg2_ops,738 },739};740 741static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {742 .cmd_rcgr = 0x26020,743 .hid_width = 5,744 .parent_map = gcc_xo_gpll0_map,745 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,746 .clkr.hw.init = &(struct clk_init_data){747 .name = "blsp2_qup1_i2c_apps_clk_src",748 .parent_data = gcc_xo_gpll0,749 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),750 .ops = &clk_rcg2_ops,751 },752};753 754static struct clk_rcg2 blsp2_uart1_apps_clk_src = {755 .cmd_rcgr = 0x2700c,756 .mnd_width = 16,757 .hid_width = 5,758 .parent_map = gcc_xo_gpll0_map,759 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,760 .clkr.hw.init = &(struct clk_init_data){761 .name = "blsp2_uart1_apps_clk_src",762 .parent_data = gcc_xo_gpll0,763 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),764 .ops = &clk_rcg2_ops,765 },766};767 768static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {769 .cmd_rcgr = 0x2800c,770 .mnd_width = 8,771 .hid_width = 5,772 .parent_map = gcc_xo_gpll0_map,773 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,774 .clkr.hw.init = &(struct clk_init_data){775 .name = "blsp2_qup2_spi_apps_clk_src",776 .parent_data = gcc_xo_gpll0,777 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),778 .ops = &clk_rcg2_ops,779 },780};781 782static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {783 .cmd_rcgr = 0x28020,784 .hid_width = 5,785 .parent_map = gcc_xo_gpll0_map,786 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,787 .clkr.hw.init = &(struct clk_init_data){788 .name = "blsp2_qup2_i2c_apps_clk_src",789 .parent_data = gcc_xo_gpll0,790 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),791 .ops = &clk_rcg2_ops,792 },793};794 795static struct clk_rcg2 blsp2_uart2_apps_clk_src = {796 .cmd_rcgr = 0x2900c,797 .mnd_width = 16,798 .hid_width = 5,799 .parent_map = gcc_xo_gpll0_map,800 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,801 .clkr.hw.init = &(struct clk_init_data){802 .name = "blsp2_uart2_apps_clk_src",803 .parent_data = gcc_xo_gpll0,804 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),805 .ops = &clk_rcg2_ops,806 },807};808 809static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {810 .cmd_rcgr = 0x2a00c,811 .mnd_width = 8,812 .hid_width = 5,813 .parent_map = gcc_xo_gpll0_map,814 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,815 .clkr.hw.init = &(struct clk_init_data){816 .name = "blsp2_qup3_spi_apps_clk_src",817 .parent_data = gcc_xo_gpll0,818 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),819 .ops = &clk_rcg2_ops,820 },821};822 823static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {824 .cmd_rcgr = 0x2a020,825 .hid_width = 5,826 .parent_map = gcc_xo_gpll0_map,827 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,828 .clkr.hw.init = &(struct clk_init_data){829 .name = "blsp2_qup3_i2c_apps_clk_src",830 .parent_data = gcc_xo_gpll0,831 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),832 .ops = &clk_rcg2_ops,833 },834};835 836static struct clk_rcg2 blsp2_uart3_apps_clk_src = {837 .cmd_rcgr = 0x2b00c,838 .mnd_width = 16,839 .hid_width = 5,840 .parent_map = gcc_xo_gpll0_map,841 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,842 .clkr.hw.init = &(struct clk_init_data){843 .name = "blsp2_uart3_apps_clk_src",844 .parent_data = gcc_xo_gpll0,845 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),846 .ops = &clk_rcg2_ops,847 },848};849 850static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {851 .cmd_rcgr = 0x2c00c,852 .mnd_width = 8,853 .hid_width = 5,854 .parent_map = gcc_xo_gpll0_map,855 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,856 .clkr.hw.init = &(struct clk_init_data){857 .name = "blsp2_qup4_spi_apps_clk_src",858 .parent_data = gcc_xo_gpll0,859 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),860 .ops = &clk_rcg2_ops,861 },862};863 864static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {865 .cmd_rcgr = 0x2c020,866 .hid_width = 5,867 .parent_map = gcc_xo_gpll0_map,868 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,869 .clkr.hw.init = &(struct clk_init_data){870 .name = "blsp2_qup4_i2c_apps_clk_src",871 .parent_data = gcc_xo_gpll0,872 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),873 .ops = &clk_rcg2_ops,874 },875};876 877static struct clk_rcg2 blsp2_uart4_apps_clk_src = {878 .cmd_rcgr = 0x2d00c,879 .mnd_width = 16,880 .hid_width = 5,881 .parent_map = gcc_xo_gpll0_map,882 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,883 .clkr.hw.init = &(struct clk_init_data){884 .name = "blsp2_uart4_apps_clk_src",885 .parent_data = gcc_xo_gpll0,886 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),887 .ops = &clk_rcg2_ops,888 },889};890 891static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {892 .cmd_rcgr = 0x2e00c,893 .mnd_width = 8,894 .hid_width = 5,895 .parent_map = gcc_xo_gpll0_map,896 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,897 .clkr.hw.init = &(struct clk_init_data){898 .name = "blsp2_qup5_spi_apps_clk_src",899 .parent_data = gcc_xo_gpll0,900 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),901 .ops = &clk_rcg2_ops,902 },903};904 905static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {906 .cmd_rcgr = 0x2e020,907 .hid_width = 5,908 .parent_map = gcc_xo_gpll0_map,909 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,910 .clkr.hw.init = &(struct clk_init_data){911 .name = "blsp2_qup5_i2c_apps_clk_src",912 .parent_data = gcc_xo_gpll0,913 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),914 .ops = &clk_rcg2_ops,915 },916};917 918static struct clk_rcg2 blsp2_uart5_apps_clk_src = {919 .cmd_rcgr = 0x2f00c,920 .mnd_width = 16,921 .hid_width = 5,922 .parent_map = gcc_xo_gpll0_map,923 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,924 .clkr.hw.init = &(struct clk_init_data){925 .name = "blsp2_uart5_apps_clk_src",926 .parent_data = gcc_xo_gpll0,927 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),928 .ops = &clk_rcg2_ops,929 },930};931 932static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {933 .cmd_rcgr = 0x3000c,934 .mnd_width = 8,935 .hid_width = 5,936 .parent_map = gcc_xo_gpll0_map,937 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,938 .clkr.hw.init = &(struct clk_init_data){939 .name = "blsp2_qup6_spi_apps_clk_src",940 .parent_data = gcc_xo_gpll0,941 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),942 .ops = &clk_rcg2_ops,943 },944};945 946static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {947 .cmd_rcgr = 0x30020,948 .hid_width = 5,949 .parent_map = gcc_xo_gpll0_map,950 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,951 .clkr.hw.init = &(struct clk_init_data){952 .name = "blsp2_qup6_i2c_apps_clk_src",953 .parent_data = gcc_xo_gpll0,954 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),955 .ops = &clk_rcg2_ops,956 },957};958 959static struct clk_rcg2 blsp2_uart6_apps_clk_src = {960 .cmd_rcgr = 0x3100c,961 .mnd_width = 16,962 .hid_width = 5,963 .parent_map = gcc_xo_gpll0_map,964 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,965 .clkr.hw.init = &(struct clk_init_data){966 .name = "blsp2_uart6_apps_clk_src",967 .parent_data = gcc_xo_gpll0,968 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),969 .ops = &clk_rcg2_ops,970 },971};972 973static const struct freq_tbl ftbl_pdm2_clk_src[] = {974 F(60000000, P_GPLL0, 10, 0, 0),975 { }976};977 978static struct clk_rcg2 pdm2_clk_src = {979 .cmd_rcgr = 0x33010,980 .hid_width = 5,981 .parent_map = gcc_xo_gpll0_map,982 .freq_tbl = ftbl_pdm2_clk_src,983 .clkr.hw.init = &(struct clk_init_data){984 .name = "pdm2_clk_src",985 .parent_data = gcc_xo_gpll0,986 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),987 .ops = &clk_rcg2_ops,988 },989};990 991static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {992 F(105495, P_XO, 1, 1, 182),993 { }994};995 996static struct clk_rcg2 tsif_ref_clk_src = {997 .cmd_rcgr = 0x36010,998 .mnd_width = 8,999 .hid_width = 5,1000 .parent_map = gcc_xo_gpll0_aud_ref_clk_map,1001 .freq_tbl = ftbl_tsif_ref_clk_src,1002 .clkr.hw.init = &(struct clk_init_data){1003 .name = "tsif_ref_clk_src",1004 .parent_data = gcc_xo_gpll0_aud_ref_clk,1005 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),1006 .ops = &clk_rcg2_ops,1007 },1008};1009 1010static struct clk_rcg2 gcc_sleep_clk_src = {1011 .cmd_rcgr = 0x43014,1012 .hid_width = 5,1013 .parent_map = gcc_sleep_clk_map,1014 .clkr.hw.init = &(struct clk_init_data){1015 .name = "gcc_sleep_clk_src",1016 .parent_data = gcc_sleep_clk,1017 .num_parents = ARRAY_SIZE(gcc_sleep_clk),1018 .ops = &clk_rcg2_ops,1019 },1020};1021 1022static struct clk_rcg2 hmss_rbcpr_clk_src = {1023 .cmd_rcgr = 0x48040,1024 .hid_width = 5,1025 .parent_map = gcc_xo_gpll0_map,1026 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,1027 .clkr.hw.init = &(struct clk_init_data){1028 .name = "hmss_rbcpr_clk_src",1029 .parent_data = gcc_xo_gpll0,1030 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),1031 .ops = &clk_rcg2_ops,1032 },1033};1034 1035static struct clk_rcg2 hmss_gpll0_clk_src = {1036 .cmd_rcgr = 0x48058,1037 .hid_width = 5,1038 .parent_map = gcc_xo_gpll0_map,1039 .clkr.hw.init = &(struct clk_init_data){1040 .name = "hmss_gpll0_clk_src",1041 .parent_data = gcc_xo_gpll0,1042 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),1043 .ops = &clk_rcg2_ops,1044 },1045};1046 1047static const struct freq_tbl ftbl_gp1_clk_src[] = {1048 F(19200000, P_XO, 1, 0, 0),1049 F(100000000, P_GPLL0, 6, 0, 0),1050 F(200000000, P_GPLL0, 3, 0, 0),1051 { }1052};1053 1054static struct clk_rcg2 gp1_clk_src = {1055 .cmd_rcgr = 0x64004,1056 .mnd_width = 8,1057 .hid_width = 5,1058 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,1059 .freq_tbl = ftbl_gp1_clk_src,1060 .clkr.hw.init = &(struct clk_init_data){1061 .name = "gp1_clk_src",1062 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,1063 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),1064 .ops = &clk_rcg2_ops,1065 },1066};1067 1068static struct clk_rcg2 gp2_clk_src = {1069 .cmd_rcgr = 0x65004,1070 .mnd_width = 8,1071 .hid_width = 5,1072 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,1073 .freq_tbl = ftbl_gp1_clk_src,1074 .clkr.hw.init = &(struct clk_init_data){1075 .name = "gp2_clk_src",1076 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,1077 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),1078 .ops = &clk_rcg2_ops,1079 },1080};1081 1082static struct clk_rcg2 gp3_clk_src = {1083 .cmd_rcgr = 0x66004,1084 .mnd_width = 8,1085 .hid_width = 5,1086 .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,1087 .freq_tbl = ftbl_gp1_clk_src,1088 .clkr.hw.init = &(struct clk_init_data){1089 .name = "gp3_clk_src",1090 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,1091 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),1092 .ops = &clk_rcg2_ops,1093 },1094};1095 1096static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {1097 F(1010526, P_XO, 1, 1, 19),1098 { }1099};1100 1101static struct clk_rcg2 pcie_aux_clk_src = {1102 .cmd_rcgr = 0x6c000,1103 .mnd_width = 16,1104 .hid_width = 5,1105 .parent_map = gcc_xo_sleep_clk_map,1106 .freq_tbl = ftbl_pcie_aux_clk_src,1107 .clkr.hw.init = &(struct clk_init_data){1108 .name = "pcie_aux_clk_src",1109 .parent_data = gcc_xo_sleep_clk,1110 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),1111 .ops = &clk_rcg2_ops,1112 },1113};1114 1115static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {1116 F(100000000, P_GPLL0, 6, 0, 0),1117 F(200000000, P_GPLL0, 3, 0, 0),1118 F(240000000, P_GPLL0, 2.5, 0, 0),1119 { }1120};1121 1122static struct clk_rcg2 ufs_axi_clk_src = {1123 .cmd_rcgr = 0x75024,1124 .mnd_width = 8,1125 .hid_width = 5,1126 .parent_map = gcc_xo_gpll0_map,1127 .freq_tbl = ftbl_ufs_axi_clk_src,1128 .clkr.hw.init = &(struct clk_init_data){1129 .name = "ufs_axi_clk_src",1130 .parent_data = gcc_xo_gpll0,1131 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),1132 .ops = &clk_rcg2_ops,1133 },1134};1135 1136static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {1137 F(19200000, P_XO, 1, 0, 0),1138 F(150000000, P_GPLL0, 4, 0, 0),1139 F(300000000, P_GPLL0, 2, 0, 0),1140 { }1141};1142 1143static struct clk_rcg2 ufs_ice_core_clk_src = {1144 .cmd_rcgr = 0x76014,1145 .hid_width = 5,1146 .parent_map = gcc_xo_gpll0_map,1147 .freq_tbl = ftbl_ufs_ice_core_clk_src,1148 .clkr.hw.init = &(struct clk_init_data){1149 .name = "ufs_ice_core_clk_src",1150 .parent_data = gcc_xo_gpll0,1151 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),1152 .ops = &clk_rcg2_ops,1153 },1154};1155 1156static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {1157 F(75000000, P_GPLL0, 8, 0, 0),1158 F(150000000, P_GPLL0, 4, 0, 0),1159 F(256000000, P_GPLL4, 1.5, 0, 0),1160 F(300000000, P_GPLL0, 2, 0, 0),1161 { }1162};1163 1164static struct clk_rcg2 qspi_ser_clk_src = {1165 .cmd_rcgr = 0x8b00c,1166 .hid_width = 5,1167 .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,1168 .freq_tbl = ftbl_qspi_ser_clk_src,1169 .clkr.hw.init = &(struct clk_init_data){1170 .name = "qspi_ser_clk_src",1171 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,1172 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),1173 .ops = &clk_rcg2_ops,1174 },1175};1176 1177static struct clk_branch gcc_sys_noc_usb3_axi_clk = {1178 .halt_reg = 0x0f03c,1179 .clkr = {1180 .enable_reg = 0x0f03c,1181 .enable_mask = BIT(0),1182 .hw.init = &(struct clk_init_data){1183 .name = "gcc_sys_noc_usb3_axi_clk",1184 .parent_hws = (const struct clk_hw*[]){1185 &usb30_master_clk_src.clkr.hw,1186 },1187 .num_parents = 1,1188 .flags = CLK_SET_RATE_PARENT,1189 .ops = &clk_branch2_ops,1190 },1191 },1192};1193 1194static struct clk_branch gcc_sys_noc_ufs_axi_clk = {1195 .halt_reg = 0x75038,1196 .clkr = {1197 .enable_reg = 0x75038,1198 .enable_mask = BIT(0),1199 .hw.init = &(struct clk_init_data){1200 .name = "gcc_sys_noc_ufs_axi_clk",1201 .parent_hws = (const struct clk_hw*[]){1202 &ufs_axi_clk_src.clkr.hw,1203 },1204 .num_parents = 1,1205 .flags = CLK_SET_RATE_PARENT,1206 .ops = &clk_branch2_ops,1207 },1208 },1209};1210 1211static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {1212 .halt_reg = 0x6010,1213 .clkr = {1214 .enable_reg = 0x6010,1215 .enable_mask = BIT(0),1216 .hw.init = &(struct clk_init_data){1217 .name = "gcc_periph_noc_usb20_ahb_clk",1218 .parent_hws = (const struct clk_hw*[]){1219 &usb20_master_clk_src.clkr.hw,1220 },1221 .num_parents = 1,1222 .flags = CLK_SET_RATE_PARENT,1223 .ops = &clk_branch2_ops,1224 },1225 },1226};1227 1228static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {1229 .halt_reg = 0x9008,1230 .clkr = {1231 .enable_reg = 0x9008,1232 .enable_mask = BIT(0),1233 .hw.init = &(struct clk_init_data){1234 .name = "gcc_mmss_noc_cfg_ahb_clk",1235 .flags = CLK_IGNORE_UNUSED,1236 .ops = &clk_branch2_ops,1237 },1238 },1239};1240 1241static struct clk_branch gcc_mmss_bimc_gfx_clk = {1242 .halt_reg = 0x9010,1243 .clkr = {1244 .enable_reg = 0x9010,1245 .enable_mask = BIT(0),1246 .hw.init = &(struct clk_init_data){1247 .name = "gcc_mmss_bimc_gfx_clk",1248 .flags = CLK_SET_RATE_PARENT,1249 .ops = &clk_branch2_ops,1250 },1251 },1252};1253 1254static struct clk_branch gcc_usb30_master_clk = {1255 .halt_reg = 0x0f008,1256 .clkr = {1257 .enable_reg = 0x0f008,1258 .enable_mask = BIT(0),1259 .hw.init = &(struct clk_init_data){1260 .name = "gcc_usb30_master_clk",1261 .parent_hws = (const struct clk_hw*[]){1262 &usb30_master_clk_src.clkr.hw,1263 },1264 .num_parents = 1,1265 .flags = CLK_SET_RATE_PARENT,1266 .ops = &clk_branch2_ops,1267 },1268 },1269};1270 1271static struct clk_branch gcc_usb30_sleep_clk = {1272 .halt_reg = 0x0f00c,1273 .clkr = {1274 .enable_reg = 0x0f00c,1275 .enable_mask = BIT(0),1276 .hw.init = &(struct clk_init_data){1277 .name = "gcc_usb30_sleep_clk",1278 .parent_hws = (const struct clk_hw*[]){1279 &gcc_sleep_clk_src.clkr.hw,1280 },1281 .num_parents = 1,1282 .flags = CLK_SET_RATE_PARENT,1283 .ops = &clk_branch2_ops,1284 },1285 },1286};1287 1288static struct clk_branch gcc_usb30_mock_utmi_clk = {1289 .halt_reg = 0x0f010,1290 .clkr = {1291 .enable_reg = 0x0f010,1292 .enable_mask = BIT(0),1293 .hw.init = &(struct clk_init_data){1294 .name = "gcc_usb30_mock_utmi_clk",1295 .parent_hws = (const struct clk_hw*[]){1296 &usb30_mock_utmi_clk_src.clkr.hw,1297 },1298 .num_parents = 1,1299 .flags = CLK_SET_RATE_PARENT,1300 .ops = &clk_branch2_ops,1301 },1302 },1303};1304 1305static struct clk_branch gcc_usb3_phy_aux_clk = {1306 .halt_reg = 0x50000,1307 .clkr = {1308 .enable_reg = 0x50000,1309 .enable_mask = BIT(0),1310 .hw.init = &(struct clk_init_data){1311 .name = "gcc_usb3_phy_aux_clk",1312 .parent_hws = (const struct clk_hw*[]){1313 &usb3_phy_aux_clk_src.clkr.hw,1314 },1315 .num_parents = 1,1316 .flags = CLK_SET_RATE_PARENT,1317 .ops = &clk_branch2_ops,1318 },1319 },1320};1321 1322static struct clk_branch gcc_usb3_phy_pipe_clk = {1323 .halt_reg = 0x50004,1324 .halt_check = BRANCH_HALT_SKIP,1325 .clkr = {1326 .enable_reg = 0x50004,1327 .enable_mask = BIT(0),1328 .hw.init = &(struct clk_init_data){1329 .name = "gcc_usb3_phy_pipe_clk",1330 .parent_data = &(const struct clk_parent_data){1331 .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",1332 },1333 .num_parents = 1,1334 .flags = CLK_SET_RATE_PARENT,1335 .ops = &clk_branch2_ops,1336 },1337 },1338};1339 1340static struct clk_branch gcc_usb20_master_clk = {1341 .halt_reg = 0x12004,1342 .clkr = {1343 .enable_reg = 0x12004,1344 .enable_mask = BIT(0),1345 .hw.init = &(struct clk_init_data){1346 .name = "gcc_usb20_master_clk",1347 .parent_hws = (const struct clk_hw*[]){1348 &usb20_master_clk_src.clkr.hw,1349 },1350 .num_parents = 1,1351 .flags = CLK_SET_RATE_PARENT,1352 .ops = &clk_branch2_ops,1353 },1354 },1355};1356 1357static struct clk_branch gcc_usb20_sleep_clk = {1358 .halt_reg = 0x12008,1359 .clkr = {1360 .enable_reg = 0x12008,1361 .enable_mask = BIT(0),1362 .hw.init = &(struct clk_init_data){1363 .name = "gcc_usb20_sleep_clk",1364 .parent_hws = (const struct clk_hw*[]){1365 &gcc_sleep_clk_src.clkr.hw,1366 },1367 .num_parents = 1,1368 .flags = CLK_SET_RATE_PARENT,1369 .ops = &clk_branch2_ops,1370 },1371 },1372};1373 1374static struct clk_branch gcc_usb20_mock_utmi_clk = {1375 .halt_reg = 0x1200c,1376 .clkr = {1377 .enable_reg = 0x1200c,1378 .enable_mask = BIT(0),1379 .hw.init = &(struct clk_init_data){1380 .name = "gcc_usb20_mock_utmi_clk",1381 .parent_hws = (const struct clk_hw*[]){1382 &usb20_mock_utmi_clk_src.clkr.hw,1383 },1384 .num_parents = 1,1385 .flags = CLK_SET_RATE_PARENT,1386 .ops = &clk_branch2_ops,1387 },1388 },1389};1390 1391static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {1392 .halt_reg = 0x6a004,1393 .clkr = {1394 .enable_reg = 0x6a004,1395 .enable_mask = BIT(0),1396 .hw.init = &(struct clk_init_data){1397 .name = "gcc_usb_phy_cfg_ahb2phy_clk",1398 .ops = &clk_branch2_ops,1399 },1400 },1401};1402 1403static struct clk_branch gcc_sdcc1_apps_clk = {1404 .halt_reg = 0x13004,1405 .clkr = {1406 .enable_reg = 0x13004,1407 .enable_mask = BIT(0),1408 .hw.init = &(struct clk_init_data){1409 .name = "gcc_sdcc1_apps_clk",1410 .parent_hws = (const struct clk_hw*[]){1411 &sdcc1_apps_clk_src.clkr.hw,1412 },1413 .num_parents = 1,1414 .flags = CLK_SET_RATE_PARENT,1415 .ops = &clk_branch2_ops,1416 },1417 },1418};1419 1420static struct clk_branch gcc_sdcc1_ahb_clk = {1421 .halt_reg = 0x13008,1422 .clkr = {1423 .enable_reg = 0x13008,1424 .enable_mask = BIT(0),1425 .hw.init = &(struct clk_init_data){1426 .name = "gcc_sdcc1_ahb_clk",1427 .ops = &clk_branch2_ops,1428 },1429 },1430};1431 1432static struct clk_branch gcc_sdcc1_ice_core_clk = {1433 .halt_reg = 0x13038,1434 .clkr = {1435 .enable_reg = 0x13038,1436 .enable_mask = BIT(0),1437 .hw.init = &(struct clk_init_data){1438 .name = "gcc_sdcc1_ice_core_clk",1439 .parent_hws = (const struct clk_hw*[]){1440 &sdcc1_ice_core_clk_src.clkr.hw,1441 },1442 .num_parents = 1,1443 .flags = CLK_SET_RATE_PARENT,1444 .ops = &clk_branch2_ops,1445 },1446 },1447};1448 1449static struct clk_branch gcc_sdcc2_apps_clk = {1450 .halt_reg = 0x14004,1451 .clkr = {1452 .enable_reg = 0x14004,1453 .enable_mask = BIT(0),1454 .hw.init = &(struct clk_init_data){1455 .name = "gcc_sdcc2_apps_clk",1456 .parent_hws = (const struct clk_hw*[]){1457 &sdcc2_apps_clk_src.clkr.hw,1458 },1459 .num_parents = 1,1460 .flags = CLK_SET_RATE_PARENT,1461 .ops = &clk_branch2_ops,1462 },1463 },1464};1465 1466static struct clk_branch gcc_sdcc2_ahb_clk = {1467 .halt_reg = 0x14008,1468 .clkr = {1469 .enable_reg = 0x14008,1470 .enable_mask = BIT(0),1471 .hw.init = &(struct clk_init_data){1472 .name = "gcc_sdcc2_ahb_clk",1473 .ops = &clk_branch2_ops,1474 },1475 },1476};1477 1478static struct clk_branch gcc_sdcc3_apps_clk = {1479 .halt_reg = 0x15004,1480 .clkr = {1481 .enable_reg = 0x15004,1482 .enable_mask = BIT(0),1483 .hw.init = &(struct clk_init_data){1484 .name = "gcc_sdcc3_apps_clk",1485 .parent_hws = (const struct clk_hw*[]){1486 &sdcc3_apps_clk_src.clkr.hw,1487 },1488 .num_parents = 1,1489 .flags = CLK_SET_RATE_PARENT,1490 .ops = &clk_branch2_ops,1491 },1492 },1493};1494 1495static struct clk_branch gcc_sdcc3_ahb_clk = {1496 .halt_reg = 0x15008,1497 .clkr = {1498 .enable_reg = 0x15008,1499 .enable_mask = BIT(0),1500 .hw.init = &(struct clk_init_data){1501 .name = "gcc_sdcc3_ahb_clk",1502 .ops = &clk_branch2_ops,1503 },1504 },1505};1506 1507static struct clk_branch gcc_sdcc4_apps_clk = {1508 .halt_reg = 0x16004,1509 .clkr = {1510 .enable_reg = 0x16004,1511 .enable_mask = BIT(0),1512 .hw.init = &(struct clk_init_data){1513 .name = "gcc_sdcc4_apps_clk",1514 .parent_hws = (const struct clk_hw*[]){1515 &sdcc4_apps_clk_src.clkr.hw,1516 },1517 .num_parents = 1,1518 .flags = CLK_SET_RATE_PARENT,1519 .ops = &clk_branch2_ops,1520 },1521 },1522};1523 1524static struct clk_branch gcc_sdcc4_ahb_clk = {1525 .halt_reg = 0x16008,1526 .clkr = {1527 .enable_reg = 0x16008,1528 .enable_mask = BIT(0),1529 .hw.init = &(struct clk_init_data){1530 .name = "gcc_sdcc4_ahb_clk",1531 .ops = &clk_branch2_ops,1532 },1533 },1534};1535 1536static struct clk_branch gcc_blsp1_ahb_clk = {1537 .halt_reg = 0x17004,1538 .halt_check = BRANCH_HALT_VOTED,1539 .clkr = {1540 .enable_reg = 0x52004,1541 .enable_mask = BIT(17),1542 .hw.init = &(struct clk_init_data){1543 .name = "gcc_blsp1_ahb_clk",1544 .ops = &clk_branch2_ops,1545 },1546 },1547};1548 1549static struct clk_branch gcc_blsp1_sleep_clk = {1550 .halt_reg = 0x17008,1551 .halt_check = BRANCH_HALT_VOTED,1552 .clkr = {1553 .enable_reg = 0x52004,1554 .enable_mask = BIT(16),1555 .hw.init = &(struct clk_init_data){1556 .name = "gcc_blsp1_sleep_clk",1557 .parent_hws = (const struct clk_hw*[]){1558 &gcc_sleep_clk_src.clkr.hw,1559 },1560 .num_parents = 1,1561 .flags = CLK_SET_RATE_PARENT,1562 .ops = &clk_branch2_ops,1563 },1564 },1565};1566 1567static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {1568 .halt_reg = 0x19004,1569 .clkr = {1570 .enable_reg = 0x19004,1571 .enable_mask = BIT(0),1572 .hw.init = &(struct clk_init_data){1573 .name = "gcc_blsp1_qup1_spi_apps_clk",1574 .parent_hws = (const struct clk_hw*[]){1575 &blsp1_qup1_spi_apps_clk_src.clkr.hw,1576 },1577 .num_parents = 1,1578 .flags = CLK_SET_RATE_PARENT,1579 .ops = &clk_branch2_ops,1580 },1581 },1582};1583 1584static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {1585 .halt_reg = 0x19008,1586 .clkr = {1587 .enable_reg = 0x19008,1588 .enable_mask = BIT(0),1589 .hw.init = &(struct clk_init_data){1590 .name = "gcc_blsp1_qup1_i2c_apps_clk",1591 .parent_hws = (const struct clk_hw*[]){1592 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,1593 },1594 .num_parents = 1,1595 .flags = CLK_SET_RATE_PARENT,1596 .ops = &clk_branch2_ops,1597 },1598 },1599};1600 1601static struct clk_branch gcc_blsp1_uart1_apps_clk = {1602 .halt_reg = 0x1a004,1603 .clkr = {1604 .enable_reg = 0x1a004,1605 .enable_mask = BIT(0),1606 .hw.init = &(struct clk_init_data){1607 .name = "gcc_blsp1_uart1_apps_clk",1608 .parent_hws = (const struct clk_hw*[]){1609 &blsp1_uart1_apps_clk_src.clkr.hw,1610 },1611 .num_parents = 1,1612 .flags = CLK_SET_RATE_PARENT,1613 .ops = &clk_branch2_ops,1614 },1615 },1616};1617 1618static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {1619 .halt_reg = 0x1b004,1620 .clkr = {1621 .enable_reg = 0x1b004,1622 .enable_mask = BIT(0),1623 .hw.init = &(struct clk_init_data){1624 .name = "gcc_blsp1_qup2_spi_apps_clk",1625 .parent_hws = (const struct clk_hw*[]){1626 &blsp1_qup2_spi_apps_clk_src.clkr.hw,1627 },1628 .num_parents = 1,1629 .flags = CLK_SET_RATE_PARENT,1630 .ops = &clk_branch2_ops,1631 },1632 },1633};1634 1635static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {1636 .halt_reg = 0x1b008,1637 .clkr = {1638 .enable_reg = 0x1b008,1639 .enable_mask = BIT(0),1640 .hw.init = &(struct clk_init_data){1641 .name = "gcc_blsp1_qup2_i2c_apps_clk",1642 .parent_hws = (const struct clk_hw*[]){1643 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,1644 },1645 .num_parents = 1,1646 .flags = CLK_SET_RATE_PARENT,1647 .ops = &clk_branch2_ops,1648 },1649 },1650};1651 1652static struct clk_branch gcc_blsp1_uart2_apps_clk = {1653 .halt_reg = 0x1c004,1654 .clkr = {1655 .enable_reg = 0x1c004,1656 .enable_mask = BIT(0),1657 .hw.init = &(struct clk_init_data){1658 .name = "gcc_blsp1_uart2_apps_clk",1659 .parent_hws = (const struct clk_hw*[]){1660 &blsp1_uart2_apps_clk_src.clkr.hw,1661 },1662 .num_parents = 1,1663 .flags = CLK_SET_RATE_PARENT,1664 .ops = &clk_branch2_ops,1665 },1666 },1667};1668 1669static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {1670 .halt_reg = 0x1d004,1671 .clkr = {1672 .enable_reg = 0x1d004,1673 .enable_mask = BIT(0),1674 .hw.init = &(struct clk_init_data){1675 .name = "gcc_blsp1_qup3_spi_apps_clk",1676 .parent_hws = (const struct clk_hw*[]){1677 &blsp1_qup3_spi_apps_clk_src.clkr.hw,1678 },1679 .num_parents = 1,1680 .flags = CLK_SET_RATE_PARENT,1681 .ops = &clk_branch2_ops,1682 },1683 },1684};1685 1686static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {1687 .halt_reg = 0x1d008,1688 .clkr = {1689 .enable_reg = 0x1d008,1690 .enable_mask = BIT(0),1691 .hw.init = &(struct clk_init_data){1692 .name = "gcc_blsp1_qup3_i2c_apps_clk",1693 .parent_hws = (const struct clk_hw*[]){1694 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,1695 },1696 .num_parents = 1,1697 .flags = CLK_SET_RATE_PARENT,1698 .ops = &clk_branch2_ops,1699 },1700 },1701};1702 1703static struct clk_branch gcc_blsp1_uart3_apps_clk = {1704 .halt_reg = 0x1e004,1705 .clkr = {1706 .enable_reg = 0x1e004,1707 .enable_mask = BIT(0),1708 .hw.init = &(struct clk_init_data){1709 .name = "gcc_blsp1_uart3_apps_clk",1710 .parent_hws = (const struct clk_hw*[]){1711 &blsp1_uart3_apps_clk_src.clkr.hw,1712 },1713 .num_parents = 1,1714 .flags = CLK_SET_RATE_PARENT,1715 .ops = &clk_branch2_ops,1716 },1717 },1718};1719 1720static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {1721 .halt_reg = 0x1f004,1722 .clkr = {1723 .enable_reg = 0x1f004,1724 .enable_mask = BIT(0),1725 .hw.init = &(struct clk_init_data){1726 .name = "gcc_blsp1_qup4_spi_apps_clk",1727 .parent_hws = (const struct clk_hw*[]){1728 &blsp1_qup4_spi_apps_clk_src.clkr.hw,1729 },1730 .num_parents = 1,1731 .flags = CLK_SET_RATE_PARENT,1732 .ops = &clk_branch2_ops,1733 },1734 },1735};1736 1737static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {1738 .halt_reg = 0x1f008,1739 .clkr = {1740 .enable_reg = 0x1f008,1741 .enable_mask = BIT(0),1742 .hw.init = &(struct clk_init_data){1743 .name = "gcc_blsp1_qup4_i2c_apps_clk",1744 .parent_hws = (const struct clk_hw*[]){1745 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,1746 },1747 .num_parents = 1,1748 .flags = CLK_SET_RATE_PARENT,1749 .ops = &clk_branch2_ops,1750 },1751 },1752};1753 1754static struct clk_branch gcc_blsp1_uart4_apps_clk = {1755 .halt_reg = 0x20004,1756 .clkr = {1757 .enable_reg = 0x20004,1758 .enable_mask = BIT(0),1759 .hw.init = &(struct clk_init_data){1760 .name = "gcc_blsp1_uart4_apps_clk",1761 .parent_hws = (const struct clk_hw*[]){1762 &blsp1_uart4_apps_clk_src.clkr.hw,1763 },1764 .num_parents = 1,1765 .flags = CLK_SET_RATE_PARENT,1766 .ops = &clk_branch2_ops,1767 },1768 },1769};1770 1771static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {1772 .halt_reg = 0x21004,1773 .clkr = {1774 .enable_reg = 0x21004,1775 .enable_mask = BIT(0),1776 .hw.init = &(struct clk_init_data){1777 .name = "gcc_blsp1_qup5_spi_apps_clk",1778 .parent_hws = (const struct clk_hw*[]){1779 &blsp1_qup5_spi_apps_clk_src.clkr.hw,1780 },1781 .num_parents = 1,1782 .flags = CLK_SET_RATE_PARENT,1783 .ops = &clk_branch2_ops,1784 },1785 },1786};1787 1788static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {1789 .halt_reg = 0x21008,1790 .clkr = {1791 .enable_reg = 0x21008,1792 .enable_mask = BIT(0),1793 .hw.init = &(struct clk_init_data){1794 .name = "gcc_blsp1_qup5_i2c_apps_clk",1795 .parent_hws = (const struct clk_hw*[]){1796 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,1797 },1798 .num_parents = 1,1799 .flags = CLK_SET_RATE_PARENT,1800 .ops = &clk_branch2_ops,1801 },1802 },1803};1804 1805static struct clk_branch gcc_blsp1_uart5_apps_clk = {1806 .halt_reg = 0x22004,1807 .clkr = {1808 .enable_reg = 0x22004,1809 .enable_mask = BIT(0),1810 .hw.init = &(struct clk_init_data){1811 .name = "gcc_blsp1_uart5_apps_clk",1812 .parent_hws = (const struct clk_hw*[]){1813 &blsp1_uart5_apps_clk_src.clkr.hw,1814 },1815 .num_parents = 1,1816 .flags = CLK_SET_RATE_PARENT,1817 .ops = &clk_branch2_ops,1818 },1819 },1820};1821 1822static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {1823 .halt_reg = 0x23004,1824 .clkr = {1825 .enable_reg = 0x23004,1826 .enable_mask = BIT(0),1827 .hw.init = &(struct clk_init_data){1828 .name = "gcc_blsp1_qup6_spi_apps_clk",1829 .parent_hws = (const struct clk_hw*[]){1830 &blsp1_qup6_spi_apps_clk_src.clkr.hw,1831 },1832 .num_parents = 1,1833 .flags = CLK_SET_RATE_PARENT,1834 .ops = &clk_branch2_ops,1835 },1836 },1837};1838 1839static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {1840 .halt_reg = 0x23008,1841 .clkr = {1842 .enable_reg = 0x23008,1843 .enable_mask = BIT(0),1844 .hw.init = &(struct clk_init_data){1845 .name = "gcc_blsp1_qup6_i2c_apps_clk",1846 .parent_hws = (const struct clk_hw*[]){1847 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,1848 },1849 .num_parents = 1,1850 .flags = CLK_SET_RATE_PARENT,1851 .ops = &clk_branch2_ops,1852 },1853 },1854};1855 1856static struct clk_branch gcc_blsp1_uart6_apps_clk = {1857 .halt_reg = 0x24004,1858 .clkr = {1859 .enable_reg = 0x24004,1860 .enable_mask = BIT(0),1861 .hw.init = &(struct clk_init_data){1862 .name = "gcc_blsp1_uart6_apps_clk",1863 .parent_hws = (const struct clk_hw*[]){1864 &blsp1_uart6_apps_clk_src.clkr.hw,1865 },1866 .num_parents = 1,1867 .flags = CLK_SET_RATE_PARENT,1868 .ops = &clk_branch2_ops,1869 },1870 },1871};1872 1873static struct clk_branch gcc_blsp2_ahb_clk = {1874 .halt_reg = 0x25004,1875 .halt_check = BRANCH_HALT_VOTED,1876 .clkr = {1877 .enable_reg = 0x52004,1878 .enable_mask = BIT(15),1879 .hw.init = &(struct clk_init_data){1880 .name = "gcc_blsp2_ahb_clk",1881 .ops = &clk_branch2_ops,1882 },1883 },1884};1885 1886static struct clk_branch gcc_blsp2_sleep_clk = {1887 .halt_reg = 0x25008,1888 .halt_check = BRANCH_HALT_VOTED,1889 .clkr = {1890 .enable_reg = 0x52004,1891 .enable_mask = BIT(14),1892 .hw.init = &(struct clk_init_data){1893 .name = "gcc_blsp2_sleep_clk",1894 .parent_hws = (const struct clk_hw*[]){1895 &gcc_sleep_clk_src.clkr.hw,1896 },1897 .num_parents = 1,1898 .flags = CLK_SET_RATE_PARENT,1899 .ops = &clk_branch2_ops,1900 },1901 },1902};1903 1904static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {1905 .halt_reg = 0x26004,1906 .clkr = {1907 .enable_reg = 0x26004,1908 .enable_mask = BIT(0),1909 .hw.init = &(struct clk_init_data){1910 .name = "gcc_blsp2_qup1_spi_apps_clk",1911 .parent_hws = (const struct clk_hw*[]){1912 &blsp2_qup1_spi_apps_clk_src.clkr.hw,1913 },1914 .num_parents = 1,1915 .flags = CLK_SET_RATE_PARENT,1916 .ops = &clk_branch2_ops,1917 },1918 },1919};1920 1921static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {1922 .halt_reg = 0x26008,1923 .clkr = {1924 .enable_reg = 0x26008,1925 .enable_mask = BIT(0),1926 .hw.init = &(struct clk_init_data){1927 .name = "gcc_blsp2_qup1_i2c_apps_clk",1928 .parent_hws = (const struct clk_hw*[]){1929 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,1930 },1931 .num_parents = 1,1932 .flags = CLK_SET_RATE_PARENT,1933 .ops = &clk_branch2_ops,1934 },1935 },1936};1937 1938static struct clk_branch gcc_blsp2_uart1_apps_clk = {1939 .halt_reg = 0x27004,1940 .clkr = {1941 .enable_reg = 0x27004,1942 .enable_mask = BIT(0),1943 .hw.init = &(struct clk_init_data){1944 .name = "gcc_blsp2_uart1_apps_clk",1945 .parent_hws = (const struct clk_hw*[]){1946 &blsp2_uart1_apps_clk_src.clkr.hw,1947 },1948 .num_parents = 1,1949 .flags = CLK_SET_RATE_PARENT,1950 .ops = &clk_branch2_ops,1951 },1952 },1953};1954 1955static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {1956 .halt_reg = 0x28004,1957 .clkr = {1958 .enable_reg = 0x28004,1959 .enable_mask = BIT(0),1960 .hw.init = &(struct clk_init_data){1961 .name = "gcc_blsp2_qup2_spi_apps_clk",1962 .parent_hws = (const struct clk_hw*[]){1963 &blsp2_qup2_spi_apps_clk_src.clkr.hw,1964 },1965 .num_parents = 1,1966 .flags = CLK_SET_RATE_PARENT,1967 .ops = &clk_branch2_ops,1968 },1969 },1970};1971 1972static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {1973 .halt_reg = 0x28008,1974 .clkr = {1975 .enable_reg = 0x28008,1976 .enable_mask = BIT(0),1977 .hw.init = &(struct clk_init_data){1978 .name = "gcc_blsp2_qup2_i2c_apps_clk",1979 .parent_hws = (const struct clk_hw*[]){1980 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,1981 },1982 .num_parents = 1,1983 .flags = CLK_SET_RATE_PARENT,1984 .ops = &clk_branch2_ops,1985 },1986 },1987};1988 1989static struct clk_branch gcc_blsp2_uart2_apps_clk = {1990 .halt_reg = 0x29004,1991 .clkr = {1992 .enable_reg = 0x29004,1993 .enable_mask = BIT(0),1994 .hw.init = &(struct clk_init_data){1995 .name = "gcc_blsp2_uart2_apps_clk",1996 .parent_hws = (const struct clk_hw*[]){1997 &blsp2_uart2_apps_clk_src.clkr.hw,1998 },1999 .num_parents = 1,2000 .flags = CLK_SET_RATE_PARENT,2001 .ops = &clk_branch2_ops,2002 },2003 },2004};2005 2006static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {2007 .halt_reg = 0x2a004,2008 .clkr = {2009 .enable_reg = 0x2a004,2010 .enable_mask = BIT(0),2011 .hw.init = &(struct clk_init_data){2012 .name = "gcc_blsp2_qup3_spi_apps_clk",2013 .parent_hws = (const struct clk_hw*[]){2014 &blsp2_qup3_spi_apps_clk_src.clkr.hw,2015 },2016 .num_parents = 1,2017 .flags = CLK_SET_RATE_PARENT,2018 .ops = &clk_branch2_ops,2019 },2020 },2021};2022 2023static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {2024 .halt_reg = 0x2a008,2025 .clkr = {2026 .enable_reg = 0x2a008,2027 .enable_mask = BIT(0),2028 .hw.init = &(struct clk_init_data){2029 .name = "gcc_blsp2_qup3_i2c_apps_clk",2030 .parent_hws = (const struct clk_hw*[]){2031 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,2032 },2033 .num_parents = 1,2034 .flags = CLK_SET_RATE_PARENT,2035 .ops = &clk_branch2_ops,2036 },2037 },2038};2039 2040static struct clk_branch gcc_blsp2_uart3_apps_clk = {2041 .halt_reg = 0x2b004,2042 .clkr = {2043 .enable_reg = 0x2b004,2044 .enable_mask = BIT(0),2045 .hw.init = &(struct clk_init_data){2046 .name = "gcc_blsp2_uart3_apps_clk",2047 .parent_hws = (const struct clk_hw*[]){2048 &blsp2_uart3_apps_clk_src.clkr.hw,2049 },2050 .num_parents = 1,2051 .flags = CLK_SET_RATE_PARENT,2052 .ops = &clk_branch2_ops,2053 },2054 },2055};2056 2057static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {2058 .halt_reg = 0x2c004,2059 .clkr = {2060 .enable_reg = 0x2c004,2061 .enable_mask = BIT(0),2062 .hw.init = &(struct clk_init_data){2063 .name = "gcc_blsp2_qup4_spi_apps_clk",2064 .parent_hws = (const struct clk_hw*[]){2065 &blsp2_qup4_spi_apps_clk_src.clkr.hw,2066 },2067 .num_parents = 1,2068 .flags = CLK_SET_RATE_PARENT,2069 .ops = &clk_branch2_ops,2070 },2071 },2072};2073 2074static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {2075 .halt_reg = 0x2c008,2076 .clkr = {2077 .enable_reg = 0x2c008,2078 .enable_mask = BIT(0),2079 .hw.init = &(struct clk_init_data){2080 .name = "gcc_blsp2_qup4_i2c_apps_clk",2081 .parent_hws = (const struct clk_hw*[]){2082 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,2083 },2084 .num_parents = 1,2085 .flags = CLK_SET_RATE_PARENT,2086 .ops = &clk_branch2_ops,2087 },2088 },2089};2090 2091static struct clk_branch gcc_blsp2_uart4_apps_clk = {2092 .halt_reg = 0x2d004,2093 .clkr = {2094 .enable_reg = 0x2d004,2095 .enable_mask = BIT(0),2096 .hw.init = &(struct clk_init_data){2097 .name = "gcc_blsp2_uart4_apps_clk",2098 .parent_hws = (const struct clk_hw*[]){2099 &blsp2_uart4_apps_clk_src.clkr.hw,2100 },2101 .num_parents = 1,2102 .flags = CLK_SET_RATE_PARENT,2103 .ops = &clk_branch2_ops,2104 },2105 },2106};2107 2108static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {2109 .halt_reg = 0x2e004,2110 .clkr = {2111 .enable_reg = 0x2e004,2112 .enable_mask = BIT(0),2113 .hw.init = &(struct clk_init_data){2114 .name = "gcc_blsp2_qup5_spi_apps_clk",2115 .parent_hws = (const struct clk_hw*[]){2116 &blsp2_qup5_spi_apps_clk_src.clkr.hw,2117 },2118 .num_parents = 1,2119 .flags = CLK_SET_RATE_PARENT,2120 .ops = &clk_branch2_ops,2121 },2122 },2123};2124 2125static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {2126 .halt_reg = 0x2e008,2127 .clkr = {2128 .enable_reg = 0x2e008,2129 .enable_mask = BIT(0),2130 .hw.init = &(struct clk_init_data){2131 .name = "gcc_blsp2_qup5_i2c_apps_clk",2132 .parent_hws = (const struct clk_hw*[]){2133 &blsp2_qup5_i2c_apps_clk_src.clkr.hw,2134 },2135 .num_parents = 1,2136 .flags = CLK_SET_RATE_PARENT,2137 .ops = &clk_branch2_ops,2138 },2139 },2140};2141 2142static struct clk_branch gcc_blsp2_uart5_apps_clk = {2143 .halt_reg = 0x2f004,2144 .clkr = {2145 .enable_reg = 0x2f004,2146 .enable_mask = BIT(0),2147 .hw.init = &(struct clk_init_data){2148 .name = "gcc_blsp2_uart5_apps_clk",2149 .parent_hws = (const struct clk_hw*[]){2150 &blsp2_uart5_apps_clk_src.clkr.hw,2151 },2152 .num_parents = 1,2153 .flags = CLK_SET_RATE_PARENT,2154 .ops = &clk_branch2_ops,2155 },2156 },2157};2158 2159static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {2160 .halt_reg = 0x30004,2161 .clkr = {2162 .enable_reg = 0x30004,2163 .enable_mask = BIT(0),2164 .hw.init = &(struct clk_init_data){2165 .name = "gcc_blsp2_qup6_spi_apps_clk",2166 .parent_hws = (const struct clk_hw*[]){2167 &blsp2_qup6_spi_apps_clk_src.clkr.hw,2168 },2169 .num_parents = 1,2170 .flags = CLK_SET_RATE_PARENT,2171 .ops = &clk_branch2_ops,2172 },2173 },2174};2175 2176static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {2177 .halt_reg = 0x30008,2178 .clkr = {2179 .enable_reg = 0x30008,2180 .enable_mask = BIT(0),2181 .hw.init = &(struct clk_init_data){2182 .name = "gcc_blsp2_qup6_i2c_apps_clk",2183 .parent_hws = (const struct clk_hw*[]){2184 &blsp2_qup6_i2c_apps_clk_src.clkr.hw,2185 },2186 .num_parents = 1,2187 .flags = CLK_SET_RATE_PARENT,2188 .ops = &clk_branch2_ops,2189 },2190 },2191};2192 2193static struct clk_branch gcc_blsp2_uart6_apps_clk = {2194 .halt_reg = 0x31004,2195 .clkr = {2196 .enable_reg = 0x31004,2197 .enable_mask = BIT(0),2198 .hw.init = &(struct clk_init_data){2199 .name = "gcc_blsp2_uart6_apps_clk",2200 .parent_hws = (const struct clk_hw*[]){2201 &blsp2_uart6_apps_clk_src.clkr.hw,2202 },2203 .num_parents = 1,2204 .flags = CLK_SET_RATE_PARENT,2205 .ops = &clk_branch2_ops,2206 },2207 },2208};2209 2210static struct clk_branch gcc_pdm_ahb_clk = {2211 .halt_reg = 0x33004,2212 .clkr = {2213 .enable_reg = 0x33004,2214 .enable_mask = BIT(0),2215 .hw.init = &(struct clk_init_data){2216 .name = "gcc_pdm_ahb_clk",2217 .ops = &clk_branch2_ops,2218 },2219 },2220};2221 2222static struct clk_branch gcc_pdm2_clk = {2223 .halt_reg = 0x3300c,2224 .clkr = {2225 .enable_reg = 0x3300c,2226 .enable_mask = BIT(0),2227 .hw.init = &(struct clk_init_data){2228 .name = "gcc_pdm2_clk",2229 .parent_hws = (const struct clk_hw*[]){2230 &pdm2_clk_src.clkr.hw,2231 },2232 .num_parents = 1,2233 .flags = CLK_SET_RATE_PARENT,2234 .ops = &clk_branch2_ops,2235 },2236 },2237};2238 2239static struct clk_branch gcc_prng_ahb_clk = {2240 .halt_reg = 0x34004,2241 .halt_check = BRANCH_HALT_VOTED,2242 .clkr = {2243 .enable_reg = 0x52004,2244 .enable_mask = BIT(13),2245 .hw.init = &(struct clk_init_data){2246 .name = "gcc_prng_ahb_clk",2247 .ops = &clk_branch2_ops,2248 },2249 },2250};2251 2252static struct clk_branch gcc_tsif_ahb_clk = {2253 .halt_reg = 0x36004,2254 .clkr = {2255 .enable_reg = 0x36004,2256 .enable_mask = BIT(0),2257 .hw.init = &(struct clk_init_data){2258 .name = "gcc_tsif_ahb_clk",2259 .ops = &clk_branch2_ops,2260 },2261 },2262};2263 2264static struct clk_branch gcc_tsif_ref_clk = {2265 .halt_reg = 0x36008,2266 .clkr = {2267 .enable_reg = 0x36008,2268 .enable_mask = BIT(0),2269 .hw.init = &(struct clk_init_data){2270 .name = "gcc_tsif_ref_clk",2271 .parent_hws = (const struct clk_hw*[]){2272 &tsif_ref_clk_src.clkr.hw,2273 },2274 .num_parents = 1,2275 .flags = CLK_SET_RATE_PARENT,2276 .ops = &clk_branch2_ops,2277 },2278 },2279};2280 2281static struct clk_branch gcc_tsif_inactivity_timers_clk = {2282 .halt_reg = 0x3600c,2283 .clkr = {2284 .enable_reg = 0x3600c,2285 .enable_mask = BIT(0),2286 .hw.init = &(struct clk_init_data){2287 .name = "gcc_tsif_inactivity_timers_clk",2288 .parent_hws = (const struct clk_hw*[]){2289 &gcc_sleep_clk_src.clkr.hw,2290 },2291 .num_parents = 1,2292 .flags = CLK_SET_RATE_PARENT,2293 .ops = &clk_branch2_ops,2294 },2295 },2296};2297 2298static struct clk_branch gcc_boot_rom_ahb_clk = {2299 .halt_reg = 0x38004,2300 .halt_check = BRANCH_HALT_VOTED,2301 .clkr = {2302 .enable_reg = 0x52004,2303 .enable_mask = BIT(10),2304 .hw.init = &(struct clk_init_data){2305 .name = "gcc_boot_rom_ahb_clk",2306 .ops = &clk_branch2_ops,2307 },2308 },2309};2310 2311static struct clk_branch gcc_bimc_gfx_clk = {2312 .halt_reg = 0x46018,2313 .clkr = {2314 .enable_reg = 0x46018,2315 .enable_mask = BIT(0),2316 .hw.init = &(struct clk_init_data){2317 .name = "gcc_bimc_gfx_clk",2318 .flags = CLK_SET_RATE_PARENT,2319 .ops = &clk_branch2_ops,2320 },2321 },2322};2323 2324static struct clk_branch gcc_hmss_rbcpr_clk = {2325 .halt_reg = 0x4800c,2326 .clkr = {2327 .enable_reg = 0x4800c,2328 .enable_mask = BIT(0),2329 .hw.init = &(struct clk_init_data){2330 .name = "gcc_hmss_rbcpr_clk",2331 .parent_hws = (const struct clk_hw*[]){2332 &hmss_rbcpr_clk_src.clkr.hw,2333 },2334 .num_parents = 1,2335 .flags = CLK_SET_RATE_PARENT,2336 .ops = &clk_branch2_ops,2337 },2338 },2339};2340 2341static struct clk_branch gcc_gp1_clk = {2342 .halt_reg = 0x64000,2343 .clkr = {2344 .enable_reg = 0x64000,2345 .enable_mask = BIT(0),2346 .hw.init = &(struct clk_init_data){2347 .name = "gcc_gp1_clk",2348 .parent_hws = (const struct clk_hw*[]){2349 &gp1_clk_src.clkr.hw,2350 },2351 .num_parents = 1,2352 .flags = CLK_SET_RATE_PARENT,2353 .ops = &clk_branch2_ops,2354 },2355 },2356};2357 2358static struct clk_branch gcc_gp2_clk = {2359 .halt_reg = 0x65000,2360 .clkr = {2361 .enable_reg = 0x65000,2362 .enable_mask = BIT(0),2363 .hw.init = &(struct clk_init_data){2364 .name = "gcc_gp2_clk",2365 .parent_hws = (const struct clk_hw*[]){2366 &gp2_clk_src.clkr.hw,2367 },2368 .num_parents = 1,2369 .flags = CLK_SET_RATE_PARENT,2370 .ops = &clk_branch2_ops,2371 },2372 },2373};2374 2375static struct clk_branch gcc_gp3_clk = {2376 .halt_reg = 0x66000,2377 .clkr = {2378 .enable_reg = 0x66000,2379 .enable_mask = BIT(0),2380 .hw.init = &(struct clk_init_data){2381 .name = "gcc_gp3_clk",2382 .parent_hws = (const struct clk_hw*[]){2383 &gp3_clk_src.clkr.hw,2384 },2385 .num_parents = 1,2386 .flags = CLK_SET_RATE_PARENT,2387 .ops = &clk_branch2_ops,2388 },2389 },2390};2391 2392static struct clk_branch gcc_pcie_0_slv_axi_clk = {2393 .halt_reg = 0x6b008,2394 .clkr = {2395 .enable_reg = 0x6b008,2396 .enable_mask = BIT(0),2397 .hw.init = &(struct clk_init_data){2398 .name = "gcc_pcie_0_slv_axi_clk",2399 .ops = &clk_branch2_ops,2400 },2401 },2402};2403 2404static struct clk_branch gcc_pcie_0_mstr_axi_clk = {2405 .halt_reg = 0x6b00c,2406 .clkr = {2407 .enable_reg = 0x6b00c,2408 .enable_mask = BIT(0),2409 .hw.init = &(struct clk_init_data){2410 .name = "gcc_pcie_0_mstr_axi_clk",2411 .ops = &clk_branch2_ops,2412 },2413 },2414};2415 2416static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {2417 .halt_reg = 0x6b010,2418 .clkr = {2419 .enable_reg = 0x6b010,2420 .enable_mask = BIT(0),2421 .hw.init = &(struct clk_init_data){2422 .name = "gcc_pcie_0_cfg_ahb_clk",2423 .ops = &clk_branch2_ops,2424 },2425 },2426};2427 2428static struct clk_branch gcc_pcie_0_aux_clk = {2429 .halt_reg = 0x6b014,2430 .clkr = {2431 .enable_reg = 0x6b014,2432 .enable_mask = BIT(0),2433 .hw.init = &(struct clk_init_data){2434 .name = "gcc_pcie_0_aux_clk",2435 .parent_hws = (const struct clk_hw*[]){2436 &pcie_aux_clk_src.clkr.hw,2437 },2438 .num_parents = 1,2439 .flags = CLK_SET_RATE_PARENT,2440 .ops = &clk_branch2_ops,2441 },2442 },2443};2444 2445static struct clk_branch gcc_pcie_0_pipe_clk = {2446 .halt_reg = 0x6b018,2447 .halt_check = BRANCH_HALT_SKIP,2448 .clkr = {2449 .enable_reg = 0x6b018,2450 .enable_mask = BIT(0),2451 .hw.init = &(struct clk_init_data){2452 .name = "gcc_pcie_0_pipe_clk",2453 .parent_data = &(const struct clk_parent_data){2454 .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",2455 },2456 .num_parents = 1,2457 .flags = CLK_SET_RATE_PARENT,2458 .ops = &clk_branch2_ops,2459 },2460 },2461};2462 2463static struct clk_branch gcc_pcie_1_slv_axi_clk = {2464 .halt_reg = 0x6d008,2465 .clkr = {2466 .enable_reg = 0x6d008,2467 .enable_mask = BIT(0),2468 .hw.init = &(struct clk_init_data){2469 .name = "gcc_pcie_1_slv_axi_clk",2470 .ops = &clk_branch2_ops,2471 },2472 },2473};2474 2475static struct clk_branch gcc_pcie_1_mstr_axi_clk = {2476 .halt_reg = 0x6d00c,2477 .clkr = {2478 .enable_reg = 0x6d00c,2479 .enable_mask = BIT(0),2480 .hw.init = &(struct clk_init_data){2481 .name = "gcc_pcie_1_mstr_axi_clk",2482 .ops = &clk_branch2_ops,2483 },2484 },2485};2486 2487static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {2488 .halt_reg = 0x6d010,2489 .clkr = {2490 .enable_reg = 0x6d010,2491 .enable_mask = BIT(0),2492 .hw.init = &(struct clk_init_data){2493 .name = "gcc_pcie_1_cfg_ahb_clk",2494 .ops = &clk_branch2_ops,2495 },2496 },2497};2498 2499static struct clk_branch gcc_pcie_1_aux_clk = {2500 .halt_reg = 0x6d014,2501 .clkr = {2502 .enable_reg = 0x6d014,2503 .enable_mask = BIT(0),2504 .hw.init = &(struct clk_init_data){2505 .name = "gcc_pcie_1_aux_clk",2506 .parent_hws = (const struct clk_hw*[]){2507 &pcie_aux_clk_src.clkr.hw,2508 },2509 .num_parents = 1,2510 .flags = CLK_SET_RATE_PARENT,2511 .ops = &clk_branch2_ops,2512 },2513 },2514};2515 2516static struct clk_branch gcc_pcie_1_pipe_clk = {2517 .halt_reg = 0x6d018,2518 .halt_check = BRANCH_HALT_SKIP,2519 .clkr = {2520 .enable_reg = 0x6d018,2521 .enable_mask = BIT(0),2522 .hw.init = &(struct clk_init_data){2523 .name = "gcc_pcie_1_pipe_clk",2524 .parent_data = &(const struct clk_parent_data){2525 .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",2526 },2527 .num_parents = 1,2528 .flags = CLK_SET_RATE_PARENT,2529 .ops = &clk_branch2_ops,2530 },2531 },2532};2533 2534static struct clk_branch gcc_pcie_2_slv_axi_clk = {2535 .halt_reg = 0x6e008,2536 .clkr = {2537 .enable_reg = 0x6e008,2538 .enable_mask = BIT(0),2539 .hw.init = &(struct clk_init_data){2540 .name = "gcc_pcie_2_slv_axi_clk",2541 .ops = &clk_branch2_ops,2542 },2543 },2544};2545 2546static struct clk_branch gcc_pcie_2_mstr_axi_clk = {2547 .halt_reg = 0x6e00c,2548 .clkr = {2549 .enable_reg = 0x6e00c,2550 .enable_mask = BIT(0),2551 .hw.init = &(struct clk_init_data){2552 .name = "gcc_pcie_2_mstr_axi_clk",2553 .ops = &clk_branch2_ops,2554 },2555 },2556};2557 2558static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {2559 .halt_reg = 0x6e010,2560 .clkr = {2561 .enable_reg = 0x6e010,2562 .enable_mask = BIT(0),2563 .hw.init = &(struct clk_init_data){2564 .name = "gcc_pcie_2_cfg_ahb_clk",2565 .ops = &clk_branch2_ops,2566 },2567 },2568};2569 2570static struct clk_branch gcc_pcie_2_aux_clk = {2571 .halt_reg = 0x6e014,2572 .clkr = {2573 .enable_reg = 0x6e014,2574 .enable_mask = BIT(0),2575 .hw.init = &(struct clk_init_data){2576 .name = "gcc_pcie_2_aux_clk",2577 .parent_hws = (const struct clk_hw*[]){2578 &pcie_aux_clk_src.clkr.hw,2579 },2580 .num_parents = 1,2581 .flags = CLK_SET_RATE_PARENT,2582 .ops = &clk_branch2_ops,2583 },2584 },2585};2586 2587static struct clk_branch gcc_pcie_2_pipe_clk = {2588 .halt_reg = 0x6e018,2589 .halt_check = BRANCH_HALT_SKIP,2590 .clkr = {2591 .enable_reg = 0x6e018,2592 .enable_mask = BIT(0),2593 .hw.init = &(struct clk_init_data){2594 .name = "gcc_pcie_2_pipe_clk",2595 .parent_data = &(const struct clk_parent_data){2596 .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",2597 },2598 .num_parents = 1,2599 .flags = CLK_SET_RATE_PARENT,2600 .ops = &clk_branch2_ops,2601 },2602 },2603};2604 2605static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {2606 .halt_reg = 0x6f004,2607 .clkr = {2608 .enable_reg = 0x6f004,2609 .enable_mask = BIT(0),2610 .hw.init = &(struct clk_init_data){2611 .name = "gcc_pcie_phy_cfg_ahb_clk",2612 .ops = &clk_branch2_ops,2613 },2614 },2615};2616 2617static struct clk_branch gcc_pcie_phy_aux_clk = {2618 .halt_reg = 0x6f008,2619 .clkr = {2620 .enable_reg = 0x6f008,2621 .enable_mask = BIT(0),2622 .hw.init = &(struct clk_init_data){2623 .name = "gcc_pcie_phy_aux_clk",2624 .parent_hws = (const struct clk_hw*[]){2625 &pcie_aux_clk_src.clkr.hw,2626 },2627 .num_parents = 1,2628 .flags = CLK_SET_RATE_PARENT,2629 .ops = &clk_branch2_ops,2630 },2631 },2632};2633 2634static struct clk_branch gcc_ufs_axi_clk = {2635 .halt_reg = 0x75008,2636 .clkr = {2637 .enable_reg = 0x75008,2638 .enable_mask = BIT(0),2639 .hw.init = &(struct clk_init_data){2640 .name = "gcc_ufs_axi_clk",2641 .parent_hws = (const struct clk_hw*[]){2642 &ufs_axi_clk_src.clkr.hw,2643 },2644 .num_parents = 1,2645 .flags = CLK_SET_RATE_PARENT,2646 .ops = &clk_branch2_ops,2647 },2648 },2649};2650 2651static struct clk_branch gcc_ufs_ahb_clk = {2652 .halt_reg = 0x7500c,2653 .clkr = {2654 .enable_reg = 0x7500c,2655 .enable_mask = BIT(0),2656 .hw.init = &(struct clk_init_data){2657 .name = "gcc_ufs_ahb_clk",2658 .ops = &clk_branch2_ops,2659 },2660 },2661};2662 2663static struct clk_fixed_factor ufs_tx_cfg_clk_src = {2664 .mult = 1,2665 .div = 16,2666 .hw.init = &(struct clk_init_data){2667 .name = "ufs_tx_cfg_clk_src",2668 .parent_hws = (const struct clk_hw*[]){2669 &ufs_axi_clk_src.clkr.hw,2670 },2671 .num_parents = 1,2672 .flags = CLK_SET_RATE_PARENT,2673 .ops = &clk_fixed_factor_ops,2674 },2675};2676 2677static struct clk_branch gcc_ufs_tx_cfg_clk = {2678 .halt_reg = 0x75010,2679 .clkr = {2680 .enable_reg = 0x75010,2681 .enable_mask = BIT(0),2682 .hw.init = &(struct clk_init_data){2683 .name = "gcc_ufs_tx_cfg_clk",2684 .parent_hws = (const struct clk_hw*[]){2685 &ufs_tx_cfg_clk_src.hw,2686 },2687 .num_parents = 1,2688 .flags = CLK_SET_RATE_PARENT,2689 .ops = &clk_branch2_ops,2690 },2691 },2692};2693 2694static struct clk_fixed_factor ufs_rx_cfg_clk_src = {2695 .mult = 1,2696 .div = 16,2697 .hw.init = &(struct clk_init_data){2698 .name = "ufs_rx_cfg_clk_src",2699 .parent_hws = (const struct clk_hw*[]){2700 &ufs_axi_clk_src.clkr.hw,2701 },2702 .num_parents = 1,2703 .flags = CLK_SET_RATE_PARENT,2704 .ops = &clk_fixed_factor_ops,2705 },2706};2707 2708static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {2709 .halt_reg = 0x7d010,2710 .halt_check = BRANCH_HALT_VOTED,2711 .clkr = {2712 .enable_reg = 0x7d010,2713 .enable_mask = BIT(0),2714 .hw.init = &(struct clk_init_data){2715 .name = "hlos1_vote_lpass_core_smmu_clk",2716 .ops = &clk_branch2_ops,2717 },2718 },2719};2720 2721static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {2722 .halt_reg = 0x7d014,2723 .halt_check = BRANCH_HALT_VOTED,2724 .clkr = {2725 .enable_reg = 0x7d014,2726 .enable_mask = BIT(0),2727 .hw.init = &(struct clk_init_data){2728 .name = "hlos1_vote_lpass_adsp_smmu_clk",2729 .ops = &clk_branch2_ops,2730 },2731 },2732};2733 2734static struct clk_branch gcc_ufs_rx_cfg_clk = {2735 .halt_reg = 0x75014,2736 .clkr = {2737 .enable_reg = 0x75014,2738 .enable_mask = BIT(0),2739 .hw.init = &(struct clk_init_data){2740 .name = "gcc_ufs_rx_cfg_clk",2741 .parent_hws = (const struct clk_hw*[]){2742 &ufs_rx_cfg_clk_src.hw,2743 },2744 .num_parents = 1,2745 .flags = CLK_SET_RATE_PARENT,2746 .ops = &clk_branch2_ops,2747 },2748 },2749};2750 2751static struct clk_branch gcc_ufs_tx_symbol_0_clk = {2752 .halt_reg = 0x75018,2753 .halt_check = BRANCH_HALT_SKIP,2754 .clkr = {2755 .enable_reg = 0x75018,2756 .enable_mask = BIT(0),2757 .hw.init = &(struct clk_init_data){2758 .name = "gcc_ufs_tx_symbol_0_clk",2759 .parent_data = &(const struct clk_parent_data){2760 .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",2761 },2762 .num_parents = 1,2763 .flags = CLK_SET_RATE_PARENT,2764 .ops = &clk_branch2_ops,2765 },2766 },2767};2768 2769static struct clk_branch gcc_ufs_rx_symbol_0_clk = {2770 .halt_reg = 0x7501c,2771 .halt_check = BRANCH_HALT_SKIP,2772 .clkr = {2773 .enable_reg = 0x7501c,2774 .enable_mask = BIT(0),2775 .hw.init = &(struct clk_init_data){2776 .name = "gcc_ufs_rx_symbol_0_clk",2777 .parent_data = &(const struct clk_parent_data){2778 .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",2779 },2780 .num_parents = 1,2781 .flags = CLK_SET_RATE_PARENT,2782 .ops = &clk_branch2_ops,2783 },2784 },2785};2786 2787static struct clk_branch gcc_ufs_rx_symbol_1_clk = {2788 .halt_reg = 0x75020,2789 .halt_check = BRANCH_HALT_SKIP,2790 .clkr = {2791 .enable_reg = 0x75020,2792 .enable_mask = BIT(0),2793 .hw.init = &(struct clk_init_data){2794 .name = "gcc_ufs_rx_symbol_1_clk",2795 .parent_data = &(const struct clk_parent_data){2796 .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",2797 },2798 .num_parents = 1,2799 .flags = CLK_SET_RATE_PARENT,2800 .ops = &clk_branch2_ops,2801 },2802 },2803};2804 2805static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {2806 .mult = 1,2807 .div = 2,2808 .hw.init = &(struct clk_init_data){2809 .name = "ufs_ice_core_postdiv_clk_src",2810 .parent_hws = (const struct clk_hw*[]){2811 &ufs_ice_core_clk_src.clkr.hw,2812 },2813 .num_parents = 1,2814 .flags = CLK_SET_RATE_PARENT,2815 .ops = &clk_fixed_factor_ops,2816 },2817};2818 2819static struct clk_branch gcc_ufs_unipro_core_clk = {2820 .halt_reg = 0x7600c,2821 .clkr = {2822 .enable_reg = 0x7600c,2823 .enable_mask = BIT(0),2824 .hw.init = &(struct clk_init_data){2825 .name = "gcc_ufs_unipro_core_clk",2826 .parent_hws = (const struct clk_hw*[]){2827 &ufs_ice_core_postdiv_clk_src.hw,2828 },2829 .num_parents = 1,2830 .flags = CLK_SET_RATE_PARENT,2831 .ops = &clk_branch2_ops,2832 },2833 },2834};2835 2836static struct clk_branch gcc_ufs_ice_core_clk = {2837 .halt_reg = 0x76010,2838 .clkr = {2839 .enable_reg = 0x76010,2840 .enable_mask = BIT(0),2841 .hw.init = &(struct clk_init_data){2842 .name = "gcc_ufs_ice_core_clk",2843 .parent_hws = (const struct clk_hw*[]){2844 &ufs_ice_core_clk_src.clkr.hw,2845 },2846 .num_parents = 1,2847 .flags = CLK_SET_RATE_PARENT,2848 .ops = &clk_branch2_ops,2849 },2850 },2851};2852 2853static struct clk_branch gcc_ufs_sys_clk_core_clk = {2854 .halt_check = BRANCH_HALT_DELAY,2855 .clkr = {2856 .enable_reg = 0x76030,2857 .enable_mask = BIT(0),2858 .hw.init = &(struct clk_init_data){2859 .name = "gcc_ufs_sys_clk_core_clk",2860 .ops = &clk_branch2_ops,2861 },2862 },2863};2864 2865static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {2866 .halt_check = BRANCH_HALT_DELAY,2867 .clkr = {2868 .enable_reg = 0x76034,2869 .enable_mask = BIT(0),2870 .hw.init = &(struct clk_init_data){2871 .name = "gcc_ufs_tx_symbol_clk_core_clk",2872 .ops = &clk_branch2_ops,2873 },2874 },2875};2876 2877static struct clk_branch gcc_aggre0_snoc_axi_clk = {2878 .halt_reg = 0x81008,2879 .clkr = {2880 .enable_reg = 0x81008,2881 .enable_mask = BIT(0),2882 .hw.init = &(struct clk_init_data){2883 .name = "gcc_aggre0_snoc_axi_clk",2884 .flags = CLK_IS_CRITICAL,2885 .ops = &clk_branch2_ops,2886 },2887 },2888};2889 2890static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {2891 .halt_reg = 0x8100c,2892 .clkr = {2893 .enable_reg = 0x8100c,2894 .enable_mask = BIT(0),2895 .hw.init = &(struct clk_init_data){2896 .name = "gcc_aggre0_cnoc_ahb_clk",2897 .flags = CLK_IS_CRITICAL,2898 .ops = &clk_branch2_ops,2899 },2900 },2901};2902 2903static struct clk_branch gcc_smmu_aggre0_axi_clk = {2904 .halt_reg = 0x81014,2905 .clkr = {2906 .enable_reg = 0x81014,2907 .enable_mask = BIT(0),2908 .hw.init = &(struct clk_init_data){2909 .name = "gcc_smmu_aggre0_axi_clk",2910 .flags = CLK_IS_CRITICAL,2911 .ops = &clk_branch2_ops,2912 },2913 },2914};2915 2916static struct clk_branch gcc_smmu_aggre0_ahb_clk = {2917 .halt_reg = 0x81018,2918 .clkr = {2919 .enable_reg = 0x81018,2920 .enable_mask = BIT(0),2921 .hw.init = &(struct clk_init_data){2922 .name = "gcc_smmu_aggre0_ahb_clk",2923 .flags = CLK_IS_CRITICAL,2924 .ops = &clk_branch2_ops,2925 },2926 },2927};2928 2929static struct clk_branch gcc_aggre2_ufs_axi_clk = {2930 .halt_reg = 0x83014,2931 .clkr = {2932 .enable_reg = 0x83014,2933 .enable_mask = BIT(0),2934 .hw.init = &(struct clk_init_data){2935 .name = "gcc_aggre2_ufs_axi_clk",2936 .parent_hws = (const struct clk_hw*[]){2937 &ufs_axi_clk_src.clkr.hw,2938 },2939 .num_parents = 1,2940 .flags = CLK_SET_RATE_PARENT,2941 .ops = &clk_branch2_ops,2942 },2943 },2944};2945 2946static struct clk_branch gcc_aggre2_usb3_axi_clk = {2947 .halt_reg = 0x83018,2948 .clkr = {2949 .enable_reg = 0x83018,2950 .enable_mask = BIT(0),2951 .hw.init = &(struct clk_init_data){2952 .name = "gcc_aggre2_usb3_axi_clk",2953 .parent_hws = (const struct clk_hw*[]){2954 &usb30_master_clk_src.clkr.hw,2955 },2956 .num_parents = 1,2957 .flags = CLK_SET_RATE_PARENT,2958 .ops = &clk_branch2_ops,2959 },2960 },2961};2962 2963static struct clk_branch gcc_dcc_ahb_clk = {2964 .halt_reg = 0x84004,2965 .clkr = {2966 .enable_reg = 0x84004,2967 .enable_mask = BIT(0),2968 .hw.init = &(struct clk_init_data){2969 .name = "gcc_dcc_ahb_clk",2970 .ops = &clk_branch2_ops,2971 },2972 },2973};2974 2975static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {2976 .halt_reg = 0x85000,2977 .clkr = {2978 .enable_reg = 0x85000,2979 .enable_mask = BIT(0),2980 .hw.init = &(struct clk_init_data){2981 .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",2982 .ops = &clk_branch2_ops,2983 },2984 },2985};2986 2987static struct clk_branch gcc_qspi_ahb_clk = {2988 .halt_reg = 0x8b004,2989 .clkr = {2990 .enable_reg = 0x8b004,2991 .enable_mask = BIT(0),2992 .hw.init = &(struct clk_init_data){2993 .name = "gcc_qspi_ahb_clk",2994 .ops = &clk_branch2_ops,2995 },2996 },2997};2998 2999static struct clk_branch gcc_qspi_ser_clk = {3000 .halt_reg = 0x8b008,3001 .clkr = {3002 .enable_reg = 0x8b008,3003 .enable_mask = BIT(0),3004 .hw.init = &(struct clk_init_data){3005 .name = "gcc_qspi_ser_clk",3006 .parent_hws = (const struct clk_hw*[]){3007 &qspi_ser_clk_src.clkr.hw,3008 },3009 .num_parents = 1,3010 .flags = CLK_SET_RATE_PARENT,3011 .ops = &clk_branch2_ops,3012 },3013 },3014};3015 3016static struct clk_branch gcc_usb3_clkref_clk = {3017 .halt_reg = 0x8800C,3018 .clkr = {3019 .enable_reg = 0x8800C,3020 .enable_mask = BIT(0),3021 .hw.init = &(struct clk_init_data){3022 .name = "gcc_usb3_clkref_clk",3023 .parent_data = &(const struct clk_parent_data){3024 .fw_name = "cxo2",3025 .name = "xo",3026 },3027 .num_parents = 1,3028 .ops = &clk_branch2_ops,3029 },3030 },3031};3032 3033static struct clk_branch gcc_hdmi_clkref_clk = {3034 .halt_reg = 0x88000,3035 .clkr = {3036 .enable_reg = 0x88000,3037 .enable_mask = BIT(0),3038 .hw.init = &(struct clk_init_data){3039 .name = "gcc_hdmi_clkref_clk",3040 .parent_data = &(const struct clk_parent_data){3041 .fw_name = "cxo2",3042 .name = "xo",3043 },3044 .num_parents = 1,3045 .ops = &clk_branch2_ops,3046 },3047 },3048};3049 3050static struct clk_branch gcc_edp_clkref_clk = {3051 .halt_reg = 0x88004,3052 .clkr = {3053 .enable_reg = 0x88004,3054 .enable_mask = BIT(0),3055 .hw.init = &(struct clk_init_data){3056 .name = "gcc_edp_clkref_clk",3057 .parent_data = &(const struct clk_parent_data){3058 .fw_name = "cxo2",3059 .name = "xo",3060 },3061 .num_parents = 1,3062 .ops = &clk_branch2_ops,3063 },3064 },3065};3066 3067static struct clk_branch gcc_ufs_clkref_clk = {3068 .halt_reg = 0x88008,3069 .clkr = {3070 .enable_reg = 0x88008,3071 .enable_mask = BIT(0),3072 .hw.init = &(struct clk_init_data){3073 .name = "gcc_ufs_clkref_clk",3074 .parent_data = &(const struct clk_parent_data){3075 .fw_name = "cxo2",3076 .name = "xo",3077 },3078 .num_parents = 1,3079 .ops = &clk_branch2_ops,3080 },3081 },3082};3083 3084static struct clk_branch gcc_pcie_clkref_clk = {3085 .halt_reg = 0x88010,3086 .clkr = {3087 .enable_reg = 0x88010,3088 .enable_mask = BIT(0),3089 .hw.init = &(struct clk_init_data){3090 .name = "gcc_pcie_clkref_clk",3091 .parent_data = &(const struct clk_parent_data){3092 .fw_name = "cxo2",3093 .name = "xo",3094 },3095 .num_parents = 1,3096 .ops = &clk_branch2_ops,3097 },3098 },3099};3100 3101static struct clk_branch gcc_rx2_usb2_clkref_clk = {3102 .halt_reg = 0x88014,3103 .clkr = {3104 .enable_reg = 0x88014,3105 .enable_mask = BIT(0),3106 .hw.init = &(struct clk_init_data){3107 .name = "gcc_rx2_usb2_clkref_clk",3108 .parent_data = &(const struct clk_parent_data){3109 .fw_name = "cxo2",3110 .name = "xo",3111 },3112 .num_parents = 1,3113 .ops = &clk_branch2_ops,3114 },3115 },3116};3117 3118static struct clk_branch gcc_rx1_usb2_clkref_clk = {3119 .halt_reg = 0x88018,3120 .clkr = {3121 .enable_reg = 0x88018,3122 .enable_mask = BIT(0),3123 .hw.init = &(struct clk_init_data){3124 .name = "gcc_rx1_usb2_clkref_clk",3125 .parent_data = &(const struct clk_parent_data){3126 .fw_name = "cxo2",3127 .name = "xo",3128 },3129 .num_parents = 1,3130 .ops = &clk_branch2_ops,3131 },3132 },3133};3134 3135static struct clk_branch gcc_mss_cfg_ahb_clk = {3136 .halt_reg = 0x8a000,3137 .clkr = {3138 .enable_reg = 0x8a000,3139 .enable_mask = BIT(0),3140 .hw.init = &(struct clk_init_data){3141 .name = "gcc_mss_cfg_ahb_clk",3142 .ops = &clk_branch2_ops,3143 },3144 },3145};3146 3147static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {3148 .halt_reg = 0x8a004,3149 .clkr = {3150 .enable_reg = 0x8a004,3151 .enable_mask = BIT(0),3152 .hw.init = &(struct clk_init_data){3153 .name = "gcc_mss_mnoc_bimc_axi_clk",3154 .ops = &clk_branch2_ops,3155 },3156 },3157};3158 3159static struct clk_branch gcc_mss_snoc_axi_clk = {3160 .halt_reg = 0x8a024,3161 .clkr = {3162 .enable_reg = 0x8a024,3163 .enable_mask = BIT(0),3164 .hw.init = &(struct clk_init_data){3165 .name = "gcc_mss_snoc_axi_clk",3166 .ops = &clk_branch2_ops,3167 },3168 },3169};3170 3171static struct clk_branch gcc_mss_q6_bimc_axi_clk = {3172 .halt_reg = 0x8a028,3173 .clkr = {3174 .enable_reg = 0x8a028,3175 .enable_mask = BIT(0),3176 .hw.init = &(struct clk_init_data){3177 .name = "gcc_mss_q6_bimc_axi_clk",3178 .ops = &clk_branch2_ops,3179 },3180 },3181};3182 3183static struct clk_hw *gcc_msm8996_hws[] = {3184 &xo.hw,3185 &gpll0_early_div.hw,3186 &ufs_tx_cfg_clk_src.hw,3187 &ufs_rx_cfg_clk_src.hw,3188 &ufs_ice_core_postdiv_clk_src.hw,3189};3190 3191static struct gdsc aggre0_noc_gdsc = {3192 .gdscr = 0x81004,3193 .gds_hw_ctrl = 0x81028,3194 .pd = {3195 .name = "aggre0_noc",3196 },3197 .pwrsts = PWRSTS_OFF_ON,3198 .flags = VOTABLE | ALWAYS_ON,3199};3200 3201static struct gdsc hlos1_vote_aggre0_noc_gdsc = {3202 .gdscr = 0x7d024,3203 .pd = {3204 .name = "hlos1_vote_aggre0_noc",3205 },3206 .pwrsts = PWRSTS_OFF_ON,3207 .flags = VOTABLE,3208};3209 3210static struct gdsc hlos1_vote_lpass_adsp_gdsc = {3211 .gdscr = 0x7d034,3212 .pd = {3213 .name = "hlos1_vote_lpass_adsp",3214 },3215 .pwrsts = PWRSTS_OFF_ON,3216 .flags = VOTABLE,3217};3218 3219static struct gdsc hlos1_vote_lpass_core_gdsc = {3220 .gdscr = 0x7d038,3221 .pd = {3222 .name = "hlos1_vote_lpass_core",3223 },3224 .pwrsts = PWRSTS_OFF_ON,3225 .flags = VOTABLE,3226};3227 3228static struct gdsc usb30_gdsc = {3229 .gdscr = 0xf004,3230 .pd = {3231 .name = "usb30",3232 },3233 /* TODO: Change to OFF_ON when USB drivers get proper suspend support */3234 .pwrsts = PWRSTS_RET_ON,3235};3236 3237static struct gdsc pcie0_gdsc = {3238 .gdscr = 0x6b004,3239 .pd = {3240 .name = "pcie0",3241 },3242 .pwrsts = PWRSTS_OFF_ON,3243};3244 3245static struct gdsc pcie1_gdsc = {3246 .gdscr = 0x6d004,3247 .pd = {3248 .name = "pcie1",3249 },3250 .pwrsts = PWRSTS_OFF_ON,3251};3252 3253static struct gdsc pcie2_gdsc = {3254 .gdscr = 0x6e004,3255 .pd = {3256 .name = "pcie2",3257 },3258 .pwrsts = PWRSTS_OFF_ON,3259};3260 3261static struct gdsc ufs_gdsc = {3262 .gdscr = 0x75004,3263 .pd = {3264 .name = "ufs",3265 },3266 .pwrsts = PWRSTS_OFF_ON,3267};3268 3269static struct clk_regmap *gcc_msm8996_clocks[] = {3270 [GPLL0_EARLY] = &gpll0_early.clkr,3271 [GPLL0] = &gpll0.clkr,3272 [GPLL4_EARLY] = &gpll4_early.clkr,3273 [GPLL4] = &gpll4.clkr,3274 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,3275 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,3276 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,3277 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,3278 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,3279 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,3280 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,3281 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,3282 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,3283 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,3284 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,3285 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,3286 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,3287 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,3288 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,3289 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,3290 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,3291 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,3292 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,3293 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,3294 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,3295 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,3296 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,3297 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,3298 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,3299 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,3300 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,3301 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,3302 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,3303 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,3304 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,3305 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,3306 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,3307 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,3308 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,3309 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,3310 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,3311 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,3312 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,3313 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,3314 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,3315 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,3316 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,3317 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,3318 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,3319 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,3320 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,3321 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,3322 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,3323 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,3324 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,3325 [GP1_CLK_SRC] = &gp1_clk_src.clkr,3326 [GP2_CLK_SRC] = &gp2_clk_src.clkr,3327 [GP3_CLK_SRC] = &gp3_clk_src.clkr,3328 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,3329 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,3330 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,3331 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,3332 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,3333 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,3334 [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,3335 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,3336 [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,3337 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,3338 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,3339 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,3340 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,3341 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,3342 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,3343 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,3344 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,3345 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,3346 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,3347 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,3348 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,3349 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,3350 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,3351 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,3352 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,3353 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,3354 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,3355 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,3356 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,3357 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,3358 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,3359 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,3360 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,3361 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,3362 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,3363 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,3364 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,3365 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,3366 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,3367 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,3368 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,3369 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,3370 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,3371 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,3372 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,3373 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,3374 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,3375 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,3376 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,3377 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,3378 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,3379 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,3380 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,3381 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,3382 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,3383 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,3384 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,3385 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,3386 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,3387 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,3388 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,3389 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,3390 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,3391 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,3392 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,3393 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,3394 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,3395 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,3396 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,3397 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,3398 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,3399 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,3400 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,3401 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,3402 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,3403 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,3404 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,3405 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,3406 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,3407 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,3408 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,3409 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,3410 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,3411 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,3412 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,3413 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,3414 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,3415 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,3416 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,3417 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,3418 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,3419 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,3420 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,3421 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,3422 [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,3423 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,3424 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,3425 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,3426 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,3427 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,3428 [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,3429 [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,3430 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,3431 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,3432 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,3433 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,3434 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,3435 [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,3436 [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,3437 [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,3438 [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,3439 [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,3440 [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,3441 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,3442 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,3443 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,3444 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,3445 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,3446 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,3447 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,3448 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,3449 [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,3450 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,3451 [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,3452 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,3453 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,3454 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,3455 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,3456 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,3457 [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,3458 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,3459 [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,3460};3461 3462static struct gdsc *gcc_msm8996_gdscs[] = {3463 [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,3464 [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,3465 [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,3466 [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,3467 [USB30_GDSC] = &usb30_gdsc,3468 [PCIE0_GDSC] = &pcie0_gdsc,3469 [PCIE1_GDSC] = &pcie1_gdsc,3470 [PCIE2_GDSC] = &pcie2_gdsc,3471 [UFS_GDSC] = &ufs_gdsc,3472};3473 3474static const struct qcom_reset_map gcc_msm8996_resets[] = {3475 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },3476 [GCC_CONFIG_NOC_BCR] = { 0x5000 },3477 [GCC_PERIPH_NOC_BCR] = { 0x6000 },3478 [GCC_IMEM_BCR] = { 0x8000 },3479 [GCC_MMSS_BCR] = { 0x9000 },3480 [GCC_PIMEM_BCR] = { 0x0a000 },3481 [GCC_QDSS_BCR] = { 0x0c000 },3482 [GCC_USB_30_BCR] = { 0x0f000 },3483 [GCC_USB_20_BCR] = { 0x12000 },3484 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },3485 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },3486 [GCC_USB3_PHY_BCR] = { 0x50020 },3487 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },3488 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },3489 [GCC_SDCC1_BCR] = { 0x13000 },3490 [GCC_SDCC2_BCR] = { 0x14000 },3491 [GCC_SDCC3_BCR] = { 0x15000 },3492 [GCC_SDCC4_BCR] = { 0x16000 },3493 [GCC_BLSP1_BCR] = { 0x17000 },3494 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },3495 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },3496 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },3497 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },3498 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },3499 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },3500 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },3501 [GCC_BLSP1_UART4_BCR] = { 0x20000 },3502 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },3503 [GCC_BLSP1_UART5_BCR] = { 0x22000 },3504 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },3505 [GCC_BLSP1_UART6_BCR] = { 0x24000 },3506 [GCC_BLSP2_BCR] = { 0x25000 },3507 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },3508 [GCC_BLSP2_UART1_BCR] = { 0x27000 },3509 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },3510 [GCC_BLSP2_UART2_BCR] = { 0x29000 },3511 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },3512 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },3513 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },3514 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },3515 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },3516 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },3517 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },3518 [GCC_BLSP2_UART6_BCR] = { 0x31000 },3519 [GCC_PDM_BCR] = { 0x33000 },3520 [GCC_PRNG_BCR] = { 0x34000 },3521 [GCC_TSIF_BCR] = { 0x36000 },3522 [GCC_TCSR_BCR] = { 0x37000 },3523 [GCC_BOOT_ROM_BCR] = { 0x38000 },3524 [GCC_MSG_RAM_BCR] = { 0x39000 },3525 [GCC_TLMM_BCR] = { 0x3a000 },3526 [GCC_MPM_BCR] = { 0x3b000 },3527 [GCC_SEC_CTRL_BCR] = { 0x3d000 },3528 [GCC_SPMI_BCR] = { 0x3f000 },3529 [GCC_SPDM_BCR] = { 0x40000 },3530 [GCC_CE1_BCR] = { 0x41000 },3531 [GCC_BIMC_BCR] = { 0x44000 },3532 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },3533 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },3534 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },3535 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },3536 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },3537 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },3538 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },3539 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },3540 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },3541 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },3542 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },3543 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },3544 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },3545 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },3546 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },3547 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },3548 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },3549 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },3550 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },3551 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },3552 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },3553 [GCC_APB2JTAG_BCR] = { 0x4c000 },3554 [GCC_RBCPR_CX_BCR] = { 0x4e000 },3555 [GCC_RBCPR_MX_BCR] = { 0x4f000 },3556 [GCC_PCIE_0_BCR] = { 0x6b000 },3557 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },3558 [GCC_PCIE_1_BCR] = { 0x6d000 },3559 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },3560 [GCC_PCIE_2_BCR] = { 0x6e000 },3561 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },3562 [GCC_PCIE_PHY_BCR] = { 0x6f000 },3563 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },3564 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },3565 [GCC_DCD_BCR] = { 0x70000 },3566 [GCC_OBT_ODT_BCR] = { 0x73000 },3567 [GCC_UFS_BCR] = { 0x75000 },3568 [GCC_SSC_BCR] = { 0x63000 },3569 [GCC_VS_BCR] = { 0x7a000 },3570 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },3571 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },3572 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },3573 [GCC_DCC_BCR] = { 0x84000 },3574 [GCC_IPA_BCR] = { 0x89000 },3575 [GCC_QSPI_BCR] = { 0x8b000 },3576 [GCC_SKL_BCR] = { 0x8c000 },3577 [GCC_MSMPU_BCR] = { 0x8d000 },3578 [GCC_MSS_Q6_BCR] = { 0x8e000 },3579 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },3580 [GCC_MSS_RESTART] = { 0x8f008 },3581};3582 3583static const struct regmap_config gcc_msm8996_regmap_config = {3584 .reg_bits = 32,3585 .reg_stride = 4,3586 .val_bits = 32,3587 .max_register = 0x8f010,3588 .fast_io = true,3589};3590 3591static const struct qcom_cc_desc gcc_msm8996_desc = {3592 .config = &gcc_msm8996_regmap_config,3593 .clks = gcc_msm8996_clocks,3594 .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),3595 .resets = gcc_msm8996_resets,3596 .num_resets = ARRAY_SIZE(gcc_msm8996_resets),3597 .gdscs = gcc_msm8996_gdscs,3598 .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),3599 .clk_hws = gcc_msm8996_hws,3600 .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),3601};3602 3603static const struct of_device_id gcc_msm8996_match_table[] = {3604 { .compatible = "qcom,gcc-msm8996" },3605 { }3606};3607MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);3608 3609static int gcc_msm8996_probe(struct platform_device *pdev)3610{3611 struct regmap *regmap;3612 3613 regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);3614 if (IS_ERR(regmap))3615 return PTR_ERR(regmap);3616 3617 /*3618 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be3619 * turned off by hardware during certain apps low power modes.3620 */3621 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));3622 3623 return qcom_cc_really_probe(&pdev->dev, &gcc_msm8996_desc, regmap);3624}3625 3626static struct platform_driver gcc_msm8996_driver = {3627 .probe = gcc_msm8996_probe,3628 .driver = {3629 .name = "gcc-msm8996",3630 .of_match_table = gcc_msm8996_match_table,3631 },3632};3633 3634static int __init gcc_msm8996_init(void)3635{3636 return platform_driver_register(&gcc_msm8996_driver);3637}3638core_initcall(gcc_msm8996_init);3639 3640static void __exit gcc_msm8996_exit(void)3641{3642 platform_driver_unregister(&gcc_msm8996_driver);3643}3644module_exit(gcc_msm8996_exit);3645 3646MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");3647MODULE_LICENSE("GPL v2");3648MODULE_ALIAS("platform:gcc-msm8996");3649