3389 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.4 */5 6#include <linux/kernel.h>7#include <linux/bitops.h>8#include <linux/err.h>9#include <linux/platform_device.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/clk-provider.h>13#include <linux/regmap.h>14#include <linux/reset-controller.h>15 16#include <dt-bindings/clock/qcom,gcc-msm8998.h>17 18#include "common.h"19#include "clk-regmap.h"20#include "clk-alpha-pll.h"21#include "clk-pll.h"22#include "clk-rcg.h"23#include "clk-branch.h"24#include "reset.h"25#include "gdsc.h"26 27#define GCC_MMSS_MISC 0x0902C28#define GCC_GPU_MISC 0x7102829 30static const struct pll_vco fabia_vco[] = {31 { 250000000, 2000000000, 0 },32 { 125000000, 1000000000, 1 },33};34 35static struct clk_alpha_pll gpll0 = {36 .offset = 0x0,37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],38 .vco_table = fabia_vco,39 .num_vco = ARRAY_SIZE(fabia_vco),40 .clkr = {41 .enable_reg = 0x52000,42 .enable_mask = BIT(0),43 .hw.init = &(struct clk_init_data){44 .name = "gpll0",45 .parent_data = (const struct clk_parent_data []) {46 { .fw_name = "xo" },47 },48 .num_parents = 1,49 .ops = &clk_alpha_pll_fixed_fabia_ops,50 }51 },52};53 54static struct clk_alpha_pll_postdiv gpll0_out_even = {55 .offset = 0x0,56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],57 .clkr.hw.init = &(struct clk_init_data){58 .name = "gpll0_out_even",59 .parent_hws = (const struct clk_hw*[]) {60 &gpll0.clkr.hw,61 },62 .num_parents = 1,63 .ops = &clk_alpha_pll_postdiv_fabia_ops,64 },65};66 67static struct clk_alpha_pll_postdiv gpll0_out_main = {68 .offset = 0x0,69 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],70 .clkr.hw.init = &(struct clk_init_data){71 .name = "gpll0_out_main",72 .parent_hws = (const struct clk_hw*[]) {73 &gpll0.clkr.hw,74 },75 .num_parents = 1,76 .ops = &clk_alpha_pll_postdiv_fabia_ops,77 },78};79 80static struct clk_alpha_pll_postdiv gpll0_out_odd = {81 .offset = 0x0,82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],83 .clkr.hw.init = &(struct clk_init_data){84 .name = "gpll0_out_odd",85 .parent_hws = (const struct clk_hw*[]) {86 &gpll0.clkr.hw,87 },88 .num_parents = 1,89 .ops = &clk_alpha_pll_postdiv_fabia_ops,90 },91};92 93static struct clk_alpha_pll_postdiv gpll0_out_test = {94 .offset = 0x0,95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],96 .clkr.hw.init = &(struct clk_init_data){97 .name = "gpll0_out_test",98 .parent_hws = (const struct clk_hw*[]) {99 &gpll0.clkr.hw,100 },101 .num_parents = 1,102 .ops = &clk_alpha_pll_postdiv_fabia_ops,103 },104};105 106static struct clk_alpha_pll gpll1 = {107 .offset = 0x1000,108 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],109 .vco_table = fabia_vco,110 .num_vco = ARRAY_SIZE(fabia_vco),111 .clkr = {112 .enable_reg = 0x52000,113 .enable_mask = BIT(1),114 .hw.init = &(struct clk_init_data){115 .name = "gpll1",116 .parent_data = (const struct clk_parent_data []) {117 { .fw_name = "xo" },118 },119 .num_parents = 1,120 .ops = &clk_alpha_pll_fixed_fabia_ops,121 }122 },123};124 125static struct clk_alpha_pll_postdiv gpll1_out_even = {126 .offset = 0x1000,127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],128 .clkr.hw.init = &(struct clk_init_data){129 .name = "gpll1_out_even",130 .parent_hws = (const struct clk_hw*[]) {131 &gpll1.clkr.hw,132 },133 .num_parents = 1,134 .ops = &clk_alpha_pll_postdiv_fabia_ops,135 },136};137 138static struct clk_alpha_pll_postdiv gpll1_out_main = {139 .offset = 0x1000,140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],141 .clkr.hw.init = &(struct clk_init_data){142 .name = "gpll1_out_main",143 .parent_hws = (const struct clk_hw*[]) {144 &gpll1.clkr.hw,145 },146 .num_parents = 1,147 .ops = &clk_alpha_pll_postdiv_fabia_ops,148 },149};150 151static struct clk_alpha_pll_postdiv gpll1_out_odd = {152 .offset = 0x1000,153 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],154 .clkr.hw.init = &(struct clk_init_data){155 .name = "gpll1_out_odd",156 .parent_hws = (const struct clk_hw*[]) {157 &gpll1.clkr.hw,158 },159 .num_parents = 1,160 .ops = &clk_alpha_pll_postdiv_fabia_ops,161 },162};163 164static struct clk_alpha_pll_postdiv gpll1_out_test = {165 .offset = 0x1000,166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],167 .clkr.hw.init = &(struct clk_init_data){168 .name = "gpll1_out_test",169 .parent_hws = (const struct clk_hw*[]) {170 &gpll1.clkr.hw,171 },172 .num_parents = 1,173 .ops = &clk_alpha_pll_postdiv_fabia_ops,174 },175};176 177static struct clk_alpha_pll gpll2 = {178 .offset = 0x2000,179 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],180 .vco_table = fabia_vco,181 .num_vco = ARRAY_SIZE(fabia_vco),182 .clkr = {183 .enable_reg = 0x52000,184 .enable_mask = BIT(2),185 .hw.init = &(struct clk_init_data){186 .name = "gpll2",187 .parent_data = (const struct clk_parent_data []) {188 { .fw_name = "xo" },189 },190 .num_parents = 1,191 .ops = &clk_alpha_pll_fixed_fabia_ops,192 }193 },194};195 196static struct clk_alpha_pll_postdiv gpll2_out_even = {197 .offset = 0x2000,198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],199 .clkr.hw.init = &(struct clk_init_data){200 .name = "gpll2_out_even",201 .parent_hws = (const struct clk_hw*[]) {202 &gpll2.clkr.hw,203 },204 .num_parents = 1,205 .ops = &clk_alpha_pll_postdiv_fabia_ops,206 },207};208 209static struct clk_alpha_pll_postdiv gpll2_out_main = {210 .offset = 0x2000,211 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],212 .clkr.hw.init = &(struct clk_init_data){213 .name = "gpll2_out_main",214 .parent_hws = (const struct clk_hw*[]) {215 &gpll2.clkr.hw,216 },217 .num_parents = 1,218 .ops = &clk_alpha_pll_postdiv_fabia_ops,219 },220};221 222static struct clk_alpha_pll_postdiv gpll2_out_odd = {223 .offset = 0x2000,224 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],225 .clkr.hw.init = &(struct clk_init_data){226 .name = "gpll2_out_odd",227 .parent_hws = (const struct clk_hw*[]) {228 &gpll2.clkr.hw,229 },230 .num_parents = 1,231 .ops = &clk_alpha_pll_postdiv_fabia_ops,232 },233};234 235static struct clk_alpha_pll_postdiv gpll2_out_test = {236 .offset = 0x2000,237 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],238 .clkr.hw.init = &(struct clk_init_data){239 .name = "gpll2_out_test",240 .parent_hws = (const struct clk_hw*[]) {241 &gpll2.clkr.hw,242 },243 .num_parents = 1,244 .ops = &clk_alpha_pll_postdiv_fabia_ops,245 },246};247 248static struct clk_alpha_pll gpll3 = {249 .offset = 0x3000,250 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],251 .vco_table = fabia_vco,252 .num_vco = ARRAY_SIZE(fabia_vco),253 .clkr = {254 .enable_reg = 0x52000,255 .enable_mask = BIT(3),256 .hw.init = &(struct clk_init_data){257 .name = "gpll3",258 .parent_data = (const struct clk_parent_data []) {259 { .fw_name = "xo" },260 },261 .num_parents = 1,262 .ops = &clk_alpha_pll_fixed_fabia_ops,263 }264 },265};266 267static struct clk_alpha_pll_postdiv gpll3_out_even = {268 .offset = 0x3000,269 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],270 .clkr.hw.init = &(struct clk_init_data){271 .name = "gpll3_out_even",272 .parent_hws = (const struct clk_hw*[]) {273 &gpll3.clkr.hw,274 },275 .num_parents = 1,276 .ops = &clk_alpha_pll_postdiv_fabia_ops,277 },278};279 280static struct clk_alpha_pll_postdiv gpll3_out_main = {281 .offset = 0x3000,282 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],283 .clkr.hw.init = &(struct clk_init_data){284 .name = "gpll3_out_main",285 .parent_hws = (const struct clk_hw*[]) {286 &gpll3.clkr.hw,287 },288 .num_parents = 1,289 .ops = &clk_alpha_pll_postdiv_fabia_ops,290 },291};292 293static struct clk_alpha_pll_postdiv gpll3_out_odd = {294 .offset = 0x3000,295 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],296 .clkr.hw.init = &(struct clk_init_data){297 .name = "gpll3_out_odd",298 .parent_hws = (const struct clk_hw*[]) {299 &gpll3.clkr.hw,300 },301 .num_parents = 1,302 .ops = &clk_alpha_pll_postdiv_fabia_ops,303 },304};305 306static struct clk_alpha_pll_postdiv gpll3_out_test = {307 .offset = 0x3000,308 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],309 .clkr.hw.init = &(struct clk_init_data){310 .name = "gpll3_out_test",311 .parent_hws = (const struct clk_hw*[]) {312 &gpll3.clkr.hw,313 },314 .num_parents = 1,315 .ops = &clk_alpha_pll_postdiv_fabia_ops,316 },317};318 319static struct clk_alpha_pll gpll4 = {320 .offset = 0x77000,321 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],322 .vco_table = fabia_vco,323 .num_vco = ARRAY_SIZE(fabia_vco),324 .clkr = {325 .enable_reg = 0x52000,326 .enable_mask = BIT(4),327 .hw.init = &(struct clk_init_data){328 .name = "gpll4",329 .parent_data = (const struct clk_parent_data []) {330 { .fw_name = "xo" },331 },332 .num_parents = 1,333 .ops = &clk_alpha_pll_fixed_fabia_ops,334 }335 },336};337 338static struct clk_alpha_pll_postdiv gpll4_out_even = {339 .offset = 0x77000,340 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],341 .clkr.hw.init = &(struct clk_init_data){342 .name = "gpll4_out_even",343 .parent_hws = (const struct clk_hw*[]) {344 &gpll4.clkr.hw,345 },346 .num_parents = 1,347 .ops = &clk_alpha_pll_postdiv_fabia_ops,348 },349};350 351static struct clk_alpha_pll_postdiv gpll4_out_main = {352 .offset = 0x77000,353 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],354 .clkr.hw.init = &(struct clk_init_data){355 .name = "gpll4_out_main",356 .parent_hws = (const struct clk_hw*[]) {357 &gpll4.clkr.hw,358 },359 .num_parents = 1,360 .ops = &clk_alpha_pll_postdiv_fabia_ops,361 },362};363 364static struct clk_alpha_pll_postdiv gpll4_out_odd = {365 .offset = 0x77000,366 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],367 .clkr.hw.init = &(struct clk_init_data){368 .name = "gpll4_out_odd",369 .parent_hws = (const struct clk_hw*[]) {370 &gpll4.clkr.hw,371 },372 .num_parents = 1,373 .ops = &clk_alpha_pll_postdiv_fabia_ops,374 },375};376 377static struct clk_alpha_pll_postdiv gpll4_out_test = {378 .offset = 0x77000,379 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],380 .clkr.hw.init = &(struct clk_init_data){381 .name = "gpll4_out_test",382 .parent_hws = (const struct clk_hw*[]) {383 &gpll4.clkr.hw,384 },385 .num_parents = 1,386 .ops = &clk_alpha_pll_postdiv_fabia_ops,387 },388};389 390enum {391 P_AUD_REF_CLK,392 P_GPLL0_OUT_MAIN,393 P_GPLL4_OUT_MAIN,394 P_PLL0_EARLY_DIV_CLK_SRC,395 P_SLEEP_CLK,396 P_XO,397};398 399static const struct parent_map gcc_parent_map_0[] = {400 { P_XO, 0 },401 { P_GPLL0_OUT_MAIN, 1 },402 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },403};404 405static const struct clk_parent_data gcc_parent_data_0[] = {406 { .fw_name = "xo" },407 { .hw = &gpll0_out_main.clkr.hw },408 { .hw = &gpll0_out_main.clkr.hw },409};410 411static const struct parent_map gcc_parent_map_1[] = {412 { P_XO, 0 },413 { P_GPLL0_OUT_MAIN, 1 },414};415 416static const struct clk_parent_data gcc_parent_data_1[] = {417 { .fw_name = "xo" },418 { .hw = &gpll0_out_main.clkr.hw },419};420 421static const struct parent_map gcc_parent_map_2[] = {422 { P_XO, 0 },423 { P_GPLL0_OUT_MAIN, 1 },424 { P_SLEEP_CLK, 5 },425 { P_PLL0_EARLY_DIV_CLK_SRC, 6 },426};427 428static const struct clk_parent_data gcc_parent_data_2[] = {429 { .fw_name = "xo" },430 { .hw = &gpll0_out_main.clkr.hw },431 { .fw_name = "sleep_clk" },432 { .hw = &gpll0_out_main.clkr.hw },433};434 435static const struct parent_map gcc_parent_map_3[] = {436 { P_XO, 0 },437 { P_SLEEP_CLK, 5 },438};439 440static const struct clk_parent_data gcc_parent_data_3[] = {441 { .fw_name = "xo" },442 { .fw_name = "sleep_clk" },443};444 445static const struct parent_map gcc_parent_map_4[] = {446 { P_XO, 0 },447 { P_GPLL0_OUT_MAIN, 1 },448 { P_GPLL4_OUT_MAIN, 5 },449};450 451static const struct clk_parent_data gcc_parent_data_4[] = {452 { .fw_name = "xo" },453 { .hw = &gpll0_out_main.clkr.hw },454 { .hw = &gpll4_out_main.clkr.hw },455};456 457static const struct parent_map gcc_parent_map_5[] = {458 { P_XO, 0 },459 { P_GPLL0_OUT_MAIN, 1 },460 { P_AUD_REF_CLK, 2 },461};462 463static const struct clk_parent_data gcc_parent_data_5[] = {464 { .fw_name = "xo" },465 { .hw = &gpll0_out_main.clkr.hw },466 { .fw_name = "aud_ref_clk" },467};468 469static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {470 F(19200000, P_XO, 1, 0, 0),471 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),472 { }473};474 475static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {476 .cmd_rcgr = 0x19020,477 .mnd_width = 0,478 .hid_width = 5,479 .parent_map = gcc_parent_map_1,480 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,481 .clkr.hw.init = &(struct clk_init_data){482 .name = "blsp1_qup1_i2c_apps_clk_src",483 .parent_data = gcc_parent_data_1,484 .num_parents = ARRAY_SIZE(gcc_parent_data_1),485 .ops = &clk_rcg2_ops,486 },487};488 489static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {490 F(960000, P_XO, 10, 1, 2),491 F(4800000, P_XO, 4, 0, 0),492 F(9600000, P_XO, 2, 0, 0),493 F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),494 F(19200000, P_XO, 1, 0, 0),495 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),496 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),497 { }498};499 500static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {501 .cmd_rcgr = 0x1900c,502 .mnd_width = 8,503 .hid_width = 5,504 .parent_map = gcc_parent_map_0,505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,506 .clkr.hw.init = &(struct clk_init_data){507 .name = "blsp1_qup1_spi_apps_clk_src",508 .parent_data = gcc_parent_data_0,509 .num_parents = ARRAY_SIZE(gcc_parent_data_0),510 .ops = &clk_rcg2_ops,511 },512};513 514static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {515 .cmd_rcgr = 0x1b020,516 .mnd_width = 0,517 .hid_width = 5,518 .parent_map = gcc_parent_map_1,519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,520 .clkr.hw.init = &(struct clk_init_data){521 .name = "blsp1_qup2_i2c_apps_clk_src",522 .parent_data = gcc_parent_data_1,523 .num_parents = ARRAY_SIZE(gcc_parent_data_1),524 .ops = &clk_rcg2_ops,525 },526};527 528static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {529 .cmd_rcgr = 0x1b00c,530 .mnd_width = 8,531 .hid_width = 5,532 .parent_map = gcc_parent_map_0,533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,534 .clkr.hw.init = &(struct clk_init_data){535 .name = "blsp1_qup2_spi_apps_clk_src",536 .parent_data = gcc_parent_data_0,537 .num_parents = ARRAY_SIZE(gcc_parent_data_0),538 .ops = &clk_rcg2_ops,539 },540};541 542static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {543 .cmd_rcgr = 0x1d020,544 .mnd_width = 0,545 .hid_width = 5,546 .parent_map = gcc_parent_map_1,547 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,548 .clkr.hw.init = &(struct clk_init_data){549 .name = "blsp1_qup3_i2c_apps_clk_src",550 .parent_data = gcc_parent_data_1,551 .num_parents = ARRAY_SIZE(gcc_parent_data_1),552 .ops = &clk_rcg2_ops,553 },554};555 556static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {557 .cmd_rcgr = 0x1d00c,558 .mnd_width = 8,559 .hid_width = 5,560 .parent_map = gcc_parent_map_0,561 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,562 .clkr.hw.init = &(struct clk_init_data){563 .name = "blsp1_qup3_spi_apps_clk_src",564 .parent_data = gcc_parent_data_0,565 .num_parents = ARRAY_SIZE(gcc_parent_data_0),566 .ops = &clk_rcg2_ops,567 },568};569 570static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {571 .cmd_rcgr = 0x1f020,572 .mnd_width = 0,573 .hid_width = 5,574 .parent_map = gcc_parent_map_1,575 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,576 .clkr.hw.init = &(struct clk_init_data){577 .name = "blsp1_qup4_i2c_apps_clk_src",578 .parent_data = gcc_parent_data_1,579 .num_parents = ARRAY_SIZE(gcc_parent_data_1),580 .ops = &clk_rcg2_ops,581 },582};583 584static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {585 .cmd_rcgr = 0x1f00c,586 .mnd_width = 8,587 .hid_width = 5,588 .parent_map = gcc_parent_map_0,589 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,590 .clkr.hw.init = &(struct clk_init_data){591 .name = "blsp1_qup4_spi_apps_clk_src",592 .parent_data = gcc_parent_data_0,593 .num_parents = ARRAY_SIZE(gcc_parent_data_0),594 .ops = &clk_rcg2_ops,595 },596};597 598static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {599 .cmd_rcgr = 0x21020,600 .mnd_width = 0,601 .hid_width = 5,602 .parent_map = gcc_parent_map_1,603 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,604 .clkr.hw.init = &(struct clk_init_data){605 .name = "blsp1_qup5_i2c_apps_clk_src",606 .parent_data = gcc_parent_data_1,607 .num_parents = ARRAY_SIZE(gcc_parent_data_1),608 .ops = &clk_rcg2_ops,609 },610};611 612static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {613 .cmd_rcgr = 0x2100c,614 .mnd_width = 8,615 .hid_width = 5,616 .parent_map = gcc_parent_map_0,617 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,618 .clkr.hw.init = &(struct clk_init_data){619 .name = "blsp1_qup5_spi_apps_clk_src",620 .parent_data = gcc_parent_data_0,621 .num_parents = ARRAY_SIZE(gcc_parent_data_0),622 .ops = &clk_rcg2_ops,623 },624};625 626static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {627 .cmd_rcgr = 0x23020,628 .mnd_width = 0,629 .hid_width = 5,630 .parent_map = gcc_parent_map_1,631 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,632 .clkr.hw.init = &(struct clk_init_data){633 .name = "blsp1_qup6_i2c_apps_clk_src",634 .parent_data = gcc_parent_data_1,635 .num_parents = ARRAY_SIZE(gcc_parent_data_1),636 .ops = &clk_rcg2_ops,637 },638};639 640static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {641 .cmd_rcgr = 0x2300c,642 .mnd_width = 8,643 .hid_width = 5,644 .parent_map = gcc_parent_map_0,645 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,646 .clkr.hw.init = &(struct clk_init_data){647 .name = "blsp1_qup6_spi_apps_clk_src",648 .parent_data = gcc_parent_data_0,649 .num_parents = ARRAY_SIZE(gcc_parent_data_0),650 .ops = &clk_rcg2_ops,651 },652};653 654static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {655 F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),656 F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),657 F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),658 F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),659 F(19200000, P_XO, 1, 0, 0),660 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),661 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),662 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),663 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),664 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),665 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),666 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),667 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),668 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),669 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),670 { }671};672 673static struct clk_rcg2 blsp1_uart1_apps_clk_src = {674 .cmd_rcgr = 0x1a00c,675 .mnd_width = 16,676 .hid_width = 5,677 .parent_map = gcc_parent_map_0,678 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,679 .clkr.hw.init = &(struct clk_init_data){680 .name = "blsp1_uart1_apps_clk_src",681 .parent_data = gcc_parent_data_0,682 .num_parents = ARRAY_SIZE(gcc_parent_data_0),683 .ops = &clk_rcg2_ops,684 },685};686 687static struct clk_rcg2 blsp1_uart2_apps_clk_src = {688 .cmd_rcgr = 0x1c00c,689 .mnd_width = 16,690 .hid_width = 5,691 .parent_map = gcc_parent_map_0,692 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,693 .clkr.hw.init = &(struct clk_init_data){694 .name = "blsp1_uart2_apps_clk_src",695 .parent_data = gcc_parent_data_0,696 .num_parents = ARRAY_SIZE(gcc_parent_data_0),697 .ops = &clk_rcg2_ops,698 },699};700 701static struct clk_rcg2 blsp1_uart3_apps_clk_src = {702 .cmd_rcgr = 0x1e00c,703 .mnd_width = 16,704 .hid_width = 5,705 .parent_map = gcc_parent_map_0,706 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,707 .clkr.hw.init = &(struct clk_init_data){708 .name = "blsp1_uart3_apps_clk_src",709 .parent_data = gcc_parent_data_0,710 .num_parents = ARRAY_SIZE(gcc_parent_data_0),711 .ops = &clk_rcg2_ops,712 },713};714 715static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {716 .cmd_rcgr = 0x26020,717 .mnd_width = 0,718 .hid_width = 5,719 .parent_map = gcc_parent_map_1,720 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,721 .clkr.hw.init = &(struct clk_init_data){722 .name = "blsp2_qup1_i2c_apps_clk_src",723 .parent_data = gcc_parent_data_1,724 .num_parents = ARRAY_SIZE(gcc_parent_data_1),725 .ops = &clk_rcg2_ops,726 },727};728 729static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {730 .cmd_rcgr = 0x2600c,731 .mnd_width = 8,732 .hid_width = 5,733 .parent_map = gcc_parent_map_0,734 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,735 .clkr.hw.init = &(struct clk_init_data){736 .name = "blsp2_qup1_spi_apps_clk_src",737 .parent_data = gcc_parent_data_0,738 .num_parents = ARRAY_SIZE(gcc_parent_data_0),739 .ops = &clk_rcg2_ops,740 },741};742 743static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {744 .cmd_rcgr = 0x28020,745 .mnd_width = 0,746 .hid_width = 5,747 .parent_map = gcc_parent_map_1,748 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,749 .clkr.hw.init = &(struct clk_init_data){750 .name = "blsp2_qup2_i2c_apps_clk_src",751 .parent_data = gcc_parent_data_1,752 .num_parents = ARRAY_SIZE(gcc_parent_data_1),753 .ops = &clk_rcg2_ops,754 },755};756 757static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {758 .cmd_rcgr = 0x2800c,759 .mnd_width = 8,760 .hid_width = 5,761 .parent_map = gcc_parent_map_0,762 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,763 .clkr.hw.init = &(struct clk_init_data){764 .name = "blsp2_qup2_spi_apps_clk_src",765 .parent_data = gcc_parent_data_0,766 .num_parents = ARRAY_SIZE(gcc_parent_data_0),767 .ops = &clk_rcg2_ops,768 },769};770 771static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {772 .cmd_rcgr = 0x2a020,773 .mnd_width = 0,774 .hid_width = 5,775 .parent_map = gcc_parent_map_1,776 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,777 .clkr.hw.init = &(struct clk_init_data){778 .name = "blsp2_qup3_i2c_apps_clk_src",779 .parent_data = gcc_parent_data_1,780 .num_parents = ARRAY_SIZE(gcc_parent_data_1),781 .ops = &clk_rcg2_ops,782 },783};784 785static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {786 .cmd_rcgr = 0x2a00c,787 .mnd_width = 8,788 .hid_width = 5,789 .parent_map = gcc_parent_map_0,790 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,791 .clkr.hw.init = &(struct clk_init_data){792 .name = "blsp2_qup3_spi_apps_clk_src",793 .parent_data = gcc_parent_data_0,794 .num_parents = ARRAY_SIZE(gcc_parent_data_0),795 .ops = &clk_rcg2_ops,796 },797};798 799static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {800 .cmd_rcgr = 0x2c020,801 .mnd_width = 0,802 .hid_width = 5,803 .parent_map = gcc_parent_map_1,804 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,805 .clkr.hw.init = &(struct clk_init_data){806 .name = "blsp2_qup4_i2c_apps_clk_src",807 .parent_data = gcc_parent_data_1,808 .num_parents = ARRAY_SIZE(gcc_parent_data_1),809 .ops = &clk_rcg2_ops,810 },811};812 813static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {814 .cmd_rcgr = 0x2c00c,815 .mnd_width = 8,816 .hid_width = 5,817 .parent_map = gcc_parent_map_0,818 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,819 .clkr.hw.init = &(struct clk_init_data){820 .name = "blsp2_qup4_spi_apps_clk_src",821 .parent_data = gcc_parent_data_0,822 .num_parents = ARRAY_SIZE(gcc_parent_data_0),823 .ops = &clk_rcg2_ops,824 },825};826 827static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {828 .cmd_rcgr = 0x2e020,829 .mnd_width = 0,830 .hid_width = 5,831 .parent_map = gcc_parent_map_1,832 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,833 .clkr.hw.init = &(struct clk_init_data){834 .name = "blsp2_qup5_i2c_apps_clk_src",835 .parent_data = gcc_parent_data_1,836 .num_parents = ARRAY_SIZE(gcc_parent_data_1),837 .ops = &clk_rcg2_ops,838 },839};840 841static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {842 .cmd_rcgr = 0x2e00c,843 .mnd_width = 8,844 .hid_width = 5,845 .parent_map = gcc_parent_map_0,846 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,847 .clkr.hw.init = &(struct clk_init_data){848 .name = "blsp2_qup5_spi_apps_clk_src",849 .parent_data = gcc_parent_data_0,850 .num_parents = ARRAY_SIZE(gcc_parent_data_0),851 .ops = &clk_rcg2_ops,852 },853};854 855static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {856 .cmd_rcgr = 0x30020,857 .mnd_width = 0,858 .hid_width = 5,859 .parent_map = gcc_parent_map_1,860 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,861 .clkr.hw.init = &(struct clk_init_data){862 .name = "blsp2_qup6_i2c_apps_clk_src",863 .parent_data = gcc_parent_data_1,864 .num_parents = ARRAY_SIZE(gcc_parent_data_1),865 .ops = &clk_rcg2_ops,866 },867};868 869static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {870 .cmd_rcgr = 0x3000c,871 .mnd_width = 8,872 .hid_width = 5,873 .parent_map = gcc_parent_map_0,874 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,875 .clkr.hw.init = &(struct clk_init_data){876 .name = "blsp2_qup6_spi_apps_clk_src",877 .parent_data = gcc_parent_data_0,878 .num_parents = ARRAY_SIZE(gcc_parent_data_0),879 .ops = &clk_rcg2_ops,880 },881};882 883static struct clk_rcg2 blsp2_uart1_apps_clk_src = {884 .cmd_rcgr = 0x2700c,885 .mnd_width = 16,886 .hid_width = 5,887 .parent_map = gcc_parent_map_0,888 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,889 .clkr.hw.init = &(struct clk_init_data){890 .name = "blsp2_uart1_apps_clk_src",891 .parent_data = gcc_parent_data_0,892 .num_parents = ARRAY_SIZE(gcc_parent_data_0),893 .ops = &clk_rcg2_ops,894 },895};896 897static struct clk_rcg2 blsp2_uart2_apps_clk_src = {898 .cmd_rcgr = 0x2900c,899 .mnd_width = 16,900 .hid_width = 5,901 .parent_map = gcc_parent_map_0,902 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,903 .clkr.hw.init = &(struct clk_init_data){904 .name = "blsp2_uart2_apps_clk_src",905 .parent_data = gcc_parent_data_0,906 .num_parents = ARRAY_SIZE(gcc_parent_data_0),907 .ops = &clk_rcg2_ops,908 },909};910 911static struct clk_rcg2 blsp2_uart3_apps_clk_src = {912 .cmd_rcgr = 0x2b00c,913 .mnd_width = 16,914 .hid_width = 5,915 .parent_map = gcc_parent_map_0,916 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,917 .clkr.hw.init = &(struct clk_init_data){918 .name = "blsp2_uart3_apps_clk_src",919 .parent_data = gcc_parent_data_0,920 .num_parents = ARRAY_SIZE(gcc_parent_data_0),921 .ops = &clk_rcg2_ops,922 },923};924 925static const struct freq_tbl ftbl_gp1_clk_src[] = {926 F(19200000, P_XO, 1, 0, 0),927 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),928 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),929 { }930};931 932static struct clk_rcg2 gp1_clk_src = {933 .cmd_rcgr = 0x64004,934 .mnd_width = 8,935 .hid_width = 5,936 .parent_map = gcc_parent_map_2,937 .freq_tbl = ftbl_gp1_clk_src,938 .clkr.hw.init = &(struct clk_init_data){939 .name = "gp1_clk_src",940 .parent_data = gcc_parent_data_2,941 .num_parents = ARRAY_SIZE(gcc_parent_data_2),942 .ops = &clk_rcg2_ops,943 },944};945 946static struct clk_rcg2 gp2_clk_src = {947 .cmd_rcgr = 0x65004,948 .mnd_width = 8,949 .hid_width = 5,950 .parent_map = gcc_parent_map_2,951 .freq_tbl = ftbl_gp1_clk_src,952 .clkr.hw.init = &(struct clk_init_data){953 .name = "gp2_clk_src",954 .parent_data = gcc_parent_data_2,955 .num_parents = ARRAY_SIZE(gcc_parent_data_2),956 .ops = &clk_rcg2_ops,957 },958};959 960static struct clk_rcg2 gp3_clk_src = {961 .cmd_rcgr = 0x66004,962 .mnd_width = 8,963 .hid_width = 5,964 .parent_map = gcc_parent_map_2,965 .freq_tbl = ftbl_gp1_clk_src,966 .clkr.hw.init = &(struct clk_init_data){967 .name = "gp3_clk_src",968 .parent_data = gcc_parent_data_2,969 .num_parents = ARRAY_SIZE(gcc_parent_data_2),970 .ops = &clk_rcg2_ops,971 },972};973 974static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {975 F(19200000, P_XO, 1, 0, 0),976 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),977 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),978 { }979};980 981static struct clk_rcg2 hmss_ahb_clk_src = {982 .cmd_rcgr = 0x48014,983 .mnd_width = 0,984 .hid_width = 5,985 .parent_map = gcc_parent_map_1,986 .freq_tbl = ftbl_hmss_ahb_clk_src,987 .clkr.hw.init = &(struct clk_init_data){988 .name = "hmss_ahb_clk_src",989 .parent_data = gcc_parent_data_1,990 .num_parents = ARRAY_SIZE(gcc_parent_data_1),991 .ops = &clk_rcg2_ops,992 },993};994 995static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {996 F(19200000, P_XO, 1, 0, 0),997 { }998};999 1000static struct clk_rcg2 hmss_rbcpr_clk_src = {1001 .cmd_rcgr = 0x48044,1002 .mnd_width = 0,1003 .hid_width = 5,1004 .parent_map = gcc_parent_map_1,1005 .freq_tbl = ftbl_hmss_rbcpr_clk_src,1006 .clkr.hw.init = &(struct clk_init_data){1007 .name = "hmss_rbcpr_clk_src",1008 .parent_data = gcc_parent_data_1,1009 .num_parents = ARRAY_SIZE(gcc_parent_data_1),1010 .ops = &clk_rcg2_ops,1011 },1012};1013 1014static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {1015 F(1010526, P_XO, 1, 1, 19),1016 { }1017};1018 1019static struct clk_rcg2 pcie_aux_clk_src = {1020 .cmd_rcgr = 0x6c000,1021 .mnd_width = 16,1022 .hid_width = 5,1023 .parent_map = gcc_parent_map_3,1024 .freq_tbl = ftbl_pcie_aux_clk_src,1025 .clkr.hw.init = &(struct clk_init_data){1026 .name = "pcie_aux_clk_src",1027 .parent_data = gcc_parent_data_3,1028 .num_parents = ARRAY_SIZE(gcc_parent_data_3),1029 .ops = &clk_rcg2_ops,1030 },1031};1032 1033static const struct freq_tbl ftbl_pdm2_clk_src[] = {1034 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1035 { }1036};1037 1038static struct clk_rcg2 pdm2_clk_src = {1039 .cmd_rcgr = 0x33010,1040 .mnd_width = 0,1041 .hid_width = 5,1042 .parent_map = gcc_parent_map_1,1043 .freq_tbl = ftbl_pdm2_clk_src,1044 .clkr.hw.init = &(struct clk_init_data){1045 .name = "pdm2_clk_src",1046 .parent_data = gcc_parent_data_1,1047 .num_parents = ARRAY_SIZE(gcc_parent_data_1),1048 .ops = &clk_rcg2_ops,1049 },1050};1051 1052static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {1053 F(144000, P_XO, 16, 3, 25),1054 F(400000, P_XO, 12, 1, 4),1055 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),1056 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),1057 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),1058 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),1059 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),1060 { }1061};1062 1063static struct clk_rcg2 sdcc2_apps_clk_src = {1064 .cmd_rcgr = 0x14010,1065 .mnd_width = 8,1066 .hid_width = 5,1067 .parent_map = gcc_parent_map_4,1068 .freq_tbl = ftbl_sdcc2_apps_clk_src,1069 .clkr.hw.init = &(struct clk_init_data){1070 .name = "sdcc2_apps_clk_src",1071 .parent_data = gcc_parent_data_4,1072 .num_parents = ARRAY_SIZE(gcc_parent_data_4),1073 .ops = &clk_rcg2_floor_ops,1074 },1075};1076 1077static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {1078 F(144000, P_XO, 16, 3, 25),1079 F(400000, P_XO, 12, 1, 4),1080 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),1081 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),1082 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),1083 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),1084 { }1085};1086 1087static struct clk_rcg2 sdcc4_apps_clk_src = {1088 .cmd_rcgr = 0x16010,1089 .mnd_width = 8,1090 .hid_width = 5,1091 .parent_map = gcc_parent_map_1,1092 .freq_tbl = ftbl_sdcc4_apps_clk_src,1093 .clkr.hw.init = &(struct clk_init_data){1094 .name = "sdcc4_apps_clk_src",1095 .parent_data = gcc_parent_data_1,1096 .num_parents = ARRAY_SIZE(gcc_parent_data_1),1097 .ops = &clk_rcg2_floor_ops,1098 },1099};1100 1101static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {1102 F(105495, P_XO, 1, 1, 182),1103 { }1104};1105 1106static struct clk_rcg2 tsif_ref_clk_src = {1107 .cmd_rcgr = 0x36010,1108 .mnd_width = 8,1109 .hid_width = 5,1110 .parent_map = gcc_parent_map_5,1111 .freq_tbl = ftbl_tsif_ref_clk_src,1112 .clkr.hw.init = &(struct clk_init_data){1113 .name = "tsif_ref_clk_src",1114 .parent_data = gcc_parent_data_5,1115 .num_parents = ARRAY_SIZE(gcc_parent_data_5),1116 .ops = &clk_rcg2_ops,1117 },1118};1119 1120static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {1121 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),1122 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),1123 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1124 { }1125};1126 1127static struct clk_rcg2 ufs_axi_clk_src = {1128 .cmd_rcgr = 0x75018,1129 .mnd_width = 8,1130 .hid_width = 5,1131 .parent_map = gcc_parent_map_0,1132 .freq_tbl = ftbl_ufs_axi_clk_src,1133 .clkr.hw.init = &(struct clk_init_data){1134 .name = "ufs_axi_clk_src",1135 .parent_data = gcc_parent_data_0,1136 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1137 .ops = &clk_rcg2_ops,1138 },1139};1140 1141static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {1142 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),1143 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1144 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1145 { }1146};1147 1148static struct clk_rcg2 ufs_unipro_core_clk_src = {1149 .cmd_rcgr = 0x76028,1150 .mnd_width = 8,1151 .hid_width = 5,1152 .parent_map = gcc_parent_map_0,1153 .freq_tbl = ftbl_ufs_unipro_core_clk_src,1154 .clkr.hw.init = &(struct clk_init_data){1155 .name = "ufs_unipro_core_clk_src",1156 .parent_data = gcc_parent_data_0,1157 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1158 .ops = &clk_rcg2_ops,1159 },1160};1161 1162static const struct freq_tbl ftbl_usb30_master_clk_src[] = {1163 F(19200000, P_XO, 1, 0, 0),1164 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1165 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),1166 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1167 { }1168};1169 1170static struct clk_rcg2 usb30_master_clk_src = {1171 .cmd_rcgr = 0xf014,1172 .mnd_width = 8,1173 .hid_width = 5,1174 .parent_map = gcc_parent_map_0,1175 .freq_tbl = ftbl_usb30_master_clk_src,1176 .clkr.hw.init = &(struct clk_init_data){1177 .name = "usb30_master_clk_src",1178 .parent_data = gcc_parent_data_0,1179 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1180 .ops = &clk_rcg2_ops,1181 },1182};1183 1184static struct clk_rcg2 usb30_mock_utmi_clk_src = {1185 .cmd_rcgr = 0xf028,1186 .mnd_width = 0,1187 .hid_width = 5,1188 .parent_map = gcc_parent_map_0,1189 .freq_tbl = ftbl_hmss_rbcpr_clk_src,1190 .clkr.hw.init = &(struct clk_init_data){1191 .name = "usb30_mock_utmi_clk_src",1192 .parent_data = gcc_parent_data_0,1193 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1194 .ops = &clk_rcg2_ops,1195 },1196};1197 1198static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {1199 F(1200000, P_XO, 16, 0, 0),1200 { }1201};1202 1203static struct clk_rcg2 usb3_phy_aux_clk_src = {1204 .cmd_rcgr = 0x5000c,1205 .mnd_width = 0,1206 .hid_width = 5,1207 .parent_map = gcc_parent_map_3,1208 .freq_tbl = ftbl_usb3_phy_aux_clk_src,1209 .clkr.hw.init = &(struct clk_init_data){1210 .name = "usb3_phy_aux_clk_src",1211 .parent_data = gcc_parent_data_3,1212 .num_parents = ARRAY_SIZE(gcc_parent_data_3),1213 .ops = &clk_rcg2_ops,1214 },1215};1216 1217static struct clk_branch gcc_aggre1_noc_xo_clk = {1218 .halt_reg = 0x8202c,1219 .halt_check = BRANCH_HALT,1220 .clkr = {1221 .enable_reg = 0x8202c,1222 .enable_mask = BIT(0),1223 .hw.init = &(struct clk_init_data){1224 .name = "gcc_aggre1_noc_xo_clk",1225 .ops = &clk_branch2_ops,1226 },1227 },1228};1229 1230static struct clk_branch gcc_aggre1_ufs_axi_clk = {1231 .halt_reg = 0x82028,1232 .halt_check = BRANCH_HALT,1233 .clkr = {1234 .enable_reg = 0x82028,1235 .enable_mask = BIT(0),1236 .hw.init = &(struct clk_init_data){1237 .name = "gcc_aggre1_ufs_axi_clk",1238 .parent_hws = (const struct clk_hw *[]) {1239 &ufs_axi_clk_src.clkr.hw,1240 },1241 .num_parents = 1,1242 .flags = CLK_SET_RATE_PARENT,1243 .ops = &clk_branch2_ops,1244 },1245 },1246};1247 1248static struct clk_branch gcc_aggre1_usb3_axi_clk = {1249 .halt_reg = 0x82024,1250 .halt_check = BRANCH_HALT,1251 .clkr = {1252 .enable_reg = 0x82024,1253 .enable_mask = BIT(0),1254 .hw.init = &(struct clk_init_data){1255 .name = "gcc_aggre1_usb3_axi_clk",1256 .parent_hws = (const struct clk_hw *[]) {1257 &usb30_master_clk_src.clkr.hw,1258 },1259 .num_parents = 1,1260 .flags = CLK_SET_RATE_PARENT,1261 .ops = &clk_branch2_ops,1262 },1263 },1264};1265 1266static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {1267 .halt_reg = 0x48090,1268 .halt_check = BRANCH_HALT,1269 .clkr = {1270 .enable_reg = 0x48090,1271 .enable_mask = BIT(0),1272 .hw.init = &(struct clk_init_data){1273 .name = "gcc_apss_qdss_tsctr_div2_clk",1274 .ops = &clk_branch2_ops,1275 },1276 },1277};1278 1279static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {1280 .halt_reg = 0x48094,1281 .halt_check = BRANCH_HALT,1282 .clkr = {1283 .enable_reg = 0x48094,1284 .enable_mask = BIT(0),1285 .hw.init = &(struct clk_init_data){1286 .name = "gcc_apss_qdss_tsctr_div8_clk",1287 .ops = &clk_branch2_ops,1288 },1289 },1290};1291 1292static struct clk_branch gcc_bimc_hmss_axi_clk = {1293 .halt_reg = 0x48004,1294 .halt_check = BRANCH_HALT_VOTED,1295 .clkr = {1296 .enable_reg = 0x52004,1297 .enable_mask = BIT(22),1298 .hw.init = &(struct clk_init_data){1299 .name = "gcc_bimc_hmss_axi_clk",1300 .ops = &clk_branch2_ops,1301 },1302 },1303};1304 1305static struct clk_branch gcc_bimc_mss_q6_axi_clk = {1306 .halt_reg = 0x4401c,1307 .halt_check = BRANCH_HALT,1308 .clkr = {1309 .enable_reg = 0x4401c,1310 .enable_mask = BIT(0),1311 .hw.init = &(struct clk_init_data){1312 .name = "gcc_bimc_mss_q6_axi_clk",1313 .ops = &clk_branch2_ops,1314 },1315 },1316};1317 1318static struct clk_branch gcc_mss_cfg_ahb_clk = {1319 .halt_reg = 0x8a000,1320 .halt_check = BRANCH_HALT,1321 .clkr = {1322 .enable_reg = 0x8a000,1323 .enable_mask = BIT(0),1324 .hw.init = &(struct clk_init_data){1325 .name = "gcc_mss_cfg_ahb_clk",1326 .ops = &clk_branch2_ops,1327 },1328 },1329};1330 1331static struct clk_branch gcc_mss_snoc_axi_clk = {1332 .halt_reg = 0x8a03c,1333 .halt_check = BRANCH_HALT,1334 .clkr = {1335 .enable_reg = 0x8a03c,1336 .enable_mask = BIT(0),1337 .hw.init = &(struct clk_init_data){1338 .name = "gcc_mss_snoc_axi_clk",1339 .ops = &clk_branch2_ops,1340 },1341 },1342};1343 1344static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {1345 .halt_reg = 0x8a004,1346 .halt_check = BRANCH_HALT,1347 .clkr = {1348 .enable_reg = 0x8a004,1349 .enable_mask = BIT(0),1350 .hw.init = &(struct clk_init_data){1351 .name = "gcc_mss_mnoc_bimc_axi_clk",1352 .ops = &clk_branch2_ops,1353 },1354 },1355};1356 1357static struct clk_branch gcc_boot_rom_ahb_clk = {1358 .halt_reg = 0x38004,1359 .halt_check = BRANCH_HALT_VOTED,1360 .hwcg_reg = 0x38004,1361 .hwcg_bit = 1,1362 .clkr = {1363 .enable_reg = 0x52004,1364 .enable_mask = BIT(10),1365 .hw.init = &(struct clk_init_data){1366 .name = "gcc_boot_rom_ahb_clk",1367 .ops = &clk_branch2_ops,1368 },1369 },1370};1371 1372static struct clk_branch gcc_mmss_gpll0_div_clk = {1373 .halt_check = BRANCH_HALT_DELAY,1374 .clkr = {1375 .enable_reg = 0x5200c,1376 .enable_mask = BIT(0),1377 .hw.init = &(struct clk_init_data){1378 .name = "gcc_mmss_gpll0_div_clk",1379 .parent_hws = (const struct clk_hw *[]) {1380 &gpll0_out_main.clkr.hw,1381 },1382 .num_parents = 1,1383 .ops = &clk_branch2_ops,1384 },1385 },1386};1387 1388static struct clk_branch gcc_mmss_gpll0_clk = {1389 .halt_check = BRANCH_HALT_DELAY,1390 .clkr = {1391 .enable_reg = 0x5200c,1392 .enable_mask = BIT(1),1393 .hw.init = &(struct clk_init_data){1394 .name = "gcc_mmss_gpll0_clk",1395 .parent_hws = (const struct clk_hw *[]) {1396 &gpll0_out_main.clkr.hw,1397 },1398 .num_parents = 1,1399 .ops = &clk_branch2_ops,1400 },1401 },1402};1403 1404static struct clk_branch gcc_mss_gpll0_div_clk_src = {1405 .halt_check = BRANCH_HALT_DELAY,1406 .clkr = {1407 .enable_reg = 0x5200c,1408 .enable_mask = BIT(2),1409 .hw.init = &(struct clk_init_data){1410 .name = "gcc_mss_gpll0_div_clk_src",1411 .ops = &clk_branch2_ops,1412 },1413 },1414};1415 1416static struct clk_branch gcc_gpu_gpll0_div_clk = {1417 .halt_check = BRANCH_HALT_DELAY,1418 .clkr = {1419 .enable_reg = 0x5200c,1420 .enable_mask = BIT(3),1421 .hw.init = &(struct clk_init_data){1422 .name = "gcc_gpu_gpll0_div_clk",1423 .parent_hws = (const struct clk_hw *[]) {1424 &gpll0_out_main.clkr.hw,1425 },1426 .num_parents = 1,1427 .ops = &clk_branch2_ops,1428 },1429 },1430};1431 1432static struct clk_branch gcc_gpu_gpll0_clk = {1433 .halt_check = BRANCH_HALT_DELAY,1434 .clkr = {1435 .enable_reg = 0x5200c,1436 .enable_mask = BIT(4),1437 .hw.init = &(struct clk_init_data){1438 .name = "gcc_gpu_gpll0_clk",1439 .parent_hws = (const struct clk_hw *[]) {1440 &gpll0_out_main.clkr.hw,1441 },1442 .num_parents = 1,1443 .ops = &clk_branch2_ops,1444 },1445 },1446};1447 1448static struct clk_branch gcc_blsp1_ahb_clk = {1449 .halt_reg = 0x17004,1450 .halt_check = BRANCH_HALT_VOTED,1451 .clkr = {1452 .enable_reg = 0x52004,1453 .enable_mask = BIT(17),1454 .hw.init = &(struct clk_init_data){1455 .name = "gcc_blsp1_ahb_clk",1456 .ops = &clk_branch2_ops,1457 },1458 },1459};1460 1461static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {1462 .halt_reg = 0x19008,1463 .halt_check = BRANCH_HALT,1464 .clkr = {1465 .enable_reg = 0x19008,1466 .enable_mask = BIT(0),1467 .hw.init = &(struct clk_init_data){1468 .name = "gcc_blsp1_qup1_i2c_apps_clk",1469 .parent_hws = (const struct clk_hw *[]) {1470 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,1471 },1472 .num_parents = 1,1473 .flags = CLK_SET_RATE_PARENT,1474 .ops = &clk_branch2_ops,1475 },1476 },1477};1478 1479static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {1480 .halt_reg = 0x19004,1481 .halt_check = BRANCH_HALT,1482 .clkr = {1483 .enable_reg = 0x19004,1484 .enable_mask = BIT(0),1485 .hw.init = &(struct clk_init_data){1486 .name = "gcc_blsp1_qup1_spi_apps_clk",1487 .parent_hws = (const struct clk_hw *[]) {1488 &blsp1_qup1_spi_apps_clk_src.clkr.hw,1489 },1490 .num_parents = 1,1491 .flags = CLK_SET_RATE_PARENT,1492 .ops = &clk_branch2_ops,1493 },1494 },1495};1496 1497static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {1498 .halt_reg = 0x1b008,1499 .halt_check = BRANCH_HALT,1500 .clkr = {1501 .enable_reg = 0x1b008,1502 .enable_mask = BIT(0),1503 .hw.init = &(struct clk_init_data){1504 .name = "gcc_blsp1_qup2_i2c_apps_clk",1505 .parent_hws = (const struct clk_hw *[]) {1506 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,1507 },1508 .num_parents = 1,1509 .flags = CLK_SET_RATE_PARENT,1510 .ops = &clk_branch2_ops,1511 },1512 },1513};1514 1515static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {1516 .halt_reg = 0x1b004,1517 .halt_check = BRANCH_HALT,1518 .clkr = {1519 .enable_reg = 0x1b004,1520 .enable_mask = BIT(0),1521 .hw.init = &(struct clk_init_data){1522 .name = "gcc_blsp1_qup2_spi_apps_clk",1523 .parent_hws = (const struct clk_hw *[]) {1524 &blsp1_qup2_spi_apps_clk_src.clkr.hw,1525 },1526 .num_parents = 1,1527 .flags = CLK_SET_RATE_PARENT,1528 .ops = &clk_branch2_ops,1529 },1530 },1531};1532 1533static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {1534 .halt_reg = 0x1d008,1535 .halt_check = BRANCH_HALT,1536 .clkr = {1537 .enable_reg = 0x1d008,1538 .enable_mask = BIT(0),1539 .hw.init = &(struct clk_init_data){1540 .name = "gcc_blsp1_qup3_i2c_apps_clk",1541 .parent_hws = (const struct clk_hw *[]) {1542 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,1543 },1544 .num_parents = 1,1545 .flags = CLK_SET_RATE_PARENT,1546 .ops = &clk_branch2_ops,1547 },1548 },1549};1550 1551static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {1552 .halt_reg = 0x1d004,1553 .halt_check = BRANCH_HALT,1554 .clkr = {1555 .enable_reg = 0x1d004,1556 .enable_mask = BIT(0),1557 .hw.init = &(struct clk_init_data){1558 .name = "gcc_blsp1_qup3_spi_apps_clk",1559 .parent_hws = (const struct clk_hw *[]) {1560 &blsp1_qup3_spi_apps_clk_src.clkr.hw,1561 },1562 .num_parents = 1,1563 .flags = CLK_SET_RATE_PARENT,1564 .ops = &clk_branch2_ops,1565 },1566 },1567};1568 1569static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {1570 .halt_reg = 0x1f008,1571 .halt_check = BRANCH_HALT,1572 .clkr = {1573 .enable_reg = 0x1f008,1574 .enable_mask = BIT(0),1575 .hw.init = &(struct clk_init_data){1576 .name = "gcc_blsp1_qup4_i2c_apps_clk",1577 .parent_hws = (const struct clk_hw *[]) {1578 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,1579 },1580 .num_parents = 1,1581 .flags = CLK_SET_RATE_PARENT,1582 .ops = &clk_branch2_ops,1583 },1584 },1585};1586 1587static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {1588 .halt_reg = 0x1f004,1589 .halt_check = BRANCH_HALT,1590 .clkr = {1591 .enable_reg = 0x1f004,1592 .enable_mask = BIT(0),1593 .hw.init = &(struct clk_init_data){1594 .name = "gcc_blsp1_qup4_spi_apps_clk",1595 .parent_hws = (const struct clk_hw *[]) {1596 &blsp1_qup4_spi_apps_clk_src.clkr.hw,1597 },1598 .num_parents = 1,1599 .flags = CLK_SET_RATE_PARENT,1600 .ops = &clk_branch2_ops,1601 },1602 },1603};1604 1605static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {1606 .halt_reg = 0x21008,1607 .halt_check = BRANCH_HALT,1608 .clkr = {1609 .enable_reg = 0x21008,1610 .enable_mask = BIT(0),1611 .hw.init = &(struct clk_init_data){1612 .name = "gcc_blsp1_qup5_i2c_apps_clk",1613 .parent_hws = (const struct clk_hw *[]) {1614 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,1615 },1616 .num_parents = 1,1617 .flags = CLK_SET_RATE_PARENT,1618 .ops = &clk_branch2_ops,1619 },1620 },1621};1622 1623static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {1624 .halt_reg = 0x21004,1625 .halt_check = BRANCH_HALT,1626 .clkr = {1627 .enable_reg = 0x21004,1628 .enable_mask = BIT(0),1629 .hw.init = &(struct clk_init_data){1630 .name = "gcc_blsp1_qup5_spi_apps_clk",1631 .parent_hws = (const struct clk_hw *[]) {1632 &blsp1_qup5_spi_apps_clk_src.clkr.hw,1633 },1634 .num_parents = 1,1635 .flags = CLK_SET_RATE_PARENT,1636 .ops = &clk_branch2_ops,1637 },1638 },1639};1640 1641static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {1642 .halt_reg = 0x23008,1643 .halt_check = BRANCH_HALT,1644 .clkr = {1645 .enable_reg = 0x23008,1646 .enable_mask = BIT(0),1647 .hw.init = &(struct clk_init_data){1648 .name = "gcc_blsp1_qup6_i2c_apps_clk",1649 .parent_hws = (const struct clk_hw *[]) {1650 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,1651 },1652 .num_parents = 1,1653 .flags = CLK_SET_RATE_PARENT,1654 .ops = &clk_branch2_ops,1655 },1656 },1657};1658 1659static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {1660 .halt_reg = 0x23004,1661 .halt_check = BRANCH_HALT,1662 .clkr = {1663 .enable_reg = 0x23004,1664 .enable_mask = BIT(0),1665 .hw.init = &(struct clk_init_data){1666 .name = "gcc_blsp1_qup6_spi_apps_clk",1667 .parent_hws = (const struct clk_hw *[]) {1668 &blsp1_qup6_spi_apps_clk_src.clkr.hw,1669 },1670 .num_parents = 1,1671 .flags = CLK_SET_RATE_PARENT,1672 .ops = &clk_branch2_ops,1673 },1674 },1675};1676 1677static struct clk_branch gcc_blsp1_sleep_clk = {1678 .halt_reg = 0x17008,1679 .halt_check = BRANCH_HALT_VOTED,1680 .clkr = {1681 .enable_reg = 0x52004,1682 .enable_mask = BIT(16),1683 .hw.init = &(struct clk_init_data){1684 .name = "gcc_blsp1_sleep_clk",1685 .ops = &clk_branch2_ops,1686 },1687 },1688};1689 1690static struct clk_branch gcc_blsp1_uart1_apps_clk = {1691 .halt_reg = 0x1a004,1692 .halt_check = BRANCH_HALT,1693 .clkr = {1694 .enable_reg = 0x1a004,1695 .enable_mask = BIT(0),1696 .hw.init = &(struct clk_init_data){1697 .name = "gcc_blsp1_uart1_apps_clk",1698 .parent_hws = (const struct clk_hw *[]) {1699 &blsp1_uart1_apps_clk_src.clkr.hw,1700 },1701 .num_parents = 1,1702 .flags = CLK_SET_RATE_PARENT,1703 .ops = &clk_branch2_ops,1704 },1705 },1706};1707 1708static struct clk_branch gcc_blsp1_uart2_apps_clk = {1709 .halt_reg = 0x1c004,1710 .halt_check = BRANCH_HALT,1711 .clkr = {1712 .enable_reg = 0x1c004,1713 .enable_mask = BIT(0),1714 .hw.init = &(struct clk_init_data){1715 .name = "gcc_blsp1_uart2_apps_clk",1716 .parent_hws = (const struct clk_hw *[]) {1717 &blsp1_uart2_apps_clk_src.clkr.hw,1718 },1719 .num_parents = 1,1720 .flags = CLK_SET_RATE_PARENT,1721 .ops = &clk_branch2_ops,1722 },1723 },1724};1725 1726static struct clk_branch gcc_blsp1_uart3_apps_clk = {1727 .halt_reg = 0x1e004,1728 .halt_check = BRANCH_HALT,1729 .clkr = {1730 .enable_reg = 0x1e004,1731 .enable_mask = BIT(0),1732 .hw.init = &(struct clk_init_data){1733 .name = "gcc_blsp1_uart3_apps_clk",1734 .parent_hws = (const struct clk_hw *[]) {1735 &blsp1_uart3_apps_clk_src.clkr.hw,1736 },1737 .num_parents = 1,1738 .flags = CLK_SET_RATE_PARENT,1739 .ops = &clk_branch2_ops,1740 },1741 },1742};1743 1744static struct clk_branch gcc_blsp2_ahb_clk = {1745 .halt_reg = 0x25004,1746 .halt_check = BRANCH_HALT_VOTED,1747 .clkr = {1748 .enable_reg = 0x52004,1749 .enable_mask = BIT(15),1750 .hw.init = &(struct clk_init_data){1751 .name = "gcc_blsp2_ahb_clk",1752 .ops = &clk_branch2_ops,1753 },1754 },1755};1756 1757static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {1758 .halt_reg = 0x26008,1759 .halt_check = BRANCH_HALT,1760 .clkr = {1761 .enable_reg = 0x26008,1762 .enable_mask = BIT(0),1763 .hw.init = &(struct clk_init_data){1764 .name = "gcc_blsp2_qup1_i2c_apps_clk",1765 .parent_hws = (const struct clk_hw *[]) {1766 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,1767 },1768 .num_parents = 1,1769 .flags = CLK_SET_RATE_PARENT,1770 .ops = &clk_branch2_ops,1771 },1772 },1773};1774 1775static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {1776 .halt_reg = 0x26004,1777 .halt_check = BRANCH_HALT,1778 .clkr = {1779 .enable_reg = 0x26004,1780 .enable_mask = BIT(0),1781 .hw.init = &(struct clk_init_data){1782 .name = "gcc_blsp2_qup1_spi_apps_clk",1783 .parent_hws = (const struct clk_hw *[]) {1784 &blsp2_qup1_spi_apps_clk_src.clkr.hw,1785 },1786 .num_parents = 1,1787 .flags = CLK_SET_RATE_PARENT,1788 .ops = &clk_branch2_ops,1789 },1790 },1791};1792 1793static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {1794 .halt_reg = 0x28008,1795 .halt_check = BRANCH_HALT,1796 .clkr = {1797 .enable_reg = 0x28008,1798 .enable_mask = BIT(0),1799 .hw.init = &(struct clk_init_data){1800 .name = "gcc_blsp2_qup2_i2c_apps_clk",1801 .parent_hws = (const struct clk_hw *[]) {1802 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,1803 },1804 .num_parents = 1,1805 .flags = CLK_SET_RATE_PARENT,1806 .ops = &clk_branch2_ops,1807 },1808 },1809};1810 1811static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {1812 .halt_reg = 0x28004,1813 .halt_check = BRANCH_HALT,1814 .clkr = {1815 .enable_reg = 0x28004,1816 .enable_mask = BIT(0),1817 .hw.init = &(struct clk_init_data){1818 .name = "gcc_blsp2_qup2_spi_apps_clk",1819 .parent_hws = (const struct clk_hw *[]) {1820 &blsp2_qup2_spi_apps_clk_src.clkr.hw,1821 },1822 .num_parents = 1,1823 .flags = CLK_SET_RATE_PARENT,1824 .ops = &clk_branch2_ops,1825 },1826 },1827};1828 1829static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {1830 .halt_reg = 0x2a008,1831 .halt_check = BRANCH_HALT,1832 .clkr = {1833 .enable_reg = 0x2a008,1834 .enable_mask = BIT(0),1835 .hw.init = &(struct clk_init_data){1836 .name = "gcc_blsp2_qup3_i2c_apps_clk",1837 .parent_hws = (const struct clk_hw *[]) {1838 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,1839 },1840 .num_parents = 1,1841 .flags = CLK_SET_RATE_PARENT,1842 .ops = &clk_branch2_ops,1843 },1844 },1845};1846 1847static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {1848 .halt_reg = 0x2a004,1849 .halt_check = BRANCH_HALT,1850 .clkr = {1851 .enable_reg = 0x2a004,1852 .enable_mask = BIT(0),1853 .hw.init = &(struct clk_init_data){1854 .name = "gcc_blsp2_qup3_spi_apps_clk",1855 .parent_hws = (const struct clk_hw *[]) {1856 &blsp2_qup3_spi_apps_clk_src.clkr.hw,1857 },1858 .num_parents = 1,1859 .flags = CLK_SET_RATE_PARENT,1860 .ops = &clk_branch2_ops,1861 },1862 },1863};1864 1865static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {1866 .halt_reg = 0x2c008,1867 .halt_check = BRANCH_HALT,1868 .clkr = {1869 .enable_reg = 0x2c008,1870 .enable_mask = BIT(0),1871 .hw.init = &(struct clk_init_data){1872 .name = "gcc_blsp2_qup4_i2c_apps_clk",1873 .parent_hws = (const struct clk_hw *[]) {1874 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,1875 },1876 .num_parents = 1,1877 .flags = CLK_SET_RATE_PARENT,1878 .ops = &clk_branch2_ops,1879 },1880 },1881};1882 1883static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {1884 .halt_reg = 0x2c004,1885 .halt_check = BRANCH_HALT,1886 .clkr = {1887 .enable_reg = 0x2c004,1888 .enable_mask = BIT(0),1889 .hw.init = &(struct clk_init_data){1890 .name = "gcc_blsp2_qup4_spi_apps_clk",1891 .parent_hws = (const struct clk_hw *[]) {1892 &blsp2_qup4_spi_apps_clk_src.clkr.hw,1893 },1894 .num_parents = 1,1895 .flags = CLK_SET_RATE_PARENT,1896 .ops = &clk_branch2_ops,1897 },1898 },1899};1900 1901static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {1902 .halt_reg = 0x2e008,1903 .halt_check = BRANCH_HALT,1904 .clkr = {1905 .enable_reg = 0x2e008,1906 .enable_mask = BIT(0),1907 .hw.init = &(struct clk_init_data){1908 .name = "gcc_blsp2_qup5_i2c_apps_clk",1909 .parent_hws = (const struct clk_hw *[]) {1910 &blsp2_qup5_i2c_apps_clk_src.clkr.hw,1911 },1912 .num_parents = 1,1913 .flags = CLK_SET_RATE_PARENT,1914 .ops = &clk_branch2_ops,1915 },1916 },1917};1918 1919static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {1920 .halt_reg = 0x2e004,1921 .halt_check = BRANCH_HALT,1922 .clkr = {1923 .enable_reg = 0x2e004,1924 .enable_mask = BIT(0),1925 .hw.init = &(struct clk_init_data){1926 .name = "gcc_blsp2_qup5_spi_apps_clk",1927 .parent_hws = (const struct clk_hw *[]) {1928 &blsp2_qup5_spi_apps_clk_src.clkr.hw,1929 },1930 .num_parents = 1,1931 .flags = CLK_SET_RATE_PARENT,1932 .ops = &clk_branch2_ops,1933 },1934 },1935};1936 1937static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {1938 .halt_reg = 0x30008,1939 .halt_check = BRANCH_HALT,1940 .clkr = {1941 .enable_reg = 0x30008,1942 .enable_mask = BIT(0),1943 .hw.init = &(struct clk_init_data){1944 .name = "gcc_blsp2_qup6_i2c_apps_clk",1945 .parent_hws = (const struct clk_hw *[]) {1946 &blsp2_qup6_i2c_apps_clk_src.clkr.hw,1947 },1948 .num_parents = 1,1949 .flags = CLK_SET_RATE_PARENT,1950 .ops = &clk_branch2_ops,1951 },1952 },1953};1954 1955static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {1956 .halt_reg = 0x30004,1957 .halt_check = BRANCH_HALT,1958 .clkr = {1959 .enable_reg = 0x30004,1960 .enable_mask = BIT(0),1961 .hw.init = &(struct clk_init_data){1962 .name = "gcc_blsp2_qup6_spi_apps_clk",1963 .parent_hws = (const struct clk_hw *[]) {1964 &blsp2_qup6_spi_apps_clk_src.clkr.hw,1965 },1966 .num_parents = 1,1967 .flags = CLK_SET_RATE_PARENT,1968 .ops = &clk_branch2_ops,1969 },1970 },1971};1972 1973static struct clk_branch gcc_blsp2_sleep_clk = {1974 .halt_reg = 0x25008,1975 .halt_check = BRANCH_HALT_VOTED,1976 .clkr = {1977 .enable_reg = 0x52004,1978 .enable_mask = BIT(14),1979 .hw.init = &(struct clk_init_data){1980 .name = "gcc_blsp2_sleep_clk",1981 .ops = &clk_branch2_ops,1982 },1983 },1984};1985 1986static struct clk_branch gcc_blsp2_uart1_apps_clk = {1987 .halt_reg = 0x27004,1988 .halt_check = BRANCH_HALT,1989 .clkr = {1990 .enable_reg = 0x27004,1991 .enable_mask = BIT(0),1992 .hw.init = &(struct clk_init_data){1993 .name = "gcc_blsp2_uart1_apps_clk",1994 .parent_hws = (const struct clk_hw *[]) {1995 &blsp2_uart1_apps_clk_src.clkr.hw,1996 },1997 .num_parents = 1,1998 .flags = CLK_SET_RATE_PARENT,1999 .ops = &clk_branch2_ops,2000 },2001 },2002};2003 2004static struct clk_branch gcc_blsp2_uart2_apps_clk = {2005 .halt_reg = 0x29004,2006 .halt_check = BRANCH_HALT,2007 .clkr = {2008 .enable_reg = 0x29004,2009 .enable_mask = BIT(0),2010 .hw.init = &(struct clk_init_data){2011 .name = "gcc_blsp2_uart2_apps_clk",2012 .parent_hws = (const struct clk_hw *[]) {2013 &blsp2_uart2_apps_clk_src.clkr.hw,2014 },2015 .num_parents = 1,2016 .flags = CLK_SET_RATE_PARENT,2017 .ops = &clk_branch2_ops,2018 },2019 },2020};2021 2022static struct clk_branch gcc_blsp2_uart3_apps_clk = {2023 .halt_reg = 0x2b004,2024 .halt_check = BRANCH_HALT,2025 .clkr = {2026 .enable_reg = 0x2b004,2027 .enable_mask = BIT(0),2028 .hw.init = &(struct clk_init_data){2029 .name = "gcc_blsp2_uart3_apps_clk",2030 .parent_hws = (const struct clk_hw *[]) {2031 &blsp2_uart3_apps_clk_src.clkr.hw,2032 },2033 .num_parents = 1,2034 .flags = CLK_SET_RATE_PARENT,2035 .ops = &clk_branch2_ops,2036 },2037 },2038};2039 2040static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {2041 .halt_reg = 0x5018,2042 .halt_check = BRANCH_HALT,2043 .clkr = {2044 .enable_reg = 0x5018,2045 .enable_mask = BIT(0),2046 .hw.init = &(struct clk_init_data){2047 .name = "gcc_cfg_noc_usb3_axi_clk",2048 .parent_hws = (const struct clk_hw *[]) {2049 &usb30_master_clk_src.clkr.hw,2050 },2051 .num_parents = 1,2052 .flags = CLK_SET_RATE_PARENT,2053 .ops = &clk_branch2_ops,2054 },2055 },2056};2057 2058static struct clk_branch gcc_gp1_clk = {2059 .halt_reg = 0x64000,2060 .halt_check = BRANCH_HALT,2061 .clkr = {2062 .enable_reg = 0x64000,2063 .enable_mask = BIT(0),2064 .hw.init = &(struct clk_init_data){2065 .name = "gcc_gp1_clk",2066 .parent_hws = (const struct clk_hw *[]) {2067 &gp1_clk_src.clkr.hw,2068 },2069 .num_parents = 1,2070 .flags = CLK_SET_RATE_PARENT,2071 .ops = &clk_branch2_ops,2072 },2073 },2074};2075 2076static struct clk_branch gcc_gp2_clk = {2077 .halt_reg = 0x65000,2078 .halt_check = BRANCH_HALT,2079 .clkr = {2080 .enable_reg = 0x65000,2081 .enable_mask = BIT(0),2082 .hw.init = &(struct clk_init_data){2083 .name = "gcc_gp2_clk",2084 .parent_hws = (const struct clk_hw *[]) {2085 &gp2_clk_src.clkr.hw,2086 },2087 .num_parents = 1,2088 .flags = CLK_SET_RATE_PARENT,2089 .ops = &clk_branch2_ops,2090 },2091 },2092};2093 2094static struct clk_branch gcc_gp3_clk = {2095 .halt_reg = 0x66000,2096 .halt_check = BRANCH_HALT,2097 .clkr = {2098 .enable_reg = 0x66000,2099 .enable_mask = BIT(0),2100 .hw.init = &(struct clk_init_data){2101 .name = "gcc_gp3_clk",2102 .parent_hws = (const struct clk_hw *[]) {2103 &gp3_clk_src.clkr.hw,2104 },2105 .num_parents = 1,2106 .flags = CLK_SET_RATE_PARENT,2107 .ops = &clk_branch2_ops,2108 },2109 },2110};2111 2112static struct clk_branch gcc_bimc_gfx_clk = {2113 .halt_reg = 0x46040,2114 .halt_check = BRANCH_HALT_SKIP,2115 .clkr = {2116 .enable_reg = 0x46040,2117 .enable_mask = BIT(0),2118 .hw.init = &(struct clk_init_data){2119 .name = "gcc_bimc_gfx_clk",2120 .ops = &clk_branch2_ops,2121 },2122 },2123};2124 2125static struct clk_branch gcc_gpu_bimc_gfx_clk = {2126 .halt_reg = 0x71010,2127 .halt_check = BRANCH_HALT_SKIP,2128 .clkr = {2129 .enable_reg = 0x71010,2130 .enable_mask = BIT(0),2131 .hw.init = &(struct clk_init_data){2132 .name = "gcc_gpu_bimc_gfx_clk",2133 .ops = &clk_branch2_ops,2134 },2135 },2136};2137 2138static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {2139 .halt_reg = 0x7100c,2140 .halt_check = BRANCH_HALT,2141 .clkr = {2142 .enable_reg = 0x7100c,2143 .enable_mask = BIT(0),2144 .hw.init = &(struct clk_init_data){2145 .name = "gcc_gpu_bimc_gfx_src_clk",2146 .ops = &clk_branch2_ops,2147 },2148 },2149};2150 2151static struct clk_branch gcc_gpu_cfg_ahb_clk = {2152 .halt_reg = 0x71004,2153 .halt_check = BRANCH_HALT_SKIP,2154 .clkr = {2155 .enable_reg = 0x71004,2156 .enable_mask = BIT(0),2157 .hw.init = &(struct clk_init_data){2158 .name = "gcc_gpu_cfg_ahb_clk",2159 .ops = &clk_branch2_ops,2160 /*2161 * The GPU IOMMU depends on this clock and hypervisor2162 * will crash the SoC if this clock goes down, due to2163 * secure contexts protection.2164 */2165 .flags = CLK_IS_CRITICAL,2166 },2167 },2168};2169 2170static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {2171 .halt_reg = 0x71018,2172 .halt_check = BRANCH_HALT,2173 .clkr = {2174 .enable_reg = 0x71018,2175 .enable_mask = BIT(0),2176 .hw.init = &(struct clk_init_data){2177 .name = "gcc_gpu_snoc_dvm_gfx_clk",2178 .ops = &clk_branch2_ops,2179 },2180 },2181};2182 2183static struct clk_branch gcc_hmss_ahb_clk = {2184 .halt_reg = 0x48000,2185 .halt_check = BRANCH_HALT_VOTED,2186 .clkr = {2187 .enable_reg = 0x52004,2188 .enable_mask = BIT(21),2189 .hw.init = &(struct clk_init_data){2190 .name = "gcc_hmss_ahb_clk",2191 .parent_hws = (const struct clk_hw *[]) {2192 &hmss_ahb_clk_src.clkr.hw,2193 },2194 .num_parents = 1,2195 .flags = CLK_SET_RATE_PARENT,2196 .ops = &clk_branch2_ops,2197 },2198 },2199};2200 2201static struct clk_branch gcc_hmss_at_clk = {2202 .halt_reg = 0x48010,2203 .halt_check = BRANCH_HALT,2204 .clkr = {2205 .enable_reg = 0x48010,2206 .enable_mask = BIT(0),2207 .hw.init = &(struct clk_init_data){2208 .name = "gcc_hmss_at_clk",2209 .ops = &clk_branch2_ops,2210 },2211 },2212};2213 2214static struct clk_branch gcc_hmss_rbcpr_clk = {2215 .halt_reg = 0x48008,2216 .halt_check = BRANCH_HALT,2217 .clkr = {2218 .enable_reg = 0x48008,2219 .enable_mask = BIT(0),2220 .hw.init = &(struct clk_init_data){2221 .name = "gcc_hmss_rbcpr_clk",2222 .parent_hws = (const struct clk_hw *[]) {2223 &hmss_rbcpr_clk_src.clkr.hw,2224 },2225 .num_parents = 1,2226 .flags = CLK_SET_RATE_PARENT,2227 .ops = &clk_branch2_ops,2228 },2229 },2230};2231 2232static struct clk_branch gcc_hmss_trig_clk = {2233 .halt_reg = 0x4800c,2234 .halt_check = BRANCH_HALT,2235 .clkr = {2236 .enable_reg = 0x4800c,2237 .enable_mask = BIT(0),2238 .hw.init = &(struct clk_init_data){2239 .name = "gcc_hmss_trig_clk",2240 .ops = &clk_branch2_ops,2241 },2242 },2243};2244 2245static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {2246 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),2247 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),2248 { }2249};2250 2251static struct clk_rcg2 hmss_gpll0_clk_src = {2252 .cmd_rcgr = 0x4805c,2253 .hid_width = 5,2254 .parent_map = gcc_parent_map_1,2255 .freq_tbl = ftbl_hmss_gpll0_clk_src,2256 .clkr.hw.init = &(struct clk_init_data) {2257 .name = "hmss_gpll0_clk_src",2258 .parent_data = gcc_parent_data_1,2259 .num_parents = ARRAY_SIZE(gcc_parent_data_1),2260 .ops = &clk_rcg2_ops,2261 },2262};2263 2264static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {2265 .halt_reg = 0x9004,2266 .halt_check = BRANCH_HALT,2267 .clkr = {2268 .enable_reg = 0x9004,2269 .enable_mask = BIT(0),2270 .hw.init = &(struct clk_init_data){2271 .name = "gcc_mmss_noc_cfg_ahb_clk",2272 .ops = &clk_branch2_ops,2273 /*2274 * Any access to mmss depends on this clock.2275 * Gating this clock has been shown to crash the system2276 * when mmssnoc_axi_rpm_clk is inited in rpmcc.2277 */2278 .flags = CLK_IS_CRITICAL,2279 },2280 },2281};2282 2283static struct clk_branch gcc_mmss_qm_ahb_clk = {2284 .halt_reg = 0x9030,2285 .halt_check = BRANCH_HALT,2286 .clkr = {2287 .enable_reg = 0x9030,2288 .enable_mask = BIT(0),2289 .hw.init = &(struct clk_init_data){2290 .name = "gcc_mmss_qm_ahb_clk",2291 .ops = &clk_branch2_ops,2292 },2293 },2294};2295 2296static struct clk_branch gcc_mmss_qm_core_clk = {2297 .halt_reg = 0x900c,2298 .halt_check = BRANCH_HALT,2299 .clkr = {2300 .enable_reg = 0x900c,2301 .enable_mask = BIT(0),2302 .hw.init = &(struct clk_init_data){2303 .name = "gcc_mmss_qm_core_clk",2304 .ops = &clk_branch2_ops,2305 },2306 },2307};2308 2309static struct clk_branch gcc_mmss_sys_noc_axi_clk = {2310 .halt_reg = 0x9000,2311 .halt_check = BRANCH_HALT,2312 .clkr = {2313 .enable_reg = 0x9000,2314 .enable_mask = BIT(0),2315 .hw.init = &(struct clk_init_data){2316 .name = "gcc_mmss_sys_noc_axi_clk",2317 .ops = &clk_branch2_ops,2318 },2319 },2320};2321 2322static struct clk_branch gcc_mss_at_clk = {2323 .halt_reg = 0x8a00c,2324 .halt_check = BRANCH_HALT,2325 .clkr = {2326 .enable_reg = 0x8a00c,2327 .enable_mask = BIT(0),2328 .hw.init = &(struct clk_init_data){2329 .name = "gcc_mss_at_clk",2330 .ops = &clk_branch2_ops,2331 },2332 },2333};2334 2335static struct clk_branch gcc_pcie_0_aux_clk = {2336 .halt_reg = 0x6b014,2337 .halt_check = BRANCH_HALT,2338 .clkr = {2339 .enable_reg = 0x6b014,2340 .enable_mask = BIT(0),2341 .hw.init = &(struct clk_init_data){2342 .name = "gcc_pcie_0_aux_clk",2343 .parent_hws = (const struct clk_hw *[]) {2344 &pcie_aux_clk_src.clkr.hw,2345 },2346 .num_parents = 1,2347 .flags = CLK_SET_RATE_PARENT,2348 .ops = &clk_branch2_ops,2349 },2350 },2351};2352 2353static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {2354 .halt_reg = 0x6b010,2355 .halt_check = BRANCH_HALT,2356 .clkr = {2357 .enable_reg = 0x6b010,2358 .enable_mask = BIT(0),2359 .hw.init = &(struct clk_init_data){2360 .name = "gcc_pcie_0_cfg_ahb_clk",2361 .ops = &clk_branch2_ops,2362 },2363 },2364};2365 2366static struct clk_branch gcc_pcie_0_mstr_axi_clk = {2367 .halt_reg = 0x6b00c,2368 .halt_check = BRANCH_HALT,2369 .clkr = {2370 .enable_reg = 0x6b00c,2371 .enable_mask = BIT(0),2372 .hw.init = &(struct clk_init_data){2373 .name = "gcc_pcie_0_mstr_axi_clk",2374 .ops = &clk_branch2_ops,2375 },2376 },2377};2378 2379static struct clk_branch gcc_pcie_0_pipe_clk = {2380 .halt_reg = 0x6b018,2381 .halt_check = BRANCH_HALT_SKIP,2382 .clkr = {2383 .enable_reg = 0x6b018,2384 .enable_mask = BIT(0),2385 .hw.init = &(struct clk_init_data){2386 .name = "gcc_pcie_0_pipe_clk",2387 .ops = &clk_branch2_ops,2388 },2389 },2390};2391 2392static struct clk_branch gcc_pcie_0_slv_axi_clk = {2393 .halt_reg = 0x6b008,2394 .halt_check = BRANCH_HALT,2395 .clkr = {2396 .enable_reg = 0x6b008,2397 .enable_mask = BIT(0),2398 .hw.init = &(struct clk_init_data){2399 .name = "gcc_pcie_0_slv_axi_clk",2400 .ops = &clk_branch2_ops,2401 },2402 },2403};2404 2405static struct clk_branch gcc_pcie_phy_aux_clk = {2406 .halt_reg = 0x6f004,2407 .halt_check = BRANCH_HALT,2408 .clkr = {2409 .enable_reg = 0x6f004,2410 .enable_mask = BIT(0),2411 .hw.init = &(struct clk_init_data){2412 .name = "gcc_pcie_phy_aux_clk",2413 .parent_hws = (const struct clk_hw *[]) {2414 &pcie_aux_clk_src.clkr.hw,2415 },2416 .num_parents = 1,2417 .flags = CLK_SET_RATE_PARENT,2418 .ops = &clk_branch2_ops,2419 },2420 },2421};2422 2423static struct clk_branch gcc_pdm2_clk = {2424 .halt_reg = 0x3300c,2425 .halt_check = BRANCH_HALT,2426 .clkr = {2427 .enable_reg = 0x3300c,2428 .enable_mask = BIT(0),2429 .hw.init = &(struct clk_init_data){2430 .name = "gcc_pdm2_clk",2431 .parent_hws = (const struct clk_hw *[]) {2432 &pdm2_clk_src.clkr.hw,2433 },2434 .num_parents = 1,2435 .flags = CLK_SET_RATE_PARENT,2436 .ops = &clk_branch2_ops,2437 },2438 },2439};2440 2441static struct clk_branch gcc_pdm_ahb_clk = {2442 .halt_reg = 0x33004,2443 .halt_check = BRANCH_HALT,2444 .clkr = {2445 .enable_reg = 0x33004,2446 .enable_mask = BIT(0),2447 .hw.init = &(struct clk_init_data){2448 .name = "gcc_pdm_ahb_clk",2449 .ops = &clk_branch2_ops,2450 },2451 },2452};2453 2454static struct clk_branch gcc_pdm_xo4_clk = {2455 .halt_reg = 0x33008,2456 .halt_check = BRANCH_HALT,2457 .clkr = {2458 .enable_reg = 0x33008,2459 .enable_mask = BIT(0),2460 .hw.init = &(struct clk_init_data){2461 .name = "gcc_pdm_xo4_clk",2462 .ops = &clk_branch2_ops,2463 },2464 },2465};2466 2467static struct clk_branch gcc_prng_ahb_clk = {2468 .halt_reg = 0x34004,2469 .halt_check = BRANCH_HALT_VOTED,2470 .clkr = {2471 .enable_reg = 0x52004,2472 .enable_mask = BIT(13),2473 .hw.init = &(struct clk_init_data){2474 .name = "gcc_prng_ahb_clk",2475 .ops = &clk_branch2_ops,2476 },2477 },2478};2479 2480static struct clk_branch gcc_sdcc2_ahb_clk = {2481 .halt_reg = 0x14008,2482 .halt_check = BRANCH_HALT,2483 .clkr = {2484 .enable_reg = 0x14008,2485 .enable_mask = BIT(0),2486 .hw.init = &(struct clk_init_data){2487 .name = "gcc_sdcc2_ahb_clk",2488 .ops = &clk_branch2_ops,2489 },2490 },2491};2492 2493static struct clk_branch gcc_sdcc2_apps_clk = {2494 .halt_reg = 0x14004,2495 .halt_check = BRANCH_HALT,2496 .clkr = {2497 .enable_reg = 0x14004,2498 .enable_mask = BIT(0),2499 .hw.init = &(struct clk_init_data){2500 .name = "gcc_sdcc2_apps_clk",2501 .parent_hws = (const struct clk_hw *[]) {2502 &sdcc2_apps_clk_src.clkr.hw,2503 },2504 .num_parents = 1,2505 .flags = CLK_SET_RATE_PARENT,2506 .ops = &clk_branch2_ops,2507 },2508 },2509};2510 2511static struct clk_branch gcc_sdcc4_ahb_clk = {2512 .halt_reg = 0x16008,2513 .halt_check = BRANCH_HALT,2514 .clkr = {2515 .enable_reg = 0x16008,2516 .enable_mask = BIT(0),2517 .hw.init = &(struct clk_init_data){2518 .name = "gcc_sdcc4_ahb_clk",2519 .ops = &clk_branch2_ops,2520 },2521 },2522};2523 2524static struct clk_branch gcc_sdcc4_apps_clk = {2525 .halt_reg = 0x16004,2526 .halt_check = BRANCH_HALT,2527 .clkr = {2528 .enable_reg = 0x16004,2529 .enable_mask = BIT(0),2530 .hw.init = &(struct clk_init_data){2531 .name = "gcc_sdcc4_apps_clk",2532 .parent_hws = (const struct clk_hw *[]) {2533 &sdcc4_apps_clk_src.clkr.hw,2534 },2535 .num_parents = 1,2536 .flags = CLK_SET_RATE_PARENT,2537 .ops = &clk_branch2_ops,2538 },2539 },2540};2541 2542static struct clk_branch gcc_tsif_ahb_clk = {2543 .halt_reg = 0x36004,2544 .halt_check = BRANCH_HALT,2545 .clkr = {2546 .enable_reg = 0x36004,2547 .enable_mask = BIT(0),2548 .hw.init = &(struct clk_init_data){2549 .name = "gcc_tsif_ahb_clk",2550 .ops = &clk_branch2_ops,2551 },2552 },2553};2554 2555static struct clk_branch gcc_tsif_inactivity_timers_clk = {2556 .halt_reg = 0x3600c,2557 .halt_check = BRANCH_HALT,2558 .clkr = {2559 .enable_reg = 0x3600c,2560 .enable_mask = BIT(0),2561 .hw.init = &(struct clk_init_data){2562 .name = "gcc_tsif_inactivity_timers_clk",2563 .ops = &clk_branch2_ops,2564 },2565 },2566};2567 2568static struct clk_branch gcc_tsif_ref_clk = {2569 .halt_reg = 0x36008,2570 .halt_check = BRANCH_HALT,2571 .clkr = {2572 .enable_reg = 0x36008,2573 .enable_mask = BIT(0),2574 .hw.init = &(struct clk_init_data){2575 .name = "gcc_tsif_ref_clk",2576 .parent_hws = (const struct clk_hw *[]) {2577 &tsif_ref_clk_src.clkr.hw,2578 },2579 .num_parents = 1,2580 .flags = CLK_SET_RATE_PARENT,2581 .ops = &clk_branch2_ops,2582 },2583 },2584};2585 2586static struct clk_branch gcc_ufs_ahb_clk = {2587 .halt_reg = 0x7500c,2588 .halt_check = BRANCH_HALT,2589 .clkr = {2590 .enable_reg = 0x7500c,2591 .enable_mask = BIT(0),2592 .hw.init = &(struct clk_init_data){2593 .name = "gcc_ufs_ahb_clk",2594 .ops = &clk_branch2_ops,2595 },2596 },2597};2598 2599static struct clk_branch gcc_ufs_axi_clk = {2600 .halt_reg = 0x75008,2601 .halt_check = BRANCH_HALT,2602 .clkr = {2603 .enable_reg = 0x75008,2604 .enable_mask = BIT(0),2605 .hw.init = &(struct clk_init_data){2606 .name = "gcc_ufs_axi_clk",2607 .parent_hws = (const struct clk_hw *[]) {2608 &ufs_axi_clk_src.clkr.hw,2609 },2610 .num_parents = 1,2611 .flags = CLK_SET_RATE_PARENT,2612 .ops = &clk_branch2_ops,2613 },2614 },2615};2616 2617static struct clk_branch gcc_ufs_ice_core_clk = {2618 .halt_reg = 0x7600c,2619 .halt_check = BRANCH_HALT,2620 .clkr = {2621 .enable_reg = 0x7600c,2622 .enable_mask = BIT(0),2623 .hw.init = &(struct clk_init_data){2624 .name = "gcc_ufs_ice_core_clk",2625 .ops = &clk_branch2_ops,2626 },2627 },2628};2629 2630static struct clk_branch gcc_ufs_phy_aux_clk = {2631 .halt_reg = 0x76040,2632 .halt_check = BRANCH_HALT,2633 .clkr = {2634 .enable_reg = 0x76040,2635 .enable_mask = BIT(0),2636 .hw.init = &(struct clk_init_data){2637 .name = "gcc_ufs_phy_aux_clk",2638 .ops = &clk_branch2_ops,2639 },2640 },2641};2642 2643static struct clk_branch gcc_ufs_rx_symbol_0_clk = {2644 .halt_reg = 0x75014,2645 .halt_check = BRANCH_HALT_SKIP,2646 .clkr = {2647 .enable_reg = 0x75014,2648 .enable_mask = BIT(0),2649 .hw.init = &(struct clk_init_data){2650 .name = "gcc_ufs_rx_symbol_0_clk",2651 .ops = &clk_branch2_ops,2652 },2653 },2654};2655 2656static struct clk_branch gcc_ufs_rx_symbol_1_clk = {2657 .halt_reg = 0x7605c,2658 .halt_check = BRANCH_HALT_SKIP,2659 .clkr = {2660 .enable_reg = 0x7605c,2661 .enable_mask = BIT(0),2662 .hw.init = &(struct clk_init_data){2663 .name = "gcc_ufs_rx_symbol_1_clk",2664 .ops = &clk_branch2_ops,2665 },2666 },2667};2668 2669static struct clk_branch gcc_ufs_tx_symbol_0_clk = {2670 .halt_reg = 0x75010,2671 .halt_check = BRANCH_HALT_SKIP,2672 .clkr = {2673 .enable_reg = 0x75010,2674 .enable_mask = BIT(0),2675 .hw.init = &(struct clk_init_data){2676 .name = "gcc_ufs_tx_symbol_0_clk",2677 .ops = &clk_branch2_ops,2678 },2679 },2680};2681 2682static struct clk_branch gcc_ufs_unipro_core_clk = {2683 .halt_reg = 0x76008,2684 .halt_check = BRANCH_HALT,2685 .clkr = {2686 .enable_reg = 0x76008,2687 .enable_mask = BIT(0),2688 .hw.init = &(struct clk_init_data){2689 .name = "gcc_ufs_unipro_core_clk",2690 .parent_hws = (const struct clk_hw *[]) {2691 &ufs_unipro_core_clk_src.clkr.hw,2692 },2693 .num_parents = 1,2694 .flags = CLK_SET_RATE_PARENT,2695 .ops = &clk_branch2_ops,2696 },2697 },2698};2699 2700static struct clk_branch gcc_usb30_master_clk = {2701 .halt_reg = 0xf008,2702 .halt_check = BRANCH_HALT,2703 .clkr = {2704 .enable_reg = 0xf008,2705 .enable_mask = BIT(0),2706 .hw.init = &(struct clk_init_data){2707 .name = "gcc_usb30_master_clk",2708 .parent_hws = (const struct clk_hw *[]) {2709 &usb30_master_clk_src.clkr.hw,2710 },2711 .num_parents = 1,2712 .flags = CLK_SET_RATE_PARENT,2713 .ops = &clk_branch2_ops,2714 },2715 },2716};2717 2718static struct clk_branch gcc_usb30_mock_utmi_clk = {2719 .halt_reg = 0xf010,2720 .halt_check = BRANCH_HALT,2721 .clkr = {2722 .enable_reg = 0xf010,2723 .enable_mask = BIT(0),2724 .hw.init = &(struct clk_init_data){2725 .name = "gcc_usb30_mock_utmi_clk",2726 .parent_hws = (const struct clk_hw *[]) {2727 &usb30_mock_utmi_clk_src.clkr.hw,2728 },2729 .num_parents = 1,2730 .flags = CLK_SET_RATE_PARENT,2731 .ops = &clk_branch2_ops,2732 },2733 },2734};2735 2736static struct clk_branch gcc_usb30_sleep_clk = {2737 .halt_reg = 0xf00c,2738 .halt_check = BRANCH_HALT,2739 .clkr = {2740 .enable_reg = 0xf00c,2741 .enable_mask = BIT(0),2742 .hw.init = &(struct clk_init_data){2743 .name = "gcc_usb30_sleep_clk",2744 .ops = &clk_branch2_ops,2745 },2746 },2747};2748 2749static struct clk_branch gcc_usb3_phy_aux_clk = {2750 .halt_reg = 0x50000,2751 .halt_check = BRANCH_HALT,2752 .clkr = {2753 .enable_reg = 0x50000,2754 .enable_mask = BIT(0),2755 .hw.init = &(struct clk_init_data){2756 .name = "gcc_usb3_phy_aux_clk",2757 .parent_hws = (const struct clk_hw *[]) {2758 &usb3_phy_aux_clk_src.clkr.hw,2759 },2760 .num_parents = 1,2761 .flags = CLK_SET_RATE_PARENT,2762 .ops = &clk_branch2_ops,2763 },2764 },2765};2766 2767static struct clk_branch gcc_usb3_phy_pipe_clk = {2768 .halt_reg = 0x50004,2769 .halt_check = BRANCH_HALT_SKIP,2770 .clkr = {2771 .enable_reg = 0x50004,2772 .enable_mask = BIT(0),2773 .hw.init = &(struct clk_init_data){2774 .name = "gcc_usb3_phy_pipe_clk",2775 .ops = &clk_branch2_ops,2776 },2777 },2778};2779 2780static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {2781 .halt_reg = 0x6a004,2782 .halt_check = BRANCH_HALT,2783 .clkr = {2784 .enable_reg = 0x6a004,2785 .enable_mask = BIT(0),2786 .hw.init = &(struct clk_init_data){2787 .name = "gcc_usb_phy_cfg_ahb2phy_clk",2788 .ops = &clk_branch2_ops,2789 },2790 },2791};2792 2793static struct clk_branch gcc_hdmi_clkref_clk = {2794 .halt_reg = 0x88000,2795 .clkr = {2796 .enable_reg = 0x88000,2797 .enable_mask = BIT(0),2798 .hw.init = &(struct clk_init_data){2799 .name = "gcc_hdmi_clkref_clk",2800 .parent_data = (const struct clk_parent_data []) {2801 { .fw_name = "xo" },2802 },2803 .num_parents = 1,2804 .ops = &clk_branch2_ops,2805 },2806 },2807};2808 2809static struct clk_branch gcc_ufs_clkref_clk = {2810 .halt_reg = 0x88004,2811 .clkr = {2812 .enable_reg = 0x88004,2813 .enable_mask = BIT(0),2814 .hw.init = &(struct clk_init_data){2815 .name = "gcc_ufs_clkref_clk",2816 .parent_data = (const struct clk_parent_data []) {2817 { .fw_name = "xo" },2818 },2819 .num_parents = 1,2820 .ops = &clk_branch2_ops,2821 },2822 },2823};2824 2825static struct clk_branch gcc_usb3_clkref_clk = {2826 .halt_reg = 0x88008,2827 .clkr = {2828 .enable_reg = 0x88008,2829 .enable_mask = BIT(0),2830 .hw.init = &(struct clk_init_data){2831 .name = "gcc_usb3_clkref_clk",2832 .parent_data = (const struct clk_parent_data []) {2833 { .fw_name = "xo" },2834 },2835 .num_parents = 1,2836 .ops = &clk_branch2_ops,2837 },2838 },2839};2840 2841static struct clk_branch gcc_pcie_clkref_clk = {2842 .halt_reg = 0x8800c,2843 .clkr = {2844 .enable_reg = 0x8800c,2845 .enable_mask = BIT(0),2846 .hw.init = &(struct clk_init_data){2847 .name = "gcc_pcie_clkref_clk",2848 .parent_data = (const struct clk_parent_data []) {2849 { .fw_name = "xo" },2850 },2851 .num_parents = 1,2852 .ops = &clk_branch2_ops,2853 },2854 },2855};2856 2857static struct clk_branch gcc_rx1_usb2_clkref_clk = {2858 .halt_reg = 0x88014,2859 .clkr = {2860 .enable_reg = 0x88014,2861 .enable_mask = BIT(0),2862 .hw.init = &(struct clk_init_data){2863 .name = "gcc_rx1_usb2_clkref_clk",2864 .parent_data = (const struct clk_parent_data []) {2865 { .fw_name = "xo" },2866 },2867 .num_parents = 1,2868 .ops = &clk_branch2_ops,2869 },2870 },2871};2872 2873static struct clk_branch gcc_im_sleep_clk = {2874 .halt_reg = 0x4300c,2875 .halt_check = BRANCH_HALT,2876 .clkr = {2877 .enable_reg = 0x4300c,2878 .enable_mask = BIT(0),2879 .hw.init = &(const struct clk_init_data){2880 .name = "gcc_im_sleep_clk",2881 .ops = &clk_branch2_ops,2882 },2883 },2884};2885 2886static struct clk_branch aggre2_snoc_north_axi_clk = {2887 .halt_reg = 0x83010,2888 .halt_check = BRANCH_HALT,2889 .clkr = {2890 .enable_reg = 0x83010,2891 .enable_mask = BIT(0),2892 .hw.init = &(const struct clk_init_data){2893 .name = "aggre2_snoc_north_axi_clk",2894 .ops = &clk_branch2_ops,2895 },2896 },2897};2898 2899static struct clk_branch ssc_xo_clk = {2900 .halt_reg = 0x63018,2901 .halt_check = BRANCH_HALT,2902 .clkr = {2903 .enable_reg = 0x63018,2904 .enable_mask = BIT(0),2905 .hw.init = &(const struct clk_init_data){2906 .name = "ssc_xo_clk",2907 .ops = &clk_branch2_ops,2908 },2909 },2910};2911 2912static struct clk_branch ssc_cnoc_ahbs_clk = {2913 .halt_reg = 0x6300c,2914 .halt_check = BRANCH_HALT,2915 .clkr = {2916 .enable_reg = 0x6300c,2917 .enable_mask = BIT(0),2918 .hw.init = &(const struct clk_init_data){2919 .name = "ssc_cnoc_ahbs_clk",2920 .ops = &clk_branch2_ops,2921 },2922 },2923};2924 2925static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {2926 .halt_reg = 0x7D010,2927 .clkr = {2928 .enable_reg = 0x7D010,2929 .enable_mask = BIT(0),2930 .hw.init = &(struct clk_init_data) {2931 .name = "hlos1_vote_lpass_core_smmu_clk",2932 .ops = &clk_branch2_ops,2933 },2934 },2935};2936 2937static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {2938 .halt_reg = 0x7D014,2939 .clkr = {2940 .enable_reg = 0x7D014,2941 .enable_mask = BIT(0),2942 .hw.init = &(struct clk_init_data) {2943 .name = "hlos1_vote_lpass_adsp_smmu_clk",2944 .ops = &clk_branch2_ops,2945 },2946 },2947};2948 2949static struct clk_branch gcc_mss_q6_bimc_axi_clk = {2950 .halt_reg = 0x8A040,2951 .clkr = {2952 .enable_reg = 0x8A040,2953 .enable_mask = BIT(0),2954 .hw.init = &(struct clk_init_data) {2955 .name = "gcc_mss_q6_bimc_axi_clk",2956 .flags = CLK_IS_CRITICAL,2957 .ops = &clk_branch2_ops,2958 },2959 },2960};2961 2962static struct gdsc pcie_0_gdsc = {2963 .gdscr = 0x6b004,2964 .gds_hw_ctrl = 0x0,2965 .pd = {2966 .name = "pcie_0_gdsc",2967 },2968 .pwrsts = PWRSTS_OFF_ON,2969 .flags = VOTABLE,2970};2971 2972static struct gdsc ufs_gdsc = {2973 .gdscr = 0x75004,2974 .gds_hw_ctrl = 0x0,2975 .pd = {2976 .name = "ufs_gdsc",2977 },2978 .pwrsts = PWRSTS_OFF_ON,2979 .flags = VOTABLE,2980};2981 2982static struct gdsc usb_30_gdsc = {2983 .gdscr = 0xf004,2984 .gds_hw_ctrl = 0x0,2985 .pd = {2986 .name = "usb_30_gdsc",2987 },2988 /* TODO: Change to OFF_ON when USB drivers get proper suspend support */2989 .pwrsts = PWRSTS_RET_ON,2990 .flags = VOTABLE,2991};2992 2993static struct gdsc hlos1_vote_lpass_adsp = {2994 .gdscr = 0x7d034,2995 .gds_hw_ctrl = 0x0,2996 .pd = {2997 .name = "lpass_adsp_gdsc",2998 },2999 .pwrsts = PWRSTS_OFF_ON,3000 .flags = VOTABLE,3001};3002 3003static struct gdsc hlos1_vote_lpass_core = {3004 .gdscr = 0x7d038,3005 .gds_hw_ctrl = 0x0,3006 .pd = {3007 .name = "lpass_core_gdsc",3008 },3009 .pwrsts = PWRSTS_OFF_ON,3010 .flags = ALWAYS_ON,3011};3012 3013static struct clk_regmap *gcc_msm8998_clocks[] = {3014 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,3015 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,3016 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,3017 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,3018 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,3019 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,3020 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,3021 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,3022 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,3023 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,3024 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,3025 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,3026 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,3027 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,3028 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,3029 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,3030 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,3031 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,3032 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,3033 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,3034 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,3035 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,3036 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,3037 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,3038 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,3039 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,3040 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,3041 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,3042 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,3043 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,3044 [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,3045 [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,3046 [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,3047 [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,3048 [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,3049 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,3050 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,3051 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,3052 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,3053 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,3054 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,3055 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,3056 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,3057 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,3058 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,3059 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,3060 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,3061 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,3062 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,3063 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,3064 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,3065 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,3066 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,3067 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,3068 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,3069 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,3070 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,3071 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,3072 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,3073 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,3074 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,3075 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,3076 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,3077 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,3078 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,3079 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,3080 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,3081 [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,3082 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,3083 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,3084 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,3085 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,3086 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,3087 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,3088 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,3089 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,3090 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,3091 [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,3092 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,3093 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,3094 [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,3095 [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,3096 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,3097 [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,3098 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,3099 [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,3100 [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,3101 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,3102 [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,3103 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,3104 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,3105 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,3106 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,3107 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,3108 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,3109 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,3110 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,3111 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,3112 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,3113 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,3114 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,3115 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,3116 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,3117 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,3118 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,3119 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,3120 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,3121 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,3122 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,3123 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,3124 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,3125 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,3126 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,3127 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,3128 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,3129 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,3130 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,3131 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,3132 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,3133 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,3134 [GP1_CLK_SRC] = &gp1_clk_src.clkr,3135 [GP2_CLK_SRC] = &gp2_clk_src.clkr,3136 [GP3_CLK_SRC] = &gp3_clk_src.clkr,3137 [GPLL0] = &gpll0.clkr,3138 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,3139 [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,3140 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,3141 [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,3142 [GPLL1] = &gpll1.clkr,3143 [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,3144 [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,3145 [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,3146 [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,3147 [GPLL2] = &gpll2.clkr,3148 [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,3149 [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,3150 [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,3151 [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,3152 [GPLL3] = &gpll3.clkr,3153 [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,3154 [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,3155 [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,3156 [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,3157 [GPLL4] = &gpll4.clkr,3158 [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,3159 [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,3160 [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,3161 [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,3162 [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,3163 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,3164 [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,3165 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,3166 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,3167 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,3168 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,3169 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,3170 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,3171 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,3172 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,3173 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,3174 [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,3175 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,3176 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,3177 [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,3178 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,3179 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,3180 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,3181 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,3182 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,3183 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,3184 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,3185 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,3186 [GCC_IM_SLEEP] = &gcc_im_sleep_clk.clkr,3187 [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr,3188 [SSC_XO] = &ssc_xo_clk.clkr,3189 [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr,3190 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,3191 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,3192 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,3193 [HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &hlos1_vote_lpass_core_smmu_clk.clkr,3194 [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr,3195 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,3196};3197 3198static struct gdsc *gcc_msm8998_gdscs[] = {3199 [PCIE_0_GDSC] = &pcie_0_gdsc,3200 [UFS_GDSC] = &ufs_gdsc,3201 [USB_30_GDSC] = &usb_30_gdsc,3202 [LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp,3203 [LPASS_CORE_GDSC] = &hlos1_vote_lpass_core,3204};3205 3206static const struct qcom_reset_map gcc_msm8998_resets[] = {3207 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },3208 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },3209 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },3210 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },3211 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },3212 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },3213 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },3214 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },3215 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },3216 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },3217 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },3218 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },3219 [GCC_PCIE_0_BCR] = { 0x6b000 },3220 [GCC_PDM_BCR] = { 0x33000 },3221 [GCC_SDCC2_BCR] = { 0x14000 },3222 [GCC_SDCC4_BCR] = { 0x16000 },3223 [GCC_TSIF_BCR] = { 0x36000 },3224 [GCC_UFS_BCR] = { 0x75000 },3225 [GCC_USB_30_BCR] = { 0xf000 },3226 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },3227 [GCC_CONFIG_NOC_BCR] = { 0x5000 },3228 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },3229 [GCC_IMEM_BCR] = { 0x8000 },3230 [GCC_PIMEM_BCR] = { 0xa000 },3231 [GCC_MMSS_BCR] = { 0xb000 },3232 [GCC_QDSS_BCR] = { 0xc000 },3233 [GCC_WCSS_BCR] = { 0x11000 },3234 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },3235 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },3236 [GCC_BLSP1_BCR] = { 0x17000 },3237 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },3238 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },3239 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },3240 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },3241 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },3242 [GCC_BLSP2_BCR] = { 0x25000 },3243 [GCC_BLSP2_UART1_BCR] = { 0x27000 },3244 [GCC_BLSP2_UART2_BCR] = { 0x29000 },3245 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },3246 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },3247 [GCC_PRNG_BCR] = { 0x34000 },3248 [GCC_TSIF_0_RESET] = { 0x36024 },3249 [GCC_TSIF_1_RESET] = { 0x36028 },3250 [GCC_TCSR_BCR] = { 0x37000 },3251 [GCC_BOOT_ROM_BCR] = { 0x38000 },3252 [GCC_MSG_RAM_BCR] = { 0x39000 },3253 [GCC_TLMM_BCR] = { 0x3a000 },3254 [GCC_MPM_BCR] = { 0x3b000 },3255 [GCC_SEC_CTRL_BCR] = { 0x3d000 },3256 [GCC_SPMI_BCR] = { 0x3f000 },3257 [GCC_SPDM_BCR] = { 0x40000 },3258 [GCC_CE1_BCR] = { 0x41000 },3259 [GCC_BIMC_BCR] = { 0x44000 },3260 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },3261 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },3262 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },3263 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },3264 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },3265 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },3266 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },3267 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },3268 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },3269 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },3270 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },3271 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },3272 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },3273 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },3274 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },3275 [GCC_APB2JTAG_BCR] = { 0x4c000 },3276 [GCC_RBCPR_CX_BCR] = { 0x4e000 },3277 [GCC_RBCPR_MX_BCR] = { 0x4f000 },3278 [GCC_USB3_PHY_BCR] = { 0x50020 },3279 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },3280 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },3281 [GCC_SSC_BCR] = { 0x63000 },3282 [GCC_SSC_RESET] = { 0x63020 },3283 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },3284 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },3285 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },3286 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },3287 [GCC_PCIE_PHY_BCR] = { 0x6f000 },3288 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },3289 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },3290 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },3291 [GCC_GPU_BCR] = { 0x71000 },3292 [GCC_SPSS_BCR] = { 0x72000 },3293 [GCC_OBT_ODT_BCR] = { 0x73000 },3294 [GCC_MSS_RESTART] = { 0x79000 },3295 [GCC_VS_BCR] = { 0x7a000 },3296 [GCC_MSS_VS_RESET] = { 0x7a100 },3297 [GCC_GPU_VS_RESET] = { 0x7a104 },3298 [GCC_APC0_VS_RESET] = { 0x7a108 },3299 [GCC_APC1_VS_RESET] = { 0x7a10c },3300 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },3301 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },3302 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },3303 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },3304 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },3305 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },3306 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },3307 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },3308 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },3309 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },3310 [GCC_DCC_BCR] = { 0x84000 },3311 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },3312 [GCC_IPA_BCR] = { 0x89000 },3313 [GCC_GLM_BCR] = { 0x8b000 },3314 [GCC_SKL_BCR] = { 0x8c000 },3315 [GCC_MSMPU_BCR] = { 0x8d000 },3316};3317 3318static const struct regmap_config gcc_msm8998_regmap_config = {3319 .reg_bits = 32,3320 .reg_stride = 4,3321 .val_bits = 32,3322 .max_register = 0x8f000,3323 .fast_io = true,3324};3325 3326static const struct qcom_cc_desc gcc_msm8998_desc = {3327 .config = &gcc_msm8998_regmap_config,3328 .clks = gcc_msm8998_clocks,3329 .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),3330 .resets = gcc_msm8998_resets,3331 .num_resets = ARRAY_SIZE(gcc_msm8998_resets),3332 .gdscs = gcc_msm8998_gdscs,3333 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),3334};3335 3336static int gcc_msm8998_probe(struct platform_device *pdev)3337{3338 struct regmap *regmap;3339 int ret;3340 3341 regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);3342 if (IS_ERR(regmap))3343 return PTR_ERR(regmap);3344 3345 /*3346 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be3347 * turned off by hardware during certain apps low power modes.3348 */3349 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));3350 if (ret)3351 return ret;3352 3353 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */3354 regmap_write(regmap, GCC_MMSS_MISC, 0x10003);3355 regmap_write(regmap, GCC_GPU_MISC, 0x10003);3356 3357 return qcom_cc_really_probe(&pdev->dev, &gcc_msm8998_desc, regmap);3358}3359 3360static const struct of_device_id gcc_msm8998_match_table[] = {3361 { .compatible = "qcom,gcc-msm8998" },3362 { }3363};3364MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);3365 3366static struct platform_driver gcc_msm8998_driver = {3367 .probe = gcc_msm8998_probe,3368 .driver = {3369 .name = "gcc-msm8998",3370 .of_match_table = gcc_msm8998_match_table,3371 },3372};3373 3374static int __init gcc_msm8998_init(void)3375{3376 return platform_driver_register(&gcc_msm8998_driver);3377}3378core_initcall(gcc_msm8998_init);3379 3380static void __exit gcc_msm8998_exit(void)3381{3382 platform_driver_unregister(&gcc_msm8998_driver);3383}3384module_exit(gcc_msm8998_exit);3385 3386MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");3387MODULE_LICENSE("GPL v2");3388MODULE_ALIAS("platform:gcc-msm8998");3389