4679 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.4 * Copyright (c) 2020-2021, Linaro Ltd.5 */6 7#include <linux/bitops.h>8#include <linux/clk-provider.h>9#include <linux/err.h>10#include <linux/kernel.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/platform_device.h>14#include <linux/regmap.h>15#include <linux/reset-controller.h>16 17#include <dt-bindings/clock/qcom,gcc-sc8180x.h>18 19#include "common.h"20#include "clk-alpha-pll.h"21#include "clk-branch.h"22#include "clk-pll.h"23#include "clk-rcg.h"24#include "clk-regmap.h"25#include "gdsc.h"26#include "reset.h"27 28enum {29 P_AUD_REF_CLK,30 P_BI_TCXO,31 P_GPLL0_OUT_EVEN,32 P_GPLL0_OUT_MAIN,33 P_GPLL1_OUT_MAIN,34 P_GPLL2_OUT_MAIN,35 P_GPLL4_OUT_MAIN,36 P_GPLL5_OUT_MAIN,37 P_GPLL7_OUT_MAIN,38 P_GPLL9_OUT_MAIN,39 P_SLEEP_CLK,40};41 42static const struct pll_vco trion_vco[] = {43 { 249600000, 2000000000, 0 },44};45 46static struct clk_alpha_pll gpll0 = {47 .offset = 0x0,48 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],49 .vco_table = trion_vco,50 .num_vco = ARRAY_SIZE(trion_vco),51 .clkr = {52 .enable_reg = 0x52000,53 .enable_mask = BIT(0),54 .hw.init = &(struct clk_init_data){55 .name = "gpll0",56 .parent_data = &(const struct clk_parent_data){57 .fw_name = "bi_tcxo",58 },59 .num_parents = 1,60 .ops = &clk_alpha_pll_fixed_trion_ops,61 },62 },63};64 65static const struct clk_div_table post_div_table_trion_even[] = {66 { 0x0, 1 },67 { 0x1, 2 },68 { 0x3, 4 },69 { 0x7, 8 },70 { }71};72 73static struct clk_alpha_pll_postdiv gpll0_out_even = {74 .offset = 0x0,75 .post_div_shift = 8,76 .post_div_table = post_div_table_trion_even,77 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],79 .width = 4,80 .clkr.hw.init = &(struct clk_init_data){81 .name = "gpll0_out_even",82 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },83 .num_parents = 1,84 .ops = &clk_alpha_pll_postdiv_trion_ops,85 },86};87 88static struct clk_alpha_pll gpll1 = {89 .offset = 0x1000,90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],91 .vco_table = trion_vco,92 .num_vco = ARRAY_SIZE(trion_vco),93 .clkr = {94 .enable_reg = 0x52000,95 .enable_mask = BIT(1),96 .hw.init = &(struct clk_init_data){97 .name = "gpll1",98 .parent_data = &(const struct clk_parent_data){99 .fw_name = "bi_tcxo",100 },101 .num_parents = 1,102 .ops = &clk_alpha_pll_fixed_trion_ops,103 },104 },105};106 107static struct clk_alpha_pll gpll4 = {108 .offset = 0x76000,109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],110 .vco_table = trion_vco,111 .num_vco = ARRAY_SIZE(trion_vco),112 .clkr = {113 .enable_reg = 0x52000,114 .enable_mask = BIT(4),115 .hw.init = &(struct clk_init_data){116 .name = "gpll4",117 .parent_data = &(const struct clk_parent_data){118 .fw_name = "bi_tcxo",119 },120 .num_parents = 1,121 .ops = &clk_alpha_pll_fixed_trion_ops,122 },123 },124};125 126static struct clk_alpha_pll gpll7 = {127 .offset = 0x1a000,128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],129 .vco_table = trion_vco,130 .num_vco = ARRAY_SIZE(trion_vco),131 .clkr = {132 .enable_reg = 0x52000,133 .enable_mask = BIT(7),134 .hw.init = &(struct clk_init_data){135 .name = "gpll7",136 .parent_data = &(const struct clk_parent_data){137 .fw_name = "bi_tcxo",138 },139 .num_parents = 1,140 .ops = &clk_alpha_pll_fixed_trion_ops,141 },142 },143};144 145static struct clk_alpha_pll gpll9 = {146 .offset = 0x1c000,147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],148 .clkr = {149 .enable_reg = 0x52000,150 .enable_mask = BIT(9),151 .hw.init = &(const struct clk_init_data) {152 .name = "gpll9",153 .parent_data = &(const struct clk_parent_data) {154 .fw_name = "bi_tcxo",155 },156 .num_parents = 1,157 .ops = &clk_alpha_pll_fixed_trion_ops,158 },159 },160};161 162static const struct parent_map gcc_parent_map_0[] = {163 { P_BI_TCXO, 0 },164 { P_GPLL0_OUT_MAIN, 1 },165 { P_GPLL0_OUT_EVEN, 6 },166};167 168static const struct clk_parent_data gcc_parents_0[] = {169 { .fw_name = "bi_tcxo" },170 { .hw = &gpll0.clkr.hw },171 { .hw = &gpll0_out_even.clkr.hw },172};173 174static const struct parent_map gcc_parent_map_1[] = {175 { P_BI_TCXO, 0 },176 { P_GPLL0_OUT_MAIN, 1 },177 { P_SLEEP_CLK, 5 },178 { P_GPLL0_OUT_EVEN, 6 },179};180 181static const struct clk_parent_data gcc_parents_1[] = {182 { .fw_name = "bi_tcxo", },183 { .hw = &gpll0.clkr.hw },184 { .fw_name = "sleep_clk", },185 { .hw = &gpll0_out_even.clkr.hw },186};187 188static const struct parent_map gcc_parent_map_2[] = {189 { P_BI_TCXO, 0 },190 { P_SLEEP_CLK, 5 },191};192 193static const struct clk_parent_data gcc_parents_2[] = {194 { .fw_name = "bi_tcxo", },195 { .fw_name = "sleep_clk", },196};197 198static const struct parent_map gcc_parent_map_3[] = {199 { P_BI_TCXO, 0 },200 { P_GPLL0_OUT_MAIN, 1 },201 { P_GPLL2_OUT_MAIN, 2 },202 { P_GPLL5_OUT_MAIN, 3 },203 { P_GPLL1_OUT_MAIN, 4 },204 { P_GPLL4_OUT_MAIN, 5 },205 { P_GPLL0_OUT_EVEN, 6 },206};207 208static const struct clk_parent_data gcc_parents_3[] = {209 { .fw_name = "bi_tcxo", },210 { .hw = &gpll0.clkr.hw },211 { .name = "gpll2" },212 { .name = "gpll5" },213 { .hw = &gpll1.clkr.hw },214 { .hw = &gpll4.clkr.hw },215 { .hw = &gpll0_out_even.clkr.hw },216};217 218static const struct parent_map gcc_parent_map_4[] = {219 { P_BI_TCXO, 0 },220};221 222static const struct clk_parent_data gcc_parents_4[] = {223 { .fw_name = "bi_tcxo", },224};225 226static const struct parent_map gcc_parent_map_5[] = {227 { P_BI_TCXO, 0 },228 { P_GPLL0_OUT_MAIN, 1 },229};230 231static const struct clk_parent_data gcc_parents_5[] = {232 { .fw_name = "bi_tcxo", },233 { .hw = &gpll0.clkr.hw },234};235 236static const struct parent_map gcc_parent_map_6[] = {237 { P_BI_TCXO, 0 },238 { P_GPLL0_OUT_MAIN, 1 },239 { P_GPLL7_OUT_MAIN, 3 },240 { P_GPLL0_OUT_EVEN, 6 },241};242 243static const struct clk_parent_data gcc_parents_6[] = {244 { .fw_name = "bi_tcxo", },245 { .hw = &gpll0.clkr.hw },246 { .hw = &gpll7.clkr.hw },247 { .hw = &gpll0_out_even.clkr.hw },248};249 250static const struct parent_map gcc_parent_map_7[] = {251 { P_BI_TCXO, 0 },252 { P_GPLL0_OUT_MAIN, 1 },253 { P_GPLL9_OUT_MAIN, 2 },254 { P_GPLL4_OUT_MAIN, 5 },255 { P_GPLL0_OUT_EVEN, 6 },256};257 258static const struct clk_parent_data gcc_parents_7[] = {259 { .fw_name = "bi_tcxo", },260 { .hw = &gpll0.clkr.hw },261 { .hw = &gpll9.clkr.hw },262 { .hw = &gpll4.clkr.hw },263 { .hw = &gpll0_out_even.clkr.hw },264};265 266static const struct parent_map gcc_parent_map_8[] = {267 { P_BI_TCXO, 0 },268 { P_GPLL0_OUT_MAIN, 1 },269 { P_AUD_REF_CLK, 2 },270 { P_GPLL0_OUT_EVEN, 6 },271};272 273static const struct clk_parent_data gcc_parents_8[] = {274 { .fw_name = "bi_tcxo", },275 { .hw = &gpll0.clkr.hw },276 { .name = "aud_ref_clk" },277 { .hw = &gpll0_out_even.clkr.hw },278};279 280static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {281 F(19200000, P_BI_TCXO, 1, 0, 0),282 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),283 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),284 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),285 { }286};287 288static struct clk_rcg2 gcc_emac_ptp_clk_src = {289 .cmd_rcgr = 0x6038,290 .mnd_width = 0,291 .hid_width = 5,292 .parent_map = gcc_parent_map_6,293 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,294 .clkr.hw.init = &(struct clk_init_data){295 .name = "gcc_emac_ptp_clk_src",296 .parent_data = gcc_parents_6,297 .num_parents = ARRAY_SIZE(gcc_parents_6),298 .flags = CLK_SET_RATE_PARENT,299 .ops = &clk_rcg2_ops,300 },301};302 303static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {304 F(2500000, P_BI_TCXO, 1, 25, 192),305 F(5000000, P_BI_TCXO, 1, 25, 96),306 F(19200000, P_BI_TCXO, 1, 0, 0),307 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),308 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),309 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),310 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),311 { }312};313 314static struct clk_rcg2 gcc_emac_rgmii_clk_src = {315 .cmd_rcgr = 0x601c,316 .mnd_width = 8,317 .hid_width = 5,318 .parent_map = gcc_parent_map_6,319 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,320 .clkr.hw.init = &(struct clk_init_data){321 .name = "gcc_emac_rgmii_clk_src",322 .parent_data = gcc_parents_6,323 .num_parents = ARRAY_SIZE(gcc_parents_6),324 .flags = CLK_SET_RATE_PARENT,325 .ops = &clk_rcg2_ops,326 },327};328 329static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {330 F(19200000, P_BI_TCXO, 1, 0, 0),331 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),332 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),333 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),334 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),335 { }336};337 338static struct clk_rcg2 gcc_gp1_clk_src = {339 .cmd_rcgr = 0x64004,340 .mnd_width = 8,341 .hid_width = 5,342 .parent_map = gcc_parent_map_1,343 .freq_tbl = ftbl_gcc_gp1_clk_src,344 .clkr.hw.init = &(struct clk_init_data){345 .name = "gcc_gp1_clk_src",346 .parent_data = gcc_parents_1,347 .num_parents = ARRAY_SIZE(gcc_parents_1),348 .flags = CLK_SET_RATE_PARENT,349 .ops = &clk_rcg2_ops,350 },351};352 353static struct clk_rcg2 gcc_gp2_clk_src = {354 .cmd_rcgr = 0x65004,355 .mnd_width = 8,356 .hid_width = 5,357 .parent_map = gcc_parent_map_1,358 .freq_tbl = ftbl_gcc_gp1_clk_src,359 .clkr.hw.init = &(struct clk_init_data){360 .name = "gcc_gp2_clk_src",361 .parent_data = gcc_parents_1,362 .num_parents = ARRAY_SIZE(gcc_parents_1),363 .flags = CLK_SET_RATE_PARENT,364 .ops = &clk_rcg2_ops,365 },366};367 368static struct clk_rcg2 gcc_gp3_clk_src = {369 .cmd_rcgr = 0x66004,370 .mnd_width = 8,371 .hid_width = 5,372 .parent_map = gcc_parent_map_1,373 .freq_tbl = ftbl_gcc_gp1_clk_src,374 .clkr.hw.init = &(struct clk_init_data){375 .name = "gcc_gp3_clk_src",376 .parent_data = gcc_parents_1,377 .num_parents = ARRAY_SIZE(gcc_parents_1),378 .flags = CLK_SET_RATE_PARENT,379 .ops = &clk_rcg2_ops,380 },381};382 383static struct clk_rcg2 gcc_gp4_clk_src = {384 .cmd_rcgr = 0xbe004,385 .mnd_width = 8,386 .hid_width = 5,387 .parent_map = gcc_parent_map_1,388 .freq_tbl = ftbl_gcc_gp1_clk_src,389 .clkr.hw.init = &(struct clk_init_data){390 .name = "gcc_gp4_clk_src",391 .parent_data = gcc_parents_1,392 .num_parents = ARRAY_SIZE(gcc_parents_1),393 .flags = CLK_SET_RATE_PARENT,394 .ops = &clk_rcg2_ops,395 },396};397 398static struct clk_rcg2 gcc_gp5_clk_src = {399 .cmd_rcgr = 0xbf004,400 .mnd_width = 8,401 .hid_width = 5,402 .parent_map = gcc_parent_map_1,403 .freq_tbl = ftbl_gcc_gp1_clk_src,404 .clkr.hw.init = &(struct clk_init_data){405 .name = "gcc_gp5_clk_src",406 .parent_data = gcc_parents_1,407 .num_parents = ARRAY_SIZE(gcc_parents_1),408 .flags = CLK_SET_RATE_PARENT,409 .ops = &clk_rcg2_ops,410 },411};412 413static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {414 F(19200000, P_BI_TCXO, 1, 0, 0),415 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),416 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),417 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),419 F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),420 F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),421 { }422};423 424static struct clk_rcg2 gcc_npu_axi_clk_src = {425 .cmd_rcgr = 0x4d014,426 .mnd_width = 0,427 .hid_width = 5,428 .parent_map = gcc_parent_map_3,429 .freq_tbl = ftbl_gcc_npu_axi_clk_src,430 .clkr.hw.init = &(struct clk_init_data){431 .name = "gcc_npu_axi_clk_src",432 .parent_data = gcc_parents_3,433 .num_parents = ARRAY_SIZE(gcc_parents_3),434 .flags = CLK_SET_RATE_PARENT,435 .ops = &clk_rcg2_ops,436 },437};438 439static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {440 F(9600000, P_BI_TCXO, 2, 0, 0),441 F(19200000, P_BI_TCXO, 1, 0, 0),442 { }443};444 445static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {446 .cmd_rcgr = 0x6b02c,447 .mnd_width = 16,448 .hid_width = 5,449 .parent_map = gcc_parent_map_2,450 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,451 .clkr.hw.init = &(struct clk_init_data){452 .name = "gcc_pcie_0_aux_clk_src",453 .parent_data = gcc_parents_2,454 .num_parents = ARRAY_SIZE(gcc_parents_2),455 .flags = CLK_SET_RATE_PARENT,456 .ops = &clk_rcg2_ops,457 },458};459 460static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {461 .cmd_rcgr = 0x8d02c,462 .mnd_width = 16,463 .hid_width = 5,464 .parent_map = gcc_parent_map_2,465 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,466 .clkr.hw.init = &(struct clk_init_data){467 .name = "gcc_pcie_1_aux_clk_src",468 .parent_data = gcc_parents_2,469 .num_parents = ARRAY_SIZE(gcc_parents_2),470 .flags = CLK_SET_RATE_PARENT,471 .ops = &clk_rcg2_ops,472 },473};474 475static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {476 .cmd_rcgr = 0x9d02c,477 .mnd_width = 16,478 .hid_width = 5,479 .parent_map = gcc_parent_map_2,480 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,481 .clkr.hw.init = &(struct clk_init_data){482 .name = "gcc_pcie_2_aux_clk_src",483 .parent_data = gcc_parents_2,484 .num_parents = ARRAY_SIZE(gcc_parents_2),485 .flags = CLK_SET_RATE_PARENT,486 .ops = &clk_rcg2_ops,487 },488};489 490static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {491 .cmd_rcgr = 0xa302c,492 .mnd_width = 16,493 .hid_width = 5,494 .parent_map = gcc_parent_map_2,495 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,496 .clkr.hw.init = &(struct clk_init_data){497 .name = "gcc_pcie_3_aux_clk_src",498 .parent_data = gcc_parents_2,499 .num_parents = ARRAY_SIZE(gcc_parents_2),500 .flags = CLK_SET_RATE_PARENT,501 .ops = &clk_rcg2_ops,502 },503};504 505static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {506 F(19200000, P_BI_TCXO, 1, 0, 0),507 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),508 { }509};510 511static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {512 .cmd_rcgr = 0x6f014,513 .mnd_width = 0,514 .hid_width = 5,515 .parent_map = gcc_parent_map_0,516 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,517 .clkr.hw.init = &(struct clk_init_data){518 .name = "gcc_pcie_phy_refgen_clk_src",519 .parent_data = gcc_parents_0,520 .num_parents = ARRAY_SIZE(gcc_parents_0),521 .flags = CLK_SET_RATE_PARENT,522 .ops = &clk_rcg2_ops,523 },524};525 526static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {527 F(9600000, P_BI_TCXO, 2, 0, 0),528 F(19200000, P_BI_TCXO, 1, 0, 0),529 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),530 { }531};532 533static struct clk_rcg2 gcc_pdm2_clk_src = {534 .cmd_rcgr = 0x33010,535 .mnd_width = 0,536 .hid_width = 5,537 .parent_map = gcc_parent_map_0,538 .freq_tbl = ftbl_gcc_pdm2_clk_src,539 .clkr.hw.init = &(struct clk_init_data){540 .name = "gcc_pdm2_clk_src",541 .parent_data = gcc_parents_0,542 .num_parents = ARRAY_SIZE(gcc_parents_0),543 .flags = CLK_SET_RATE_PARENT,544 .ops = &clk_rcg2_ops,545 },546};547 548static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = {549 F(19200000, P_BI_TCXO, 1, 0, 0),550 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),551 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),552 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),553 { }554};555 556static struct clk_rcg2 gcc_qspi_1_core_clk_src = {557 .cmd_rcgr = 0x4a00c,558 .mnd_width = 0,559 .hid_width = 5,560 .parent_map = gcc_parent_map_0,561 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src,562 .clkr.hw.init = &(struct clk_init_data){563 .name = "gcc_qspi_1_core_clk_src",564 .parent_data = gcc_parents_0,565 .num_parents = ARRAY_SIZE(gcc_parents_0),566 .flags = CLK_SET_RATE_PARENT,567 .ops = &clk_rcg2_ops,568 },569};570 571static struct clk_rcg2 gcc_qspi_core_clk_src = {572 .cmd_rcgr = 0x4b008,573 .mnd_width = 0,574 .hid_width = 5,575 .parent_map = gcc_parent_map_0,576 .freq_tbl = ftbl_gcc_qspi_1_core_clk_src,577 .clkr.hw.init = &(struct clk_init_data){578 .name = "gcc_qspi_core_clk_src",579 .parent_data = gcc_parents_0,580 .num_parents = ARRAY_SIZE(gcc_parents_0),581 .flags = CLK_SET_RATE_PARENT,582 .ops = &clk_rcg2_ops,583 },584};585 586static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {587 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),588 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),589 F(19200000, P_BI_TCXO, 1, 0, 0),590 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),591 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),592 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),593 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),594 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),595 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),596 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),597 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),598 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),599 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),600 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),601 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),602 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),603 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),604 { }605};606 607static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {608 .name = "gcc_qupv3_wrap0_s0_clk_src",609 .parent_data = gcc_parents_0,610 .num_parents = ARRAY_SIZE(gcc_parents_0),611 .flags = CLK_SET_RATE_PARENT,612 .ops = &clk_rcg2_ops,613};614 615static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {616 .cmd_rcgr = 0x17148,617 .mnd_width = 16,618 .hid_width = 5,619 .parent_map = gcc_parent_map_0,620 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,621 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,622};623 624static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {625 .name = "gcc_qupv3_wrap0_s1_clk_src",626 .parent_data = gcc_parents_0,627 .num_parents = ARRAY_SIZE(gcc_parents_0),628 .flags = CLK_SET_RATE_PARENT,629 .ops = &clk_rcg2_ops,630};631 632static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {633 .cmd_rcgr = 0x17278,634 .mnd_width = 16,635 .hid_width = 5,636 .parent_map = gcc_parent_map_0,637 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,638 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,639};640 641static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {642 .name = "gcc_qupv3_wrap0_s2_clk_src",643 .parent_data = gcc_parents_0,644 .num_parents = ARRAY_SIZE(gcc_parents_0),645 .flags = CLK_SET_RATE_PARENT,646 .ops = &clk_rcg2_ops,647};648 649static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {650 .cmd_rcgr = 0x173a8,651 .mnd_width = 16,652 .hid_width = 5,653 .parent_map = gcc_parent_map_0,654 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,655 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,656};657 658static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {659 .name = "gcc_qupv3_wrap0_s3_clk_src",660 .parent_data = gcc_parents_0,661 .num_parents = ARRAY_SIZE(gcc_parents_0),662 .flags = CLK_SET_RATE_PARENT,663 .ops = &clk_rcg2_ops,664};665 666static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {667 .cmd_rcgr = 0x174d8,668 .mnd_width = 16,669 .hid_width = 5,670 .parent_map = gcc_parent_map_0,671 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,672 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,673};674 675static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {676 .name = "gcc_qupv3_wrap0_s4_clk_src",677 .parent_data = gcc_parents_0,678 .num_parents = ARRAY_SIZE(gcc_parents_0),679 .flags = CLK_SET_RATE_PARENT,680 .ops = &clk_rcg2_ops,681};682 683static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {684 .cmd_rcgr = 0x17608,685 .mnd_width = 16,686 .hid_width = 5,687 .parent_map = gcc_parent_map_0,688 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,689 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,690};691 692static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {693 .name = "gcc_qupv3_wrap0_s5_clk_src",694 .parent_data = gcc_parents_0,695 .num_parents = ARRAY_SIZE(gcc_parents_0),696 .flags = CLK_SET_RATE_PARENT,697 .ops = &clk_rcg2_ops,698};699 700static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {701 .cmd_rcgr = 0x17738,702 .mnd_width = 16,703 .hid_width = 5,704 .parent_map = gcc_parent_map_0,705 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,706 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,707};708 709static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {710 .name = "gcc_qupv3_wrap0_s6_clk_src",711 .parent_data = gcc_parents_0,712 .num_parents = ARRAY_SIZE(gcc_parents_0),713 .flags = CLK_SET_RATE_PARENT,714 .ops = &clk_rcg2_ops,715};716 717static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {718 .cmd_rcgr = 0x17868,719 .mnd_width = 16,720 .hid_width = 5,721 .parent_map = gcc_parent_map_0,722 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,723 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,724};725 726static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {727 .name = "gcc_qupv3_wrap0_s7_clk_src",728 .parent_data = gcc_parents_0,729 .num_parents = ARRAY_SIZE(gcc_parents_0),730 .flags = CLK_SET_RATE_PARENT,731 .ops = &clk_rcg2_ops,732};733 734static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {735 .cmd_rcgr = 0x17998,736 .mnd_width = 16,737 .hid_width = 5,738 .parent_map = gcc_parent_map_0,739 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,740 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,741};742 743static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {744 .name = "gcc_qupv3_wrap1_s0_clk_src",745 .parent_data = gcc_parents_0,746 .num_parents = ARRAY_SIZE(gcc_parents_0),747 .flags = CLK_SET_RATE_PARENT,748 .ops = &clk_rcg2_ops,749};750 751static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {752 .cmd_rcgr = 0x18148,753 .mnd_width = 16,754 .hid_width = 5,755 .parent_map = gcc_parent_map_0,756 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,757 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,758};759 760static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {761 .name = "gcc_qupv3_wrap1_s1_clk_src",762 .parent_data = gcc_parents_0,763 .num_parents = ARRAY_SIZE(gcc_parents_0),764 .flags = CLK_SET_RATE_PARENT,765 .ops = &clk_rcg2_ops,766};767 768static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {769 .cmd_rcgr = 0x18278,770 .mnd_width = 16,771 .hid_width = 5,772 .parent_map = gcc_parent_map_0,773 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,774 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,775};776 777static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {778 .name = "gcc_qupv3_wrap1_s2_clk_src",779 .parent_data = gcc_parents_0,780 .num_parents = ARRAY_SIZE(gcc_parents_0),781 .flags = CLK_SET_RATE_PARENT,782 .ops = &clk_rcg2_ops,783};784 785static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {786 .cmd_rcgr = 0x183a8,787 .mnd_width = 16,788 .hid_width = 5,789 .parent_map = gcc_parent_map_0,790 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,791 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,792};793 794static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {795 .name = "gcc_qupv3_wrap1_s3_clk_src",796 .parent_data = gcc_parents_0,797 .num_parents = ARRAY_SIZE(gcc_parents_0),798 .flags = CLK_SET_RATE_PARENT,799 .ops = &clk_rcg2_ops,800};801 802static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {803 .cmd_rcgr = 0x184d8,804 .mnd_width = 16,805 .hid_width = 5,806 .parent_map = gcc_parent_map_0,807 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,808 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,809};810 811static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {812 .name = "gcc_qupv3_wrap1_s4_clk_src",813 .parent_data = gcc_parents_0,814 .num_parents = ARRAY_SIZE(gcc_parents_0),815 .flags = CLK_SET_RATE_PARENT,816 .ops = &clk_rcg2_ops,817};818 819static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {820 .cmd_rcgr = 0x18608,821 .mnd_width = 16,822 .hid_width = 5,823 .parent_map = gcc_parent_map_0,824 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,825 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,826};827 828static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {829 .name = "gcc_qupv3_wrap1_s5_clk_src",830 .parent_data = gcc_parents_0,831 .num_parents = ARRAY_SIZE(gcc_parents_0),832 .flags = CLK_SET_RATE_PARENT,833 .ops = &clk_rcg2_ops,834};835 836static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {837 .cmd_rcgr = 0x18738,838 .mnd_width = 16,839 .hid_width = 5,840 .parent_map = gcc_parent_map_0,841 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,842 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,843};844 845static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {846 .name = "gcc_qupv3_wrap2_s0_clk_src",847 .parent_data = gcc_parents_0,848 .num_parents = ARRAY_SIZE(gcc_parents_0),849 .flags = CLK_SET_RATE_PARENT,850 .ops = &clk_rcg2_ops,851};852 853static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {854 .cmd_rcgr = 0x1e148,855 .mnd_width = 16,856 .hid_width = 5,857 .parent_map = gcc_parent_map_0,858 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,859 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,860};861 862static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {863 .name = "gcc_qupv3_wrap2_s1_clk_src",864 .parent_data = gcc_parents_0,865 .num_parents = ARRAY_SIZE(gcc_parents_0),866 .flags = CLK_SET_RATE_PARENT,867 .ops = &clk_rcg2_ops,868};869 870static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {871 .cmd_rcgr = 0x1e278,872 .mnd_width = 16,873 .hid_width = 5,874 .parent_map = gcc_parent_map_0,875 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,876 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,877};878 879static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {880 .name = "gcc_qupv3_wrap2_s2_clk_src",881 .parent_data = gcc_parents_0,882 .num_parents = ARRAY_SIZE(gcc_parents_0),883 .flags = CLK_SET_RATE_PARENT,884 .ops = &clk_rcg2_ops,885};886 887 888static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {889 .cmd_rcgr = 0x1e3a8,890 .mnd_width = 16,891 .hid_width = 5,892 .parent_map = gcc_parent_map_0,893 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,894 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,895};896 897static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {898 .name = "gcc_qupv3_wrap2_s3_clk_src",899 .parent_data = gcc_parents_0,900 .num_parents = ARRAY_SIZE(gcc_parents_0),901 .flags = CLK_SET_RATE_PARENT,902 .ops = &clk_rcg2_ops,903};904 905static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {906 .cmd_rcgr = 0x1e4d8,907 .mnd_width = 16,908 .hid_width = 5,909 .parent_map = gcc_parent_map_0,910 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,911 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,912};913 914static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {915 .name = "gcc_qupv3_wrap2_s4_clk_src",916 .parent_data = gcc_parents_0,917 .num_parents = ARRAY_SIZE(gcc_parents_0),918 .flags = CLK_SET_RATE_PARENT,919 .ops = &clk_rcg2_ops,920};921 922static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {923 .cmd_rcgr = 0x1e608,924 .mnd_width = 16,925 .hid_width = 5,926 .parent_map = gcc_parent_map_0,927 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,928 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,929};930 931static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {932 .name = "gcc_qupv3_wrap2_s5_clk_src",933 .parent_data = gcc_parents_0,934 .num_parents = ARRAY_SIZE(gcc_parents_0),935 .flags = CLK_SET_RATE_PARENT,936 .ops = &clk_rcg2_ops,937};938 939static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {940 .cmd_rcgr = 0x1e738,941 .mnd_width = 16,942 .hid_width = 5,943 .parent_map = gcc_parent_map_0,944 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,945 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,946};947 948static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {949 F(400000, P_BI_TCXO, 12, 1, 4),950 F(9600000, P_BI_TCXO, 2, 0, 0),951 F(19200000, P_BI_TCXO, 1, 0, 0),952 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),953 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),954 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),955 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),956 { }957};958 959static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {960 .cmd_rcgr = 0x1400c,961 .mnd_width = 8,962 .hid_width = 5,963 .parent_map = gcc_parent_map_7,964 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,965 .clkr.hw.init = &(struct clk_init_data){966 .name = "gcc_sdcc2_apps_clk_src",967 .parent_data = gcc_parents_7,968 .num_parents = ARRAY_SIZE(gcc_parents_7),969 .flags = CLK_SET_RATE_PARENT,970 .ops = &clk_rcg2_floor_ops,971 },972};973 974static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {975 F(400000, P_BI_TCXO, 12, 1, 4),976 F(9600000, P_BI_TCXO, 2, 0, 0),977 F(19200000, P_BI_TCXO, 1, 0, 0),978 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),979 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),980 { }981};982 983static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {984 .cmd_rcgr = 0x1600c,985 .mnd_width = 8,986 .hid_width = 5,987 .parent_map = gcc_parent_map_5,988 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,989 .clkr.hw.init = &(struct clk_init_data){990 .name = "gcc_sdcc4_apps_clk_src",991 .parent_data = gcc_parents_5,992 .num_parents = ARRAY_SIZE(gcc_parents_5),993 .flags = CLK_SET_RATE_PARENT,994 .ops = &clk_rcg2_floor_ops,995 },996};997 998static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {999 F(105495, P_BI_TCXO, 2, 1, 91),1000 { }1001};1002 1003static struct clk_rcg2 gcc_tsif_ref_clk_src = {1004 .cmd_rcgr = 0x36010,1005 .mnd_width = 8,1006 .hid_width = 5,1007 .parent_map = gcc_parent_map_8,1008 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,1009 .clkr.hw.init = &(struct clk_init_data){1010 .name = "gcc_tsif_ref_clk_src",1011 .parent_data = gcc_parents_8,1012 .num_parents = ARRAY_SIZE(gcc_parents_8),1013 .flags = CLK_SET_RATE_PARENT,1014 .ops = &clk_rcg2_ops,1015 },1016};1017 1018static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = {1019 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),1020 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),1021 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1022 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),1023 { }1024};1025 1026static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = {1027 .cmd_rcgr = 0xa2020,1028 .mnd_width = 8,1029 .hid_width = 5,1030 .parent_map = gcc_parent_map_0,1031 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,1032 .clkr.hw.init = &(struct clk_init_data){1033 .name = "gcc_ufs_card_2_axi_clk_src",1034 .parent_data = gcc_parents_0,1035 .num_parents = ARRAY_SIZE(gcc_parents_0),1036 .flags = CLK_SET_RATE_PARENT,1037 .ops = &clk_rcg2_ops,1038 },1039};1040 1041static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = {1042 .cmd_rcgr = 0xa2060,1043 .mnd_width = 0,1044 .hid_width = 5,1045 .parent_map = gcc_parent_map_0,1046 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,1047 .clkr.hw.init = &(struct clk_init_data){1048 .name = "gcc_ufs_card_2_ice_core_clk_src",1049 .parent_data = gcc_parents_0,1050 .num_parents = ARRAY_SIZE(gcc_parents_0),1051 .flags = CLK_SET_RATE_PARENT,1052 .ops = &clk_rcg2_ops,1053 },1054};1055 1056static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = {1057 F(19200000, P_BI_TCXO, 1, 0, 0),1058 { }1059};1060 1061static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = {1062 .cmd_rcgr = 0xa2094,1063 .mnd_width = 0,1064 .hid_width = 5,1065 .parent_map = gcc_parent_map_4,1066 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,1067 .clkr.hw.init = &(struct clk_init_data){1068 .name = "gcc_ufs_card_2_phy_aux_clk_src",1069 .parent_data = gcc_parents_4,1070 .num_parents = ARRAY_SIZE(gcc_parents_4),1071 .flags = CLK_SET_RATE_PARENT,1072 .ops = &clk_rcg2_ops,1073 },1074};1075 1076static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = {1077 .cmd_rcgr = 0xa2078,1078 .mnd_width = 0,1079 .hid_width = 5,1080 .parent_map = gcc_parent_map_0,1081 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,1082 .clkr.hw.init = &(struct clk_init_data){1083 .name = "gcc_ufs_card_2_unipro_core_clk_src",1084 .parent_data = gcc_parents_0,1085 .num_parents = ARRAY_SIZE(gcc_parents_0),1086 .flags = CLK_SET_RATE_PARENT,1087 .ops = &clk_rcg2_ops,1088 },1089};1090 1091static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {1092 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),1093 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),1094 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),1095 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),1096 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1097 { }1098};1099 1100static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {1101 .cmd_rcgr = 0x75020,1102 .mnd_width = 8,1103 .hid_width = 5,1104 .parent_map = gcc_parent_map_0,1105 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,1106 .clkr.hw.init = &(struct clk_init_data){1107 .name = "gcc_ufs_card_axi_clk_src",1108 .parent_data = gcc_parents_0,1109 .num_parents = ARRAY_SIZE(gcc_parents_0),1110 .flags = CLK_SET_RATE_PARENT,1111 .ops = &clk_rcg2_ops,1112 },1113};1114 1115static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {1116 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),1117 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1118 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),1119 { }1120};1121 1122static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {1123 .cmd_rcgr = 0x75060,1124 .mnd_width = 0,1125 .hid_width = 5,1126 .parent_map = gcc_parent_map_0,1127 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,1128 .clkr.hw.init = &(struct clk_init_data){1129 .name = "gcc_ufs_card_ice_core_clk_src",1130 .parent_data = gcc_parents_0,1131 .num_parents = ARRAY_SIZE(gcc_parents_0),1132 .flags = CLK_SET_RATE_PARENT,1133 .ops = &clk_rcg2_ops,1134 },1135};1136 1137static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {1138 .cmd_rcgr = 0x75094,1139 .mnd_width = 0,1140 .hid_width = 5,1141 .parent_map = gcc_parent_map_4,1142 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,1143 .clkr.hw.init = &(struct clk_init_data){1144 .name = "gcc_ufs_card_phy_aux_clk_src",1145 .parent_data = gcc_parents_4,1146 .num_parents = ARRAY_SIZE(gcc_parents_4),1147 .flags = CLK_SET_RATE_PARENT,1148 .ops = &clk_rcg2_ops,1149 },1150};1151 1152static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {1153 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),1154 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),1155 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1156 { }1157};1158 1159static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {1160 .cmd_rcgr = 0x75078,1161 .mnd_width = 0,1162 .hid_width = 5,1163 .parent_map = gcc_parent_map_0,1164 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,1165 .clkr.hw.init = &(struct clk_init_data){1166 .name = "gcc_ufs_card_unipro_core_clk_src",1167 .parent_data = gcc_parents_0,1168 .num_parents = ARRAY_SIZE(gcc_parents_0),1169 .flags = CLK_SET_RATE_PARENT,1170 .ops = &clk_rcg2_ops,1171 },1172};1173 1174static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {1175 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),1176 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),1177 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),1178 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),1179 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),1180 { }1181};1182 1183static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {1184 .cmd_rcgr = 0x77020,1185 .mnd_width = 8,1186 .hid_width = 5,1187 .parent_map = gcc_parent_map_0,1188 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,1189 .clkr.hw.init = &(struct clk_init_data){1190 .name = "gcc_ufs_phy_axi_clk_src",1191 .parent_data = gcc_parents_0,1192 .num_parents = ARRAY_SIZE(gcc_parents_0),1193 .flags = CLK_SET_RATE_PARENT,1194 .ops = &clk_rcg2_ops,1195 },1196};1197 1198static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {1199 .cmd_rcgr = 0x77060,1200 .mnd_width = 0,1201 .hid_width = 5,1202 .parent_map = gcc_parent_map_0,1203 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,1204 .clkr.hw.init = &(struct clk_init_data){1205 .name = "gcc_ufs_phy_ice_core_clk_src",1206 .parent_data = gcc_parents_0,1207 .num_parents = ARRAY_SIZE(gcc_parents_0),1208 .flags = CLK_SET_RATE_PARENT,1209 .ops = &clk_rcg2_ops,1210 },1211};1212 1213static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {1214 .cmd_rcgr = 0x77094,1215 .mnd_width = 0,1216 .hid_width = 5,1217 .parent_map = gcc_parent_map_4,1218 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,1219 .clkr.hw.init = &(struct clk_init_data){1220 .name = "gcc_ufs_phy_phy_aux_clk_src",1221 .parent_data = gcc_parents_4,1222 .num_parents = ARRAY_SIZE(gcc_parents_4),1223 .flags = CLK_SET_RATE_PARENT,1224 .ops = &clk_rcg2_ops,1225 },1226};1227 1228static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {1229 .cmd_rcgr = 0x77078,1230 .mnd_width = 0,1231 .hid_width = 5,1232 .parent_map = gcc_parent_map_0,1233 .freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,1234 .clkr.hw.init = &(struct clk_init_data){1235 .name = "gcc_ufs_phy_unipro_core_clk_src",1236 .parent_data = gcc_parents_0,1237 .num_parents = ARRAY_SIZE(gcc_parents_0),1238 .flags = CLK_SET_RATE_PARENT,1239 .ops = &clk_rcg2_ops,1240 },1241};1242 1243static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {1244 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),1245 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),1246 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1247 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),1248 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1249 { }1250};1251 1252static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {1253 .cmd_rcgr = 0xa601c,1254 .mnd_width = 8,1255 .hid_width = 5,1256 .parent_map = gcc_parent_map_0,1257 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,1258 .clkr.hw.init = &(struct clk_init_data){1259 .name = "gcc_usb30_mp_master_clk_src",1260 .parent_data = gcc_parents_0,1261 .num_parents = ARRAY_SIZE(gcc_parents_0),1262 .flags = CLK_SET_RATE_PARENT,1263 .ops = &clk_rcg2_ops,1264 },1265};1266 1267static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = {1268 F(19200000, P_BI_TCXO, 1, 0, 0),1269 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),1270 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),1271 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),1272 { }1273};1274 1275static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {1276 .cmd_rcgr = 0xa6034,1277 .mnd_width = 0,1278 .hid_width = 5,1279 .parent_map = gcc_parent_map_0,1280 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,1281 .clkr.hw.init = &(struct clk_init_data){1282 .name = "gcc_usb30_mp_mock_utmi_clk_src",1283 .parent_data = gcc_parents_0,1284 .num_parents = ARRAY_SIZE(gcc_parents_0),1285 .flags = CLK_SET_RATE_PARENT,1286 .ops = &clk_rcg2_ops,1287 },1288};1289 1290static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {1291 .cmd_rcgr = 0xf01c,1292 .mnd_width = 8,1293 .hid_width = 5,1294 .parent_map = gcc_parent_map_0,1295 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,1296 .clkr.hw.init = &(struct clk_init_data){1297 .name = "gcc_usb30_prim_master_clk_src",1298 .parent_data = gcc_parents_0,1299 .num_parents = ARRAY_SIZE(gcc_parents_0),1300 .flags = CLK_SET_RATE_PARENT,1301 .ops = &clk_rcg2_ops,1302 },1303};1304 1305static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {1306 .cmd_rcgr = 0xf034,1307 .mnd_width = 0,1308 .hid_width = 5,1309 .parent_map = gcc_parent_map_0,1310 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,1311 .clkr.hw.init = &(struct clk_init_data){1312 .name = "gcc_usb30_prim_mock_utmi_clk_src",1313 .parent_data = gcc_parents_0,1314 .num_parents = ARRAY_SIZE(gcc_parents_0),1315 .flags = CLK_SET_RATE_PARENT,1316 .ops = &clk_rcg2_ops,1317 },1318};1319 1320static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {1321 .cmd_rcgr = 0x1001c,1322 .mnd_width = 8,1323 .hid_width = 5,1324 .parent_map = gcc_parent_map_0,1325 .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,1326 .clkr.hw.init = &(struct clk_init_data){1327 .name = "gcc_usb30_sec_master_clk_src",1328 .parent_data = gcc_parents_0,1329 .num_parents = ARRAY_SIZE(gcc_parents_0),1330 .flags = CLK_SET_RATE_PARENT,1331 .ops = &clk_rcg2_ops,1332 },1333};1334 1335static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {1336 .cmd_rcgr = 0x10034,1337 .mnd_width = 0,1338 .hid_width = 5,1339 .parent_map = gcc_parent_map_0,1340 .freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,1341 .clkr.hw.init = &(struct clk_init_data){1342 .name = "gcc_usb30_sec_mock_utmi_clk_src",1343 .parent_data = gcc_parents_0,1344 .num_parents = ARRAY_SIZE(gcc_parents_0),1345 .flags = CLK_SET_RATE_PARENT,1346 .ops = &clk_rcg2_ops,1347 },1348};1349 1350static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {1351 .cmd_rcgr = 0xa6068,1352 .mnd_width = 0,1353 .hid_width = 5,1354 .parent_map = gcc_parent_map_2,1355 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,1356 .clkr.hw.init = &(struct clk_init_data){1357 .name = "gcc_usb3_mp_phy_aux_clk_src",1358 .parent_data = gcc_parents_2,1359 .num_parents = ARRAY_SIZE(gcc_parents_2),1360 .flags = CLK_SET_RATE_PARENT,1361 .ops = &clk_rcg2_ops,1362 },1363};1364 1365static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {1366 .cmd_rcgr = 0xf060,1367 .mnd_width = 0,1368 .hid_width = 5,1369 .parent_map = gcc_parent_map_2,1370 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,1371 .clkr.hw.init = &(struct clk_init_data){1372 .name = "gcc_usb3_prim_phy_aux_clk_src",1373 .parent_data = gcc_parents_2,1374 .num_parents = ARRAY_SIZE(gcc_parents_2),1375 .flags = CLK_SET_RATE_PARENT,1376 .ops = &clk_rcg2_ops,1377 },1378};1379 1380static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {1381 .cmd_rcgr = 0x10060,1382 .mnd_width = 0,1383 .hid_width = 5,1384 .parent_map = gcc_parent_map_2,1385 .freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,1386 .clkr.hw.init = &(struct clk_init_data){1387 .name = "gcc_usb3_sec_phy_aux_clk_src",1388 .parent_data = gcc_parents_2,1389 .num_parents = ARRAY_SIZE(gcc_parents_2),1390 .flags = CLK_SET_RATE_PARENT,1391 .ops = &clk_rcg2_ops,1392 },1393};1394 1395static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {1396 .halt_reg = 0x90018,1397 .halt_check = BRANCH_HALT,1398 .clkr = {1399 .enable_reg = 0x90018,1400 .enable_mask = BIT(0),1401 .hw.init = &(struct clk_init_data){1402 .name = "gcc_aggre_noc_pcie_tbu_clk",1403 .ops = &clk_branch2_ops,1404 },1405 },1406};1407 1408static struct clk_branch gcc_aggre_ufs_card_axi_clk = {1409 .halt_reg = 0x750c0,1410 .halt_check = BRANCH_HALT,1411 .hwcg_reg = 0x750c0,1412 .hwcg_bit = 1,1413 .clkr = {1414 .enable_reg = 0x750c0,1415 .enable_mask = BIT(0),1416 .hw.init = &(struct clk_init_data){1417 .name = "gcc_aggre_ufs_card_axi_clk",1418 .parent_hws = (const struct clk_hw *[]){1419 &gcc_ufs_card_axi_clk_src.clkr.hw1420 },1421 .num_parents = 1,1422 .flags = CLK_SET_RATE_PARENT,1423 .ops = &clk_branch2_ops,1424 },1425 },1426};1427 1428static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {1429 .halt_reg = 0x750c0,1430 .halt_check = BRANCH_HALT,1431 .hwcg_reg = 0x750c0,1432 .hwcg_bit = 1,1433 .clkr = {1434 .enable_reg = 0x750c0,1435 .enable_mask = BIT(1),1436 .hw.init = &(struct clk_init_data){1437 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",1438 .parent_hws = (const struct clk_hw *[]){1439 &gcc_aggre_ufs_card_axi_clk.clkr.hw1440 },1441 .num_parents = 1,1442 .flags = CLK_SET_RATE_PARENT,1443 .ops = &clk_branch_simple_ops,1444 },1445 },1446};1447 1448static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {1449 .halt_reg = 0x770c0,1450 .halt_check = BRANCH_HALT,1451 .hwcg_reg = 0x770c0,1452 .hwcg_bit = 1,1453 .clkr = {1454 .enable_reg = 0x770c0,1455 .enable_mask = BIT(0),1456 .hw.init = &(struct clk_init_data){1457 .name = "gcc_aggre_ufs_phy_axi_clk",1458 .parent_hws = (const struct clk_hw *[]){1459 &gcc_ufs_phy_axi_clk_src.clkr.hw1460 },1461 .num_parents = 1,1462 .flags = CLK_SET_RATE_PARENT,1463 .ops = &clk_branch2_ops,1464 },1465 },1466};1467 1468static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {1469 .halt_reg = 0x770c0,1470 .halt_check = BRANCH_HALT,1471 .hwcg_reg = 0x770c0,1472 .hwcg_bit = 1,1473 .clkr = {1474 .enable_reg = 0x770c0,1475 .enable_mask = BIT(1),1476 .hw.init = &(struct clk_init_data){1477 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",1478 .parent_hws = (const struct clk_hw *[]){1479 &gcc_aggre_ufs_phy_axi_clk.clkr.hw1480 },1481 .num_parents = 1,1482 .flags = CLK_SET_RATE_PARENT,1483 .ops = &clk_branch_simple_ops,1484 },1485 },1486};1487 1488static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {1489 .halt_reg = 0xa6084,1490 .halt_check = BRANCH_HALT,1491 .clkr = {1492 .enable_reg = 0xa6084,1493 .enable_mask = BIT(0),1494 .hw.init = &(struct clk_init_data){1495 .name = "gcc_aggre_usb3_mp_axi_clk",1496 .parent_hws = (const struct clk_hw *[]){1497 &gcc_usb30_mp_master_clk_src.clkr.hw1498 },1499 .num_parents = 1,1500 .flags = CLK_SET_RATE_PARENT,1501 .ops = &clk_branch2_ops,1502 },1503 },1504};1505 1506static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {1507 .halt_reg = 0xf07c,1508 .halt_check = BRANCH_HALT,1509 .clkr = {1510 .enable_reg = 0xf07c,1511 .enable_mask = BIT(0),1512 .hw.init = &(struct clk_init_data){1513 .name = "gcc_aggre_usb3_prim_axi_clk",1514 .parent_hws = (const struct clk_hw *[]){1515 &gcc_usb30_prim_master_clk_src.clkr.hw1516 },1517 .num_parents = 1,1518 .flags = CLK_SET_RATE_PARENT,1519 .ops = &clk_branch2_ops,1520 },1521 },1522};1523 1524static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {1525 .halt_reg = 0x1007c,1526 .halt_check = BRANCH_HALT,1527 .clkr = {1528 .enable_reg = 0x1007c,1529 .enable_mask = BIT(0),1530 .hw.init = &(struct clk_init_data){1531 .name = "gcc_aggre_usb3_sec_axi_clk",1532 .parent_hws = (const struct clk_hw *[]){1533 &gcc_usb30_sec_master_clk_src.clkr.hw1534 },1535 .num_parents = 1,1536 .flags = CLK_SET_RATE_PARENT,1537 .ops = &clk_branch2_ops,1538 },1539 },1540};1541 1542static struct clk_branch gcc_boot_rom_ahb_clk = {1543 .halt_reg = 0x38004,1544 .halt_check = BRANCH_HALT_VOTED,1545 .hwcg_reg = 0x38004,1546 .hwcg_bit = 1,1547 .clkr = {1548 .enable_reg = 0x52004,1549 .enable_mask = BIT(10),1550 .hw.init = &(struct clk_init_data){1551 .name = "gcc_boot_rom_ahb_clk",1552 .ops = &clk_branch2_ops,1553 },1554 },1555};1556 1557static struct clk_branch gcc_camera_hf_axi_clk = {1558 .halt_reg = 0xb030,1559 .halt_check = BRANCH_HALT,1560 .clkr = {1561 .enable_reg = 0xb030,1562 .enable_mask = BIT(0),1563 .hw.init = &(struct clk_init_data){1564 .name = "gcc_camera_hf_axi_clk",1565 .ops = &clk_branch2_ops,1566 },1567 },1568};1569 1570static struct clk_branch gcc_camera_sf_axi_clk = {1571 .halt_reg = 0xb034,1572 .halt_check = BRANCH_HALT,1573 .clkr = {1574 .enable_reg = 0xb034,1575 .enable_mask = BIT(0),1576 .hw.init = &(struct clk_init_data){1577 .name = "gcc_camera_sf_axi_clk",1578 .ops = &clk_branch2_ops,1579 },1580 },1581};1582 1583static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {1584 .halt_reg = 0xa609c,1585 .halt_check = BRANCH_HALT,1586 .clkr = {1587 .enable_reg = 0xa609c,1588 .enable_mask = BIT(0),1589 .hw.init = &(struct clk_init_data){1590 .name = "gcc_cfg_noc_usb3_mp_axi_clk",1591 .parent_hws = (const struct clk_hw *[]){1592 &gcc_usb30_mp_master_clk_src.clkr.hw1593 },1594 .num_parents = 1,1595 .flags = CLK_SET_RATE_PARENT,1596 .ops = &clk_branch2_ops,1597 },1598 },1599};1600 1601static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {1602 .halt_reg = 0xf078,1603 .halt_check = BRANCH_HALT,1604 .clkr = {1605 .enable_reg = 0xf078,1606 .enable_mask = BIT(0),1607 .hw.init = &(struct clk_init_data){1608 .name = "gcc_cfg_noc_usb3_prim_axi_clk",1609 .parent_hws = (const struct clk_hw *[]){1610 &gcc_usb30_prim_master_clk_src.clkr.hw1611 },1612 .num_parents = 1,1613 .flags = CLK_SET_RATE_PARENT,1614 .ops = &clk_branch2_ops,1615 },1616 },1617};1618 1619static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {1620 .halt_reg = 0x10078,1621 .halt_check = BRANCH_HALT,1622 .clkr = {1623 .enable_reg = 0x10078,1624 .enable_mask = BIT(0),1625 .hw.init = &(struct clk_init_data){1626 .name = "gcc_cfg_noc_usb3_sec_axi_clk",1627 .parent_hws = (const struct clk_hw *[]){1628 &gcc_usb30_sec_master_clk_src.clkr.hw1629 },1630 .num_parents = 1,1631 .flags = CLK_SET_RATE_PARENT,1632 .ops = &clk_branch2_ops,1633 },1634 },1635};1636 1637static struct clk_branch gcc_cpuss_rbcpr_clk = {1638 .halt_reg = 0x48008,1639 .halt_check = BRANCH_HALT,1640 .clkr = {1641 .enable_reg = 0x48008,1642 .enable_mask = BIT(0),1643 .hw.init = &(struct clk_init_data){1644 .name = "gcc_cpuss_rbcpr_clk",1645 .ops = &clk_branch2_ops,1646 },1647 },1648};1649 1650static struct clk_branch gcc_ddrss_gpu_axi_clk = {1651 .halt_reg = 0x71154,1652 .halt_check = BRANCH_VOTED,1653 .clkr = {1654 .enable_reg = 0x71154,1655 .enable_mask = BIT(0),1656 .hw.init = &(struct clk_init_data){1657 .name = "gcc_ddrss_gpu_axi_clk",1658 .ops = &clk_branch2_ops,1659 },1660 },1661};1662 1663static struct clk_branch gcc_disp_hf_axi_clk = {1664 .halt_reg = 0xb038,1665 .halt_check = BRANCH_HALT,1666 .clkr = {1667 .enable_reg = 0xb038,1668 .enable_mask = BIT(0),1669 .hw.init = &(struct clk_init_data){1670 .name = "gcc_disp_hf_axi_clk",1671 .ops = &clk_branch2_ops,1672 },1673 },1674};1675 1676static struct clk_branch gcc_disp_sf_axi_clk = {1677 .halt_reg = 0xb03c,1678 .halt_check = BRANCH_HALT,1679 .clkr = {1680 .enable_reg = 0xb03c,1681 .enable_mask = BIT(0),1682 .hw.init = &(struct clk_init_data){1683 .name = "gcc_disp_sf_axi_clk",1684 .ops = &clk_branch2_ops,1685 },1686 },1687};1688 1689static struct clk_branch gcc_emac_axi_clk = {1690 .halt_reg = 0x6010,1691 .halt_check = BRANCH_HALT,1692 .clkr = {1693 .enable_reg = 0x6010,1694 .enable_mask = BIT(0),1695 .hw.init = &(struct clk_init_data){1696 .name = "gcc_emac_axi_clk",1697 .ops = &clk_branch2_ops,1698 },1699 },1700};1701 1702static struct clk_branch gcc_emac_ptp_clk = {1703 .halt_reg = 0x6034,1704 .halt_check = BRANCH_HALT,1705 .clkr = {1706 .enable_reg = 0x6034,1707 .enable_mask = BIT(0),1708 .hw.init = &(struct clk_init_data){1709 .name = "gcc_emac_ptp_clk",1710 .parent_hws = (const struct clk_hw *[]){1711 &gcc_emac_ptp_clk_src.clkr.hw1712 },1713 .num_parents = 1,1714 .flags = CLK_SET_RATE_PARENT,1715 .ops = &clk_branch2_ops,1716 },1717 },1718};1719 1720static struct clk_branch gcc_emac_rgmii_clk = {1721 .halt_reg = 0x6018,1722 .halt_check = BRANCH_HALT,1723 .clkr = {1724 .enable_reg = 0x6018,1725 .enable_mask = BIT(0),1726 .hw.init = &(struct clk_init_data){1727 .name = "gcc_emac_rgmii_clk",1728 .parent_hws = (const struct clk_hw *[]){1729 &gcc_emac_rgmii_clk_src.clkr.hw1730 },1731 .num_parents = 1,1732 .flags = CLK_SET_RATE_PARENT,1733 .ops = &clk_branch2_ops,1734 },1735 },1736};1737 1738static struct clk_branch gcc_emac_slv_ahb_clk = {1739 .halt_reg = 0x6014,1740 .halt_check = BRANCH_HALT,1741 .hwcg_reg = 0x6014,1742 .hwcg_bit = 1,1743 .clkr = {1744 .enable_reg = 0x6014,1745 .enable_mask = BIT(0),1746 .hw.init = &(struct clk_init_data){1747 .name = "gcc_emac_slv_ahb_clk",1748 .ops = &clk_branch2_ops,1749 },1750 },1751};1752 1753static struct clk_branch gcc_gp1_clk = {1754 .halt_reg = 0x64000,1755 .halt_check = BRANCH_HALT,1756 .clkr = {1757 .enable_reg = 0x64000,1758 .enable_mask = BIT(0),1759 .hw.init = &(struct clk_init_data){1760 .name = "gcc_gp1_clk",1761 .parent_hws = (const struct clk_hw *[]){1762 &gcc_gp1_clk_src.clkr.hw1763 },1764 .num_parents = 1,1765 .flags = CLK_SET_RATE_PARENT,1766 .ops = &clk_branch2_ops,1767 },1768 },1769};1770 1771static struct clk_branch gcc_gp2_clk = {1772 .halt_reg = 0x65000,1773 .halt_check = BRANCH_HALT,1774 .clkr = {1775 .enable_reg = 0x65000,1776 .enable_mask = BIT(0),1777 .hw.init = &(struct clk_init_data){1778 .name = "gcc_gp2_clk",1779 .parent_hws = (const struct clk_hw *[]){1780 &gcc_gp2_clk_src.clkr.hw1781 },1782 .num_parents = 1,1783 .flags = CLK_SET_RATE_PARENT,1784 .ops = &clk_branch2_ops,1785 },1786 },1787};1788 1789static struct clk_branch gcc_gp3_clk = {1790 .halt_reg = 0x66000,1791 .halt_check = BRANCH_HALT,1792 .clkr = {1793 .enable_reg = 0x66000,1794 .enable_mask = BIT(0),1795 .hw.init = &(struct clk_init_data){1796 .name = "gcc_gp3_clk",1797 .parent_hws = (const struct clk_hw *[]){1798 &gcc_gp3_clk_src.clkr.hw1799 },1800 .num_parents = 1,1801 .flags = CLK_SET_RATE_PARENT,1802 .ops = &clk_branch2_ops,1803 },1804 },1805};1806 1807static struct clk_branch gcc_gp4_clk = {1808 .halt_reg = 0xbe000,1809 .halt_check = BRANCH_HALT,1810 .clkr = {1811 .enable_reg = 0xbe000,1812 .enable_mask = BIT(0),1813 .hw.init = &(struct clk_init_data){1814 .name = "gcc_gp4_clk",1815 .parent_hws = (const struct clk_hw *[]){1816 &gcc_gp4_clk_src.clkr.hw1817 },1818 .num_parents = 1,1819 .flags = CLK_SET_RATE_PARENT,1820 .ops = &clk_branch2_ops,1821 },1822 },1823};1824 1825static struct clk_branch gcc_gp5_clk = {1826 .halt_reg = 0xbf000,1827 .halt_check = BRANCH_HALT,1828 .clkr = {1829 .enable_reg = 0xbf000,1830 .enable_mask = BIT(0),1831 .hw.init = &(struct clk_init_data){1832 .name = "gcc_gp5_clk",1833 .parent_hws = (const struct clk_hw *[]){1834 &gcc_gp5_clk_src.clkr.hw1835 },1836 .num_parents = 1,1837 .flags = CLK_SET_RATE_PARENT,1838 .ops = &clk_branch2_ops,1839 },1840 },1841};1842 1843static struct clk_branch gcc_gpu_gpll0_clk_src = {1844 .halt_check = BRANCH_HALT_DELAY,1845 .clkr = {1846 .enable_reg = 0x52004,1847 .enable_mask = BIT(15),1848 .hw.init = &(struct clk_init_data){1849 .name = "gcc_gpu_gpll0_clk_src",1850 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },1851 .num_parents = 1,1852 .flags = CLK_SET_RATE_PARENT,1853 .ops = &clk_branch2_ops,1854 },1855 },1856};1857 1858static struct clk_branch gcc_gpu_gpll0_div_clk_src = {1859 .halt_check = BRANCH_HALT_DELAY,1860 .clkr = {1861 .enable_reg = 0x52004,1862 .enable_mask = BIT(16),1863 .hw.init = &(struct clk_init_data){1864 .name = "gcc_gpu_gpll0_div_clk_src",1865 .parent_hws = (const struct clk_hw *[]){1866 &gpll0_out_even.clkr.hw1867 },1868 .num_parents = 1,1869 .flags = CLK_SET_RATE_PARENT,1870 .ops = &clk_branch2_ops,1871 },1872 },1873};1874 1875static struct clk_branch gcc_gpu_memnoc_gfx_clk = {1876 .halt_reg = 0x7100c,1877 .halt_check = BRANCH_VOTED,1878 .clkr = {1879 .enable_reg = 0x7100c,1880 .enable_mask = BIT(0),1881 .hw.init = &(struct clk_init_data){1882 .name = "gcc_gpu_memnoc_gfx_clk",1883 .ops = &clk_branch2_ops,1884 },1885 },1886};1887 1888static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {1889 .halt_reg = 0x71018,1890 .halt_check = BRANCH_HALT,1891 .clkr = {1892 .enable_reg = 0x71018,1893 .enable_mask = BIT(0),1894 .hw.init = &(struct clk_init_data){1895 .name = "gcc_gpu_snoc_dvm_gfx_clk",1896 .ops = &clk_branch2_ops,1897 },1898 },1899};1900 1901static struct clk_branch gcc_npu_at_clk = {1902 .halt_reg = 0x4d010,1903 .halt_check = BRANCH_VOTED,1904 .clkr = {1905 .enable_reg = 0x4d010,1906 .enable_mask = BIT(0),1907 .hw.init = &(struct clk_init_data){1908 .name = "gcc_npu_at_clk",1909 .ops = &clk_branch2_ops,1910 },1911 },1912};1913 1914static struct clk_branch gcc_npu_axi_clk = {1915 .halt_reg = 0x4d008,1916 .halt_check = BRANCH_VOTED,1917 .clkr = {1918 .enable_reg = 0x4d008,1919 .enable_mask = BIT(0),1920 .hw.init = &(struct clk_init_data){1921 .name = "gcc_npu_axi_clk",1922 .parent_hws = (const struct clk_hw *[]){1923 &gcc_npu_axi_clk_src.clkr.hw1924 },1925 .num_parents = 1,1926 .flags = CLK_SET_RATE_PARENT,1927 .ops = &clk_branch2_ops,1928 },1929 },1930};1931 1932static struct clk_branch gcc_npu_gpll0_clk_src = {1933 .halt_check = BRANCH_HALT_DELAY,1934 .clkr = {1935 .enable_reg = 0x52004,1936 .enable_mask = BIT(18),1937 .hw.init = &(struct clk_init_data){1938 .name = "gcc_npu_gpll0_clk_src",1939 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },1940 .num_parents = 1,1941 .flags = CLK_SET_RATE_PARENT,1942 .ops = &clk_branch2_ops,1943 },1944 },1945};1946 1947static struct clk_branch gcc_npu_gpll0_div_clk_src = {1948 .halt_check = BRANCH_HALT_DELAY,1949 .clkr = {1950 .enable_reg = 0x52004,1951 .enable_mask = BIT(19),1952 .hw.init = &(struct clk_init_data){1953 .name = "gcc_npu_gpll0_div_clk_src",1954 .parent_hws = (const struct clk_hw *[]){1955 &gpll0_out_even.clkr.hw1956 },1957 .num_parents = 1,1958 .flags = CLK_SET_RATE_PARENT,1959 .ops = &clk_branch2_ops,1960 },1961 },1962};1963 1964static struct clk_branch gcc_npu_trig_clk = {1965 .halt_reg = 0x4d00c,1966 .halt_check = BRANCH_VOTED,1967 .clkr = {1968 .enable_reg = 0x4d00c,1969 .enable_mask = BIT(0),1970 .hw.init = &(struct clk_init_data){1971 .name = "gcc_npu_trig_clk",1972 .ops = &clk_branch2_ops,1973 },1974 },1975};1976 1977static struct clk_branch gcc_pcie0_phy_refgen_clk = {1978 .halt_reg = 0x6f02c,1979 .halt_check = BRANCH_HALT,1980 .clkr = {1981 .enable_reg = 0x6f02c,1982 .enable_mask = BIT(0),1983 .hw.init = &(struct clk_init_data){1984 .name = "gcc_pcie0_phy_refgen_clk",1985 .parent_hws = (const struct clk_hw *[]){1986 &gcc_pcie_phy_refgen_clk_src.clkr.hw1987 },1988 .num_parents = 1,1989 .flags = CLK_SET_RATE_PARENT,1990 .ops = &clk_branch2_ops,1991 },1992 },1993};1994 1995static struct clk_branch gcc_pcie1_phy_refgen_clk = {1996 .halt_reg = 0x6f030,1997 .halt_check = BRANCH_HALT,1998 .clkr = {1999 .enable_reg = 0x6f030,2000 .enable_mask = BIT(0),2001 .hw.init = &(struct clk_init_data){2002 .name = "gcc_pcie1_phy_refgen_clk",2003 .parent_hws = (const struct clk_hw *[]){2004 &gcc_pcie_phy_refgen_clk_src.clkr.hw2005 },2006 .num_parents = 1,2007 .flags = CLK_SET_RATE_PARENT,2008 .ops = &clk_branch2_ops,2009 },2010 },2011};2012 2013static struct clk_branch gcc_pcie2_phy_refgen_clk = {2014 .halt_reg = 0x6f034,2015 .halt_check = BRANCH_HALT,2016 .clkr = {2017 .enable_reg = 0x6f034,2018 .enable_mask = BIT(0),2019 .hw.init = &(struct clk_init_data){2020 .name = "gcc_pcie2_phy_refgen_clk",2021 .parent_hws = (const struct clk_hw *[]){2022 &gcc_pcie_phy_refgen_clk_src.clkr.hw2023 },2024 .num_parents = 1,2025 .flags = CLK_SET_RATE_PARENT,2026 .ops = &clk_branch2_ops,2027 },2028 },2029};2030 2031static struct clk_branch gcc_pcie3_phy_refgen_clk = {2032 .halt_reg = 0x6f038,2033 .halt_check = BRANCH_HALT,2034 .clkr = {2035 .enable_reg = 0x6f038,2036 .enable_mask = BIT(0),2037 .hw.init = &(struct clk_init_data){2038 .name = "gcc_pcie3_phy_refgen_clk",2039 .parent_hws = (const struct clk_hw *[]){2040 &gcc_pcie_phy_refgen_clk_src.clkr.hw2041 },2042 .num_parents = 1,2043 .flags = CLK_SET_RATE_PARENT,2044 .ops = &clk_branch2_ops,2045 },2046 },2047};2048 2049static struct clk_branch gcc_pcie_0_aux_clk = {2050 .halt_reg = 0x6b020,2051 .halt_check = BRANCH_HALT_VOTED,2052 .clkr = {2053 .enable_reg = 0x5200c,2054 .enable_mask = BIT(3),2055 .hw.init = &(struct clk_init_data){2056 .name = "gcc_pcie_0_aux_clk",2057 .parent_hws = (const struct clk_hw *[]){2058 &gcc_pcie_0_aux_clk_src.clkr.hw2059 },2060 .num_parents = 1,2061 .flags = CLK_SET_RATE_PARENT,2062 .ops = &clk_branch2_ops,2063 },2064 },2065};2066 2067static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {2068 .halt_reg = 0x6b01c,2069 .halt_check = BRANCH_HALT_VOTED,2070 .hwcg_reg = 0x6b01c,2071 .hwcg_bit = 1,2072 .clkr = {2073 .enable_reg = 0x5200c,2074 .enable_mask = BIT(2),2075 .hw.init = &(struct clk_init_data){2076 .name = "gcc_pcie_0_cfg_ahb_clk",2077 .ops = &clk_branch2_ops,2078 },2079 },2080};2081 2082static struct clk_branch gcc_pcie_0_clkref_clk = {2083 .halt_reg = 0x8c00c,2084 .halt_check = BRANCH_HALT,2085 .clkr = {2086 .enable_reg = 0x8c00c,2087 .enable_mask = BIT(0),2088 .hw.init = &(struct clk_init_data){2089 .name = "gcc_pcie_0_clkref_clk",2090 .ops = &clk_branch2_ops,2091 },2092 },2093};2094 2095static struct clk_branch gcc_pcie_0_mstr_axi_clk = {2096 .halt_reg = 0x6b018,2097 .halt_check = BRANCH_HALT_VOTED,2098 .clkr = {2099 .enable_reg = 0x5200c,2100 .enable_mask = BIT(1),2101 .hw.init = &(struct clk_init_data){2102 .name = "gcc_pcie_0_mstr_axi_clk",2103 .ops = &clk_branch2_ops,2104 },2105 },2106};2107 2108static struct clk_branch gcc_pcie_0_pipe_clk = {2109 .halt_reg = 0x6b024,2110 .halt_check = BRANCH_HALT_SKIP,2111 .clkr = {2112 .enable_reg = 0x5200c,2113 .enable_mask = BIT(4),2114 .hw.init = &(struct clk_init_data){2115 .name = "gcc_pcie_0_pipe_clk",2116 .ops = &clk_branch2_ops,2117 },2118 },2119};2120 2121static struct clk_branch gcc_pcie_0_slv_axi_clk = {2122 .halt_reg = 0x6b014,2123 .halt_check = BRANCH_HALT_VOTED,2124 .hwcg_reg = 0x6b014,2125 .hwcg_bit = 1,2126 .clkr = {2127 .enable_reg = 0x5200c,2128 .enable_mask = BIT(0),2129 .hw.init = &(struct clk_init_data){2130 .name = "gcc_pcie_0_slv_axi_clk",2131 .ops = &clk_branch2_ops,2132 },2133 },2134};2135 2136static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {2137 .halt_reg = 0x6b010,2138 .halt_check = BRANCH_HALT_VOTED,2139 .clkr = {2140 .enable_reg = 0x5200c,2141 .enable_mask = BIT(5),2142 .hw.init = &(struct clk_init_data){2143 .name = "gcc_pcie_0_slv_q2a_axi_clk",2144 .ops = &clk_branch2_ops,2145 },2146 },2147};2148 2149static struct clk_branch gcc_pcie_1_aux_clk = {2150 .halt_reg = 0x8d020,2151 .halt_check = BRANCH_HALT_VOTED,2152 .clkr = {2153 .enable_reg = 0x52004,2154 .enable_mask = BIT(29),2155 .hw.init = &(struct clk_init_data){2156 .name = "gcc_pcie_1_aux_clk",2157 .parent_hws = (const struct clk_hw *[]){2158 &gcc_pcie_1_aux_clk_src.clkr.hw2159 },2160 .num_parents = 1,2161 .flags = CLK_SET_RATE_PARENT,2162 .ops = &clk_branch2_ops,2163 },2164 },2165};2166 2167static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {2168 .halt_reg = 0x8d01c,2169 .halt_check = BRANCH_HALT_VOTED,2170 .hwcg_reg = 0x8d01c,2171 .hwcg_bit = 1,2172 .clkr = {2173 .enable_reg = 0x52004,2174 .enable_mask = BIT(28),2175 .hw.init = &(struct clk_init_data){2176 .name = "gcc_pcie_1_cfg_ahb_clk",2177 .ops = &clk_branch2_ops,2178 },2179 },2180};2181 2182static struct clk_branch gcc_pcie_1_clkref_clk = {2183 .halt_reg = 0x8c02c,2184 .halt_check = BRANCH_HALT,2185 .clkr = {2186 .enable_reg = 0x8c02c,2187 .enable_mask = BIT(0),2188 .hw.init = &(struct clk_init_data){2189 .name = "gcc_pcie_1_clkref_clk",2190 .ops = &clk_branch2_ops,2191 },2192 },2193};2194 2195static struct clk_branch gcc_pcie_1_mstr_axi_clk = {2196 .halt_reg = 0x8d018,2197 .halt_check = BRANCH_HALT_VOTED,2198 .clkr = {2199 .enable_reg = 0x52004,2200 .enable_mask = BIT(27),2201 .hw.init = &(struct clk_init_data){2202 .name = "gcc_pcie_1_mstr_axi_clk",2203 .ops = &clk_branch2_ops,2204 },2205 },2206};2207 2208static struct clk_branch gcc_pcie_1_pipe_clk = {2209 .halt_reg = 0x8d024,2210 .halt_check = BRANCH_HALT_SKIP,2211 .clkr = {2212 .enable_reg = 0x52004,2213 .enable_mask = BIT(30),2214 .hw.init = &(struct clk_init_data){2215 .name = "gcc_pcie_1_pipe_clk",2216 .ops = &clk_branch2_ops,2217 },2218 },2219};2220 2221static struct clk_branch gcc_pcie_1_slv_axi_clk = {2222 .halt_reg = 0x8d014,2223 .halt_check = BRANCH_HALT_VOTED,2224 .hwcg_reg = 0x8d014,2225 .hwcg_bit = 1,2226 .clkr = {2227 .enable_reg = 0x52004,2228 .enable_mask = BIT(26),2229 .hw.init = &(struct clk_init_data){2230 .name = "gcc_pcie_1_slv_axi_clk",2231 .ops = &clk_branch2_ops,2232 },2233 },2234};2235 2236static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {2237 .halt_reg = 0x8d010,2238 .halt_check = BRANCH_HALT_VOTED,2239 .clkr = {2240 .enable_reg = 0x52004,2241 .enable_mask = BIT(25),2242 .hw.init = &(struct clk_init_data){2243 .name = "gcc_pcie_1_slv_q2a_axi_clk",2244 .ops = &clk_branch2_ops,2245 },2246 },2247};2248 2249static struct clk_branch gcc_pcie_2_aux_clk = {2250 .halt_reg = 0x9d020,2251 .halt_check = BRANCH_HALT_VOTED,2252 .clkr = {2253 .enable_reg = 0x52014,2254 .enable_mask = BIT(14),2255 .hw.init = &(struct clk_init_data){2256 .name = "gcc_pcie_2_aux_clk",2257 .parent_hws = (const struct clk_hw *[]){2258 &gcc_pcie_2_aux_clk_src.clkr.hw2259 },2260 .num_parents = 1,2261 .flags = CLK_SET_RATE_PARENT,2262 .ops = &clk_branch2_ops,2263 },2264 },2265};2266 2267static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {2268 .halt_reg = 0x9d01c,2269 .halt_check = BRANCH_HALT_VOTED,2270 .hwcg_reg = 0x9d01c,2271 .hwcg_bit = 1,2272 .clkr = {2273 .enable_reg = 0x52014,2274 .enable_mask = BIT(13),2275 .hw.init = &(struct clk_init_data){2276 .name = "gcc_pcie_2_cfg_ahb_clk",2277 .ops = &clk_branch2_ops,2278 },2279 },2280};2281 2282static struct clk_branch gcc_pcie_2_clkref_clk = {2283 .halt_reg = 0x8c014,2284 .halt_check = BRANCH_HALT,2285 .clkr = {2286 .enable_reg = 0x8c014,2287 .enable_mask = BIT(0),2288 .hw.init = &(struct clk_init_data){2289 .name = "gcc_pcie_2_clkref_clk",2290 .ops = &clk_branch2_ops,2291 },2292 },2293};2294 2295static struct clk_branch gcc_pcie_2_mstr_axi_clk = {2296 .halt_reg = 0x9d018,2297 .halt_check = BRANCH_HALT_VOTED,2298 .clkr = {2299 .enable_reg = 0x52014,2300 .enable_mask = BIT(12),2301 .hw.init = &(struct clk_init_data){2302 .name = "gcc_pcie_2_mstr_axi_clk",2303 .ops = &clk_branch2_ops,2304 },2305 },2306};2307 2308static struct clk_branch gcc_pcie_2_pipe_clk = {2309 .halt_reg = 0x9d024,2310 .halt_check = BRANCH_HALT_SKIP,2311 .clkr = {2312 .enable_reg = 0x52014,2313 .enable_mask = BIT(15),2314 .hw.init = &(struct clk_init_data){2315 .name = "gcc_pcie_2_pipe_clk",2316 .ops = &clk_branch2_ops,2317 },2318 },2319};2320 2321static struct clk_branch gcc_pcie_2_slv_axi_clk = {2322 .halt_reg = 0x9d014,2323 .halt_check = BRANCH_HALT_VOTED,2324 .hwcg_reg = 0x9d014,2325 .hwcg_bit = 1,2326 .clkr = {2327 .enable_reg = 0x52014,2328 .enable_mask = BIT(11),2329 .hw.init = &(struct clk_init_data){2330 .name = "gcc_pcie_2_slv_axi_clk",2331 .ops = &clk_branch2_ops,2332 },2333 },2334};2335 2336static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {2337 .halt_reg = 0x9d010,2338 .halt_check = BRANCH_HALT_VOTED,2339 .clkr = {2340 .enable_reg = 0x52014,2341 .enable_mask = BIT(10),2342 .hw.init = &(struct clk_init_data){2343 .name = "gcc_pcie_2_slv_q2a_axi_clk",2344 .ops = &clk_branch2_ops,2345 },2346 },2347};2348 2349static struct clk_branch gcc_pcie_3_aux_clk = {2350 .halt_reg = 0xa3020,2351 .halt_check = BRANCH_HALT_VOTED,2352 .clkr = {2353 .enable_reg = 0x52014,2354 .enable_mask = BIT(20),2355 .hw.init = &(struct clk_init_data){2356 .name = "gcc_pcie_3_aux_clk",2357 .parent_hws = (const struct clk_hw *[]){2358 &gcc_pcie_3_aux_clk_src.clkr.hw2359 },2360 .num_parents = 1,2361 .flags = CLK_SET_RATE_PARENT,2362 .ops = &clk_branch2_ops,2363 },2364 },2365};2366 2367static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {2368 .halt_reg = 0xa301c,2369 .halt_check = BRANCH_HALT_VOTED,2370 .hwcg_reg = 0xa301c,2371 .hwcg_bit = 1,2372 .clkr = {2373 .enable_reg = 0x52014,2374 .enable_mask = BIT(19),2375 .hw.init = &(struct clk_init_data){2376 .name = "gcc_pcie_3_cfg_ahb_clk",2377 .ops = &clk_branch2_ops,2378 },2379 },2380};2381 2382static struct clk_branch gcc_pcie_3_clkref_clk = {2383 .halt_reg = 0x8c018,2384 .halt_check = BRANCH_HALT,2385 .clkr = {2386 .enable_reg = 0x8c018,2387 .enable_mask = BIT(0),2388 .hw.init = &(struct clk_init_data){2389 .name = "gcc_pcie_3_clkref_clk",2390 .ops = &clk_branch2_ops,2391 },2392 },2393};2394 2395static struct clk_branch gcc_pcie_3_mstr_axi_clk = {2396 .halt_reg = 0xa3018,2397 .halt_check = BRANCH_HALT_VOTED,2398 .clkr = {2399 .enable_reg = 0x52014,2400 .enable_mask = BIT(18),2401 .hw.init = &(struct clk_init_data){2402 .name = "gcc_pcie_3_mstr_axi_clk",2403 .ops = &clk_branch2_ops,2404 },2405 },2406};2407 2408static struct clk_branch gcc_pcie_3_pipe_clk = {2409 .halt_reg = 0xa3024,2410 .halt_check = BRANCH_HALT_SKIP,2411 .clkr = {2412 .enable_reg = 0x52014,2413 .enable_mask = BIT(21),2414 .hw.init = &(struct clk_init_data){2415 .name = "gcc_pcie_3_pipe_clk",2416 .ops = &clk_branch2_ops,2417 },2418 },2419};2420 2421static struct clk_branch gcc_pcie_3_slv_axi_clk = {2422 .halt_reg = 0xa3014,2423 .halt_check = BRANCH_HALT_VOTED,2424 .hwcg_reg = 0xa3014,2425 .hwcg_bit = 1,2426 .clkr = {2427 .enable_reg = 0x52014,2428 .enable_mask = BIT(17),2429 .hw.init = &(struct clk_init_data){2430 .name = "gcc_pcie_3_slv_axi_clk",2431 .ops = &clk_branch2_ops,2432 },2433 },2434};2435 2436static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {2437 .halt_reg = 0xa3010,2438 .halt_check = BRANCH_HALT_VOTED,2439 .clkr = {2440 .enable_reg = 0x52014,2441 .enable_mask = BIT(16),2442 .hw.init = &(struct clk_init_data){2443 .name = "gcc_pcie_3_slv_q2a_axi_clk",2444 .ops = &clk_branch2_ops,2445 },2446 },2447};2448 2449static struct clk_branch gcc_pcie_phy_aux_clk = {2450 .halt_reg = 0x6f004,2451 .halt_check = BRANCH_HALT,2452 .clkr = {2453 .enable_reg = 0x6f004,2454 .enable_mask = BIT(0),2455 .hw.init = &(struct clk_init_data){2456 .name = "gcc_pcie_phy_aux_clk",2457 .parent_hws = (const struct clk_hw *[]){2458 &gcc_pcie_0_aux_clk_src.clkr.hw2459 },2460 .num_parents = 1,2461 .flags = CLK_SET_RATE_PARENT,2462 .ops = &clk_branch2_ops,2463 },2464 },2465};2466 2467static struct clk_branch gcc_pdm2_clk = {2468 .halt_reg = 0x3300c,2469 .halt_check = BRANCH_HALT,2470 .clkr = {2471 .enable_reg = 0x3300c,2472 .enable_mask = BIT(0),2473 .hw.init = &(struct clk_init_data){2474 .name = "gcc_pdm2_clk",2475 .parent_hws = (const struct clk_hw *[]){2476 &gcc_pdm2_clk_src.clkr.hw2477 },2478 .num_parents = 1,2479 .flags = CLK_SET_RATE_PARENT,2480 .ops = &clk_branch2_ops,2481 },2482 },2483};2484 2485static struct clk_branch gcc_pdm_ahb_clk = {2486 .halt_reg = 0x33004,2487 .halt_check = BRANCH_HALT,2488 .hwcg_reg = 0x33004,2489 .hwcg_bit = 1,2490 .clkr = {2491 .enable_reg = 0x33004,2492 .enable_mask = BIT(0),2493 .hw.init = &(struct clk_init_data){2494 .name = "gcc_pdm_ahb_clk",2495 .ops = &clk_branch2_ops,2496 },2497 },2498};2499 2500static struct clk_branch gcc_pdm_xo4_clk = {2501 .halt_reg = 0x33008,2502 .halt_check = BRANCH_HALT,2503 .clkr = {2504 .enable_reg = 0x33008,2505 .enable_mask = BIT(0),2506 .hw.init = &(struct clk_init_data){2507 .name = "gcc_pdm_xo4_clk",2508 .ops = &clk_branch2_ops,2509 },2510 },2511};2512 2513static struct clk_branch gcc_prng_ahb_clk = {2514 .halt_reg = 0x34004,2515 .halt_check = BRANCH_HALT_VOTED,2516 .clkr = {2517 .enable_reg = 0x52004,2518 .enable_mask = BIT(13),2519 .hw.init = &(struct clk_init_data){2520 .name = "gcc_prng_ahb_clk",2521 .ops = &clk_branch2_ops,2522 },2523 },2524};2525 2526static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {2527 .halt_reg = 0xb018,2528 .halt_check = BRANCH_HALT,2529 .hwcg_reg = 0xb018,2530 .hwcg_bit = 1,2531 .clkr = {2532 .enable_reg = 0xb018,2533 .enable_mask = BIT(0),2534 .hw.init = &(struct clk_init_data){2535 .name = "gcc_qmip_camera_nrt_ahb_clk",2536 .ops = &clk_branch2_ops,2537 },2538 },2539};2540 2541static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {2542 .halt_reg = 0xb01c,2543 .halt_check = BRANCH_HALT,2544 .hwcg_reg = 0xb01c,2545 .hwcg_bit = 1,2546 .clkr = {2547 .enable_reg = 0xb01c,2548 .enable_mask = BIT(0),2549 .hw.init = &(struct clk_init_data){2550 .name = "gcc_qmip_camera_rt_ahb_clk",2551 .ops = &clk_branch2_ops,2552 },2553 },2554};2555 2556static struct clk_branch gcc_qmip_disp_ahb_clk = {2557 .halt_reg = 0xb020,2558 .halt_check = BRANCH_HALT,2559 .hwcg_reg = 0xb020,2560 .hwcg_bit = 1,2561 .clkr = {2562 .enable_reg = 0xb020,2563 .enable_mask = BIT(0),2564 .hw.init = &(struct clk_init_data){2565 .name = "gcc_qmip_disp_ahb_clk",2566 .ops = &clk_branch2_ops,2567 },2568 },2569};2570 2571static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {2572 .halt_reg = 0xb010,2573 .halt_check = BRANCH_HALT,2574 .hwcg_reg = 0xb010,2575 .hwcg_bit = 1,2576 .clkr = {2577 .enable_reg = 0xb010,2578 .enable_mask = BIT(0),2579 .hw.init = &(struct clk_init_data){2580 .name = "gcc_qmip_video_cvp_ahb_clk",2581 .ops = &clk_branch2_ops,2582 },2583 },2584};2585 2586static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {2587 .halt_reg = 0xb014,2588 .halt_check = BRANCH_HALT,2589 .hwcg_reg = 0xb014,2590 .hwcg_bit = 1,2591 .clkr = {2592 .enable_reg = 0xb014,2593 .enable_mask = BIT(0),2594 .hw.init = &(struct clk_init_data){2595 .name = "gcc_qmip_video_vcodec_ahb_clk",2596 .ops = &clk_branch2_ops,2597 },2598 },2599};2600 2601static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = {2602 .halt_reg = 0x4a004,2603 .halt_check = BRANCH_HALT,2604 .clkr = {2605 .enable_reg = 0x4a004,2606 .enable_mask = BIT(0),2607 .hw.init = &(struct clk_init_data){2608 .name = "gcc_qspi_1_cnoc_periph_ahb_clk",2609 .ops = &clk_branch2_ops,2610 },2611 },2612};2613 2614static struct clk_branch gcc_qspi_1_core_clk = {2615 .halt_reg = 0x4a008,2616 .halt_check = BRANCH_HALT,2617 .clkr = {2618 .enable_reg = 0x4a008,2619 .enable_mask = BIT(0),2620 .hw.init = &(struct clk_init_data){2621 .name = "gcc_qspi_1_core_clk",2622 .parent_hws = (const struct clk_hw *[]){2623 &gcc_qspi_1_core_clk_src.clkr.hw2624 },2625 .num_parents = 1,2626 .flags = CLK_SET_RATE_PARENT,2627 .ops = &clk_branch2_ops,2628 },2629 },2630};2631 2632static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {2633 .halt_reg = 0x4b000,2634 .halt_check = BRANCH_HALT,2635 .clkr = {2636 .enable_reg = 0x4b000,2637 .enable_mask = BIT(0),2638 .hw.init = &(struct clk_init_data){2639 .name = "gcc_qspi_cnoc_periph_ahb_clk",2640 .ops = &clk_branch2_ops,2641 },2642 },2643};2644 2645static struct clk_branch gcc_qspi_core_clk = {2646 .halt_reg = 0x4b004,2647 .halt_check = BRANCH_HALT,2648 .clkr = {2649 .enable_reg = 0x4b004,2650 .enable_mask = BIT(0),2651 .hw.init = &(struct clk_init_data){2652 .name = "gcc_qspi_core_clk",2653 .parent_hws = (const struct clk_hw *[]){2654 &gcc_qspi_core_clk_src.clkr.hw2655 },2656 .num_parents = 1,2657 .flags = CLK_SET_RATE_PARENT,2658 .ops = &clk_branch2_ops,2659 },2660 },2661};2662 2663static struct clk_branch gcc_qupv3_wrap0_s0_clk = {2664 .halt_reg = 0x17144,2665 .halt_check = BRANCH_HALT_VOTED,2666 .clkr = {2667 .enable_reg = 0x5200c,2668 .enable_mask = BIT(10),2669 .hw.init = &(struct clk_init_data){2670 .name = "gcc_qupv3_wrap0_s0_clk",2671 .parent_hws = (const struct clk_hw *[]){2672 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw2673 },2674 .num_parents = 1,2675 .flags = CLK_SET_RATE_PARENT,2676 .ops = &clk_branch2_ops,2677 },2678 },2679};2680 2681static struct clk_branch gcc_qupv3_wrap0_s1_clk = {2682 .halt_reg = 0x17274,2683 .halt_check = BRANCH_HALT_VOTED,2684 .clkr = {2685 .enable_reg = 0x5200c,2686 .enable_mask = BIT(11),2687 .hw.init = &(struct clk_init_data){2688 .name = "gcc_qupv3_wrap0_s1_clk",2689 .parent_hws = (const struct clk_hw *[]){2690 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw2691 },2692 .num_parents = 1,2693 .flags = CLK_SET_RATE_PARENT,2694 .ops = &clk_branch2_ops,2695 },2696 },2697};2698 2699static struct clk_branch gcc_qupv3_wrap0_s2_clk = {2700 .halt_reg = 0x173a4,2701 .halt_check = BRANCH_HALT_VOTED,2702 .clkr = {2703 .enable_reg = 0x5200c,2704 .enable_mask = BIT(12),2705 .hw.init = &(struct clk_init_data){2706 .name = "gcc_qupv3_wrap0_s2_clk",2707 .parent_hws = (const struct clk_hw *[]){2708 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw2709 },2710 .num_parents = 1,2711 .flags = CLK_SET_RATE_PARENT,2712 .ops = &clk_branch2_ops,2713 },2714 },2715};2716 2717static struct clk_branch gcc_qupv3_wrap0_s3_clk = {2718 .halt_reg = 0x174d4,2719 .halt_check = BRANCH_HALT_VOTED,2720 .clkr = {2721 .enable_reg = 0x5200c,2722 .enable_mask = BIT(13),2723 .hw.init = &(struct clk_init_data){2724 .name = "gcc_qupv3_wrap0_s3_clk",2725 .parent_hws = (const struct clk_hw *[]){2726 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw2727 },2728 .num_parents = 1,2729 .flags = CLK_SET_RATE_PARENT,2730 .ops = &clk_branch2_ops,2731 },2732 },2733};2734 2735static struct clk_branch gcc_qupv3_wrap0_s4_clk = {2736 .halt_reg = 0x17604,2737 .halt_check = BRANCH_HALT_VOTED,2738 .clkr = {2739 .enable_reg = 0x5200c,2740 .enable_mask = BIT(14),2741 .hw.init = &(struct clk_init_data){2742 .name = "gcc_qupv3_wrap0_s4_clk",2743 .parent_hws = (const struct clk_hw *[]){2744 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw2745 },2746 .num_parents = 1,2747 .flags = CLK_SET_RATE_PARENT,2748 .ops = &clk_branch2_ops,2749 },2750 },2751};2752 2753static struct clk_branch gcc_qupv3_wrap0_s5_clk = {2754 .halt_reg = 0x17734,2755 .halt_check = BRANCH_HALT_VOTED,2756 .clkr = {2757 .enable_reg = 0x5200c,2758 .enable_mask = BIT(15),2759 .hw.init = &(struct clk_init_data){2760 .name = "gcc_qupv3_wrap0_s5_clk",2761 .parent_hws = (const struct clk_hw *[]){2762 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw2763 },2764 .num_parents = 1,2765 .flags = CLK_SET_RATE_PARENT,2766 .ops = &clk_branch2_ops,2767 },2768 },2769};2770 2771static struct clk_branch gcc_qupv3_wrap0_s6_clk = {2772 .halt_reg = 0x17864,2773 .halt_check = BRANCH_HALT_VOTED,2774 .clkr = {2775 .enable_reg = 0x5200c,2776 .enable_mask = BIT(16),2777 .hw.init = &(struct clk_init_data){2778 .name = "gcc_qupv3_wrap0_s6_clk",2779 .parent_hws = (const struct clk_hw *[]){2780 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw2781 },2782 .num_parents = 1,2783 .flags = CLK_SET_RATE_PARENT,2784 .ops = &clk_branch2_ops,2785 },2786 },2787};2788 2789static struct clk_branch gcc_qupv3_wrap0_s7_clk = {2790 .halt_reg = 0x17994,2791 .halt_check = BRANCH_HALT_VOTED,2792 .clkr = {2793 .enable_reg = 0x5200c,2794 .enable_mask = BIT(17),2795 .hw.init = &(struct clk_init_data){2796 .name = "gcc_qupv3_wrap0_s7_clk",2797 .parent_hws = (const struct clk_hw *[]){2798 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw2799 },2800 .num_parents = 1,2801 .flags = CLK_SET_RATE_PARENT,2802 .ops = &clk_branch2_ops,2803 },2804 },2805};2806 2807static struct clk_branch gcc_qupv3_wrap1_s0_clk = {2808 .halt_reg = 0x18144,2809 .halt_check = BRANCH_HALT_VOTED,2810 .clkr = {2811 .enable_reg = 0x5200c,2812 .enable_mask = BIT(22),2813 .hw.init = &(struct clk_init_data){2814 .name = "gcc_qupv3_wrap1_s0_clk",2815 .parent_hws = (const struct clk_hw *[]){2816 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw2817 },2818 .num_parents = 1,2819 .flags = CLK_SET_RATE_PARENT,2820 .ops = &clk_branch2_ops,2821 },2822 },2823};2824 2825static struct clk_branch gcc_qupv3_wrap1_s1_clk = {2826 .halt_reg = 0x18274,2827 .halt_check = BRANCH_HALT_VOTED,2828 .clkr = {2829 .enable_reg = 0x5200c,2830 .enable_mask = BIT(23),2831 .hw.init = &(struct clk_init_data){2832 .name = "gcc_qupv3_wrap1_s1_clk",2833 .parent_hws = (const struct clk_hw *[]){2834 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw2835 },2836 .num_parents = 1,2837 .flags = CLK_SET_RATE_PARENT,2838 .ops = &clk_branch2_ops,2839 },2840 },2841};2842 2843static struct clk_branch gcc_qupv3_wrap1_s2_clk = {2844 .halt_reg = 0x183a4,2845 .halt_check = BRANCH_HALT_VOTED,2846 .clkr = {2847 .enable_reg = 0x5200c,2848 .enable_mask = BIT(24),2849 .hw.init = &(struct clk_init_data){2850 .name = "gcc_qupv3_wrap1_s2_clk",2851 .parent_hws = (const struct clk_hw *[]){2852 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw2853 },2854 .num_parents = 1,2855 .flags = CLK_SET_RATE_PARENT,2856 .ops = &clk_branch2_ops,2857 },2858 },2859};2860 2861static struct clk_branch gcc_qupv3_wrap1_s3_clk = {2862 .halt_reg = 0x184d4,2863 .halt_check = BRANCH_HALT_VOTED,2864 .clkr = {2865 .enable_reg = 0x5200c,2866 .enable_mask = BIT(25),2867 .hw.init = &(struct clk_init_data){2868 .name = "gcc_qupv3_wrap1_s3_clk",2869 .parent_hws = (const struct clk_hw *[]){2870 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw2871 },2872 .num_parents = 1,2873 .flags = CLK_SET_RATE_PARENT,2874 .ops = &clk_branch2_ops,2875 },2876 },2877};2878 2879static struct clk_branch gcc_qupv3_wrap1_s4_clk = {2880 .halt_reg = 0x18604,2881 .halt_check = BRANCH_HALT_VOTED,2882 .clkr = {2883 .enable_reg = 0x5200c,2884 .enable_mask = BIT(26),2885 .hw.init = &(struct clk_init_data){2886 .name = "gcc_qupv3_wrap1_s4_clk",2887 .parent_hws = (const struct clk_hw *[]){2888 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw2889 },2890 .num_parents = 1,2891 .flags = CLK_SET_RATE_PARENT,2892 .ops = &clk_branch2_ops,2893 },2894 },2895};2896 2897static struct clk_branch gcc_qupv3_wrap1_s5_clk = {2898 .halt_reg = 0x18734,2899 .halt_check = BRANCH_HALT_VOTED,2900 .clkr = {2901 .enable_reg = 0x5200c,2902 .enable_mask = BIT(27),2903 .hw.init = &(struct clk_init_data){2904 .name = "gcc_qupv3_wrap1_s5_clk",2905 .parent_hws = (const struct clk_hw *[]){2906 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw2907 },2908 .num_parents = 1,2909 .flags = CLK_SET_RATE_PARENT,2910 .ops = &clk_branch2_ops,2911 },2912 },2913};2914 2915static struct clk_branch gcc_qupv3_wrap2_s0_clk = {2916 .halt_reg = 0x1e144,2917 .halt_check = BRANCH_HALT_VOTED,2918 .clkr = {2919 .enable_reg = 0x52014,2920 .enable_mask = BIT(4),2921 .hw.init = &(struct clk_init_data){2922 .name = "gcc_qupv3_wrap2_s0_clk",2923 .parent_hws = (const struct clk_hw *[]){2924 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw2925 },2926 .num_parents = 1,2927 .flags = CLK_SET_RATE_PARENT,2928 .ops = &clk_branch2_ops,2929 },2930 },2931};2932 2933static struct clk_branch gcc_qupv3_wrap2_s1_clk = {2934 .halt_reg = 0x1e274,2935 .halt_check = BRANCH_HALT_VOTED,2936 .clkr = {2937 .enable_reg = 0x52014,2938 .enable_mask = BIT(5),2939 .hw.init = &(struct clk_init_data){2940 .name = "gcc_qupv3_wrap2_s1_clk",2941 .parent_hws = (const struct clk_hw *[]){2942 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw2943 },2944 .num_parents = 1,2945 .flags = CLK_SET_RATE_PARENT,2946 .ops = &clk_branch2_ops,2947 },2948 },2949};2950 2951static struct clk_branch gcc_qupv3_wrap2_s2_clk = {2952 .halt_reg = 0x1e3a4,2953 .halt_check = BRANCH_HALT_VOTED,2954 .clkr = {2955 .enable_reg = 0x52014,2956 .enable_mask = BIT(6),2957 .hw.init = &(struct clk_init_data){2958 .name = "gcc_qupv3_wrap2_s2_clk",2959 .parent_hws = (const struct clk_hw *[]){2960 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw2961 },2962 .num_parents = 1,2963 .flags = CLK_SET_RATE_PARENT,2964 .ops = &clk_branch2_ops,2965 },2966 },2967};2968 2969static struct clk_branch gcc_qupv3_wrap2_s3_clk = {2970 .halt_reg = 0x1e4d4,2971 .halt_check = BRANCH_HALT_VOTED,2972 .clkr = {2973 .enable_reg = 0x52014,2974 .enable_mask = BIT(7),2975 .hw.init = &(struct clk_init_data){2976 .name = "gcc_qupv3_wrap2_s3_clk",2977 .parent_hws = (const struct clk_hw *[]){2978 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw2979 },2980 .num_parents = 1,2981 .flags = CLK_SET_RATE_PARENT,2982 .ops = &clk_branch2_ops,2983 },2984 },2985};2986 2987static struct clk_branch gcc_qupv3_wrap2_s4_clk = {2988 .halt_reg = 0x1e604,2989 .halt_check = BRANCH_HALT_VOTED,2990 .clkr = {2991 .enable_reg = 0x52014,2992 .enable_mask = BIT(8),2993 .hw.init = &(struct clk_init_data){2994 .name = "gcc_qupv3_wrap2_s4_clk",2995 .parent_hws = (const struct clk_hw *[]){2996 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw2997 },2998 .num_parents = 1,2999 .flags = CLK_SET_RATE_PARENT,3000 .ops = &clk_branch2_ops,3001 },3002 },3003};3004 3005static struct clk_branch gcc_qupv3_wrap2_s5_clk = {3006 .halt_reg = 0x1e734,3007 .halt_check = BRANCH_HALT_VOTED,3008 .clkr = {3009 .enable_reg = 0x52014,3010 .enable_mask = BIT(9),3011 .hw.init = &(struct clk_init_data){3012 .name = "gcc_qupv3_wrap2_s5_clk",3013 .parent_hws = (const struct clk_hw *[]){3014 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw3015 },3016 .num_parents = 1,3017 .flags = CLK_SET_RATE_PARENT,3018 .ops = &clk_branch2_ops,3019 },3020 },3021};3022 3023static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {3024 .halt_reg = 0x17004,3025 .halt_check = BRANCH_HALT_VOTED,3026 .clkr = {3027 .enable_reg = 0x5200c,3028 .enable_mask = BIT(6),3029 .hw.init = &(struct clk_init_data){3030 .name = "gcc_qupv3_wrap_0_m_ahb_clk",3031 .ops = &clk_branch2_ops,3032 },3033 },3034};3035 3036static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {3037 .halt_reg = 0x17008,3038 .halt_check = BRANCH_HALT_VOTED,3039 .hwcg_reg = 0x17008,3040 .hwcg_bit = 1,3041 .clkr = {3042 .enable_reg = 0x5200c,3043 .enable_mask = BIT(7),3044 .hw.init = &(struct clk_init_data){3045 .name = "gcc_qupv3_wrap_0_s_ahb_clk",3046 .ops = &clk_branch2_ops,3047 },3048 },3049};3050 3051static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {3052 .halt_reg = 0x18004,3053 .halt_check = BRANCH_HALT_VOTED,3054 .clkr = {3055 .enable_reg = 0x5200c,3056 .enable_mask = BIT(20),3057 .hw.init = &(struct clk_init_data){3058 .name = "gcc_qupv3_wrap_1_m_ahb_clk",3059 .ops = &clk_branch2_ops,3060 },3061 },3062};3063 3064static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {3065 .halt_reg = 0x18008,3066 .halt_check = BRANCH_HALT_VOTED,3067 .hwcg_reg = 0x18008,3068 .hwcg_bit = 1,3069 .clkr = {3070 .enable_reg = 0x5200c,3071 .enable_mask = BIT(21),3072 .hw.init = &(struct clk_init_data){3073 .name = "gcc_qupv3_wrap_1_s_ahb_clk",3074 .ops = &clk_branch2_ops,3075 },3076 },3077};3078 3079static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {3080 .halt_reg = 0x1e004,3081 .halt_check = BRANCH_HALT_VOTED,3082 .clkr = {3083 .enable_reg = 0x52014,3084 .enable_mask = BIT(2),3085 .hw.init = &(struct clk_init_data){3086 .name = "gcc_qupv3_wrap_2_m_ahb_clk",3087 .ops = &clk_branch2_ops,3088 },3089 },3090};3091 3092static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {3093 .halt_reg = 0x1e008,3094 .halt_check = BRANCH_HALT_VOTED,3095 .hwcg_reg = 0x1e008,3096 .hwcg_bit = 1,3097 .clkr = {3098 .enable_reg = 0x52014,3099 .enable_mask = BIT(1),3100 .hw.init = &(struct clk_init_data){3101 .name = "gcc_qupv3_wrap_2_s_ahb_clk",3102 .ops = &clk_branch2_ops,3103 },3104 },3105};3106 3107static struct clk_branch gcc_sdcc2_ahb_clk = {3108 .halt_reg = 0x14008,3109 .halt_check = BRANCH_HALT,3110 .clkr = {3111 .enable_reg = 0x14008,3112 .enable_mask = BIT(0),3113 .hw.init = &(struct clk_init_data){3114 .name = "gcc_sdcc2_ahb_clk",3115 .ops = &clk_branch2_ops,3116 },3117 },3118};3119 3120static struct clk_branch gcc_sdcc2_apps_clk = {3121 .halt_reg = 0x14004,3122 .halt_check = BRANCH_HALT,3123 .clkr = {3124 .enable_reg = 0x14004,3125 .enable_mask = BIT(0),3126 .hw.init = &(struct clk_init_data){3127 .name = "gcc_sdcc2_apps_clk",3128 .parent_hws = (const struct clk_hw *[]){3129 &gcc_sdcc2_apps_clk_src.clkr.hw3130 },3131 .num_parents = 1,3132 .flags = CLK_SET_RATE_PARENT,3133 .ops = &clk_branch2_ops,3134 },3135 },3136};3137 3138static struct clk_branch gcc_sdcc4_ahb_clk = {3139 .halt_reg = 0x16008,3140 .halt_check = BRANCH_HALT,3141 .clkr = {3142 .enable_reg = 0x16008,3143 .enable_mask = BIT(0),3144 .hw.init = &(struct clk_init_data){3145 .name = "gcc_sdcc4_ahb_clk",3146 .ops = &clk_branch2_ops,3147 },3148 },3149};3150 3151static struct clk_branch gcc_sdcc4_apps_clk = {3152 .halt_reg = 0x16004,3153 .halt_check = BRANCH_HALT,3154 .clkr = {3155 .enable_reg = 0x16004,3156 .enable_mask = BIT(0),3157 .hw.init = &(struct clk_init_data){3158 .name = "gcc_sdcc4_apps_clk",3159 .parent_hws = (const struct clk_hw *[]){3160 &gcc_sdcc4_apps_clk_src.clkr.hw3161 },3162 .num_parents = 1,3163 .flags = CLK_SET_RATE_PARENT,3164 .ops = &clk_branch2_ops,3165 },3166 },3167};3168 3169static struct clk_branch gcc_tsif_ahb_clk = {3170 .halt_reg = 0x36004,3171 .halt_check = BRANCH_HALT,3172 .clkr = {3173 .enable_reg = 0x36004,3174 .enable_mask = BIT(0),3175 .hw.init = &(struct clk_init_data){3176 .name = "gcc_tsif_ahb_clk",3177 .ops = &clk_branch2_ops,3178 },3179 },3180};3181 3182static struct clk_branch gcc_tsif_inactivity_timers_clk = {3183 .halt_reg = 0x3600c,3184 .halt_check = BRANCH_HALT,3185 .clkr = {3186 .enable_reg = 0x3600c,3187 .enable_mask = BIT(0),3188 .hw.init = &(struct clk_init_data){3189 .name = "gcc_tsif_inactivity_timers_clk",3190 .ops = &clk_branch2_ops,3191 },3192 },3193};3194 3195static struct clk_branch gcc_tsif_ref_clk = {3196 .halt_reg = 0x36008,3197 .halt_check = BRANCH_HALT,3198 .clkr = {3199 .enable_reg = 0x36008,3200 .enable_mask = BIT(0),3201 .hw.init = &(struct clk_init_data){3202 .name = "gcc_tsif_ref_clk",3203 .parent_hws = (const struct clk_hw *[]){3204 &gcc_tsif_ref_clk_src.clkr.hw3205 },3206 .num_parents = 1,3207 .flags = CLK_SET_RATE_PARENT,3208 .ops = &clk_branch2_ops,3209 },3210 },3211};3212 3213static struct clk_branch gcc_ufs_card_2_ahb_clk = {3214 .halt_reg = 0xa2014,3215 .halt_check = BRANCH_HALT,3216 .hwcg_reg = 0xa2014,3217 .hwcg_bit = 1,3218 .clkr = {3219 .enable_reg = 0xa2014,3220 .enable_mask = BIT(0),3221 .hw.init = &(struct clk_init_data){3222 .name = "gcc_ufs_card_2_ahb_clk",3223 .ops = &clk_branch2_ops,3224 },3225 },3226};3227 3228static struct clk_branch gcc_ufs_card_2_axi_clk = {3229 .halt_reg = 0xa2010,3230 .halt_check = BRANCH_HALT,3231 .hwcg_reg = 0xa2010,3232 .hwcg_bit = 1,3233 .clkr = {3234 .enable_reg = 0xa2010,3235 .enable_mask = BIT(0),3236 .hw.init = &(struct clk_init_data){3237 .name = "gcc_ufs_card_2_axi_clk",3238 .parent_hws = (const struct clk_hw *[]){3239 &gcc_ufs_card_2_axi_clk_src.clkr.hw3240 },3241 .num_parents = 1,3242 .flags = CLK_SET_RATE_PARENT,3243 .ops = &clk_branch2_ops,3244 },3245 },3246};3247 3248static struct clk_branch gcc_ufs_card_2_ice_core_clk = {3249 .halt_reg = 0xa205c,3250 .halt_check = BRANCH_HALT,3251 .hwcg_reg = 0xa205c,3252 .hwcg_bit = 1,3253 .clkr = {3254 .enable_reg = 0xa205c,3255 .enable_mask = BIT(0),3256 .hw.init = &(struct clk_init_data){3257 .name = "gcc_ufs_card_2_ice_core_clk",3258 .parent_hws = (const struct clk_hw *[]){3259 &gcc_ufs_card_2_ice_core_clk_src.clkr.hw3260 },3261 .num_parents = 1,3262 .flags = CLK_SET_RATE_PARENT,3263 .ops = &clk_branch2_ops,3264 },3265 },3266};3267 3268static struct clk_branch gcc_ufs_card_2_phy_aux_clk = {3269 .halt_reg = 0xa2090,3270 .halt_check = BRANCH_HALT,3271 .hwcg_reg = 0xa2090,3272 .hwcg_bit = 1,3273 .clkr = {3274 .enable_reg = 0xa2090,3275 .enable_mask = BIT(0),3276 .hw.init = &(struct clk_init_data){3277 .name = "gcc_ufs_card_2_phy_aux_clk",3278 .parent_hws = (const struct clk_hw *[]){3279 &gcc_ufs_card_2_phy_aux_clk_src.clkr.hw3280 },3281 .num_parents = 1,3282 .flags = CLK_SET_RATE_PARENT,3283 .ops = &clk_branch2_ops,3284 },3285 },3286};3287 3288static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = {3289 .halt_reg = 0xa201c,3290 .halt_check = BRANCH_HALT,3291 .clkr = {3292 .enable_reg = 0xa201c,3293 .enable_mask = BIT(0),3294 .hw.init = &(struct clk_init_data){3295 .name = "gcc_ufs_card_2_rx_symbol_0_clk",3296 .ops = &clk_branch2_ops,3297 },3298 },3299};3300 3301static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = {3302 .halt_reg = 0xa20ac,3303 .halt_check = BRANCH_HALT,3304 .clkr = {3305 .enable_reg = 0xa20ac,3306 .enable_mask = BIT(0),3307 .hw.init = &(struct clk_init_data){3308 .name = "gcc_ufs_card_2_rx_symbol_1_clk",3309 .ops = &clk_branch2_ops,3310 },3311 },3312};3313 3314static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = {3315 .halt_reg = 0xa2018,3316 .halt_check = BRANCH_HALT,3317 .clkr = {3318 .enable_reg = 0xa2018,3319 .enable_mask = BIT(0),3320 .hw.init = &(struct clk_init_data){3321 .name = "gcc_ufs_card_2_tx_symbol_0_clk",3322 .ops = &clk_branch2_ops,3323 },3324 },3325};3326 3327static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {3328 .halt_reg = 0xa2058,3329 .halt_check = BRANCH_HALT,3330 .hwcg_reg = 0xa2058,3331 .hwcg_bit = 1,3332 .clkr = {3333 .enable_reg = 0xa2058,3334 .enable_mask = BIT(0),3335 .hw.init = &(struct clk_init_data){3336 .name = "gcc_ufs_card_2_unipro_core_clk",3337 .parent_hws = (const struct clk_hw *[]){3338 &gcc_ufs_card_2_unipro_core_clk_src.clkr.hw3339 },3340 .num_parents = 1,3341 .flags = CLK_SET_RATE_PARENT,3342 .ops = &clk_branch2_ops,3343 },3344 },3345};3346 3347static struct clk_branch gcc_ufs_card_clkref_en = {3348 .halt_reg = 0x8c004,3349 .halt_check = BRANCH_HALT,3350 .clkr = {3351 .enable_reg = 0x8c004,3352 .enable_mask = BIT(0),3353 .hw.init = &(const struct clk_init_data) {3354 .name = "gcc_ufs_card_clkref_en",3355 .ops = &clk_branch2_ops,3356 },3357 },3358};3359 3360static struct clk_branch gcc_ufs_card_ahb_clk = {3361 .halt_reg = 0x75014,3362 .halt_check = BRANCH_HALT,3363 .hwcg_reg = 0x75014,3364 .hwcg_bit = 1,3365 .clkr = {3366 .enable_reg = 0x75014,3367 .enable_mask = BIT(0),3368 .hw.init = &(struct clk_init_data){3369 .name = "gcc_ufs_card_ahb_clk",3370 .ops = &clk_branch2_ops,3371 },3372 },3373};3374 3375static struct clk_branch gcc_ufs_card_axi_clk = {3376 .halt_reg = 0x75010,3377 .halt_check = BRANCH_HALT,3378 .hwcg_reg = 0x75010,3379 .hwcg_bit = 1,3380 .clkr = {3381 .enable_reg = 0x75010,3382 .enable_mask = BIT(0),3383 .hw.init = &(struct clk_init_data){3384 .name = "gcc_ufs_card_axi_clk",3385 .parent_hws = (const struct clk_hw *[]){3386 &gcc_ufs_card_axi_clk_src.clkr.hw3387 },3388 .num_parents = 1,3389 .flags = CLK_SET_RATE_PARENT,3390 .ops = &clk_branch2_ops,3391 },3392 },3393};3394 3395static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {3396 .halt_reg = 0x75010,3397 .halt_check = BRANCH_HALT,3398 .hwcg_reg = 0x75010,3399 .hwcg_bit = 1,3400 .clkr = {3401 .enable_reg = 0x75010,3402 .enable_mask = BIT(1),3403 .hw.init = &(struct clk_init_data){3404 .name = "gcc_ufs_card_axi_hw_ctl_clk",3405 .parent_hws = (const struct clk_hw *[]){3406 &gcc_ufs_card_axi_clk.clkr.hw3407 },3408 .num_parents = 1,3409 .flags = CLK_SET_RATE_PARENT,3410 .ops = &clk_branch_simple_ops,3411 },3412 },3413};3414 3415static struct clk_branch gcc_ufs_card_ice_core_clk = {3416 .halt_reg = 0x7505c,3417 .halt_check = BRANCH_HALT,3418 .hwcg_reg = 0x7505c,3419 .hwcg_bit = 1,3420 .clkr = {3421 .enable_reg = 0x7505c,3422 .enable_mask = BIT(0),3423 .hw.init = &(struct clk_init_data){3424 .name = "gcc_ufs_card_ice_core_clk",3425 .parent_hws = (const struct clk_hw *[]){3426 &gcc_ufs_card_ice_core_clk_src.clkr.hw3427 },3428 .num_parents = 1,3429 .flags = CLK_SET_RATE_PARENT,3430 .ops = &clk_branch2_ops,3431 },3432 },3433};3434 3435static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {3436 .halt_reg = 0x7505c,3437 .halt_check = BRANCH_HALT,3438 .hwcg_reg = 0x7505c,3439 .hwcg_bit = 1,3440 .clkr = {3441 .enable_reg = 0x7505c,3442 .enable_mask = BIT(1),3443 .hw.init = &(struct clk_init_data){3444 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",3445 .parent_hws = (const struct clk_hw *[]){3446 &gcc_ufs_card_ice_core_clk.clkr.hw3447 },3448 .num_parents = 1,3449 .flags = CLK_SET_RATE_PARENT,3450 .ops = &clk_branch_simple_ops,3451 },3452 },3453};3454 3455static struct clk_branch gcc_ufs_card_phy_aux_clk = {3456 .halt_reg = 0x75090,3457 .halt_check = BRANCH_HALT,3458 .hwcg_reg = 0x75090,3459 .hwcg_bit = 1,3460 .clkr = {3461 .enable_reg = 0x75090,3462 .enable_mask = BIT(0),3463 .hw.init = &(struct clk_init_data){3464 .name = "gcc_ufs_card_phy_aux_clk",3465 .parent_hws = (const struct clk_hw *[]){3466 &gcc_ufs_card_phy_aux_clk_src.clkr.hw3467 },3468 .num_parents = 1,3469 .flags = CLK_SET_RATE_PARENT,3470 .ops = &clk_branch2_ops,3471 },3472 },3473};3474 3475static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {3476 .halt_reg = 0x75090,3477 .halt_check = BRANCH_HALT,3478 .hwcg_reg = 0x75090,3479 .hwcg_bit = 1,3480 .clkr = {3481 .enable_reg = 0x75090,3482 .enable_mask = BIT(1),3483 .hw.init = &(struct clk_init_data){3484 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",3485 .parent_hws = (const struct clk_hw *[]){3486 &gcc_ufs_card_phy_aux_clk.clkr.hw3487 },3488 .num_parents = 1,3489 .flags = CLK_SET_RATE_PARENT,3490 .ops = &clk_branch_simple_ops,3491 },3492 },3493};3494 3495static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {3496 .halt_reg = 0x7501c,3497 .halt_check = BRANCH_HALT_DELAY,3498 .clkr = {3499 .enable_reg = 0x7501c,3500 .enable_mask = BIT(0),3501 .hw.init = &(struct clk_init_data){3502 .name = "gcc_ufs_card_rx_symbol_0_clk",3503 .ops = &clk_branch2_ops,3504 },3505 },3506};3507 3508static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {3509 .halt_reg = 0x750ac,3510 .halt_check = BRANCH_HALT_DELAY,3511 .clkr = {3512 .enable_reg = 0x750ac,3513 .enable_mask = BIT(0),3514 .hw.init = &(struct clk_init_data){3515 .name = "gcc_ufs_card_rx_symbol_1_clk",3516 .ops = &clk_branch2_ops,3517 },3518 },3519};3520 3521static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {3522 .halt_reg = 0x75018,3523 .halt_check = BRANCH_HALT_DELAY,3524 .clkr = {3525 .enable_reg = 0x75018,3526 .enable_mask = BIT(0),3527 .hw.init = &(struct clk_init_data){3528 .name = "gcc_ufs_card_tx_symbol_0_clk",3529 .ops = &clk_branch2_ops,3530 },3531 },3532};3533 3534static struct clk_branch gcc_ufs_card_unipro_core_clk = {3535 .halt_reg = 0x75058,3536 .halt_check = BRANCH_HALT,3537 .hwcg_reg = 0x75058,3538 .hwcg_bit = 1,3539 .clkr = {3540 .enable_reg = 0x75058,3541 .enable_mask = BIT(0),3542 .hw.init = &(struct clk_init_data){3543 .name = "gcc_ufs_card_unipro_core_clk",3544 .parent_hws = (const struct clk_hw *[]){3545 &gcc_ufs_card_unipro_core_clk_src.clkr.hw3546 },3547 .num_parents = 1,3548 .flags = CLK_SET_RATE_PARENT,3549 .ops = &clk_branch2_ops,3550 },3551 },3552};3553 3554static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {3555 .halt_reg = 0x75058,3556 .halt_check = BRANCH_HALT,3557 .hwcg_reg = 0x75058,3558 .hwcg_bit = 1,3559 .clkr = {3560 .enable_reg = 0x75058,3561 .enable_mask = BIT(1),3562 .hw.init = &(struct clk_init_data){3563 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",3564 .parent_hws = (const struct clk_hw *[]){3565 &gcc_ufs_card_unipro_core_clk.clkr.hw3566 },3567 .num_parents = 1,3568 .flags = CLK_SET_RATE_PARENT,3569 .ops = &clk_branch_simple_ops,3570 },3571 },3572};3573 3574static struct clk_branch gcc_ufs_mem_clkref_en = {3575 .halt_reg = 0x8c000,3576 .halt_check = BRANCH_HALT,3577 .clkr = {3578 .enable_reg = 0x8c000,3579 .enable_mask = BIT(0),3580 .hw.init = &(const struct clk_init_data) {3581 .name = "gcc_ufs_mem_clkref_en",3582 .ops = &clk_branch2_ops,3583 },3584 },3585};3586 3587static struct clk_branch gcc_ufs_phy_ahb_clk = {3588 .halt_reg = 0x77014,3589 .halt_check = BRANCH_HALT,3590 .hwcg_reg = 0x77014,3591 .hwcg_bit = 1,3592 .clkr = {3593 .enable_reg = 0x77014,3594 .enable_mask = BIT(0),3595 .hw.init = &(struct clk_init_data){3596 .name = "gcc_ufs_phy_ahb_clk",3597 .ops = &clk_branch2_ops,3598 },3599 },3600};3601 3602static struct clk_branch gcc_ufs_phy_axi_clk = {3603 .halt_reg = 0x77010,3604 .halt_check = BRANCH_HALT,3605 .hwcg_reg = 0x77010,3606 .hwcg_bit = 1,3607 .clkr = {3608 .enable_reg = 0x77010,3609 .enable_mask = BIT(0),3610 .hw.init = &(struct clk_init_data){3611 .name = "gcc_ufs_phy_axi_clk",3612 .parent_hws = (const struct clk_hw *[]){3613 &gcc_ufs_phy_axi_clk_src.clkr.hw3614 },3615 .num_parents = 1,3616 .flags = CLK_SET_RATE_PARENT,3617 .ops = &clk_branch2_ops,3618 },3619 },3620};3621 3622static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {3623 .halt_reg = 0x77010,3624 .halt_check = BRANCH_HALT,3625 .hwcg_reg = 0x77010,3626 .hwcg_bit = 1,3627 .clkr = {3628 .enable_reg = 0x77010,3629 .enable_mask = BIT(1),3630 .hw.init = &(struct clk_init_data){3631 .name = "gcc_ufs_phy_axi_hw_ctl_clk",3632 .parent_hws = (const struct clk_hw *[]){3633 &gcc_ufs_phy_axi_clk.clkr.hw3634 },3635 .num_parents = 1,3636 .flags = CLK_SET_RATE_PARENT,3637 .ops = &clk_branch_simple_ops,3638 },3639 },3640};3641 3642static struct clk_branch gcc_ufs_phy_ice_core_clk = {3643 .halt_reg = 0x7705c,3644 .halt_check = BRANCH_HALT,3645 .hwcg_reg = 0x7705c,3646 .hwcg_bit = 1,3647 .clkr = {3648 .enable_reg = 0x7705c,3649 .enable_mask = BIT(0),3650 .hw.init = &(struct clk_init_data){3651 .name = "gcc_ufs_phy_ice_core_clk",3652 .parent_hws = (const struct clk_hw *[]){3653 &gcc_ufs_phy_ice_core_clk_src.clkr.hw3654 },3655 .num_parents = 1,3656 .flags = CLK_SET_RATE_PARENT,3657 .ops = &clk_branch2_ops,3658 },3659 },3660};3661 3662static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {3663 .halt_reg = 0x7705c,3664 .halt_check = BRANCH_HALT,3665 .hwcg_reg = 0x7705c,3666 .hwcg_bit = 1,3667 .clkr = {3668 .enable_reg = 0x7705c,3669 .enable_mask = BIT(1),3670 .hw.init = &(struct clk_init_data){3671 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",3672 .parent_hws = (const struct clk_hw *[]){3673 &gcc_ufs_phy_ice_core_clk.clkr.hw3674 },3675 .num_parents = 1,3676 .flags = CLK_SET_RATE_PARENT,3677 .ops = &clk_branch_simple_ops,3678 },3679 },3680};3681 3682static struct clk_branch gcc_ufs_phy_phy_aux_clk = {3683 .halt_reg = 0x77090,3684 .halt_check = BRANCH_HALT,3685 .hwcg_reg = 0x77090,3686 .hwcg_bit = 1,3687 .clkr = {3688 .enable_reg = 0x77090,3689 .enable_mask = BIT(0),3690 .hw.init = &(struct clk_init_data){3691 .name = "gcc_ufs_phy_phy_aux_clk",3692 .parent_hws = (const struct clk_hw *[]){3693 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw3694 },3695 .num_parents = 1,3696 .flags = CLK_SET_RATE_PARENT,3697 .ops = &clk_branch2_ops,3698 },3699 },3700};3701 3702static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {3703 .halt_reg = 0x77090,3704 .halt_check = BRANCH_HALT,3705 .hwcg_reg = 0x77090,3706 .hwcg_bit = 1,3707 .clkr = {3708 .enable_reg = 0x77090,3709 .enable_mask = BIT(1),3710 .hw.init = &(struct clk_init_data){3711 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",3712 .parent_hws = (const struct clk_hw *[]){3713 &gcc_ufs_phy_phy_aux_clk.clkr.hw3714 },3715 .num_parents = 1,3716 .flags = CLK_SET_RATE_PARENT,3717 .ops = &clk_branch_simple_ops,3718 },3719 },3720};3721 3722static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {3723 .halt_reg = 0x7701c,3724 .halt_check = BRANCH_HALT_SKIP,3725 .clkr = {3726 .enable_reg = 0x7701c,3727 .enable_mask = BIT(0),3728 .hw.init = &(struct clk_init_data){3729 .name = "gcc_ufs_phy_rx_symbol_0_clk",3730 .ops = &clk_branch2_ops,3731 },3732 },3733};3734 3735static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {3736 .halt_reg = 0x770ac,3737 .halt_check = BRANCH_HALT_SKIP,3738 .clkr = {3739 .enable_reg = 0x770ac,3740 .enable_mask = BIT(0),3741 .hw.init = &(struct clk_init_data){3742 .name = "gcc_ufs_phy_rx_symbol_1_clk",3743 .ops = &clk_branch2_ops,3744 },3745 },3746};3747 3748static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {3749 .halt_reg = 0x77018,3750 .halt_check = BRANCH_HALT_SKIP,3751 .clkr = {3752 .enable_reg = 0x77018,3753 .enable_mask = BIT(0),3754 .hw.init = &(struct clk_init_data){3755 .name = "gcc_ufs_phy_tx_symbol_0_clk",3756 .ops = &clk_branch2_ops,3757 },3758 },3759};3760 3761static struct clk_branch gcc_ufs_phy_unipro_core_clk = {3762 .halt_reg = 0x77058,3763 .halt_check = BRANCH_HALT,3764 .hwcg_reg = 0x77058,3765 .hwcg_bit = 1,3766 .clkr = {3767 .enable_reg = 0x77058,3768 .enable_mask = BIT(0),3769 .hw.init = &(struct clk_init_data){3770 .name = "gcc_ufs_phy_unipro_core_clk",3771 .parent_hws = (const struct clk_hw *[]){3772 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw3773 },3774 .num_parents = 1,3775 .flags = CLK_SET_RATE_PARENT,3776 .ops = &clk_branch2_ops,3777 },3778 },3779};3780 3781static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {3782 .halt_reg = 0x77058,3783 .halt_check = BRANCH_HALT,3784 .hwcg_reg = 0x77058,3785 .hwcg_bit = 1,3786 .clkr = {3787 .enable_reg = 0x77058,3788 .enable_mask = BIT(1),3789 .hw.init = &(struct clk_init_data){3790 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",3791 .parent_hws = (const struct clk_hw *[]){3792 &gcc_ufs_phy_unipro_core_clk.clkr.hw3793 },3794 .num_parents = 1,3795 .flags = CLK_SET_RATE_PARENT,3796 .ops = &clk_branch_simple_ops,3797 },3798 },3799};3800 3801static struct clk_branch gcc_usb30_mp_master_clk = {3802 .halt_reg = 0xa6010,3803 .halt_check = BRANCH_HALT,3804 .clkr = {3805 .enable_reg = 0xa6010,3806 .enable_mask = BIT(0),3807 .hw.init = &(struct clk_init_data){3808 .name = "gcc_usb30_mp_master_clk",3809 .parent_hws = (const struct clk_hw *[]){3810 &gcc_usb30_mp_master_clk_src.clkr.hw },3811 .num_parents = 1,3812 .flags = CLK_SET_RATE_PARENT,3813 .ops = &clk_branch2_ops,3814 },3815 },3816};3817 3818static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {3819 .halt_reg = 0xa6018,3820 .halt_check = BRANCH_HALT,3821 .clkr = {3822 .enable_reg = 0xa6018,3823 .enable_mask = BIT(0),3824 .hw.init = &(struct clk_init_data){3825 .name = "gcc_usb30_mp_mock_utmi_clk",3826 .parent_hws = (const struct clk_hw *[]){3827 &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw3828 },3829 .num_parents = 1,3830 .flags = CLK_SET_RATE_PARENT,3831 .ops = &clk_branch2_ops,3832 },3833 },3834};3835 3836static struct clk_branch gcc_usb30_mp_sleep_clk = {3837 .halt_reg = 0xa6014,3838 .halt_check = BRANCH_HALT,3839 .clkr = {3840 .enable_reg = 0xa6014,3841 .enable_mask = BIT(0),3842 .hw.init = &(struct clk_init_data){3843 .name = "gcc_usb30_mp_sleep_clk",3844 .ops = &clk_branch2_ops,3845 },3846 },3847};3848 3849static struct clk_branch gcc_usb30_prim_master_clk = {3850 .halt_reg = 0xf010,3851 .halt_check = BRANCH_HALT,3852 .clkr = {3853 .enable_reg = 0xf010,3854 .enable_mask = BIT(0),3855 .hw.init = &(struct clk_init_data){3856 .name = "gcc_usb30_prim_master_clk",3857 .parent_hws = (const struct clk_hw *[]){3858 &gcc_usb30_prim_master_clk_src.clkr.hw },3859 .num_parents = 1,3860 .flags = CLK_SET_RATE_PARENT,3861 .ops = &clk_branch2_ops,3862 },3863 },3864};3865 3866static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {3867 .halt_reg = 0xf018,3868 .halt_check = BRANCH_HALT,3869 .clkr = {3870 .enable_reg = 0xf018,3871 .enable_mask = BIT(0),3872 .hw.init = &(struct clk_init_data){3873 .name = "gcc_usb30_prim_mock_utmi_clk",3874 .parent_hws = (const struct clk_hw *[]){3875 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw3876 },3877 .num_parents = 1,3878 .flags = CLK_SET_RATE_PARENT,3879 .ops = &clk_branch2_ops,3880 },3881 },3882};3883 3884static struct clk_branch gcc_usb30_prim_sleep_clk = {3885 .halt_reg = 0xf014,3886 .halt_check = BRANCH_HALT,3887 .clkr = {3888 .enable_reg = 0xf014,3889 .enable_mask = BIT(0),3890 .hw.init = &(struct clk_init_data){3891 .name = "gcc_usb30_prim_sleep_clk",3892 .ops = &clk_branch2_ops,3893 },3894 },3895};3896 3897static struct clk_branch gcc_usb30_sec_master_clk = {3898 .halt_reg = 0x10010,3899 .halt_check = BRANCH_HALT,3900 .clkr = {3901 .enable_reg = 0x10010,3902 .enable_mask = BIT(0),3903 .hw.init = &(struct clk_init_data){3904 .name = "gcc_usb30_sec_master_clk",3905 .parent_hws = (const struct clk_hw *[]){3906 &gcc_usb30_sec_master_clk_src.clkr.hw },3907 .num_parents = 1,3908 .flags = CLK_SET_RATE_PARENT,3909 .ops = &clk_branch2_ops,3910 },3911 },3912};3913 3914static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {3915 .halt_reg = 0x10018,3916 .halt_check = BRANCH_HALT,3917 .clkr = {3918 .enable_reg = 0x10018,3919 .enable_mask = BIT(0),3920 .hw.init = &(struct clk_init_data){3921 .name = "gcc_usb30_sec_mock_utmi_clk",3922 .parent_hws = (const struct clk_hw *[]){3923 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw3924 },3925 .num_parents = 1,3926 .flags = CLK_SET_RATE_PARENT,3927 .ops = &clk_branch2_ops,3928 },3929 },3930};3931 3932static struct clk_branch gcc_usb30_sec_sleep_clk = {3933 .halt_reg = 0x10014,3934 .halt_check = BRANCH_HALT,3935 .clkr = {3936 .enable_reg = 0x10014,3937 .enable_mask = BIT(0),3938 .hw.init = &(struct clk_init_data){3939 .name = "gcc_usb30_sec_sleep_clk",3940 .ops = &clk_branch2_ops,3941 },3942 },3943};3944 3945static struct clk_branch gcc_usb3_mp_phy_aux_clk = {3946 .halt_reg = 0xa6050,3947 .halt_check = BRANCH_HALT,3948 .clkr = {3949 .enable_reg = 0xa6050,3950 .enable_mask = BIT(0),3951 .hw.init = &(struct clk_init_data){3952 .name = "gcc_usb3_mp_phy_aux_clk",3953 .parent_hws = (const struct clk_hw *[]){3954 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw3955 },3956 .num_parents = 1,3957 .flags = CLK_SET_RATE_PARENT,3958 .ops = &clk_branch2_ops,3959 },3960 },3961};3962 3963static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {3964 .halt_reg = 0xa6054,3965 .halt_check = BRANCH_HALT,3966 .clkr = {3967 .enable_reg = 0xa6054,3968 .enable_mask = BIT(0),3969 .hw.init = &(struct clk_init_data){3970 .name = "gcc_usb3_mp_phy_com_aux_clk",3971 .parent_hws = (const struct clk_hw *[]){3972 &gcc_usb3_mp_phy_aux_clk_src.clkr.hw3973 },3974 .num_parents = 1,3975 .flags = CLK_SET_RATE_PARENT,3976 .ops = &clk_branch2_ops,3977 },3978 },3979};3980 3981static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {3982 .halt_reg = 0xa6058,3983 .halt_check = BRANCH_HALT_SKIP,3984 .clkr = {3985 .enable_reg = 0xa6058,3986 .enable_mask = BIT(0),3987 .hw.init = &(struct clk_init_data){3988 .name = "gcc_usb3_mp_phy_pipe_0_clk",3989 .ops = &clk_branch2_ops,3990 },3991 },3992};3993 3994static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {3995 .halt_reg = 0xa605c,3996 .halt_check = BRANCH_HALT_SKIP,3997 .clkr = {3998 .enable_reg = 0xa605c,3999 .enable_mask = BIT(0),4000 .hw.init = &(struct clk_init_data){4001 .name = "gcc_usb3_mp_phy_pipe_1_clk",4002 .ops = &clk_branch2_ops,4003 },4004 },4005};4006 4007static struct clk_branch gcc_usb3_prim_clkref_clk = {4008 .halt_reg = 0x8c008,4009 .halt_check = BRANCH_HALT,4010 .clkr = {4011 .enable_reg = 0x8c008,4012 .enable_mask = BIT(0),4013 .hw.init = &(struct clk_init_data){4014 .name = "gcc_usb3_prim_clkref_clk",4015 .ops = &clk_branch2_ops,4016 },4017 },4018};4019 4020static struct clk_branch gcc_usb3_prim_phy_aux_clk = {4021 .halt_reg = 0xf050,4022 .halt_check = BRANCH_HALT,4023 .clkr = {4024 .enable_reg = 0xf050,4025 .enable_mask = BIT(0),4026 .hw.init = &(struct clk_init_data){4027 .name = "gcc_usb3_prim_phy_aux_clk",4028 .parent_hws = (const struct clk_hw *[]){4029 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw4030 },4031 .num_parents = 1,4032 .flags = CLK_SET_RATE_PARENT,4033 .ops = &clk_branch2_ops,4034 },4035 },4036};4037 4038static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {4039 .halt_reg = 0xf054,4040 .halt_check = BRANCH_HALT,4041 .clkr = {4042 .enable_reg = 0xf054,4043 .enable_mask = BIT(0),4044 .hw.init = &(struct clk_init_data){4045 .name = "gcc_usb3_prim_phy_com_aux_clk",4046 .parent_hws = (const struct clk_hw *[]){4047 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw4048 },4049 .num_parents = 1,4050 .flags = CLK_SET_RATE_PARENT,4051 .ops = &clk_branch2_ops,4052 },4053 },4054};4055 4056static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {4057 .halt_reg = 0xf058,4058 .halt_check = BRANCH_HALT_SKIP,4059 .clkr = {4060 .enable_reg = 0xf058,4061 .enable_mask = BIT(0),4062 .hw.init = &(struct clk_init_data){4063 .name = "gcc_usb3_prim_phy_pipe_clk",4064 .ops = &clk_branch2_ops,4065 },4066 },4067};4068 4069static struct clk_branch gcc_usb3_sec_clkref_clk = {4070 .halt_reg = 0x8c028,4071 .halt_check = BRANCH_HALT,4072 .clkr = {4073 .enable_reg = 0x8c028,4074 .enable_mask = BIT(0),4075 .hw.init = &(struct clk_init_data){4076 .name = "gcc_usb3_sec_clkref_clk",4077 .ops = &clk_branch2_ops,4078 },4079 },4080};4081 4082static struct clk_branch gcc_usb3_sec_phy_aux_clk = {4083 .halt_reg = 0x10050,4084 .halt_check = BRANCH_HALT,4085 .clkr = {4086 .enable_reg = 0x10050,4087 .enable_mask = BIT(0),4088 .hw.init = &(struct clk_init_data){4089 .name = "gcc_usb3_sec_phy_aux_clk",4090 .parent_hws = (const struct clk_hw *[]){4091 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw4092 },4093 .num_parents = 1,4094 .flags = CLK_SET_RATE_PARENT,4095 .ops = &clk_branch2_ops,4096 },4097 },4098};4099 4100static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {4101 .halt_reg = 0x10054,4102 .halt_check = BRANCH_HALT,4103 .clkr = {4104 .enable_reg = 0x10054,4105 .enable_mask = BIT(0),4106 .hw.init = &(struct clk_init_data){4107 .name = "gcc_usb3_sec_phy_com_aux_clk",4108 .parent_hws = (const struct clk_hw *[]){4109 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw4110 },4111 .num_parents = 1,4112 .flags = CLK_SET_RATE_PARENT,4113 .ops = &clk_branch2_ops,4114 },4115 },4116};4117 4118static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {4119 .halt_reg = 0x10058,4120 .halt_check = BRANCH_HALT_SKIP,4121 .clkr = {4122 .enable_reg = 0x10058,4123 .enable_mask = BIT(0),4124 .hw.init = &(struct clk_init_data){4125 .name = "gcc_usb3_sec_phy_pipe_clk",4126 .ops = &clk_branch2_ops,4127 },4128 },4129};4130 4131static struct clk_branch gcc_video_axi0_clk = {4132 .halt_reg = 0xb024,4133 .halt_check = BRANCH_HALT,4134 .clkr = {4135 .enable_reg = 0xb024,4136 .enable_mask = BIT(0),4137 .hw.init = &(struct clk_init_data){4138 .name = "gcc_video_axi0_clk",4139 .ops = &clk_branch2_ops,4140 },4141 },4142};4143 4144static struct clk_branch gcc_video_axi1_clk = {4145 .halt_reg = 0xb028,4146 .halt_check = BRANCH_HALT,4147 .clkr = {4148 .enable_reg = 0xb028,4149 .enable_mask = BIT(0),4150 .hw.init = &(struct clk_init_data){4151 .name = "gcc_video_axi1_clk",4152 .ops = &clk_branch2_ops,4153 },4154 },4155};4156 4157static struct clk_branch gcc_video_axic_clk = {4158 .halt_reg = 0xb02c,4159 .halt_check = BRANCH_HALT,4160 .clkr = {4161 .enable_reg = 0xb02c,4162 .enable_mask = BIT(0),4163 .hw.init = &(struct clk_init_data){4164 .name = "gcc_video_axic_clk",4165 .ops = &clk_branch2_ops,4166 },4167 },4168};4169 4170static struct gdsc usb30_sec_gdsc = {4171 .gdscr = 0x10004,4172 .pd = {4173 .name = "usb30_sec_gdsc",4174 },4175 .pwrsts = PWRSTS_OFF_ON,4176 .flags = POLL_CFG_GDSCR,4177};4178 4179static struct gdsc emac_gdsc = {4180 .gdscr = 0x6004,4181 .pd = {4182 .name = "emac_gdsc",4183 },4184 .pwrsts = PWRSTS_OFF_ON,4185 .flags = POLL_CFG_GDSCR,4186};4187 4188static struct gdsc usb30_prim_gdsc = {4189 .gdscr = 0xf004,4190 .pd = {4191 .name = "usb30_prim_gdsc",4192 },4193 .pwrsts = PWRSTS_OFF_ON,4194 .flags = POLL_CFG_GDSCR,4195};4196 4197static struct gdsc pcie_0_gdsc = {4198 .gdscr = 0x6b004,4199 .pd = {4200 .name = "pcie_0_gdsc",4201 },4202 .pwrsts = PWRSTS_OFF_ON,4203 .flags = POLL_CFG_GDSCR,4204};4205 4206static struct gdsc ufs_card_gdsc = {4207 .gdscr = 0x75004,4208 .pd = {4209 .name = "ufs_card_gdsc",4210 },4211 .pwrsts = PWRSTS_OFF_ON,4212 .flags = POLL_CFG_GDSCR,4213};4214 4215static struct gdsc ufs_phy_gdsc = {4216 .gdscr = 0x77004,4217 .pd = {4218 .name = "ufs_phy_gdsc",4219 },4220 .pwrsts = PWRSTS_OFF_ON,4221 .flags = POLL_CFG_GDSCR,4222};4223 4224static struct gdsc pcie_1_gdsc = {4225 .gdscr = 0x8d004,4226 .pd = {4227 .name = "pcie_1_gdsc",4228 },4229 .pwrsts = PWRSTS_OFF_ON,4230 .flags = POLL_CFG_GDSCR,4231};4232 4233static struct gdsc pcie_2_gdsc = {4234 .gdscr = 0x9d004,4235 .pd = {4236 .name = "pcie_2_gdsc",4237 },4238 .pwrsts = PWRSTS_OFF_ON,4239 .flags = POLL_CFG_GDSCR,4240};4241 4242static struct gdsc ufs_card_2_gdsc = {4243 .gdscr = 0xa2004,4244 .pd = {4245 .name = "ufs_card_2_gdsc",4246 },4247 .pwrsts = PWRSTS_OFF_ON,4248 .flags = POLL_CFG_GDSCR,4249};4250 4251static struct gdsc pcie_3_gdsc = {4252 .gdscr = 0xa3004,4253 .pd = {4254 .name = "pcie_3_gdsc",4255 },4256 .pwrsts = PWRSTS_OFF_ON,4257 .flags = POLL_CFG_GDSCR,4258};4259 4260static struct gdsc usb30_mp_gdsc = {4261 .gdscr = 0xa6004,4262 .pd = {4263 .name = "usb30_mp_gdsc",4264 },4265 .pwrsts = PWRSTS_OFF_ON,4266 .flags = POLL_CFG_GDSCR,4267};4268 4269static struct clk_regmap *gcc_sc8180x_clocks[] = {4270 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,4271 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,4272 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,4273 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,4274 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,4275 [GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,4276 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,4277 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,4278 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,4279 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,4280 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,4281 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,4282 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,4283 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,4284 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,4285 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,4286 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,4287 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,4288 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,4289 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,4290 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,4291 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,4292 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,4293 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,4294 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,4295 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,4296 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,4297 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,4298 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,4299 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,4300 [GCC_GP4_CLK] = &gcc_gp4_clk.clkr,4301 [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,4302 [GCC_GP5_CLK] = &gcc_gp5_clk.clkr,4303 [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,4304 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,4305 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,4306 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,4307 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,4308 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,4309 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,4310 [GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,4311 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,4312 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,4313 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,4314 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,4315 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,4316 [GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,4317 [GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr,4318 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,4319 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,4320 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,4321 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,4322 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,4323 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,4324 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,4325 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,4326 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,4327 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,4328 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,4329 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,4330 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,4331 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,4332 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,4333 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,4334 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,4335 [GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,4336 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,4337 [GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,4338 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,4339 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,4340 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,4341 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,4342 [GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,4343 [GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,4344 [GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,4345 [GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,4346 [GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,4347 [GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,4348 [GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,4349 [GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,4350 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,4351 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,4352 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,4353 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,4354 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,4355 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,4356 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,4357 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,4358 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,4359 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,4360 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,4361 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,4362 [GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr,4363 [GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr,4364 [GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr,4365 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,4366 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,4367 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,4368 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,4369 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,4370 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,4371 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,4372 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,4373 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,4374 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,4375 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,4376 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,4377 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,4378 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,4379 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,4380 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,4381 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,4382 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,4383 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,4384 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,4385 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,4386 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,4387 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,4388 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,4389 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,4390 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,4391 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,4392 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,4393 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,4394 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,4395 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,4396 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,4397 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,4398 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,4399 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,4400 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,4401 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,4402 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,4403 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,4404 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,4405 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,4406 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,4407 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,4408 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,4409 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,4410 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,4411 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,4412 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,4413 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,4414 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,4415 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,4416 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,4417 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,4418 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,4419 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,4420 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,4421 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,4422 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,4423 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,4424 [GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr,4425 [GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr,4426 [GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr,4427 [GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr,4428 [GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr,4429 [GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr,4430 [GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr,4431 [GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr,4432 [GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr,4433 [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,4434 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,4435 [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,4436 [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr,4437 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,4438 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,4439 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,4440 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,4441 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,4442 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,4443 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,4444 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,4445 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,4446 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,4447 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,4448 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,4449 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,4450 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,4451 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,4452 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,4453 [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr,4454 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,4455 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,4456 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,4457 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,4458 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,4459 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,4460 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,4461 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,4462 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,4463 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,4464 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,4465 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,4466 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,4467 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,4468 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,4469 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,4470 [GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,4471 [GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,4472 [GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,4473 [GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,4474 [GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,4475 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,4476 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,4477 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,4478 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,4479 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,4480 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,4481 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,4482 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,4483 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,4484 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,4485 [GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,4486 [GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,4487 [GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,4488 [GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,4489 [GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,4490 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,4491 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,4492 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,4493 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,4494 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,4495 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,4496 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,4497 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,4498 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,4499 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,4500 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,4501 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,4502 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,4503 [GPLL0] = &gpll0.clkr,4504 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,4505 [GPLL1] = &gpll1.clkr,4506 [GPLL4] = &gpll4.clkr,4507 [GPLL7] = &gpll7.clkr,4508 [GPLL9] = &gpll9.clkr,4509};4510 4511static const struct qcom_reset_map gcc_sc8180x_resets[] = {4512 [GCC_EMAC_BCR] = { 0x6000 },4513 [GCC_GPU_BCR] = { 0x71000 },4514 [GCC_MMSS_BCR] = { 0xb000 },4515 [GCC_NPU_BCR] = { 0x4d000 },4516 [GCC_PCIE_0_BCR] = { 0x6b000 },4517 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },4518 [GCC_PCIE_1_BCR] = { 0x8d000 },4519 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },4520 [GCC_PCIE_2_BCR] = { 0x9d000 },4521 [GCC_PCIE_2_PHY_BCR] = { 0xa701c },4522 [GCC_PCIE_3_BCR] = { 0xa3000 },4523 [GCC_PCIE_3_PHY_BCR] = { 0xa801c },4524 [GCC_PCIE_PHY_BCR] = { 0x6f000 },4525 [GCC_PDM_BCR] = { 0x33000 },4526 [GCC_PRNG_BCR] = { 0x34000 },4527 [GCC_QSPI_1_BCR] = { 0x4a000 },4528 [GCC_QSPI_BCR] = { 0x24008 },4529 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },4530 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },4531 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },4532 [GCC_QUSB2PHY_5_BCR] = { 0x12010 },4533 [GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },4534 [GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },4535 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },4536 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },4537 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },4538 [GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },4539 [GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },4540 [GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },4541 [GCC_USB3_PHY_SEC_BCR] = { 0x50018 },4542 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },4543 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },4544 [GCC_USB3_UNIPHY_MP0_BCR] = { 0x50024 },4545 [GCC_USB3_UNIPHY_MP1_BCR] = { 0x50028 },4546 [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5002c },4547 [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50030 },4548 [GCC_SDCC2_BCR] = { 0x14000 },4549 [GCC_SDCC4_BCR] = { 0x16000 },4550 [GCC_TSIF_BCR] = { 0x36000 },4551 [GCC_UFS_CARD_2_BCR] = { 0xa2000 },4552 [GCC_UFS_CARD_BCR] = { 0x75000 },4553 [GCC_UFS_PHY_BCR] = { 0x77000 },4554 [GCC_USB30_MP_BCR] = { 0xa6000 },4555 [GCC_USB30_PRIM_BCR] = { 0xf000 },4556 [GCC_USB30_SEC_BCR] = { 0x10000 },4557 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },4558 [GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },4559 [GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },4560 [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },4561};4562 4563static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {4564 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),4565 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),4566 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),4567 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),4568 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),4569 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),4570 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),4571 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),4572 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),4573 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),4574 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),4575 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),4576 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),4577 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),4578 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),4579 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),4580 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),4581 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),4582 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),4583 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),4584};4585 4586static struct gdsc *gcc_sc8180x_gdscs[] = {4587 [EMAC_GDSC] = &emac_gdsc,4588 [PCIE_0_GDSC] = &pcie_0_gdsc,4589 [PCIE_1_GDSC] = &pcie_1_gdsc,4590 [PCIE_2_GDSC] = &pcie_2_gdsc,4591 [PCIE_3_GDSC] = &pcie_3_gdsc,4592 [UFS_CARD_GDSC] = &ufs_card_gdsc,4593 [UFS_CARD_2_GDSC] = &ufs_card_2_gdsc,4594 [UFS_PHY_GDSC] = &ufs_phy_gdsc,4595 [USB30_MP_GDSC] = &usb30_mp_gdsc,4596 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,4597 [USB30_SEC_GDSC] = &usb30_sec_gdsc,4598};4599 4600static const struct regmap_config gcc_sc8180x_regmap_config = {4601 .reg_bits = 32,4602 .reg_stride = 4,4603 .val_bits = 32,4604 .max_register = 0xc0004,4605 .fast_io = true,4606};4607 4608static const struct qcom_cc_desc gcc_sc8180x_desc = {4609 .config = &gcc_sc8180x_regmap_config,4610 .clks = gcc_sc8180x_clocks,4611 .num_clks = ARRAY_SIZE(gcc_sc8180x_clocks),4612 .resets = gcc_sc8180x_resets,4613 .num_resets = ARRAY_SIZE(gcc_sc8180x_resets),4614 .gdscs = gcc_sc8180x_gdscs,4615 .num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),4616};4617 4618static const struct of_device_id gcc_sc8180x_match_table[] = {4619 { .compatible = "qcom,gcc-sc8180x" },4620 { }4621};4622MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);4623 4624static int gcc_sc8180x_probe(struct platform_device *pdev)4625{4626 struct regmap *regmap;4627 int ret;4628 4629 regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);4630 if (IS_ERR(regmap))4631 return PTR_ERR(regmap);4632 4633 /* Keep some clocks always-on */4634 qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */4635 qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */4636 qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */4637 qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */4638 qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */4639 qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */4640 qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */4641 qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */4642 qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */4643 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */4644 4645 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */4646 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);4647 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);4648 4649 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,4650 ARRAY_SIZE(gcc_dfs_clocks));4651 if (ret)4652 return ret;4653 4654 return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);4655}4656 4657static struct platform_driver gcc_sc8180x_driver = {4658 .probe = gcc_sc8180x_probe,4659 .driver = {4660 .name = "gcc-sc8180x",4661 .of_match_table = gcc_sc8180x_match_table,4662 },4663};4664 4665static int __init gcc_sc8180x_init(void)4666{4667 return platform_driver_register(&gcc_sc8180x_driver);4668}4669core_initcall(gcc_sc8180x_init);4670 4671static void __exit gcc_sc8180x_exit(void)4672{4673 platform_driver_unregister(&gcc_sc8180x_driver);4674}4675module_exit(gcc_sc8180x_exit);4676 4677MODULE_DESCRIPTION("QTI GCC SC8180x driver");4678MODULE_LICENSE("GPL v2");4679