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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.4 * Copyright (c) 2022, Linaro Ltd.5 */6 7#include <linux/clk-provider.h>8#include <linux/err.h>9#include <linux/kernel.h>10#include <linux/module.h>11#include <linux/pm_runtime.h>12#include <linux/of.h>13#include <linux/platform_device.h>14#include <linux/regmap.h>15 16#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>17 18#include "clk-alpha-pll.h"19#include "clk-branch.h"20#include "clk-rcg.h"21#include "clk-regmap.h"22#include "clk-regmap-divider.h"23#include "clk-regmap-mux.h"24#include "clk-regmap-phy-mux.h"25#include "common.h"26#include "gdsc.h"27#include "reset.h"28 29/* Need to match the order of clocks in DT binding */30enum {31	DT_BI_TCXO,32	DT_SLEEP_CLK,33	DT_UFS_PHY_RX_SYMBOL_0_CLK,34	DT_UFS_PHY_RX_SYMBOL_1_CLK,35	DT_UFS_PHY_TX_SYMBOL_0_CLK,36	DT_UFS_CARD_RX_SYMBOL_0_CLK,37	DT_UFS_CARD_RX_SYMBOL_1_CLK,38	DT_UFS_CARD_TX_SYMBOL_0_CLK,39	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,40	DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,41	DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC,42	DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,43	DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,44	DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,45	DT_QUSB4PHY_GCC_USB4_RX0_CLK,46	DT_QUSB4PHY_GCC_USB4_RX1_CLK,47	DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,48	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,49	DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,50	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,51	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,52	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,53	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,54	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,55	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,56	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,57	DT_PCIE_2A_PIPE_CLK,58	DT_PCIE_2B_PIPE_CLK,59	DT_PCIE_3A_PIPE_CLK,60	DT_PCIE_3B_PIPE_CLK,61	DT_PCIE_4_PIPE_CLK,62	DT_RXC0_REF_CLK,63	DT_RXC1_REF_CLK,64};65 66enum {67	P_BI_TCXO,68	P_GCC_GPLL0_OUT_EVEN,69	P_GCC_GPLL0_OUT_MAIN,70	P_GCC_GPLL2_OUT_MAIN,71	P_GCC_GPLL4_OUT_MAIN,72	P_GCC_GPLL7_OUT_MAIN,73	P_GCC_GPLL8_OUT_MAIN,74	P_GCC_GPLL9_OUT_MAIN,75	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,76	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,77	P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC,78	P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC,79	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,80	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,81	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,82	P_GCC_USB4_PHY_DP_GMUX_CLK_SRC,83	P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC,84	P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,85	P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,86	P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,87	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,88	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,89	P_QUSB4PHY_GCC_USB4_RX0_CLK,90	P_QUSB4PHY_GCC_USB4_RX1_CLK,91	P_RXC0_REF_CLK,92	P_RXC1_REF_CLK,93	P_SLEEP_CLK,94	P_UFS_CARD_RX_SYMBOL_0_CLK,95	P_UFS_CARD_RX_SYMBOL_1_CLK,96	P_UFS_CARD_TX_SYMBOL_0_CLK,97	P_UFS_PHY_RX_SYMBOL_0_CLK,98	P_UFS_PHY_RX_SYMBOL_1_CLK,99	P_UFS_PHY_TX_SYMBOL_0_CLK,100	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,101	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,102	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,103	P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,104	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,105	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,106	P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK,107	P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK,108};109 110static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };111 112static struct clk_alpha_pll gcc_gpll0 = {113	.offset = 0x0,114	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],115	.clkr = {116		.enable_reg = 0x52028,117		.enable_mask = BIT(0),118		.hw.init = &(const struct clk_init_data) {119			.name = "gcc_gpll0",120			.parent_data = &gcc_parent_data_tcxo,121			.num_parents = 1,122			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,123		},124	},125};126 127static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {128	{ 0x1, 2 },129	{ }130};131 132static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {133	.offset = 0x0,134	.post_div_shift = 8,135	.post_div_table = post_div_table_gcc_gpll0_out_even,136	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),137	.width = 4,138	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],139	.clkr.hw.init = &(const struct clk_init_data) {140		.name = "gcc_gpll0_out_even",141		.parent_hws = (const struct clk_hw*[]){142			&gcc_gpll0.clkr.hw,143		},144		.num_parents = 1,145		.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,146	},147};148 149static struct clk_alpha_pll gcc_gpll2 = {150	.offset = 0x2000,151	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],152	.clkr = {153		.enable_reg = 0x52028,154		.enable_mask = BIT(2),155		.hw.init = &(const struct clk_init_data) {156			.name = "gcc_gpll2",157			.parent_data = &gcc_parent_data_tcxo,158			.num_parents = 1,159			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,160		},161	},162};163 164static struct clk_alpha_pll gcc_gpll4 = {165	.offset = 0x76000,166	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],167	.clkr = {168		.enable_reg = 0x52028,169		.enable_mask = BIT(4),170		.hw.init = &(const struct clk_init_data) {171			.name = "gcc_gpll4",172			.parent_data = &gcc_parent_data_tcxo,173			.num_parents = 1,174			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,175		},176	},177};178 179static struct clk_alpha_pll gcc_gpll7 = {180	.offset = 0x1a000,181	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],182	.clkr = {183		.enable_reg = 0x52028,184		.enable_mask = BIT(7),185		.hw.init = &(const struct clk_init_data) {186			.name = "gcc_gpll7",187			.parent_data = &gcc_parent_data_tcxo,188			.num_parents = 1,189			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,190		},191	},192};193 194static struct clk_alpha_pll gcc_gpll8 = {195	.offset = 0x1b000,196	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],197	.clkr = {198		.enable_reg = 0x52028,199		.enable_mask = BIT(8),200		.hw.init = &(const struct clk_init_data) {201			.name = "gcc_gpll8",202			.parent_data = &gcc_parent_data_tcxo,203			.num_parents = 1,204			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,205		},206	},207};208 209static struct clk_alpha_pll gcc_gpll9 = {210	.offset = 0x1c000,211	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],212	.clkr = {213		.enable_reg = 0x52028,214		.enable_mask = BIT(9),215		.hw.init = &(const struct clk_init_data) {216			.name = "gcc_gpll9",217			.parent_data = &gcc_parent_data_tcxo,218			.num_parents = 1,219			.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,220		},221	},222};223 224static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src;225static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src;226 227static const struct parent_map gcc_parent_map_0[] = {228	{ P_BI_TCXO, 0 },229	{ P_GCC_GPLL0_OUT_MAIN, 1 },230	{ P_GCC_GPLL0_OUT_EVEN, 6 },231};232 233static const struct clk_parent_data gcc_parent_data_0[] = {234	{ .index = DT_BI_TCXO },235	{ .hw = &gcc_gpll0.clkr.hw },236	{ .hw = &gcc_gpll0_out_even.clkr.hw },237};238 239static const struct parent_map gcc_parent_map_1[] = {240	{ P_BI_TCXO, 0 },241	{ P_SLEEP_CLK, 5 },242};243 244static const struct clk_parent_data gcc_parent_data_1[] = {245	{ .index = DT_BI_TCXO },246	{ .index = DT_SLEEP_CLK },247};248 249static const struct parent_map gcc_parent_map_2[] = {250	{ P_BI_TCXO, 0 },251	{ P_GCC_GPLL0_OUT_MAIN, 1 },252	{ P_SLEEP_CLK, 5 },253	{ P_GCC_GPLL0_OUT_EVEN, 6 },254};255 256static const struct clk_parent_data gcc_parent_data_2[] = {257	{ .index = DT_BI_TCXO },258	{ .hw = &gcc_gpll0.clkr.hw },259	{ .index = DT_SLEEP_CLK },260	{ .hw = &gcc_gpll0_out_even.clkr.hw },261};262 263static const struct parent_map gcc_parent_map_3[] = {264	{ P_BI_TCXO, 0 },265};266 267static const struct clk_parent_data gcc_parent_data_3[] = {268	{ .index = DT_BI_TCXO },269};270 271static const struct parent_map gcc_parent_map_4[] = {272	{ P_BI_TCXO, 0 },273	{ P_GCC_GPLL7_OUT_MAIN, 2 },274	{ P_GCC_GPLL4_OUT_MAIN, 5 },275	{ P_GCC_GPLL0_OUT_EVEN, 6 },276};277 278static const struct clk_parent_data gcc_parent_data_4[] = {279	{ .index = DT_BI_TCXO },280	{ .hw = &gcc_gpll7.clkr.hw },281	{ .hw = &gcc_gpll4.clkr.hw },282	{ .hw = &gcc_gpll0_out_even.clkr.hw },283};284 285static const struct parent_map gcc_parent_map_5[] = {286	{ P_BI_TCXO, 0 },287	{ P_GCC_GPLL0_OUT_MAIN, 1 },288	{ P_GCC_GPLL8_OUT_MAIN, 2 },289	{ P_GCC_GPLL0_OUT_EVEN, 6 },290};291 292static const struct clk_parent_data gcc_parent_data_5[] = {293	{ .index = DT_BI_TCXO },294	{ .hw = &gcc_gpll0.clkr.hw },295	{ .hw = &gcc_gpll8.clkr.hw },296	{ .hw = &gcc_gpll0_out_even.clkr.hw },297};298 299static const struct parent_map gcc_parent_map_6[] = {300	{ P_BI_TCXO, 0 },301	{ P_GCC_GPLL0_OUT_MAIN, 1 },302	{ P_GCC_GPLL7_OUT_MAIN, 2 },303};304 305static const struct clk_parent_data gcc_parent_data_6[] = {306	{ .index = DT_BI_TCXO },307	{ .hw = &gcc_gpll0.clkr.hw },308	{ .hw = &gcc_gpll7.clkr.hw },309};310 311static const struct parent_map gcc_parent_map_7[] = {312	{ P_BI_TCXO, 0 },313	{ P_GCC_GPLL0_OUT_MAIN, 1 },314	{ P_GCC_GPLL2_OUT_MAIN, 2 },315};316 317static const struct clk_parent_data gcc_parent_data_7[] = {318	{ .index = DT_BI_TCXO },319	{ .hw = &gcc_gpll0.clkr.hw },320	{ .hw = &gcc_gpll2.clkr.hw },321};322 323static const struct parent_map gcc_parent_map_8[] = {324	{ P_BI_TCXO, 0 },325	{ P_GCC_GPLL7_OUT_MAIN, 2 },326	{ P_RXC0_REF_CLK, 3 },327	{ P_GCC_GPLL0_OUT_EVEN, 6 },328};329 330static const struct clk_parent_data gcc_parent_data_8[] = {331	{ .index = DT_BI_TCXO },332	{ .hw = &gcc_gpll7.clkr.hw },333	{ .index = DT_RXC0_REF_CLK },334	{ .hw = &gcc_gpll0_out_even.clkr.hw },335};336 337static const struct parent_map gcc_parent_map_9[] = {338	{ P_BI_TCXO, 0 },339	{ P_GCC_GPLL7_OUT_MAIN, 2 },340	{ P_RXC1_REF_CLK, 3 },341	{ P_GCC_GPLL0_OUT_EVEN, 6 },342};343 344static const struct clk_parent_data gcc_parent_data_9[] = {345	{ .index = DT_BI_TCXO },346	{ .hw = &gcc_gpll7.clkr.hw },347	{ .index = DT_RXC1_REF_CLK },348	{ .hw = &gcc_gpll0_out_even.clkr.hw },349};350 351static const struct parent_map gcc_parent_map_15[] = {352	{ P_BI_TCXO, 0 },353	{ P_GCC_GPLL0_OUT_MAIN, 1 },354	{ P_GCC_GPLL9_OUT_MAIN, 2 },355	{ P_GCC_GPLL4_OUT_MAIN, 5 },356	{ P_GCC_GPLL0_OUT_EVEN, 6 },357};358 359static const struct clk_parent_data gcc_parent_data_15[] = {360	{ .index = DT_BI_TCXO },361	{ .hw = &gcc_gpll0.clkr.hw },362	{ .hw = &gcc_gpll9.clkr.hw },363	{ .hw = &gcc_gpll4.clkr.hw },364	{ .hw = &gcc_gpll0_out_even.clkr.hw },365};366 367static const struct parent_map gcc_parent_map_16[] = {368	{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },369	{ P_BI_TCXO, 2 },370};371 372static const struct clk_parent_data gcc_parent_data_16[] = {373	{ .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },374	{ .index = DT_BI_TCXO },375};376 377static const struct parent_map gcc_parent_map_17[] = {378	{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },379	{ P_BI_TCXO, 2 },380};381 382static const struct clk_parent_data gcc_parent_data_17[] = {383	{ .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },384	{ .index = DT_BI_TCXO },385};386 387static const struct parent_map gcc_parent_map_18[] = {388	{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },389	{ P_BI_TCXO, 2 },390};391 392static const struct clk_parent_data gcc_parent_data_18[] = {393	{ .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },394	{ .index = DT_BI_TCXO },395};396 397static const struct parent_map gcc_parent_map_19[] = {398	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },399	{ P_BI_TCXO, 2 },400};401 402static const struct clk_parent_data gcc_parent_data_19[] = {403	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },404	{ .index = DT_BI_TCXO },405};406 407static const struct parent_map gcc_parent_map_20[] = {408	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },409	{ P_BI_TCXO, 2 },410};411 412static const struct clk_parent_data gcc_parent_data_20[] = {413	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },414	{ .index = DT_BI_TCXO },415};416 417static const struct parent_map gcc_parent_map_21[] = {418	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },419	{ P_BI_TCXO, 2 },420};421 422static const struct clk_parent_data gcc_parent_data_21[] = {423	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },424	{ .index = DT_BI_TCXO },425};426 427static const struct parent_map gcc_parent_map_22[] = {428	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },429	{ P_BI_TCXO, 2 },430};431 432static const struct clk_parent_data gcc_parent_data_22[] = {433	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },434	{ .index = DT_BI_TCXO },435};436 437static const struct parent_map gcc_parent_map_23[] = {438	{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },439	{ P_BI_TCXO, 2 },440};441 442static const struct clk_parent_data gcc_parent_data_23[] = {443	{ .index = DT_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK },444	{ .index = DT_BI_TCXO },445};446 447static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {448	.reg = 0xf060,449	.shift = 0,450	.width = 2,451	.parent_map = gcc_parent_map_22,452	.clkr = {453		.hw.init = &(const struct clk_init_data) {454			.name = "gcc_usb3_prim_phy_pipe_clk_src",455			.parent_data = gcc_parent_data_22,456			.num_parents = ARRAY_SIZE(gcc_parent_data_22),457			.ops = &clk_regmap_mux_closest_ops,458		},459	},460};461 462static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {463	.reg = 0x10060,464	.shift = 0,465	.width = 2,466	.parent_map = gcc_parent_map_23,467	.clkr = {468		.hw.init = &(const struct clk_init_data) {469			.name = "gcc_usb3_sec_phy_pipe_clk_src",470			.parent_data = gcc_parent_data_23,471			.num_parents = ARRAY_SIZE(gcc_parent_data_23),472			.ops = &clk_regmap_mux_closest_ops,473		},474	},475};476 477static const struct parent_map gcc_parent_map_24[] = {478	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },479	{ P_BI_TCXO, 2 },480};481 482static const struct clk_parent_data gcc_parent_data_24[] = {483	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK },484	{ .index = DT_BI_TCXO },485};486 487static const struct parent_map gcc_parent_map_25[] = {488	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },489	{ P_BI_TCXO, 2 },490};491 492static const struct clk_parent_data gcc_parent_data_25[] = {493	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK },494	{ .index = DT_BI_TCXO },495};496 497static const struct parent_map gcc_parent_map_26[] = {498	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },499	{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },500	{ P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC, 3 },501};502 503static const struct clk_parent_data gcc_parent_data_26[] = {504	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },505	{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },506	{ .index = DT_GCC_USB4_PHY_PIPEGMUX_CLK_SRC },507};508 509static const struct parent_map gcc_parent_map_27[] = {510	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },511	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },512	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },513};514 515static const struct clk_parent_data gcc_parent_data_27[] = {516	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },517	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },518	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },519};520 521static const struct parent_map gcc_parent_map_28[] = {522	{ P_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC, 0 },523	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },524};525 526static const struct clk_parent_data gcc_parent_data_28[] = {527	{ .index = DT_GCC_USB4_1_PHY_DP_GMUX_CLK_SRC },528	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },529};530 531static const struct parent_map gcc_parent_map_29[] = {532	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },533	{ P_BI_TCXO, 2 },534};535 536static const struct clk_parent_data gcc_parent_data_29[] = {537	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },538	{ .index = DT_BI_TCXO },539};540 541static const struct parent_map gcc_parent_map_30[] = {542	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },543	{ P_GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC, 1 },544};545 546static const struct clk_parent_data gcc_parent_data_30[] = {547	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },548	{ .hw = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr.hw },549};550 551static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipegmux_clk_src = {552	.reg = 0xb80dc,553	.shift = 0,554	.width = 1,555	.parent_map = gcc_parent_map_30,556	.clkr = {557		.hw.init = &(const struct clk_init_data) {558			.name = "gcc_usb4_1_phy_pcie_pipegmux_clk_src",559			.parent_data = gcc_parent_data_30,560			.num_parents = ARRAY_SIZE(gcc_parent_data_30),561			.ops = &clk_regmap_mux_closest_ops,562		},563	},564};565 566static const struct parent_map gcc_parent_map_31[] = {567	{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },568	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },569};570 571static const struct clk_parent_data gcc_parent_data_31[] = {572	{ .hw = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr.hw },573	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },574};575 576static const struct parent_map gcc_parent_map_32[] = {577	{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },578	{ P_BI_TCXO, 2 },579};580 581static const struct clk_parent_data gcc_parent_data_32[] = {582	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },583	{ .index = DT_BI_TCXO },584};585 586static const struct parent_map gcc_parent_map_33[] = {587	{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },588	{ P_BI_TCXO, 2 },589};590 591static const struct clk_parent_data gcc_parent_data_33[] = {592	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },593	{ .index = DT_BI_TCXO },594};595 596static const struct parent_map gcc_parent_map_34[] = {597	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },598	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },599};600 601static const struct clk_parent_data gcc_parent_data_34[] = {602	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },603	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },604};605 606static const struct parent_map gcc_parent_map_35[] = {607	{ P_GCC_USB4_PHY_DP_GMUX_CLK_SRC, 0 },608	{ P_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },609};610 611static const struct clk_parent_data gcc_parent_data_35[] = {612	{ .index = DT_GCC_USB4_PHY_DP_GMUX_CLK_SRC },613	{ .index = DT_USB4_PHY_GCC_USB4RTR_MAX_PIPE_CLK },614};615 616static const struct parent_map gcc_parent_map_36[] = {617	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },618	{ P_BI_TCXO, 2 },619};620 621static const struct clk_parent_data gcc_parent_data_36[] = {622	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },623	{ .index = DT_BI_TCXO },624};625 626static const struct parent_map gcc_parent_map_37[] = {627	{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },628	{ P_GCC_USB4_PHY_PCIE_PIPE_CLK_SRC, 1 },629};630 631static const struct clk_parent_data gcc_parent_data_37[] = {632	{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },633	{ .hw = &gcc_usb4_phy_pcie_pipe_clk_src.clkr.hw },634};635 636static struct clk_regmap_mux gcc_usb4_phy_pcie_pipegmux_clk_src = {637	.reg = 0x2a0dc,638	.shift = 0,639	.width = 1,640	.parent_map = gcc_parent_map_37,641	.clkr = {642		.hw.init = &(const struct clk_init_data) {643			.name = "gcc_usb4_phy_pcie_pipegmux_clk_src",644			.parent_data = gcc_parent_data_37,645			.num_parents = ARRAY_SIZE(gcc_parent_data_37),646			.ops = &clk_regmap_mux_closest_ops,647		},648	},649};650 651static const struct parent_map gcc_parent_map_38[] = {652	{ P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },653	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },654};655 656static const struct clk_parent_data gcc_parent_data_38[] = {657	{ .hw = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr.hw },658	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },659};660 661static const struct parent_map gcc_parent_map_39[] = {662	{ P_QUSB4PHY_GCC_USB4_RX0_CLK, 0 },663	{ P_BI_TCXO, 2 },664};665 666static const struct clk_parent_data gcc_parent_data_39[] = {667	{ .index = DT_QUSB4PHY_GCC_USB4_RX0_CLK },668	{ .index = DT_BI_TCXO },669};670 671static const struct parent_map gcc_parent_map_40[] = {672	{ P_QUSB4PHY_GCC_USB4_RX1_CLK, 0 },673	{ P_BI_TCXO, 2 },674};675 676static const struct clk_parent_data gcc_parent_data_40[] = {677	{ .index = DT_QUSB4PHY_GCC_USB4_RX1_CLK },678	{ .index = DT_BI_TCXO },679};680 681static const struct parent_map gcc_parent_map_41[] = {682	{ P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },683	{ P_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },684};685 686static const struct clk_parent_data gcc_parent_data_41[] = {687	{ .index = DT_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC },688	{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },689};690 691static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {692	.reg = 0x9d05c,693	.clkr = {694		.hw.init = &(const struct clk_init_data) {695			.name = "gcc_pcie_2a_pipe_clk_src",696			.parent_data = &(const struct clk_parent_data){697				.index = DT_PCIE_2A_PIPE_CLK,698			},699			.num_parents = 1,700			.ops = &clk_regmap_phy_mux_ops,701		},702	},703};704 705static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {706	.reg = 0x9e05c,707	.clkr = {708		.hw.init = &(const struct clk_init_data) {709			.name = "gcc_pcie_2b_pipe_clk_src",710			.parent_data = &(const struct clk_parent_data){711				.index = DT_PCIE_2B_PIPE_CLK,712			},713			.num_parents = 1,714			.ops = &clk_regmap_phy_mux_ops,715		},716	},717};718 719static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {720	.reg = 0xa005c,721	.clkr = {722		.hw.init = &(const struct clk_init_data) {723			.name = "gcc_pcie_3a_pipe_clk_src",724			.parent_data = &(const struct clk_parent_data){725				.index = DT_PCIE_3A_PIPE_CLK,726			},727			.num_parents = 1,728			.ops = &clk_regmap_phy_mux_ops,729		},730	},731};732 733static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {734	.reg = 0xa205c,735	.clkr = {736		.hw.init = &(const struct clk_init_data) {737			.name = "gcc_pcie_3b_pipe_clk_src",738			.parent_data = &(const struct clk_parent_data){739				.index = DT_PCIE_3B_PIPE_CLK,740			},741			.num_parents = 1,742			.ops = &clk_regmap_phy_mux_ops,743		},744	},745};746 747static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {748	.reg = 0x6b05c,749	.clkr = {750		.hw.init = &(const struct clk_init_data) {751			.name = "gcc_pcie_4_pipe_clk_src",752			.parent_data = &(const struct clk_parent_data){753				.index = DT_PCIE_4_PIPE_CLK,754			},755			.num_parents = 1,756			.ops = &clk_regmap_phy_mux_ops,757		},758	},759};760 761static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {762	.reg = 0x75058,763	.shift = 0,764	.width = 2,765	.parent_map = gcc_parent_map_16,766	.clkr = {767		.hw.init = &(const struct clk_init_data) {768			.name = "gcc_ufs_card_rx_symbol_0_clk_src",769			.parent_data = gcc_parent_data_16,770			.num_parents = ARRAY_SIZE(gcc_parent_data_16),771			.ops = &clk_regmap_mux_closest_ops,772		},773	},774};775 776static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {777	.reg = 0x750c8,778	.shift = 0,779	.width = 2,780	.parent_map = gcc_parent_map_17,781	.clkr = {782		.hw.init = &(const struct clk_init_data) {783			.name = "gcc_ufs_card_rx_symbol_1_clk_src",784			.parent_data = gcc_parent_data_17,785			.num_parents = ARRAY_SIZE(gcc_parent_data_17),786			.ops = &clk_regmap_mux_closest_ops,787		},788	},789};790 791static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {792	.reg = 0x75048,793	.shift = 0,794	.width = 2,795	.parent_map = gcc_parent_map_18,796	.clkr = {797		.hw.init = &(const struct clk_init_data) {798			.name = "gcc_ufs_card_tx_symbol_0_clk_src",799			.parent_data = gcc_parent_data_18,800			.num_parents = ARRAY_SIZE(gcc_parent_data_18),801			.ops = &clk_regmap_mux_closest_ops,802		},803	},804};805 806static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {807	.reg = 0x77058,808	.shift = 0,809	.width = 2,810	.parent_map = gcc_parent_map_19,811	.clkr = {812		.hw.init = &(const struct clk_init_data) {813			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",814			.parent_data = gcc_parent_data_19,815			.num_parents = ARRAY_SIZE(gcc_parent_data_19),816			.ops = &clk_regmap_mux_closest_ops,817		},818	},819};820 821static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {822	.reg = 0x770c8,823	.shift = 0,824	.width = 2,825	.parent_map = gcc_parent_map_20,826	.clkr = {827		.hw.init = &(const struct clk_init_data) {828			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",829			.parent_data = gcc_parent_data_20,830			.num_parents = ARRAY_SIZE(gcc_parent_data_20),831			.ops = &clk_regmap_mux_closest_ops,832		},833	},834};835 836static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {837	.reg = 0x77048,838	.shift = 0,839	.width = 2,840	.parent_map = gcc_parent_map_21,841	.clkr = {842		.hw.init = &(const struct clk_init_data) {843			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",844			.parent_data = gcc_parent_data_21,845			.num_parents = ARRAY_SIZE(gcc_parent_data_21),846			.ops = &clk_regmap_mux_closest_ops,847		},848	},849};850 851static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {852	.reg = 0xf064,853	.shift = 0,854	.width = 2,855	.parent_map = gcc_parent_map_26,856	.clkr = {857		.hw.init = &(const struct clk_init_data) {858			.name = "gcc_usb34_prim_phy_pipe_clk_src",859			.parent_data = gcc_parent_data_26,860			.num_parents = ARRAY_SIZE(gcc_parent_data_26),861			.ops = &clk_regmap_mux_closest_ops,862		},863	},864};865 866static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {867	.reg = 0x10064,868	.shift = 0,869	.width = 2,870	.parent_map = gcc_parent_map_27,871	.clkr = {872		.hw.init = &(const struct clk_init_data) {873			.name = "gcc_usb34_sec_phy_pipe_clk_src",874			.parent_data = gcc_parent_data_27,875			.num_parents = ARRAY_SIZE(gcc_parent_data_27),876			.ops = &clk_regmap_mux_closest_ops,877		},878	},879};880 881static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = {882	.reg = 0xab060,883	.shift = 0,884	.width = 2,885	.parent_map = gcc_parent_map_24,886	.clkr = {887		.hw.init = &(const struct clk_init_data) {888			.name = "gcc_usb3_mp_phy_pipe_0_clk_src",889			.parent_data = gcc_parent_data_24,890			.num_parents = ARRAY_SIZE(gcc_parent_data_24),891			.ops = &clk_regmap_mux_closest_ops,892		},893	},894};895 896static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = {897	.reg = 0xab068,898	.shift = 0,899	.width = 2,900	.parent_map = gcc_parent_map_25,901	.clkr = {902		.hw.init = &(const struct clk_init_data) {903			.name = "gcc_usb3_mp_phy_pipe_1_clk_src",904			.parent_data = gcc_parent_data_25,905			.num_parents = ARRAY_SIZE(gcc_parent_data_25),906			.ops = &clk_regmap_mux_closest_ops,907		},908	},909};910 911static struct clk_regmap_mux gcc_usb4_1_phy_dp_clk_src = {912	.reg = 0xb8050,913	.shift = 0,914	.width = 2,915	.parent_map = gcc_parent_map_28,916	.clkr = {917		.hw.init = &(const struct clk_init_data) {918			.name = "gcc_usb4_1_phy_dp_clk_src",919			.parent_data = gcc_parent_data_28,920			.num_parents = ARRAY_SIZE(gcc_parent_data_28),921			.ops = &clk_regmap_mux_closest_ops,922		},923	},924};925 926static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {927	.reg = 0xb80b0,928	.shift = 0,929	.width = 2,930	.parent_map = gcc_parent_map_29,931	.clkr = {932		.hw.init = &(const struct clk_init_data) {933			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",934			.parent_data = gcc_parent_data_29,935			.num_parents = ARRAY_SIZE(gcc_parent_data_29),936			.ops = &clk_regmap_mux_closest_ops,937		},938	},939};940 941static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {942	.reg = 0xb80e0,943	.shift = 0,944	.width = 2,945	.parent_map = gcc_parent_map_31,946	.clkr = {947		.hw.init = &(const struct clk_init_data) {948			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",949			.parent_data = gcc_parent_data_31,950			.num_parents = ARRAY_SIZE(gcc_parent_data_31),951			.ops = &clk_regmap_mux_closest_ops,952		},953	},954};955 956static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = {957	.reg = 0xb8090,958	.shift = 0,959	.width = 2,960	.parent_map = gcc_parent_map_32,961	.clkr = {962		.hw.init = &(const struct clk_init_data) {963			.name = "gcc_usb4_1_phy_rx0_clk_src",964			.parent_data = gcc_parent_data_32,965			.num_parents = ARRAY_SIZE(gcc_parent_data_32),966			.ops = &clk_regmap_mux_closest_ops,967		},968	},969};970 971static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = {972	.reg = 0xb809c,973	.shift = 0,974	.width = 2,975	.parent_map = gcc_parent_map_33,976	.clkr = {977		.hw.init = &(const struct clk_init_data) {978			.name = "gcc_usb4_1_phy_rx1_clk_src",979			.parent_data = gcc_parent_data_33,980			.num_parents = ARRAY_SIZE(gcc_parent_data_33),981			.ops = &clk_regmap_mux_closest_ops,982		},983	},984};985 986static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = {987	.reg = 0xb80c0,988	.shift = 0,989	.width = 2,990	.parent_map = gcc_parent_map_34,991	.clkr = {992		.hw.init = &(const struct clk_init_data) {993			.name = "gcc_usb4_1_phy_sys_clk_src",994			.parent_data = gcc_parent_data_34,995			.num_parents = ARRAY_SIZE(gcc_parent_data_34),996			.ops = &clk_regmap_mux_closest_ops,997		},998	},999};1000 1001static struct clk_regmap_mux gcc_usb4_phy_dp_clk_src = {1002	.reg = 0x2a050,1003	.shift = 0,1004	.width = 2,1005	.parent_map = gcc_parent_map_35,1006	.clkr = {1007		.hw.init = &(const struct clk_init_data) {1008			.name = "gcc_usb4_phy_dp_clk_src",1009			.parent_data = gcc_parent_data_35,1010			.num_parents = ARRAY_SIZE(gcc_parent_data_35),1011			.ops = &clk_regmap_mux_closest_ops,1012		},1013	},1014};1015 1016static struct clk_regmap_mux gcc_usb4_phy_p2rr2p_pipe_clk_src = {1017	.reg = 0x2a0b0,1018	.shift = 0,1019	.width = 2,1020	.parent_map = gcc_parent_map_36,1021	.clkr = {1022		.hw.init = &(const struct clk_init_data) {1023			.name = "gcc_usb4_phy_p2rr2p_pipe_clk_src",1024			.parent_data = gcc_parent_data_36,1025			.num_parents = ARRAY_SIZE(gcc_parent_data_36),1026			.ops = &clk_regmap_mux_closest_ops,1027		},1028	},1029};1030 1031static struct clk_regmap_mux gcc_usb4_phy_pcie_pipe_mux_clk_src = {1032	.reg = 0x2a0e0,1033	.shift = 0,1034	.width = 2,1035	.parent_map = gcc_parent_map_38,1036	.clkr = {1037		.hw.init = &(const struct clk_init_data) {1038			.name = "gcc_usb4_phy_pcie_pipe_mux_clk_src",1039			.parent_data = gcc_parent_data_38,1040			.num_parents = ARRAY_SIZE(gcc_parent_data_38),1041			.ops = &clk_regmap_mux_closest_ops,1042		},1043	},1044};1045 1046static struct clk_regmap_mux gcc_usb4_phy_rx0_clk_src = {1047	.reg = 0x2a090,1048	.shift = 0,1049	.width = 2,1050	.parent_map = gcc_parent_map_39,1051	.clkr = {1052		.hw.init = &(const struct clk_init_data) {1053			.name = "gcc_usb4_phy_rx0_clk_src",1054			.parent_data = gcc_parent_data_39,1055			.num_parents = ARRAY_SIZE(gcc_parent_data_39),1056			.ops = &clk_regmap_mux_closest_ops,1057		},1058	},1059};1060 1061static struct clk_regmap_mux gcc_usb4_phy_rx1_clk_src = {1062	.reg = 0x2a09c,1063	.shift = 0,1064	.width = 2,1065	.parent_map = gcc_parent_map_40,1066	.clkr = {1067		.hw.init = &(const struct clk_init_data) {1068			.name = "gcc_usb4_phy_rx1_clk_src",1069			.parent_data = gcc_parent_data_40,1070			.num_parents = ARRAY_SIZE(gcc_parent_data_40),1071			.ops = &clk_regmap_mux_closest_ops,1072		},1073	},1074};1075 1076static struct clk_regmap_mux gcc_usb4_phy_sys_clk_src = {1077	.reg = 0x2a0c0,1078	.shift = 0,1079	.width = 2,1080	.parent_map = gcc_parent_map_41,1081	.clkr = {1082		.hw.init = &(const struct clk_init_data) {1083			.name = "gcc_usb4_phy_sys_clk_src",1084			.parent_data = gcc_parent_data_41,1085			.num_parents = ARRAY_SIZE(gcc_parent_data_41),1086			.ops = &clk_regmap_mux_closest_ops,1087		},1088	},1089};1090 1091static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {1092	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),1093	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),1094	F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),1095	{ }1096};1097 1098static struct clk_rcg2 gcc_emac0_ptp_clk_src = {1099	.cmd_rcgr = 0xaa020,1100	.mnd_width = 0,1101	.hid_width = 5,1102	.parent_map = gcc_parent_map_4,1103	.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,1104	.clkr.hw.init = &(const struct clk_init_data) {1105		.name = "gcc_emac0_ptp_clk_src",1106		.parent_data = gcc_parent_data_4,1107		.num_parents = ARRAY_SIZE(gcc_parent_data_4),1108		.ops = &clk_rcg2_shared_ops,1109	},1110};1111 1112static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {1113	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),1114	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),1115	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),1116	{ }1117};1118 1119static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {1120	.cmd_rcgr = 0xaa040,1121	.mnd_width = 8,1122	.hid_width = 5,1123	.parent_map = gcc_parent_map_8,1124	.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,1125	.clkr.hw.init = &(const struct clk_init_data) {1126		.name = "gcc_emac0_rgmii_clk_src",1127		.parent_data = gcc_parent_data_8,1128		.num_parents = ARRAY_SIZE(gcc_parent_data_8),1129		.ops = &clk_rcg2_shared_ops,1130	},1131};1132 1133static struct clk_rcg2 gcc_emac1_ptp_clk_src = {1134	.cmd_rcgr = 0xba020,1135	.mnd_width = 0,1136	.hid_width = 5,1137	.parent_map = gcc_parent_map_4,1138	.freq_tbl = ftbl_gcc_emac0_ptp_clk_src,1139	.clkr.hw.init = &(const struct clk_init_data) {1140		.name = "gcc_emac1_ptp_clk_src",1141		.parent_data = gcc_parent_data_4,1142		.num_parents = ARRAY_SIZE(gcc_parent_data_4),1143		.ops = &clk_rcg2_shared_ops,1144	},1145};1146 1147static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {1148	.cmd_rcgr = 0xba040,1149	.mnd_width = 8,1150	.hid_width = 5,1151	.parent_map = gcc_parent_map_9,1152	.freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,1153	.clkr.hw.init = &(const struct clk_init_data) {1154		.name = "gcc_emac1_rgmii_clk_src",1155		.parent_data = gcc_parent_data_9,1156		.num_parents = ARRAY_SIZE(gcc_parent_data_9),1157		.ops = &clk_rcg2_shared_ops,1158	},1159};1160 1161static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {1162	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),1163	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),1164	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),1165	{ }1166};1167 1168static struct clk_rcg2 gcc_gp1_clk_src = {1169	.cmd_rcgr = 0x64004,1170	.mnd_width = 16,1171	.hid_width = 5,1172	.parent_map = gcc_parent_map_2,1173	.freq_tbl = ftbl_gcc_gp1_clk_src,1174	.clkr.hw.init = &(const struct clk_init_data) {1175		.name = "gcc_gp1_clk_src",1176		.parent_data = gcc_parent_data_2,1177		.num_parents = ARRAY_SIZE(gcc_parent_data_2),1178		.ops = &clk_rcg2_shared_ops,1179	},1180};1181 1182static struct clk_rcg2 gcc_gp2_clk_src = {1183	.cmd_rcgr = 0x65004,1184	.mnd_width = 16,1185	.hid_width = 5,1186	.parent_map = gcc_parent_map_2,1187	.freq_tbl = ftbl_gcc_gp1_clk_src,1188	.clkr.hw.init = &(const struct clk_init_data) {1189		.name = "gcc_gp2_clk_src",1190		.parent_data = gcc_parent_data_2,1191		.num_parents = ARRAY_SIZE(gcc_parent_data_2),1192		.ops = &clk_rcg2_shared_ops,1193	},1194};1195 1196static struct clk_rcg2 gcc_gp3_clk_src = {1197	.cmd_rcgr = 0x66004,1198	.mnd_width = 16,1199	.hid_width = 5,1200	.parent_map = gcc_parent_map_2,1201	.freq_tbl = ftbl_gcc_gp1_clk_src,1202	.clkr.hw.init = &(const struct clk_init_data) {1203		.name = "gcc_gp3_clk_src",1204		.parent_data = gcc_parent_data_2,1205		.num_parents = ARRAY_SIZE(gcc_parent_data_2),1206		.ops = &clk_rcg2_shared_ops,1207	},1208};1209 1210static struct clk_rcg2 gcc_gp4_clk_src = {1211	.cmd_rcgr = 0xc2004,1212	.mnd_width = 16,1213	.hid_width = 5,1214	.parent_map = gcc_parent_map_2,1215	.freq_tbl = ftbl_gcc_gp1_clk_src,1216	.clkr.hw.init = &(const struct clk_init_data) {1217		.name = "gcc_gp4_clk_src",1218		.parent_data = gcc_parent_data_2,1219		.num_parents = ARRAY_SIZE(gcc_parent_data_2),1220		.ops = &clk_rcg2_shared_ops,1221	},1222};1223 1224static struct clk_rcg2 gcc_gp5_clk_src = {1225	.cmd_rcgr = 0xc3004,1226	.mnd_width = 16,1227	.hid_width = 5,1228	.parent_map = gcc_parent_map_2,1229	.freq_tbl = ftbl_gcc_gp1_clk_src,1230	.clkr.hw.init = &(const struct clk_init_data) {1231		.name = "gcc_gp5_clk_src",1232		.parent_data = gcc_parent_data_2,1233		.num_parents = ARRAY_SIZE(gcc_parent_data_2),1234		.ops = &clk_rcg2_shared_ops,1235	},1236};1237 1238static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {1239	F(9600000, P_BI_TCXO, 2, 0, 0),1240	F(19200000, P_BI_TCXO, 1, 0, 0),1241	{ }1242};1243 1244static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {1245	.cmd_rcgr = 0xa4054,1246	.mnd_width = 16,1247	.hid_width = 5,1248	.parent_map = gcc_parent_map_1,1249	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,1250	.clkr.hw.init = &(const struct clk_init_data) {1251		.name = "gcc_pcie_0_aux_clk_src",1252		.parent_data = gcc_parent_data_1,1253		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1254		.ops = &clk_rcg2_shared_ops,1255	},1256};1257 1258static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {1259	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),1260	{ }1261};1262 1263static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {1264	.cmd_rcgr = 0xa403c,1265	.mnd_width = 0,1266	.hid_width = 5,1267	.parent_map = gcc_parent_map_0,1268	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1269	.clkr.hw.init = &(const struct clk_init_data) {1270		.name = "gcc_pcie_0_phy_rchng_clk_src",1271		.parent_data = gcc_parent_data_0,1272		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1273		.ops = &clk_rcg2_shared_ops,1274	},1275};1276 1277static const struct freq_tbl ftbl_gcc_pcie_1_aux_clk_src[] = {1278	F(19200000, P_BI_TCXO, 1, 0, 0),1279	{ }1280};1281 1282static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {1283	.cmd_rcgr = 0x8d054,1284	.mnd_width = 16,1285	.hid_width = 5,1286	.parent_map = gcc_parent_map_1,1287	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1288	.clkr.hw.init = &(const struct clk_init_data) {1289		.name = "gcc_pcie_1_aux_clk_src",1290		.parent_data = gcc_parent_data_1,1291		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1292		.ops = &clk_rcg2_shared_ops,1293	},1294};1295 1296static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {1297	.cmd_rcgr = 0x8d03c,1298	.mnd_width = 0,1299	.hid_width = 5,1300	.parent_map = gcc_parent_map_0,1301	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1302	.clkr.hw.init = &(const struct clk_init_data) {1303		.name = "gcc_pcie_1_phy_rchng_clk_src",1304		.parent_data = gcc_parent_data_0,1305		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1306		.ops = &clk_rcg2_shared_ops,1307	},1308};1309 1310static struct clk_rcg2 gcc_pcie_2a_aux_clk_src = {1311	.cmd_rcgr = 0x9d064,1312	.mnd_width = 16,1313	.hid_width = 5,1314	.parent_map = gcc_parent_map_1,1315	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1316	.clkr.hw.init = &(const struct clk_init_data) {1317		.name = "gcc_pcie_2a_aux_clk_src",1318		.parent_data = gcc_parent_data_1,1319		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1320		.ops = &clk_rcg2_shared_ops,1321	},1322};1323 1324static struct clk_rcg2 gcc_pcie_2a_phy_rchng_clk_src = {1325	.cmd_rcgr = 0x9d044,1326	.mnd_width = 0,1327	.hid_width = 5,1328	.parent_map = gcc_parent_map_0,1329	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1330	.clkr.hw.init = &(const struct clk_init_data) {1331		.name = "gcc_pcie_2a_phy_rchng_clk_src",1332		.parent_data = gcc_parent_data_0,1333		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1334		.ops = &clk_rcg2_shared_ops,1335	},1336};1337 1338static struct clk_rcg2 gcc_pcie_2b_aux_clk_src = {1339	.cmd_rcgr = 0x9e064,1340	.mnd_width = 16,1341	.hid_width = 5,1342	.parent_map = gcc_parent_map_1,1343	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1344	.clkr.hw.init = &(const struct clk_init_data) {1345		.name = "gcc_pcie_2b_aux_clk_src",1346		.parent_data = gcc_parent_data_1,1347		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1348		.ops = &clk_rcg2_shared_ops,1349	},1350};1351 1352static struct clk_rcg2 gcc_pcie_2b_phy_rchng_clk_src = {1353	.cmd_rcgr = 0x9e044,1354	.mnd_width = 0,1355	.hid_width = 5,1356	.parent_map = gcc_parent_map_0,1357	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1358	.clkr.hw.init = &(const struct clk_init_data) {1359		.name = "gcc_pcie_2b_phy_rchng_clk_src",1360		.parent_data = gcc_parent_data_0,1361		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1362		.ops = &clk_rcg2_shared_ops,1363	},1364};1365 1366static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = {1367	.cmd_rcgr = 0xa0064,1368	.mnd_width = 16,1369	.hid_width = 5,1370	.parent_map = gcc_parent_map_1,1371	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1372	.clkr.hw.init = &(const struct clk_init_data) {1373		.name = "gcc_pcie_3a_aux_clk_src",1374		.parent_data = gcc_parent_data_1,1375		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1376		.ops = &clk_rcg2_shared_ops,1377	},1378};1379 1380static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = {1381	.cmd_rcgr = 0xa0044,1382	.mnd_width = 0,1383	.hid_width = 5,1384	.parent_map = gcc_parent_map_0,1385	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1386	.clkr.hw.init = &(const struct clk_init_data) {1387		.name = "gcc_pcie_3a_phy_rchng_clk_src",1388		.parent_data = gcc_parent_data_0,1389		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1390		.ops = &clk_rcg2_shared_ops,1391	},1392};1393 1394static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = {1395	.cmd_rcgr = 0xa2064,1396	.mnd_width = 16,1397	.hid_width = 5,1398	.parent_map = gcc_parent_map_1,1399	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1400	.clkr.hw.init = &(const struct clk_init_data) {1401		.name = "gcc_pcie_3b_aux_clk_src",1402		.parent_data = gcc_parent_data_1,1403		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1404		.ops = &clk_rcg2_shared_ops,1405	},1406};1407 1408static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = {1409	.cmd_rcgr = 0xa2044,1410	.mnd_width = 0,1411	.hid_width = 5,1412	.parent_map = gcc_parent_map_0,1413	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1414	.clkr.hw.init = &(const struct clk_init_data) {1415		.name = "gcc_pcie_3b_phy_rchng_clk_src",1416		.parent_data = gcc_parent_data_0,1417		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1418		.ops = &clk_rcg2_shared_ops,1419	},1420};1421 1422static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {1423	.cmd_rcgr = 0x6b064,1424	.mnd_width = 16,1425	.hid_width = 5,1426	.parent_map = gcc_parent_map_1,1427	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,1428	.clkr.hw.init = &(const struct clk_init_data) {1429		.name = "gcc_pcie_4_aux_clk_src",1430		.parent_data = gcc_parent_data_1,1431		.num_parents = ARRAY_SIZE(gcc_parent_data_1),1432		.ops = &clk_rcg2_shared_ops,1433	},1434};1435 1436static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {1437	.cmd_rcgr = 0x6b044,1438	.mnd_width = 0,1439	.hid_width = 5,1440	.parent_map = gcc_parent_map_0,1441	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,1442	.clkr.hw.init = &(const struct clk_init_data) {1443		.name = "gcc_pcie_4_phy_rchng_clk_src",1444		.parent_data = gcc_parent_data_0,1445		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1446		.ops = &clk_rcg2_shared_ops,1447	},1448};1449 1450static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {1451	.cmd_rcgr = 0xae00c,1452	.mnd_width = 0,1453	.hid_width = 5,1454	.parent_map = gcc_parent_map_3,1455	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,1456	.clkr.hw.init = &(const struct clk_init_data) {1457		.name = "gcc_pcie_rscc_xo_clk_src",1458		.parent_data = gcc_parent_data_3,1459		.num_parents = ARRAY_SIZE(gcc_parent_data_3),1460		.ops = &clk_rcg2_shared_ops,1461	},1462};1463 1464static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {1465	F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),1466	{ }1467};1468 1469static struct clk_rcg2 gcc_pdm2_clk_src = {1470	.cmd_rcgr = 0x33010,1471	.mnd_width = 0,1472	.hid_width = 5,1473	.parent_map = gcc_parent_map_0,1474	.freq_tbl = ftbl_gcc_pdm2_clk_src,1475	.clkr.hw.init = &(const struct clk_init_data) {1476		.name = "gcc_pdm2_clk_src",1477		.parent_data = gcc_parent_data_0,1478		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1479		.ops = &clk_rcg2_shared_ops,1480	},1481};1482 1483static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {1484	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),1485	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),1486	F(19200000, P_BI_TCXO, 1, 0, 0),1487	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),1488	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),1489	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),1490	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),1491	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),1492	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),1493	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),1494	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),1495	{ }1496};1497 1498static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {1499	.name = "gcc_qupv3_wrap0_s0_clk_src",1500	.parent_data = gcc_parent_data_0,1501	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1502	.flags = CLK_SET_RATE_PARENT,1503	.ops = &clk_rcg2_ops,1504};1505 1506static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {1507	.cmd_rcgr = 0x17148,1508	.mnd_width = 16,1509	.hid_width = 5,1510	.parent_map = gcc_parent_map_0,1511	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1512	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,1513};1514 1515static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {1516	.name = "gcc_qupv3_wrap0_s1_clk_src",1517	.parent_data = gcc_parent_data_0,1518	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1519	.flags = CLK_SET_RATE_PARENT,1520	.ops = &clk_rcg2_ops,1521};1522 1523static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {1524	.cmd_rcgr = 0x17278,1525	.mnd_width = 16,1526	.hid_width = 5,1527	.parent_map = gcc_parent_map_0,1528	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1529	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,1530};1531 1532static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {1533	.name = "gcc_qupv3_wrap0_s2_clk_src",1534	.parent_data = gcc_parent_data_0,1535	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1536	.flags = CLK_SET_RATE_PARENT,1537	.ops = &clk_rcg2_ops,1538};1539 1540static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {1541	.cmd_rcgr = 0x173a8,1542	.mnd_width = 16,1543	.hid_width = 5,1544	.parent_map = gcc_parent_map_0,1545	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1546	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,1547};1548 1549static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {1550	.name = "gcc_qupv3_wrap0_s3_clk_src",1551	.parent_data = gcc_parent_data_0,1552	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1553	.flags = CLK_SET_RATE_PARENT,1554	.ops = &clk_rcg2_ops,1555};1556 1557static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {1558	.cmd_rcgr = 0x174d8,1559	.mnd_width = 16,1560	.hid_width = 5,1561	.parent_map = gcc_parent_map_0,1562	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1563	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,1564};1565 1566static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {1567	.name = "gcc_qupv3_wrap0_s4_clk_src",1568	.parent_data = gcc_parent_data_0,1569	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1570	.flags = CLK_SET_RATE_PARENT,1571	.ops = &clk_rcg2_ops,1572};1573 1574static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {1575	.cmd_rcgr = 0x17608,1576	.mnd_width = 16,1577	.hid_width = 5,1578	.parent_map = gcc_parent_map_0,1579	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1580	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,1581};1582 1583static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {1584	.name = "gcc_qupv3_wrap0_s5_clk_src",1585	.parent_data = gcc_parent_data_0,1586	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1587	.flags = CLK_SET_RATE_PARENT,1588	.ops = &clk_rcg2_ops,1589};1590 1591static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {1592	.cmd_rcgr = 0x17738,1593	.mnd_width = 16,1594	.hid_width = 5,1595	.parent_map = gcc_parent_map_0,1596	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1597	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,1598};1599 1600static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s6_clk_src[] = {1601	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),1602	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),1603	F(19200000, P_BI_TCXO, 1, 0, 0),1604	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),1605	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),1606	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),1607	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),1608	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),1609	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),1610	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),1611	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),1612	{ }1613};1614 1615static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {1616	.name = "gcc_qupv3_wrap0_s6_clk_src",1617	.parent_data = gcc_parent_data_0,1618	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1619	.flags = CLK_SET_RATE_PARENT,1620	.ops = &clk_rcg2_ops,1621};1622 1623static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {1624	.cmd_rcgr = 0x17868,1625	.mnd_width = 16,1626	.hid_width = 5,1627	.parent_map = gcc_parent_map_0,1628	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1629	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,1630};1631 1632static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {1633	.name = "gcc_qupv3_wrap0_s7_clk_src",1634	.parent_data = gcc_parent_data_0,1635	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1636	.flags = CLK_SET_RATE_PARENT,1637	.ops = &clk_rcg2_ops,1638};1639 1640static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {1641	.cmd_rcgr = 0x17998,1642	.mnd_width = 16,1643	.hid_width = 5,1644	.parent_map = gcc_parent_map_0,1645	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1646	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,1647};1648 1649static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {1650	.name = "gcc_qupv3_wrap1_s0_clk_src",1651	.parent_data = gcc_parent_data_0,1652	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1653	.flags = CLK_SET_RATE_PARENT,1654	.ops = &clk_rcg2_ops,1655};1656 1657static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {1658	.cmd_rcgr = 0x18148,1659	.mnd_width = 16,1660	.hid_width = 5,1661	.parent_map = gcc_parent_map_0,1662	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1663	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,1664};1665 1666static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {1667	.name = "gcc_qupv3_wrap1_s1_clk_src",1668	.parent_data = gcc_parent_data_0,1669	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1670	.flags = CLK_SET_RATE_PARENT,1671	.ops = &clk_rcg2_ops,1672};1673 1674static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {1675	.cmd_rcgr = 0x18278,1676	.mnd_width = 16,1677	.hid_width = 5,1678	.parent_map = gcc_parent_map_0,1679	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1680	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,1681};1682 1683static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {1684	.name = "gcc_qupv3_wrap1_s2_clk_src",1685	.parent_data = gcc_parent_data_0,1686	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1687	.flags = CLK_SET_RATE_PARENT,1688	.ops = &clk_rcg2_ops,1689};1690 1691static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {1692	.cmd_rcgr = 0x183a8,1693	.mnd_width = 16,1694	.hid_width = 5,1695	.parent_map = gcc_parent_map_0,1696	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1697	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,1698};1699 1700static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {1701	.name = "gcc_qupv3_wrap1_s3_clk_src",1702	.parent_data = gcc_parent_data_0,1703	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1704	.flags = CLK_SET_RATE_PARENT,1705	.ops = &clk_rcg2_ops,1706};1707 1708static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {1709	.cmd_rcgr = 0x184d8,1710	.mnd_width = 16,1711	.hid_width = 5,1712	.parent_map = gcc_parent_map_0,1713	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1714	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,1715};1716 1717static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {1718	.name = "gcc_qupv3_wrap1_s4_clk_src",1719	.parent_data = gcc_parent_data_0,1720	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1721	.flags = CLK_SET_RATE_PARENT,1722	.ops = &clk_rcg2_ops,1723};1724 1725static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {1726	.cmd_rcgr = 0x18608,1727	.mnd_width = 16,1728	.hid_width = 5,1729	.parent_map = gcc_parent_map_0,1730	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1731	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,1732};1733 1734static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {1735	.name = "gcc_qupv3_wrap1_s5_clk_src",1736	.parent_data = gcc_parent_data_0,1737	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1738	.flags = CLK_SET_RATE_PARENT,1739	.ops = &clk_rcg2_ops,1740};1741 1742static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {1743	.cmd_rcgr = 0x18738,1744	.mnd_width = 16,1745	.hid_width = 5,1746	.parent_map = gcc_parent_map_0,1747	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1748	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,1749};1750 1751static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {1752	.name = "gcc_qupv3_wrap1_s6_clk_src",1753	.parent_data = gcc_parent_data_0,1754	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1755	.flags = CLK_SET_RATE_PARENT,1756	.ops = &clk_rcg2_ops,1757};1758 1759static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {1760	.cmd_rcgr = 0x18868,1761	.mnd_width = 16,1762	.hid_width = 5,1763	.parent_map = gcc_parent_map_0,1764	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1765	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,1766};1767 1768static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {1769	.name = "gcc_qupv3_wrap1_s7_clk_src",1770	.parent_data = gcc_parent_data_0,1771	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1772	.flags = CLK_SET_RATE_PARENT,1773	.ops = &clk_rcg2_ops,1774};1775 1776static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {1777	.cmd_rcgr = 0x18998,1778	.mnd_width = 16,1779	.hid_width = 5,1780	.parent_map = gcc_parent_map_0,1781	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1782	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,1783};1784 1785static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {1786	.name = "gcc_qupv3_wrap2_s0_clk_src",1787	.parent_data = gcc_parent_data_0,1788	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1789	.flags = CLK_SET_RATE_PARENT,1790	.ops = &clk_rcg2_ops,1791};1792 1793static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {1794	.cmd_rcgr = 0x1e148,1795	.mnd_width = 16,1796	.hid_width = 5,1797	.parent_map = gcc_parent_map_0,1798	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1799	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,1800};1801 1802static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {1803	.name = "gcc_qupv3_wrap2_s1_clk_src",1804	.parent_data = gcc_parent_data_0,1805	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1806	.flags = CLK_SET_RATE_PARENT,1807	.ops = &clk_rcg2_ops,1808};1809 1810static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {1811	.cmd_rcgr = 0x1e278,1812	.mnd_width = 16,1813	.hid_width = 5,1814	.parent_map = gcc_parent_map_0,1815	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1816	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,1817};1818 1819static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {1820	.name = "gcc_qupv3_wrap2_s2_clk_src",1821	.parent_data = gcc_parent_data_0,1822	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1823	.flags = CLK_SET_RATE_PARENT,1824	.ops = &clk_rcg2_ops,1825};1826 1827static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {1828	.cmd_rcgr = 0x1e3a8,1829	.mnd_width = 16,1830	.hid_width = 5,1831	.parent_map = gcc_parent_map_0,1832	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1833	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,1834};1835 1836static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {1837	.name = "gcc_qupv3_wrap2_s3_clk_src",1838	.parent_data = gcc_parent_data_0,1839	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1840	.flags = CLK_SET_RATE_PARENT,1841	.ops = &clk_rcg2_ops,1842};1843 1844static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {1845	.cmd_rcgr = 0x1e4d8,1846	.mnd_width = 16,1847	.hid_width = 5,1848	.parent_map = gcc_parent_map_0,1849	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1850	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,1851};1852 1853static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {1854	.name = "gcc_qupv3_wrap2_s4_clk_src",1855	.parent_data = gcc_parent_data_0,1856	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1857	.flags = CLK_SET_RATE_PARENT,1858	.ops = &clk_rcg2_ops,1859};1860 1861static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {1862	.cmd_rcgr = 0x1e608,1863	.mnd_width = 16,1864	.hid_width = 5,1865	.parent_map = gcc_parent_map_0,1866	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1867	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,1868};1869 1870static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {1871	.name = "gcc_qupv3_wrap2_s5_clk_src",1872	.parent_data = gcc_parent_data_0,1873	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1874	.flags = CLK_SET_RATE_PARENT,1875	.ops = &clk_rcg2_ops,1876};1877 1878static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {1879	.cmd_rcgr = 0x1e738,1880	.mnd_width = 16,1881	.hid_width = 5,1882	.parent_map = gcc_parent_map_0,1883	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1884	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,1885};1886 1887static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {1888	.name = "gcc_qupv3_wrap2_s6_clk_src",1889	.parent_data = gcc_parent_data_0,1890	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1891	.flags = CLK_SET_RATE_PARENT,1892	.ops = &clk_rcg2_ops,1893};1894 1895static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {1896	.cmd_rcgr = 0x1e868,1897	.mnd_width = 16,1898	.hid_width = 5,1899	.parent_map = gcc_parent_map_0,1900	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1901	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,1902};1903 1904static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {1905	.name = "gcc_qupv3_wrap2_s7_clk_src",1906	.parent_data = gcc_parent_data_0,1907	.num_parents = ARRAY_SIZE(gcc_parent_data_0),1908	.flags = CLK_SET_RATE_PARENT,1909	.ops = &clk_rcg2_ops,1910};1911 1912static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {1913	.cmd_rcgr = 0x1e998,1914	.mnd_width = 16,1915	.hid_width = 5,1916	.parent_map = gcc_parent_map_0,1917	.freq_tbl = ftbl_gcc_qupv3_wrap0_s6_clk_src,1918	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,1919};1920 1921static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {1922	F(400000, P_BI_TCXO, 12, 1, 4),1923	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),1924	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),1925	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),1926	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),1927	{ }1928};1929 1930static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {1931	.cmd_rcgr = 0x1400c,1932	.mnd_width = 8,1933	.hid_width = 5,1934	.parent_map = gcc_parent_map_15,1935	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,1936	.clkr.hw.init = &(const struct clk_init_data) {1937		.name = "gcc_sdcc2_apps_clk_src",1938		.parent_data = gcc_parent_data_15,1939		.num_parents = ARRAY_SIZE(gcc_parent_data_15),1940		.ops = &clk_rcg2_shared_ops,1941	},1942};1943 1944static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {1945	F(400000, P_BI_TCXO, 12, 1, 4),1946	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),1947	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),1948	{ }1949};1950 1951static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {1952	.cmd_rcgr = 0x1600c,1953	.mnd_width = 8,1954	.hid_width = 5,1955	.parent_map = gcc_parent_map_0,1956	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,1957	.clkr.hw.init = &(const struct clk_init_data) {1958		.name = "gcc_sdcc4_apps_clk_src",1959		.parent_data = gcc_parent_data_0,1960		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1961		.ops = &clk_rcg2_shared_ops,1962	},1963};1964 1965static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {1966	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),1967	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),1968	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),1969	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),1970	{ }1971};1972 1973static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {1974	.cmd_rcgr = 0x75024,1975	.mnd_width = 8,1976	.hid_width = 5,1977	.parent_map = gcc_parent_map_0,1978	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,1979	.clkr.hw.init = &(const struct clk_init_data) {1980		.name = "gcc_ufs_card_axi_clk_src",1981		.parent_data = gcc_parent_data_0,1982		.num_parents = ARRAY_SIZE(gcc_parent_data_0),1983		.ops = &clk_rcg2_shared_ops,1984	},1985};1986 1987static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {1988	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),1989	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),1990	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),1991	{ }1992};1993 1994static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {1995	.cmd_rcgr = 0x7506c,1996	.mnd_width = 0,1997	.hid_width = 5,1998	.parent_map = gcc_parent_map_0,1999	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,2000	.clkr.hw.init = &(const struct clk_init_data) {2001		.name = "gcc_ufs_card_ice_core_clk_src",2002		.parent_data = gcc_parent_data_0,2003		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2004		.ops = &clk_rcg2_shared_ops,2005	},2006};2007 2008static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {2009	.cmd_rcgr = 0x750a0,2010	.mnd_width = 0,2011	.hid_width = 5,2012	.parent_map = gcc_parent_map_3,2013	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2014	.clkr.hw.init = &(const struct clk_init_data) {2015		.name = "gcc_ufs_card_phy_aux_clk_src",2016		.parent_data = gcc_parent_data_3,2017		.num_parents = ARRAY_SIZE(gcc_parent_data_3),2018		.ops = &clk_rcg2_shared_ops,2019	},2020};2021 2022static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {2023	.cmd_rcgr = 0x75084,2024	.mnd_width = 0,2025	.hid_width = 5,2026	.parent_map = gcc_parent_map_0,2027	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,2028	.clkr.hw.init = &(const struct clk_init_data) {2029		.name = "gcc_ufs_card_unipro_core_clk_src",2030		.parent_data = gcc_parent_data_0,2031		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2032		.ops = &clk_rcg2_shared_ops,2033	},2034};2035 2036static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {2037	.cmd_rcgr = 0x77024,2038	.mnd_width = 8,2039	.hid_width = 5,2040	.parent_map = gcc_parent_map_0,2041	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,2042	.clkr.hw.init = &(const struct clk_init_data) {2043		.name = "gcc_ufs_phy_axi_clk_src",2044		.parent_data = gcc_parent_data_0,2045		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2046		.ops = &clk_rcg2_shared_ops,2047	},2048};2049 2050static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {2051	.cmd_rcgr = 0x7706c,2052	.mnd_width = 0,2053	.hid_width = 5,2054	.parent_map = gcc_parent_map_0,2055	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,2056	.clkr.hw.init = &(const struct clk_init_data) {2057		.name = "gcc_ufs_phy_ice_core_clk_src",2058		.parent_data = gcc_parent_data_0,2059		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2060		.ops = &clk_rcg2_shared_ops,2061	},2062};2063 2064static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {2065	.cmd_rcgr = 0x770a0,2066	.mnd_width = 0,2067	.hid_width = 5,2068	.parent_map = gcc_parent_map_3,2069	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,2070	.clkr.hw.init = &(const struct clk_init_data) {2071		.name = "gcc_ufs_phy_phy_aux_clk_src",2072		.parent_data = gcc_parent_data_3,2073		.num_parents = ARRAY_SIZE(gcc_parent_data_3),2074		.ops = &clk_rcg2_shared_ops,2075	},2076};2077 2078static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {2079	.cmd_rcgr = 0x77084,2080	.mnd_width = 0,2081	.hid_width = 5,2082	.parent_map = gcc_parent_map_0,2083	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,2084	.clkr.hw.init = &(const struct clk_init_data) {2085		.name = "gcc_ufs_phy_unipro_core_clk_src",2086		.parent_data = gcc_parent_data_0,2087		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2088		.ops = &clk_rcg2_shared_ops,2089	},2090};2091 2092static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {2093	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),2094	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),2095	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),2096	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),2097	{ }2098};2099 2100static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {2101	.cmd_rcgr = 0xab020,2102	.mnd_width = 8,2103	.hid_width = 5,2104	.parent_map = gcc_parent_map_0,2105	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,2106	.clkr.hw.init = &(const struct clk_init_data) {2107		.name = "gcc_usb30_mp_master_clk_src",2108		.parent_data = gcc_parent_data_0,2109		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2110		.ops = &clk_rcg2_shared_ops,2111	},2112};2113 2114static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {2115	.cmd_rcgr = 0xab038,2116	.mnd_width = 0,2117	.hid_width = 5,2118	.parent_map = gcc_parent_map_0,2119	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2120	.clkr.hw.init = &(const struct clk_init_data) {2121		.name = "gcc_usb30_mp_mock_utmi_clk_src",2122		.parent_data = gcc_parent_data_0,2123		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2124		.ops = &clk_rcg2_shared_ops,2125	},2126};2127 2128static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {2129	.cmd_rcgr = 0xf020,2130	.mnd_width = 8,2131	.hid_width = 5,2132	.parent_map = gcc_parent_map_0,2133	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,2134	.clkr.hw.init = &(const struct clk_init_data) {2135		.name = "gcc_usb30_prim_master_clk_src",2136		.parent_data = gcc_parent_data_0,2137		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2138		.ops = &clk_rcg2_shared_ops,2139	},2140};2141 2142static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {2143	.cmd_rcgr = 0xf038,2144	.mnd_width = 0,2145	.hid_width = 5,2146	.parent_map = gcc_parent_map_0,2147	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2148	.clkr.hw.init = &(const struct clk_init_data) {2149		.name = "gcc_usb30_prim_mock_utmi_clk_src",2150		.parent_data = gcc_parent_data_0,2151		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2152		.ops = &clk_rcg2_shared_ops,2153	},2154};2155 2156static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {2157	.cmd_rcgr = 0x10020,2158	.mnd_width = 8,2159	.hid_width = 5,2160	.parent_map = gcc_parent_map_0,2161	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,2162	.clkr.hw.init = &(const struct clk_init_data) {2163		.name = "gcc_usb30_sec_master_clk_src",2164		.parent_data = gcc_parent_data_0,2165		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2166		.ops = &clk_rcg2_shared_ops,2167	},2168};2169 2170static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {2171	.cmd_rcgr = 0x10038,2172	.mnd_width = 0,2173	.hid_width = 5,2174	.parent_map = gcc_parent_map_0,2175	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2176	.clkr.hw.init = &(const struct clk_init_data) {2177		.name = "gcc_usb30_sec_mock_utmi_clk_src",2178		.parent_data = gcc_parent_data_0,2179		.num_parents = ARRAY_SIZE(gcc_parent_data_0),2180		.ops = &clk_rcg2_shared_ops,2181	},2182};2183 2184static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {2185	.cmd_rcgr = 0xab06c,2186	.mnd_width = 0,2187	.hid_width = 5,2188	.parent_map = gcc_parent_map_1,2189	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2190	.clkr.hw.init = &(const struct clk_init_data) {2191		.name = "gcc_usb3_mp_phy_aux_clk_src",2192		.parent_data = gcc_parent_data_1,2193		.num_parents = ARRAY_SIZE(gcc_parent_data_1),2194		.ops = &clk_rcg2_shared_ops,2195	},2196};2197 2198static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {2199	.cmd_rcgr = 0xf068,2200	.mnd_width = 0,2201	.hid_width = 5,2202	.parent_map = gcc_parent_map_1,2203	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2204	.clkr.hw.init = &(const struct clk_init_data) {2205		.name = "gcc_usb3_prim_phy_aux_clk_src",2206		.parent_data = gcc_parent_data_1,2207		.num_parents = ARRAY_SIZE(gcc_parent_data_1),2208		.ops = &clk_rcg2_shared_ops,2209	},2210};2211 2212static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {2213	.cmd_rcgr = 0x10068,2214	.mnd_width = 0,2215	.hid_width = 5,2216	.parent_map = gcc_parent_map_1,2217	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2218	.clkr.hw.init = &(const struct clk_init_data) {2219		.name = "gcc_usb3_sec_phy_aux_clk_src",2220		.parent_data = gcc_parent_data_1,2221		.num_parents = ARRAY_SIZE(gcc_parent_data_1),2222		.ops = &clk_rcg2_shared_ops,2223	},2224};2225 2226static const struct freq_tbl ftbl_gcc_usb4_1_master_clk_src[] = {2227	F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),2228	F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),2229	F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),2230	{ }2231};2232 2233static struct clk_rcg2 gcc_usb4_1_master_clk_src = {2234	.cmd_rcgr = 0xb8018,2235	.mnd_width = 8,2236	.hid_width = 5,2237	.parent_map = gcc_parent_map_5,2238	.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,2239	.clkr.hw.init = &(const struct clk_init_data) {2240		.name = "gcc_usb4_1_master_clk_src",2241		.parent_data = gcc_parent_data_5,2242		.num_parents = ARRAY_SIZE(gcc_parent_data_5),2243		.ops = &clk_rcg2_shared_ops,2244	},2245};2246 2247static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = {2248	F(19200000, P_BI_TCXO, 1, 0, 0),2249	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),2250	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),2251	{ }2252};2253 2254static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {2255	.cmd_rcgr = 0xb80c4,2256	.mnd_width = 0,2257	.hid_width = 5,2258	.parent_map = gcc_parent_map_6,2259	.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,2260	.clkr.hw.init = &(const struct clk_init_data) {2261		.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",2262		.parent_data = gcc_parent_data_6,2263		.num_parents = ARRAY_SIZE(gcc_parent_data_6),2264		.ops = &clk_rcg2_shared_ops,2265	},2266};2267 2268static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {2269	.cmd_rcgr = 0xb8070,2270	.mnd_width = 0,2271	.hid_width = 5,2272	.parent_map = gcc_parent_map_1,2273	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2274	.clkr.hw.init = &(const struct clk_init_data) {2275		.name = "gcc_usb4_1_sb_if_clk_src",2276		.parent_data = gcc_parent_data_1,2277		.num_parents = ARRAY_SIZE(gcc_parent_data_1),2278		.ops = &clk_rcg2_shared_ops,2279	},2280};2281 2282static const struct freq_tbl ftbl_gcc_usb4_1_tmu_clk_src[] = {2283	F(19200000, P_BI_TCXO, 1, 0, 0),2284	F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),2285	{ }2286};2287 2288static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {2289	.cmd_rcgr = 0xb8054,2290	.mnd_width = 0,2291	.hid_width = 5,2292	.parent_map = gcc_parent_map_7,2293	.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,2294	.clkr.hw.init = &(const struct clk_init_data) {2295		.name = "gcc_usb4_1_tmu_clk_src",2296		.parent_data = gcc_parent_data_7,2297		.num_parents = ARRAY_SIZE(gcc_parent_data_7),2298		.ops = &clk_rcg2_shared_ops,2299	},2300};2301 2302static struct clk_rcg2 gcc_usb4_master_clk_src = {2303	.cmd_rcgr = 0x2a018,2304	.mnd_width = 8,2305	.hid_width = 5,2306	.parent_map = gcc_parent_map_5,2307	.freq_tbl = ftbl_gcc_usb4_1_master_clk_src,2308	.clkr.hw.init = &(const struct clk_init_data) {2309		.name = "gcc_usb4_master_clk_src",2310		.parent_data = gcc_parent_data_5,2311		.num_parents = ARRAY_SIZE(gcc_parent_data_5),2312		.ops = &clk_rcg2_shared_ops,2313	},2314};2315 2316static struct clk_rcg2 gcc_usb4_phy_pcie_pipe_clk_src = {2317	.cmd_rcgr = 0x2a0c4,2318	.mnd_width = 0,2319	.hid_width = 5,2320	.parent_map = gcc_parent_map_6,2321	.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,2322	.clkr.hw.init = &(const struct clk_init_data) {2323		.name = "gcc_usb4_phy_pcie_pipe_clk_src",2324		.parent_data = gcc_parent_data_6,2325		.num_parents = ARRAY_SIZE(gcc_parent_data_6),2326		.ops = &clk_rcg2_shared_ops,2327	},2328};2329 2330static struct clk_rcg2 gcc_usb4_sb_if_clk_src = {2331	.cmd_rcgr = 0x2a070,2332	.mnd_width = 0,2333	.hid_width = 5,2334	.parent_map = gcc_parent_map_1,2335	.freq_tbl = ftbl_gcc_pcie_1_aux_clk_src,2336	.clkr.hw.init = &(const struct clk_init_data) {2337		.name = "gcc_usb4_sb_if_clk_src",2338		.parent_data = gcc_parent_data_1,2339		.num_parents = ARRAY_SIZE(gcc_parent_data_1),2340		.ops = &clk_rcg2_shared_ops,2341	},2342};2343 2344static struct clk_rcg2 gcc_usb4_tmu_clk_src = {2345	.cmd_rcgr = 0x2a054,2346	.mnd_width = 0,2347	.hid_width = 5,2348	.parent_map = gcc_parent_map_7,2349	.freq_tbl = ftbl_gcc_usb4_1_tmu_clk_src,2350	.clkr.hw.init = &(const struct clk_init_data) {2351		.name = "gcc_usb4_tmu_clk_src",2352		.parent_data = gcc_parent_data_7,2353		.num_parents = ARRAY_SIZE(gcc_parent_data_7),2354		.ops = &clk_rcg2_shared_ops,2355	},2356};2357 2358static struct clk_regmap_div gcc_pcie_2a_pipe_div_clk_src = {2359	.reg = 0x9d060,2360	.shift = 0,2361	.width = 4,2362	.clkr.hw.init = &(const struct clk_init_data) {2363		.name = "gcc_pcie_2a_pipe_div_clk_src",2364		.parent_hws = (const struct clk_hw*[]){2365			&gcc_pcie_2a_pipe_clk_src.clkr.hw,2366		},2367		.num_parents = 1,2368		.flags = CLK_SET_RATE_PARENT,2369		.ops = &clk_regmap_div_ro_ops,2370	},2371};2372 2373static struct clk_regmap_div gcc_pcie_2b_pipe_div_clk_src = {2374	.reg = 0x9e060,2375	.shift = 0,2376	.width = 4,2377	.clkr.hw.init = &(const struct clk_init_data) {2378		.name = "gcc_pcie_2b_pipe_div_clk_src",2379		.parent_hws = (const struct clk_hw*[]){2380			&gcc_pcie_2b_pipe_clk_src.clkr.hw,2381		},2382		.num_parents = 1,2383		.flags = CLK_SET_RATE_PARENT,2384		.ops = &clk_regmap_div_ro_ops,2385	},2386};2387 2388static struct clk_regmap_div gcc_pcie_3a_pipe_div_clk_src = {2389	.reg = 0xa0060,2390	.shift = 0,2391	.width = 4,2392	.clkr.hw.init = &(const struct clk_init_data) {2393		.name = "gcc_pcie_3a_pipe_div_clk_src",2394		.parent_hws = (const struct clk_hw*[]){2395			&gcc_pcie_3a_pipe_clk_src.clkr.hw,2396		},2397		.num_parents = 1,2398		.flags = CLK_SET_RATE_PARENT,2399		.ops = &clk_regmap_div_ro_ops,2400	},2401};2402 2403static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = {2404	.reg = 0xa2060,2405	.shift = 0,2406	.width = 4,2407	.clkr.hw.init = &(const struct clk_init_data) {2408		.name = "gcc_pcie_3b_pipe_div_clk_src",2409		.parent_hws = (const struct clk_hw*[]){2410			&gcc_pcie_3b_pipe_clk_src.clkr.hw,2411		},2412		.num_parents = 1,2413		.flags = CLK_SET_RATE_PARENT,2414		.ops = &clk_regmap_div_ro_ops,2415	},2416};2417 2418static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {2419	.reg = 0x6b060,2420	.shift = 0,2421	.width = 4,2422	.clkr.hw.init = &(const struct clk_init_data) {2423		.name = "gcc_pcie_4_pipe_div_clk_src",2424		.parent_hws = (const struct clk_hw*[]){2425			&gcc_pcie_4_pipe_clk_src.clkr.hw,2426		},2427		.num_parents = 1,2428		.flags = CLK_SET_RATE_PARENT,2429		.ops = &clk_regmap_div_ro_ops,2430	},2431};2432 2433static struct clk_regmap_div gcc_qupv3_wrap0_s4_div_clk_src = {2434	.reg = 0x17ac8,2435	.shift = 0,2436	.width = 4,2437	.clkr.hw.init = &(const struct clk_init_data) {2438		.name = "gcc_qupv3_wrap0_s4_div_clk_src",2439		.parent_hws = (const struct clk_hw*[]){2440			&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,2441		},2442		.num_parents = 1,2443		.flags = CLK_SET_RATE_PARENT,2444		.ops = &clk_regmap_div_ro_ops,2445	},2446};2447 2448static struct clk_regmap_div gcc_qupv3_wrap1_s4_div_clk_src = {2449	.reg = 0x18ac8,2450	.shift = 0,2451	.width = 4,2452	.clkr.hw.init = &(const struct clk_init_data) {2453		.name = "gcc_qupv3_wrap1_s4_div_clk_src",2454		.parent_hws = (const struct clk_hw*[]){2455			&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,2456		},2457		.num_parents = 1,2458		.flags = CLK_SET_RATE_PARENT,2459		.ops = &clk_regmap_div_ro_ops,2460	},2461};2462 2463static struct clk_regmap_div gcc_qupv3_wrap2_s4_div_clk_src = {2464	.reg = 0x1eac8,2465	.shift = 0,2466	.width = 4,2467	.clkr.hw.init = &(const struct clk_init_data) {2468		.name = "gcc_qupv3_wrap2_s4_div_clk_src",2469		.parent_hws = (const struct clk_hw*[]){2470			&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,2471		},2472		.num_parents = 1,2473		.flags = CLK_SET_RATE_PARENT,2474		.ops = &clk_regmap_div_ro_ops,2475	},2476};2477 2478static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {2479	.reg = 0xab050,2480	.shift = 0,2481	.width = 4,2482	.clkr.hw.init = &(const struct clk_init_data) {2483		.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",2484		.parent_hws = (const struct clk_hw*[]){2485			&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,2486		},2487		.num_parents = 1,2488		.flags = CLK_SET_RATE_PARENT,2489		.ops = &clk_regmap_div_ro_ops,2490	},2491};2492 2493static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {2494	.reg = 0xf050,2495	.shift = 0,2496	.width = 4,2497	.clkr.hw.init = &(const struct clk_init_data) {2498		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",2499		.parent_hws = (const struct clk_hw*[]){2500			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,2501		},2502		.num_parents = 1,2503		.flags = CLK_SET_RATE_PARENT,2504		.ops = &clk_regmap_div_ro_ops,2505	},2506};2507 2508static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {2509	.reg = 0x10050,2510	.shift = 0,2511	.width = 4,2512	.clkr.hw.init = &(const struct clk_init_data) {2513		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",2514		.parent_hws = (const struct clk_hw*[]){2515			&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,2516		},2517		.num_parents = 1,2518		.flags = CLK_SET_RATE_PARENT,2519		.ops = &clk_regmap_div_ro_ops,2520	},2521};2522 2523static struct clk_branch gcc_aggre_noc_pcie0_tunnel_axi_clk = {2524	.halt_reg = 0xa41a8,2525	.halt_check = BRANCH_HALT_SKIP,2526	.hwcg_reg = 0xa41a8,2527	.hwcg_bit = 1,2528	.clkr = {2529		.enable_reg = 0x52018,2530		.enable_mask = BIT(14),2531		.hw.init = &(const struct clk_init_data) {2532			.name = "gcc_aggre_noc_pcie0_tunnel_axi_clk",2533			.ops = &clk_branch2_ops,2534		},2535	},2536};2537 2538static struct clk_branch gcc_aggre_noc_pcie1_tunnel_axi_clk = {2539	.halt_reg = 0x8d07c,2540	.halt_check = BRANCH_HALT_SKIP,2541	.hwcg_reg = 0x8d07c,2542	.hwcg_bit = 1,2543	.clkr = {2544		.enable_reg = 0x52018,2545		.enable_mask = BIT(21),2546		.hw.init = &(const struct clk_init_data) {2547			.name = "gcc_aggre_noc_pcie1_tunnel_axi_clk",2548			.ops = &clk_branch2_ops,2549		},2550	},2551};2552 2553static struct clk_branch gcc_aggre_noc_pcie_4_axi_clk = {2554	.halt_reg = 0x6b1b8,2555	.halt_check = BRANCH_HALT_SKIP,2556	.hwcg_reg = 0x6b1b8,2557	.hwcg_bit = 1,2558	.clkr = {2559		.enable_reg = 0x52000,2560		.enable_mask = BIT(12),2561		.hw.init = &(const struct clk_init_data) {2562			.name = "gcc_aggre_noc_pcie_4_axi_clk",2563			.ops = &clk_branch2_ops,2564		},2565	},2566};2567 2568static struct clk_branch gcc_aggre_noc_pcie_south_sf_axi_clk = {2569	.halt_reg = 0xbf13c,2570	.halt_check = BRANCH_HALT_SKIP,2571	.hwcg_reg = 0xbf13c,2572	.hwcg_bit = 1,2573	.clkr = {2574		.enable_reg = 0x52018,2575		.enable_mask = BIT(13),2576		.hw.init = &(const struct clk_init_data) {2577			.name = "gcc_aggre_noc_pcie_south_sf_axi_clk",2578			.ops = &clk_branch2_ops,2579		},2580	},2581};2582 2583static struct clk_branch gcc_aggre_ufs_card_axi_clk = {2584	.halt_reg = 0x750cc,2585	.halt_check = BRANCH_HALT_VOTED,2586	.hwcg_reg = 0x750cc,2587	.hwcg_bit = 1,2588	.clkr = {2589		.enable_reg = 0x750cc,2590		.enable_mask = BIT(0),2591		.hw.init = &(const struct clk_init_data) {2592			.name = "gcc_aggre_ufs_card_axi_clk",2593			.parent_hws = (const struct clk_hw*[]){2594				&gcc_ufs_card_axi_clk_src.clkr.hw,2595			},2596			.num_parents = 1,2597			.flags = CLK_SET_RATE_PARENT,2598			.ops = &clk_branch2_ops,2599		},2600	},2601};2602 2603static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {2604	.halt_reg = 0x750cc,2605	.halt_check = BRANCH_HALT_VOTED,2606	.hwcg_reg = 0x750cc,2607	.hwcg_bit = 1,2608	.clkr = {2609		.enable_reg = 0x750cc,2610		.enable_mask = BIT(1),2611		.hw.init = &(const struct clk_init_data) {2612			.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",2613			.parent_hws = (const struct clk_hw*[]){2614				&gcc_ufs_card_axi_clk_src.clkr.hw,2615			},2616			.num_parents = 1,2617			.flags = CLK_SET_RATE_PARENT,2618			.ops = &clk_branch2_ops,2619		},2620	},2621};2622 2623static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {2624	.halt_reg = 0x770cc,2625	.halt_check = BRANCH_HALT_VOTED,2626	.hwcg_reg = 0x770cc,2627	.hwcg_bit = 1,2628	.clkr = {2629		.enable_reg = 0x770cc,2630		.enable_mask = BIT(0),2631		.hw.init = &(const struct clk_init_data) {2632			.name = "gcc_aggre_ufs_phy_axi_clk",2633			.parent_hws = (const struct clk_hw*[]){2634				&gcc_ufs_phy_axi_clk_src.clkr.hw,2635			},2636			.num_parents = 1,2637			.flags = CLK_SET_RATE_PARENT,2638			.ops = &clk_branch2_ops,2639		},2640	},2641};2642 2643static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {2644	.halt_reg = 0x770cc,2645	.halt_check = BRANCH_HALT_VOTED,2646	.hwcg_reg = 0x770cc,2647	.hwcg_bit = 1,2648	.clkr = {2649		.enable_reg = 0x770cc,2650		.enable_mask = BIT(1),2651		.hw.init = &(const struct clk_init_data) {2652			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",2653			.parent_hws = (const struct clk_hw*[]){2654				&gcc_ufs_phy_axi_clk_src.clkr.hw,2655			},2656			.num_parents = 1,2657			.flags = CLK_SET_RATE_PARENT,2658			.ops = &clk_branch2_ops,2659		},2660	},2661};2662 2663static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {2664	.halt_reg = 0xab084,2665	.halt_check = BRANCH_HALT_VOTED,2666	.hwcg_reg = 0xab084,2667	.hwcg_bit = 1,2668	.clkr = {2669		.enable_reg = 0xab084,2670		.enable_mask = BIT(0),2671		.hw.init = &(const struct clk_init_data) {2672			.name = "gcc_aggre_usb3_mp_axi_clk",2673			.parent_hws = (const struct clk_hw*[]){2674				&gcc_usb30_mp_master_clk_src.clkr.hw,2675			},2676			.num_parents = 1,2677			.flags = CLK_SET_RATE_PARENT,2678			.ops = &clk_branch2_ops,2679		},2680	},2681};2682 2683static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {2684	.halt_reg = 0xf080,2685	.halt_check = BRANCH_HALT_VOTED,2686	.hwcg_reg = 0xf080,2687	.hwcg_bit = 1,2688	.clkr = {2689		.enable_reg = 0xf080,2690		.enable_mask = BIT(0),2691		.hw.init = &(const struct clk_init_data) {2692			.name = "gcc_aggre_usb3_prim_axi_clk",2693			.parent_hws = (const struct clk_hw*[]){2694				&gcc_usb30_prim_master_clk_src.clkr.hw,2695			},2696			.num_parents = 1,2697			.flags = CLK_SET_RATE_PARENT,2698			.ops = &clk_branch2_ops,2699		},2700	},2701};2702 2703static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {2704	.halt_reg = 0x10080,2705	.halt_check = BRANCH_HALT_VOTED,2706	.hwcg_reg = 0x10080,2707	.hwcg_bit = 1,2708	.clkr = {2709		.enable_reg = 0x10080,2710		.enable_mask = BIT(0),2711		.hw.init = &(const struct clk_init_data) {2712			.name = "gcc_aggre_usb3_sec_axi_clk",2713			.parent_hws = (const struct clk_hw*[]){2714				&gcc_usb30_sec_master_clk_src.clkr.hw,2715			},2716			.num_parents = 1,2717			.flags = CLK_SET_RATE_PARENT,2718			.ops = &clk_branch2_ops,2719		},2720	},2721};2722 2723static struct clk_branch gcc_aggre_usb4_1_axi_clk = {2724	.halt_reg = 0xb80e4,2725	.halt_check = BRANCH_HALT_VOTED,2726	.hwcg_reg = 0xb80e4,2727	.hwcg_bit = 1,2728	.clkr = {2729		.enable_reg = 0xb80e4,2730		.enable_mask = BIT(0),2731		.hw.init = &(const struct clk_init_data) {2732			.name = "gcc_aggre_usb4_1_axi_clk",2733			.parent_hws = (const struct clk_hw*[]){2734				&gcc_usb4_1_master_clk_src.clkr.hw,2735			},2736			.num_parents = 1,2737			.flags = CLK_SET_RATE_PARENT,2738			.ops = &clk_branch2_ops,2739		},2740	},2741};2742 2743static struct clk_branch gcc_aggre_usb4_axi_clk = {2744	.halt_reg = 0x2a0e4,2745	.halt_check = BRANCH_HALT_VOTED,2746	.hwcg_reg = 0x2a0e4,2747	.hwcg_bit = 1,2748	.clkr = {2749		.enable_reg = 0x2a0e4,2750		.enable_mask = BIT(0),2751		.hw.init = &(const struct clk_init_data) {2752			.name = "gcc_aggre_usb4_axi_clk",2753			.parent_hws = (const struct clk_hw*[]){2754				&gcc_usb4_master_clk_src.clkr.hw,2755			},2756			.num_parents = 1,2757			.flags = CLK_SET_RATE_PARENT,2758			.ops = &clk_branch2_ops,2759		},2760	},2761};2762 2763static struct clk_branch gcc_aggre_usb_noc_axi_clk = {2764	.halt_reg = 0x5d024,2765	.halt_check = BRANCH_HALT_VOTED,2766	.hwcg_reg = 0x5d024,2767	.hwcg_bit = 1,2768	.clkr = {2769		.enable_reg = 0x5d024,2770		.enable_mask = BIT(0),2771		.hw.init = &(const struct clk_init_data) {2772			.name = "gcc_aggre_usb_noc_axi_clk",2773			.ops = &clk_branch2_ops,2774		},2775	},2776};2777 2778static struct clk_branch gcc_aggre_usb_noc_north_axi_clk = {2779	.halt_reg = 0x5d020,2780	.halt_check = BRANCH_HALT_VOTED,2781	.hwcg_reg = 0x5d020,2782	.hwcg_bit = 1,2783	.clkr = {2784		.enable_reg = 0x5d020,2785		.enable_mask = BIT(0),2786		.hw.init = &(const struct clk_init_data) {2787			.name = "gcc_aggre_usb_noc_north_axi_clk",2788			.ops = &clk_branch2_ops,2789		},2790	},2791};2792 2793static struct clk_branch gcc_aggre_usb_noc_south_axi_clk = {2794	.halt_reg = 0x5d01c,2795	.halt_check = BRANCH_HALT_VOTED,2796	.hwcg_reg = 0x5d01c,2797	.hwcg_bit = 1,2798	.clkr = {2799		.enable_reg = 0x5d01c,2800		.enable_mask = BIT(0),2801		.hw.init = &(const struct clk_init_data) {2802			.name = "gcc_aggre_usb_noc_south_axi_clk",2803			.ops = &clk_branch2_ops,2804		},2805	},2806};2807 2808static struct clk_branch gcc_ahb2phy0_clk = {2809	.halt_reg = 0x6a004,2810	.halt_check = BRANCH_HALT_VOTED,2811	.hwcg_reg = 0x6a004,2812	.hwcg_bit = 1,2813	.clkr = {2814		.enable_reg = 0x6a004,2815		.enable_mask = BIT(0),2816		.hw.init = &(const struct clk_init_data) {2817			.name = "gcc_ahb2phy0_clk",2818			.ops = &clk_branch2_ops,2819		},2820	},2821};2822 2823static struct clk_branch gcc_ahb2phy2_clk = {2824	.halt_reg = 0x6a008,2825	.halt_check = BRANCH_HALT_VOTED,2826	.hwcg_reg = 0x6a008,2827	.hwcg_bit = 1,2828	.clkr = {2829		.enable_reg = 0x6a008,2830		.enable_mask = BIT(0),2831		.hw.init = &(const struct clk_init_data) {2832			.name = "gcc_ahb2phy2_clk",2833			.ops = &clk_branch2_ops,2834		},2835	},2836};2837 2838static struct clk_branch gcc_boot_rom_ahb_clk = {2839	.halt_reg = 0x38004,2840	.halt_check = BRANCH_HALT_VOTED,2841	.hwcg_reg = 0x38004,2842	.hwcg_bit = 1,2843	.clkr = {2844		.enable_reg = 0x52000,2845		.enable_mask = BIT(10),2846		.hw.init = &(const struct clk_init_data) {2847			.name = "gcc_boot_rom_ahb_clk",2848			.ops = &clk_branch2_ops,2849		},2850	},2851};2852 2853static struct clk_branch gcc_camera_hf_axi_clk = {2854	.halt_reg = 0x26010,2855	.halt_check = BRANCH_HALT_SKIP,2856	.hwcg_reg = 0x26010,2857	.hwcg_bit = 1,2858	.clkr = {2859		.enable_reg = 0x26010,2860		.enable_mask = BIT(0),2861		.hw.init = &(const struct clk_init_data) {2862			.name = "gcc_camera_hf_axi_clk",2863			.ops = &clk_branch2_ops,2864		},2865	},2866};2867 2868static struct clk_branch gcc_camera_sf_axi_clk = {2869	.halt_reg = 0x26014,2870	.halt_check = BRANCH_HALT_SKIP,2871	.hwcg_reg = 0x26014,2872	.hwcg_bit = 1,2873	.clkr = {2874		.enable_reg = 0x26014,2875		.enable_mask = BIT(0),2876		.hw.init = &(const struct clk_init_data) {2877			.name = "gcc_camera_sf_axi_clk",2878			.ops = &clk_branch2_ops,2879		},2880	},2881};2882 2883static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {2884	.halt_reg = 0x2601c,2885	.halt_check = BRANCH_HALT_SKIP,2886	.hwcg_reg = 0x2601c,2887	.hwcg_bit = 1,2888	.clkr = {2889		.enable_reg = 0x2601c,2890		.enable_mask = BIT(0),2891		.hw.init = &(const struct clk_init_data) {2892			.name = "gcc_camera_throttle_nrt_axi_clk",2893			.ops = &clk_branch2_ops,2894		},2895	},2896};2897 2898static struct clk_branch gcc_camera_throttle_rt_axi_clk = {2899	.halt_reg = 0x26018,2900	.halt_check = BRANCH_HALT_SKIP,2901	.hwcg_reg = 0x26018,2902	.hwcg_bit = 1,2903	.clkr = {2904		.enable_reg = 0x26018,2905		.enable_mask = BIT(0),2906		.hw.init = &(const struct clk_init_data) {2907			.name = "gcc_camera_throttle_rt_axi_clk",2908			.ops = &clk_branch2_ops,2909		},2910	},2911};2912 2913static struct clk_branch gcc_camera_throttle_xo_clk = {2914	.halt_reg = 0x26024,2915	.halt_check = BRANCH_HALT,2916	.clkr = {2917		.enable_reg = 0x26024,2918		.enable_mask = BIT(0),2919		.hw.init = &(const struct clk_init_data) {2920			.name = "gcc_camera_throttle_xo_clk",2921			.ops = &clk_branch2_ops,2922		},2923	},2924};2925 2926static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {2927	.halt_reg = 0xab088,2928	.halt_check = BRANCH_HALT_VOTED,2929	.hwcg_reg = 0xab088,2930	.hwcg_bit = 1,2931	.clkr = {2932		.enable_reg = 0xab088,2933		.enable_mask = BIT(0),2934		.hw.init = &(const struct clk_init_data) {2935			.name = "gcc_cfg_noc_usb3_mp_axi_clk",2936			.parent_hws = (const struct clk_hw*[]){2937				&gcc_usb30_mp_master_clk_src.clkr.hw,2938			},2939			.num_parents = 1,2940			.flags = CLK_SET_RATE_PARENT,2941			.ops = &clk_branch2_ops,2942		},2943	},2944};2945 2946static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {2947	.halt_reg = 0xf084,2948	.halt_check = BRANCH_HALT_VOTED,2949	.hwcg_reg = 0xf084,2950	.hwcg_bit = 1,2951	.clkr = {2952		.enable_reg = 0xf084,2953		.enable_mask = BIT(0),2954		.hw.init = &(const struct clk_init_data) {2955			.name = "gcc_cfg_noc_usb3_prim_axi_clk",2956			.parent_hws = (const struct clk_hw*[]){2957				&gcc_usb30_prim_master_clk_src.clkr.hw,2958			},2959			.num_parents = 1,2960			.flags = CLK_SET_RATE_PARENT,2961			.ops = &clk_branch2_ops,2962		},2963	},2964};2965 2966static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {2967	.halt_reg = 0x10084,2968	.halt_check = BRANCH_HALT_VOTED,2969	.hwcg_reg = 0x10084,2970	.hwcg_bit = 1,2971	.clkr = {2972		.enable_reg = 0x10084,2973		.enable_mask = BIT(0),2974		.hw.init = &(const struct clk_init_data) {2975			.name = "gcc_cfg_noc_usb3_sec_axi_clk",2976			.parent_hws = (const struct clk_hw*[]){2977				&gcc_usb30_sec_master_clk_src.clkr.hw,2978			},2979			.num_parents = 1,2980			.flags = CLK_SET_RATE_PARENT,2981			.ops = &clk_branch2_ops,2982		},2983	},2984};2985 2986static struct clk_branch gcc_cnoc_pcie0_tunnel_clk = {2987	.halt_reg = 0xa4074,2988	.halt_check = BRANCH_HALT_VOTED,2989	.clkr = {2990		.enable_reg = 0x52020,2991		.enable_mask = BIT(8),2992		.hw.init = &(const struct clk_init_data) {2993			.name = "gcc_cnoc_pcie0_tunnel_clk",2994			.ops = &clk_branch2_ops,2995		},2996	},2997};2998 2999static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {3000	.halt_reg = 0x8d074,3001	.halt_check = BRANCH_HALT_VOTED,3002	.clkr = {3003		.enable_reg = 0x52020,3004		.enable_mask = BIT(9),3005		.hw.init = &(const struct clk_init_data) {3006			.name = "gcc_cnoc_pcie1_tunnel_clk",3007			.ops = &clk_branch2_ops,3008		},3009	},3010};3011 3012static struct clk_branch gcc_cnoc_pcie4_qx_clk = {3013	.halt_reg = 0x6b084,3014	.halt_check = BRANCH_HALT_VOTED,3015	.hwcg_reg = 0x6b084,3016	.hwcg_bit = 1,3017	.clkr = {3018		.enable_reg = 0x52020,3019		.enable_mask = BIT(10),3020		.hw.init = &(const struct clk_init_data) {3021			.name = "gcc_cnoc_pcie4_qx_clk",3022			.ops = &clk_branch2_ops,3023		},3024	},3025};3026 3027static struct clk_branch gcc_ddrss_gpu_axi_clk = {3028	.halt_reg = 0x7115c,3029	.halt_check = BRANCH_HALT_SKIP,3030	.hwcg_reg = 0x7115c,3031	.hwcg_bit = 1,3032	.clkr = {3033		.enable_reg = 0x7115c,3034		.enable_mask = BIT(0),3035		.hw.init = &(const struct clk_init_data) {3036			.name = "gcc_ddrss_gpu_axi_clk",3037			.ops = &clk_branch2_aon_ops,3038		},3039	},3040};3041 3042static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {3043	.halt_reg = 0xa602c,3044	.halt_check = BRANCH_HALT_SKIP,3045	.hwcg_reg = 0xa602c,3046	.hwcg_bit = 1,3047	.clkr = {3048		.enable_reg = 0x52000,3049		.enable_mask = BIT(19),3050		.hw.init = &(const struct clk_init_data) {3051			.name = "gcc_ddrss_pcie_sf_tbu_clk",3052			.ops = &clk_branch2_ops,3053		},3054	},3055};3056 3057static struct clk_branch gcc_disp1_hf_axi_clk = {3058	.halt_reg = 0xbb010,3059	.halt_check = BRANCH_HALT_SKIP,3060	.hwcg_reg = 0xbb010,3061	.hwcg_bit = 1,3062	.clkr = {3063		.enable_reg = 0xbb010,3064		.enable_mask = BIT(0),3065		.hw.init = &(const struct clk_init_data) {3066			.name = "gcc_disp1_hf_axi_clk",3067			.ops = &clk_branch2_ops,3068		},3069	},3070};3071 3072static struct clk_branch gcc_disp1_sf_axi_clk = {3073	.halt_reg = 0xbb018,3074	.halt_check = BRANCH_HALT_SKIP,3075	.hwcg_reg = 0xbb018,3076	.hwcg_bit = 1,3077	.clkr = {3078		.enable_reg = 0xbb018,3079		.enable_mask = BIT(0),3080		.hw.init = &(const struct clk_init_data) {3081			.name = "gcc_disp1_sf_axi_clk",3082			.ops = &clk_branch2_ops,3083		},3084	},3085};3086 3087static struct clk_branch gcc_disp1_throttle_nrt_axi_clk = {3088	.halt_reg = 0xbb024,3089	.halt_check = BRANCH_HALT_SKIP,3090	.hwcg_reg = 0xbb024,3091	.hwcg_bit = 1,3092	.clkr = {3093		.enable_reg = 0xbb024,3094		.enable_mask = BIT(0),3095		.hw.init = &(const struct clk_init_data) {3096			.name = "gcc_disp1_throttle_nrt_axi_clk",3097			.ops = &clk_branch2_ops,3098		},3099	},3100};3101 3102static struct clk_branch gcc_disp1_throttle_rt_axi_clk = {3103	.halt_reg = 0xbb020,3104	.halt_check = BRANCH_HALT_SKIP,3105	.hwcg_reg = 0xbb020,3106	.hwcg_bit = 1,3107	.clkr = {3108		.enable_reg = 0xbb020,3109		.enable_mask = BIT(0),3110		.hw.init = &(const struct clk_init_data) {3111			.name = "gcc_disp1_throttle_rt_axi_clk",3112			.ops = &clk_branch2_ops,3113		},3114	},3115};3116 3117static struct clk_branch gcc_disp_hf_axi_clk = {3118	.halt_reg = 0x27010,3119	.halt_check = BRANCH_HALT_SKIP,3120	.hwcg_reg = 0x27010,3121	.hwcg_bit = 1,3122	.clkr = {3123		.enable_reg = 0x27010,3124		.enable_mask = BIT(0),3125		.hw.init = &(const struct clk_init_data) {3126			.name = "gcc_disp_hf_axi_clk",3127			.ops = &clk_branch2_ops,3128		},3129	},3130};3131 3132static struct clk_branch gcc_disp_sf_axi_clk = {3133	.halt_reg = 0x27018,3134	.halt_check = BRANCH_HALT_SKIP,3135	.hwcg_reg = 0x27018,3136	.hwcg_bit = 1,3137	.clkr = {3138		.enable_reg = 0x27018,3139		.enable_mask = BIT(0),3140		.hw.init = &(const struct clk_init_data) {3141			.name = "gcc_disp_sf_axi_clk",3142			.ops = &clk_branch2_ops,3143		},3144	},3145};3146 3147static struct clk_branch gcc_disp_throttle_nrt_axi_clk = {3148	.halt_reg = 0x27024,3149	.halt_check = BRANCH_HALT_SKIP,3150	.hwcg_reg = 0x27024,3151	.hwcg_bit = 1,3152	.clkr = {3153		.enable_reg = 0x27024,3154		.enable_mask = BIT(0),3155		.hw.init = &(const struct clk_init_data) {3156			.name = "gcc_disp_throttle_nrt_axi_clk",3157			.ops = &clk_branch2_ops,3158		},3159	},3160};3161 3162static struct clk_branch gcc_disp_throttle_rt_axi_clk = {3163	.halt_reg = 0x27020,3164	.halt_check = BRANCH_HALT_SKIP,3165	.hwcg_reg = 0x27020,3166	.hwcg_bit = 1,3167	.clkr = {3168		.enable_reg = 0x27020,3169		.enable_mask = BIT(0),3170		.hw.init = &(const struct clk_init_data) {3171			.name = "gcc_disp_throttle_rt_axi_clk",3172			.ops = &clk_branch2_ops,3173		},3174	},3175};3176 3177static struct clk_branch gcc_emac0_axi_clk = {3178	.halt_reg = 0xaa010,3179	.halt_check = BRANCH_HALT_VOTED,3180	.hwcg_reg = 0xaa010,3181	.hwcg_bit = 1,3182	.clkr = {3183		.enable_reg = 0xaa010,3184		.enable_mask = BIT(0),3185		.hw.init = &(const struct clk_init_data) {3186			.name = "gcc_emac0_axi_clk",3187			.ops = &clk_branch2_ops,3188		},3189	},3190};3191 3192static struct clk_branch gcc_emac0_ptp_clk = {3193	.halt_reg = 0xaa01c,3194	.halt_check = BRANCH_HALT,3195	.clkr = {3196		.enable_reg = 0xaa01c,3197		.enable_mask = BIT(0),3198		.hw.init = &(const struct clk_init_data) {3199			.name = "gcc_emac0_ptp_clk",3200			.parent_hws = (const struct clk_hw*[]){3201				&gcc_emac0_ptp_clk_src.clkr.hw,3202			},3203			.num_parents = 1,3204			.flags = CLK_SET_RATE_PARENT,3205			.ops = &clk_branch2_ops,3206		},3207	},3208};3209 3210static struct clk_branch gcc_emac0_rgmii_clk = {3211	.halt_reg = 0xaa038,3212	.halt_check = BRANCH_HALT,3213	.clkr = {3214		.enable_reg = 0xaa038,3215		.enable_mask = BIT(0),3216		.hw.init = &(const struct clk_init_data) {3217			.name = "gcc_emac0_rgmii_clk",3218			.parent_hws = (const struct clk_hw*[]){3219				&gcc_emac0_rgmii_clk_src.clkr.hw,3220			},3221			.num_parents = 1,3222			.flags = CLK_SET_RATE_PARENT,3223			.ops = &clk_branch2_ops,3224		},3225	},3226};3227 3228static struct clk_branch gcc_emac0_slv_ahb_clk = {3229	.halt_reg = 0xaa018,3230	.halt_check = BRANCH_HALT_VOTED,3231	.hwcg_reg = 0xaa018,3232	.hwcg_bit = 1,3233	.clkr = {3234		.enable_reg = 0xaa018,3235		.enable_mask = BIT(0),3236		.hw.init = &(const struct clk_init_data) {3237			.name = "gcc_emac0_slv_ahb_clk",3238			.ops = &clk_branch2_ops,3239		},3240	},3241};3242 3243static struct clk_branch gcc_emac1_axi_clk = {3244	.halt_reg = 0xba010,3245	.halt_check = BRANCH_HALT_VOTED,3246	.hwcg_reg = 0xba010,3247	.hwcg_bit = 1,3248	.clkr = {3249		.enable_reg = 0xba010,3250		.enable_mask = BIT(0),3251		.hw.init = &(const struct clk_init_data) {3252			.name = "gcc_emac1_axi_clk",3253			.ops = &clk_branch2_ops,3254		},3255	},3256};3257 3258static struct clk_branch gcc_emac1_ptp_clk = {3259	.halt_reg = 0xba01c,3260	.halt_check = BRANCH_HALT,3261	.clkr = {3262		.enable_reg = 0xba01c,3263		.enable_mask = BIT(0),3264		.hw.init = &(const struct clk_init_data) {3265			.name = "gcc_emac1_ptp_clk",3266			.parent_hws = (const struct clk_hw*[]){3267				&gcc_emac1_ptp_clk_src.clkr.hw,3268			},3269			.num_parents = 1,3270			.flags = CLK_SET_RATE_PARENT,3271			.ops = &clk_branch2_ops,3272		},3273	},3274};3275 3276static struct clk_branch gcc_emac1_rgmii_clk = {3277	.halt_reg = 0xba038,3278	.halt_check = BRANCH_HALT,3279	.clkr = {3280		.enable_reg = 0xba038,3281		.enable_mask = BIT(0),3282		.hw.init = &(const struct clk_init_data) {3283			.name = "gcc_emac1_rgmii_clk",3284			.parent_hws = (const struct clk_hw*[]){3285				&gcc_emac1_rgmii_clk_src.clkr.hw,3286			},3287			.num_parents = 1,3288			.flags = CLK_SET_RATE_PARENT,3289			.ops = &clk_branch2_ops,3290		},3291	},3292};3293 3294static struct clk_branch gcc_emac1_slv_ahb_clk = {3295	.halt_reg = 0xba018,3296	.halt_check = BRANCH_HALT_VOTED,3297	.hwcg_reg = 0xba018,3298	.hwcg_bit = 1,3299	.clkr = {3300		.enable_reg = 0xba018,3301		.enable_mask = BIT(0),3302		.hw.init = &(const struct clk_init_data) {3303			.name = "gcc_emac1_slv_ahb_clk",3304			.ops = &clk_branch2_ops,3305		},3306	},3307};3308 3309static struct clk_branch gcc_gp1_clk = {3310	.halt_reg = 0x64000,3311	.halt_check = BRANCH_HALT,3312	.clkr = {3313		.enable_reg = 0x64000,3314		.enable_mask = BIT(0),3315		.hw.init = &(const struct clk_init_data) {3316			.name = "gcc_gp1_clk",3317			.parent_hws = (const struct clk_hw*[]){3318				&gcc_gp1_clk_src.clkr.hw,3319			},3320			.num_parents = 1,3321			.flags = CLK_SET_RATE_PARENT,3322			.ops = &clk_branch2_ops,3323		},3324	},3325};3326 3327static struct clk_branch gcc_gp2_clk = {3328	.halt_reg = 0x65000,3329	.halt_check = BRANCH_HALT,3330	.clkr = {3331		.enable_reg = 0x65000,3332		.enable_mask = BIT(0),3333		.hw.init = &(const struct clk_init_data) {3334			.name = "gcc_gp2_clk",3335			.parent_hws = (const struct clk_hw*[]){3336				&gcc_gp2_clk_src.clkr.hw,3337			},3338			.num_parents = 1,3339			.flags = CLK_SET_RATE_PARENT,3340			.ops = &clk_branch2_ops,3341		},3342	},3343};3344 3345static struct clk_branch gcc_gp3_clk = {3346	.halt_reg = 0x66000,3347	.halt_check = BRANCH_HALT,3348	.clkr = {3349		.enable_reg = 0x66000,3350		.enable_mask = BIT(0),3351		.hw.init = &(const struct clk_init_data) {3352			.name = "gcc_gp3_clk",3353			.parent_hws = (const struct clk_hw*[]){3354				&gcc_gp3_clk_src.clkr.hw,3355			},3356			.num_parents = 1,3357			.flags = CLK_SET_RATE_PARENT,3358			.ops = &clk_branch2_ops,3359		},3360	},3361};3362 3363static struct clk_branch gcc_gp4_clk = {3364	.halt_reg = 0xc2000,3365	.halt_check = BRANCH_HALT,3366	.clkr = {3367		.enable_reg = 0xc2000,3368		.enable_mask = BIT(0),3369		.hw.init = &(const struct clk_init_data) {3370			.name = "gcc_gp4_clk",3371			.parent_hws = (const struct clk_hw*[]){3372				&gcc_gp4_clk_src.clkr.hw,3373			},3374			.num_parents = 1,3375			.flags = CLK_SET_RATE_PARENT,3376			.ops = &clk_branch2_ops,3377		},3378	},3379};3380 3381static struct clk_branch gcc_gp5_clk = {3382	.halt_reg = 0xc3000,3383	.halt_check = BRANCH_HALT,3384	.clkr = {3385		.enable_reg = 0xc3000,3386		.enable_mask = BIT(0),3387		.hw.init = &(const struct clk_init_data) {3388			.name = "gcc_gp5_clk",3389			.parent_hws = (const struct clk_hw*[]){3390				&gcc_gp5_clk_src.clkr.hw,3391			},3392			.num_parents = 1,3393			.flags = CLK_SET_RATE_PARENT,3394			.ops = &clk_branch2_ops,3395		},3396	},3397};3398 3399static struct clk_branch gcc_gpu_gpll0_clk_src = {3400	.halt_check = BRANCH_HALT_DELAY,3401	.clkr = {3402		.enable_reg = 0x52000,3403		.enable_mask = BIT(15),3404		.hw.init = &(const struct clk_init_data) {3405			.name = "gcc_gpu_gpll0_clk_src",3406			.parent_hws = (const struct clk_hw*[]){3407				&gcc_gpll0.clkr.hw,3408			},3409			.num_parents = 1,3410			.flags = CLK_SET_RATE_PARENT,3411			.ops = &clk_branch2_ops,3412		},3413	},3414};3415 3416static struct clk_branch gcc_gpu_gpll0_div_clk_src = {3417	.halt_check = BRANCH_HALT_DELAY,3418	.clkr = {3419		.enable_reg = 0x52000,3420		.enable_mask = BIT(16),3421		.hw.init = &(const struct clk_init_data) {3422			.name = "gcc_gpu_gpll0_div_clk_src",3423			.parent_hws = (const struct clk_hw*[]){3424				&gcc_gpll0_out_even.clkr.hw,3425			},3426			.num_parents = 1,3427			.flags = CLK_SET_RATE_PARENT,3428			.ops = &clk_branch2_ops,3429		},3430	},3431};3432 3433static struct clk_branch gcc_gpu_iref_en = {3434	.halt_reg = 0x8c014,3435	.halt_check = BRANCH_HALT,3436	.clkr = {3437		.enable_reg = 0x8c014,3438		.enable_mask = BIT(0),3439		.hw.init = &(const struct clk_init_data) {3440			.name = "gcc_gpu_iref_en",3441			.ops = &clk_branch2_ops,3442		},3443	},3444};3445 3446static struct clk_branch gcc_gpu_memnoc_gfx_clk = {3447	.halt_reg = 0x71010,3448	.halt_check = BRANCH_HALT_VOTED,3449	.hwcg_reg = 0x71010,3450	.hwcg_bit = 1,3451	.clkr = {3452		.enable_reg = 0x71010,3453		.enable_mask = BIT(0),3454		.hw.init = &(const struct clk_init_data) {3455			.name = "gcc_gpu_memnoc_gfx_clk",3456			.ops = &clk_branch2_aon_ops,3457		},3458	},3459};3460 3461static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {3462	.halt_reg = 0x71020,3463	.halt_check = BRANCH_HALT,3464	.clkr = {3465		.enable_reg = 0x71020,3466		.enable_mask = BIT(0),3467		.hw.init = &(const struct clk_init_data) {3468			.name = "gcc_gpu_snoc_dvm_gfx_clk",3469			.ops = &clk_branch2_aon_ops,3470		},3471	},3472};3473 3474static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {3475	.halt_reg = 0x71008,3476	.halt_check = BRANCH_HALT_VOTED,3477	.hwcg_reg = 0x71008,3478	.hwcg_bit = 1,3479	.clkr = {3480		.enable_reg = 0x71008,3481		.enable_mask = BIT(0),3482		.hw.init = &(const struct clk_init_data) {3483			.name = "gcc_gpu_tcu_throttle_ahb_clk",3484			.ops = &clk_branch2_ops,3485		},3486	},3487};3488 3489static struct clk_branch gcc_gpu_tcu_throttle_clk = {3490	.halt_reg = 0x71018,3491	.halt_check = BRANCH_HALT_VOTED,3492	.hwcg_reg = 0x71018,3493	.hwcg_bit = 1,3494	.clkr = {3495		.enable_reg = 0x71018,3496		.enable_mask = BIT(0),3497		.hw.init = &(const struct clk_init_data) {3498			.name = "gcc_gpu_tcu_throttle_clk",3499			.ops = &clk_branch2_ops,3500		},3501	},3502};3503 3504static struct clk_branch gcc_pcie0_phy_rchng_clk = {3505	.halt_reg = 0xa4038,3506	.halt_check = BRANCH_HALT_VOTED,3507	.clkr = {3508		.enable_reg = 0x52018,3509		.enable_mask = BIT(11),3510		.hw.init = &(const struct clk_init_data) {3511			.name = "gcc_pcie0_phy_rchng_clk",3512			.parent_hws = (const struct clk_hw*[]){3513				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,3514			},3515			.num_parents = 1,3516			.flags = CLK_SET_RATE_PARENT,3517			.ops = &clk_branch2_ops,3518		},3519	},3520};3521 3522static struct clk_branch gcc_pcie1_phy_rchng_clk = {3523	.halt_reg = 0x8d038,3524	.halt_check = BRANCH_HALT_VOTED,3525	.clkr = {3526		.enable_reg = 0x52000,3527		.enable_mask = BIT(23),3528		.hw.init = &(const struct clk_init_data) {3529			.name = "gcc_pcie1_phy_rchng_clk",3530			.parent_hws = (const struct clk_hw*[]){3531				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,3532			},3533			.num_parents = 1,3534			.flags = CLK_SET_RATE_PARENT,3535			.ops = &clk_branch2_ops,3536		},3537	},3538};3539 3540static struct clk_branch gcc_pcie2a_phy_rchng_clk = {3541	.halt_reg = 0x9d040,3542	.halt_check = BRANCH_HALT_VOTED,3543	.clkr = {3544		.enable_reg = 0x52010,3545		.enable_mask = BIT(15),3546		.hw.init = &(const struct clk_init_data) {3547			.name = "gcc_pcie2a_phy_rchng_clk",3548			.parent_hws = (const struct clk_hw*[]){3549				&gcc_pcie_2a_phy_rchng_clk_src.clkr.hw,3550			},3551			.num_parents = 1,3552			.flags = CLK_SET_RATE_PARENT,3553			.ops = &clk_branch2_ops,3554		},3555	},3556};3557 3558static struct clk_branch gcc_pcie2b_phy_rchng_clk = {3559	.halt_reg = 0x9e040,3560	.halt_check = BRANCH_HALT_VOTED,3561	.clkr = {3562		.enable_reg = 0x52010,3563		.enable_mask = BIT(22),3564		.hw.init = &(const struct clk_init_data) {3565			.name = "gcc_pcie2b_phy_rchng_clk",3566			.parent_hws = (const struct clk_hw*[]){3567				&gcc_pcie_2b_phy_rchng_clk_src.clkr.hw,3568			},3569			.num_parents = 1,3570			.flags = CLK_SET_RATE_PARENT,3571			.ops = &clk_branch2_ops,3572		},3573	},3574};3575 3576static struct clk_branch gcc_pcie3a_phy_rchng_clk = {3577	.halt_reg = 0xa0040,3578	.halt_check = BRANCH_HALT_VOTED,3579	.clkr = {3580		.enable_reg = 0x52010,3581		.enable_mask = BIT(29),3582		.hw.init = &(const struct clk_init_data) {3583			.name = "gcc_pcie3a_phy_rchng_clk",3584			.parent_hws = (const struct clk_hw*[]){3585				&gcc_pcie_3a_phy_rchng_clk_src.clkr.hw,3586			},3587			.num_parents = 1,3588			.flags = CLK_SET_RATE_PARENT,3589			.ops = &clk_branch2_ops,3590		},3591	},3592};3593 3594static struct clk_branch gcc_pcie3b_phy_rchng_clk = {3595	.halt_reg = 0xa2040,3596	.halt_check = BRANCH_HALT_VOTED,3597	.clkr = {3598		.enable_reg = 0x52018,3599		.enable_mask = BIT(4),3600		.hw.init = &(const struct clk_init_data) {3601			.name = "gcc_pcie3b_phy_rchng_clk",3602			.parent_hws = (const struct clk_hw*[]){3603				&gcc_pcie_3b_phy_rchng_clk_src.clkr.hw,3604			},3605			.num_parents = 1,3606			.flags = CLK_SET_RATE_PARENT,3607			.ops = &clk_branch2_ops,3608		},3609	},3610};3611 3612static struct clk_branch gcc_pcie4_phy_rchng_clk = {3613	.halt_reg = 0x6b040,3614	.halt_check = BRANCH_HALT_VOTED,3615	.clkr = {3616		.enable_reg = 0x52000,3617		.enable_mask = BIT(22),3618		.hw.init = &(const struct clk_init_data) {3619			.name = "gcc_pcie4_phy_rchng_clk",3620			.parent_hws = (const struct clk_hw*[]){3621				&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,3622			},3623			.num_parents = 1,3624			.flags = CLK_SET_RATE_PARENT,3625			.ops = &clk_branch2_ops,3626		},3627	},3628};3629 3630static struct clk_branch gcc_pcie_0_aux_clk = {3631	.halt_reg = 0xa4028,3632	.halt_check = BRANCH_HALT_VOTED,3633	.clkr = {3634		.enable_reg = 0x52018,3635		.enable_mask = BIT(9),3636		.hw.init = &(const struct clk_init_data) {3637			.name = "gcc_pcie_0_aux_clk",3638			.parent_hws = (const struct clk_hw*[]){3639				&gcc_pcie_0_aux_clk_src.clkr.hw,3640			},3641			.num_parents = 1,3642			.flags = CLK_SET_RATE_PARENT,3643			.ops = &clk_branch2_ops,3644		},3645	},3646};3647 3648static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {3649	.halt_reg = 0xa4024,3650	.halt_check = BRANCH_HALT_VOTED,3651	.hwcg_reg = 0xa4024,3652	.hwcg_bit = 1,3653	.clkr = {3654		.enable_reg = 0x52018,3655		.enable_mask = BIT(8),3656		.hw.init = &(const struct clk_init_data) {3657			.name = "gcc_pcie_0_cfg_ahb_clk",3658			.ops = &clk_branch2_ops,3659		},3660	},3661};3662 3663static struct clk_branch gcc_pcie_0_mstr_axi_clk = {3664	.halt_reg = 0xa401c,3665	.halt_check = BRANCH_HALT_SKIP,3666	.hwcg_reg = 0xa401c,3667	.hwcg_bit = 1,3668	.clkr = {3669		.enable_reg = 0x52018,3670		.enable_mask = BIT(7),3671		.hw.init = &(const struct clk_init_data) {3672			.name = "gcc_pcie_0_mstr_axi_clk",3673			.ops = &clk_branch2_ops,3674		},3675	},3676};3677 3678static struct clk_branch gcc_pcie_0_pipe_clk = {3679	.halt_reg = 0xa4030,3680	.halt_check = BRANCH_HALT_SKIP,3681	.clkr = {3682		.enable_reg = 0x52018,3683		.enable_mask = BIT(10),3684		.hw.init = &(const struct clk_init_data) {3685			.name = "gcc_pcie_0_pipe_clk",3686			.parent_hws = (const struct clk_hw*[]){3687				&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,3688			},3689			.num_parents = 1,3690			.flags = CLK_SET_RATE_PARENT,3691			.ops = &clk_branch2_ops,3692		},3693	},3694};3695 3696static struct clk_branch gcc_pcie_0_slv_axi_clk = {3697	.halt_reg = 0xa4014,3698	.halt_check = BRANCH_HALT_VOTED,3699	.hwcg_reg = 0xa4014,3700	.hwcg_bit = 1,3701	.clkr = {3702		.enable_reg = 0x52018,3703		.enable_mask = BIT(6),3704		.hw.init = &(const struct clk_init_data) {3705			.name = "gcc_pcie_0_slv_axi_clk",3706			.ops = &clk_branch2_ops,3707		},3708	},3709};3710 3711static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {3712	.halt_reg = 0xa4010,3713	.halt_check = BRANCH_HALT_VOTED,3714	.clkr = {3715		.enable_reg = 0x52018,3716		.enable_mask = BIT(5),3717		.hw.init = &(const struct clk_init_data) {3718			.name = "gcc_pcie_0_slv_q2a_axi_clk",3719			.ops = &clk_branch2_ops,3720		},3721	},3722};3723 3724static struct clk_branch gcc_pcie_1_aux_clk = {3725	.halt_reg = 0x8d028,3726	.halt_check = BRANCH_HALT_VOTED,3727	.clkr = {3728		.enable_reg = 0x52000,3729		.enable_mask = BIT(29),3730		.hw.init = &(const struct clk_init_data) {3731			.name = "gcc_pcie_1_aux_clk",3732			.parent_hws = (const struct clk_hw*[]){3733				&gcc_pcie_1_aux_clk_src.clkr.hw,3734			},3735			.num_parents = 1,3736			.flags = CLK_SET_RATE_PARENT,3737			.ops = &clk_branch2_ops,3738		},3739	},3740};3741 3742static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {3743	.halt_reg = 0x8d024,3744	.halt_check = BRANCH_HALT_VOTED,3745	.hwcg_reg = 0x8d024,3746	.hwcg_bit = 1,3747	.clkr = {3748		.enable_reg = 0x52000,3749		.enable_mask = BIT(28),3750		.hw.init = &(const struct clk_init_data) {3751			.name = "gcc_pcie_1_cfg_ahb_clk",3752			.ops = &clk_branch2_ops,3753		},3754	},3755};3756 3757static struct clk_branch gcc_pcie_1_mstr_axi_clk = {3758	.halt_reg = 0x8d01c,3759	.halt_check = BRANCH_HALT_SKIP,3760	.hwcg_reg = 0x8d01c,3761	.hwcg_bit = 1,3762	.clkr = {3763		.enable_reg = 0x52000,3764		.enable_mask = BIT(27),3765		.hw.init = &(const struct clk_init_data) {3766			.name = "gcc_pcie_1_mstr_axi_clk",3767			.ops = &clk_branch2_ops,3768		},3769	},3770};3771 3772static struct clk_branch gcc_pcie_1_pipe_clk = {3773	.halt_reg = 0x8d030,3774	.halt_check = BRANCH_HALT_SKIP,3775	.clkr = {3776		.enable_reg = 0x52000,3777		.enable_mask = BIT(30),3778		.hw.init = &(const struct clk_init_data) {3779			.name = "gcc_pcie_1_pipe_clk",3780			.parent_hws = (const struct clk_hw*[]){3781				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,3782			},3783			.num_parents = 1,3784			.flags = CLK_SET_RATE_PARENT,3785			.ops = &clk_branch2_ops,3786		},3787	},3788};3789 3790static struct clk_branch gcc_pcie_1_slv_axi_clk = {3791	.halt_reg = 0x8d014,3792	.halt_check = BRANCH_HALT_VOTED,3793	.hwcg_reg = 0x8d014,3794	.hwcg_bit = 1,3795	.clkr = {3796		.enable_reg = 0x52000,3797		.enable_mask = BIT(26),3798		.hw.init = &(const struct clk_init_data) {3799			.name = "gcc_pcie_1_slv_axi_clk",3800			.ops = &clk_branch2_ops,3801		},3802	},3803};3804 3805static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {3806	.halt_reg = 0x8d010,3807	.halt_check = BRANCH_HALT_VOTED,3808	.clkr = {3809		.enable_reg = 0x52000,3810		.enable_mask = BIT(25),3811		.hw.init = &(const struct clk_init_data) {3812			.name = "gcc_pcie_1_slv_q2a_axi_clk",3813			.ops = &clk_branch2_ops,3814		},3815	},3816};3817 3818static struct clk_branch gcc_pcie_2a2b_clkref_clk = {3819	.halt_reg = 0x8c034,3820	.halt_check = BRANCH_HALT,3821	.clkr = {3822		.enable_reg = 0x8c034,3823		.enable_mask = BIT(0),3824		.hw.init = &(const struct clk_init_data) {3825			.name = "gcc_pcie_2a2b_clkref_clk",3826			.ops = &clk_branch2_ops,3827		},3828	},3829};3830 3831static struct clk_branch gcc_pcie_2a_aux_clk = {3832	.halt_reg = 0x9d028,3833	.halt_check = BRANCH_HALT_VOTED,3834	.clkr = {3835		.enable_reg = 0x52010,3836		.enable_mask = BIT(13),3837		.hw.init = &(const struct clk_init_data) {3838			.name = "gcc_pcie_2a_aux_clk",3839			.parent_hws = (const struct clk_hw*[]){3840				&gcc_pcie_2a_aux_clk_src.clkr.hw,3841			},3842			.num_parents = 1,3843			.flags = CLK_SET_RATE_PARENT,3844			.ops = &clk_branch2_ops,3845		},3846	},3847};3848 3849static struct clk_branch gcc_pcie_2a_cfg_ahb_clk = {3850	.halt_reg = 0x9d024,3851	.halt_check = BRANCH_HALT_VOTED,3852	.hwcg_reg = 0x9d024,3853	.hwcg_bit = 1,3854	.clkr = {3855		.enable_reg = 0x52010,3856		.enable_mask = BIT(12),3857		.hw.init = &(const struct clk_init_data) {3858			.name = "gcc_pcie_2a_cfg_ahb_clk",3859			.ops = &clk_branch2_ops,3860		},3861	},3862};3863 3864static struct clk_branch gcc_pcie_2a_mstr_axi_clk = {3865	.halt_reg = 0x9d01c,3866	.halt_check = BRANCH_HALT_SKIP,3867	.hwcg_reg = 0x9d01c,3868	.hwcg_bit = 1,3869	.clkr = {3870		.enable_reg = 0x52010,3871		.enable_mask = BIT(11),3872		.hw.init = &(const struct clk_init_data) {3873			.name = "gcc_pcie_2a_mstr_axi_clk",3874			.ops = &clk_branch2_ops,3875		},3876	},3877};3878 3879static struct clk_branch gcc_pcie_2a_pipe_clk = {3880	.halt_reg = 0x9d030,3881	.halt_check = BRANCH_HALT_SKIP,3882	.clkr = {3883		.enable_reg = 0x52010,3884		.enable_mask = BIT(14),3885		.hw.init = &(const struct clk_init_data) {3886			.name = "gcc_pcie_2a_pipe_clk",3887			.parent_hws = (const struct clk_hw*[]){3888				&gcc_pcie_2a_pipe_clk_src.clkr.hw,3889			},3890			.num_parents = 1,3891			.flags = CLK_SET_RATE_PARENT,3892			.ops = &clk_branch2_ops,3893		},3894	},3895};3896 3897static struct clk_branch gcc_pcie_2a_pipediv2_clk = {3898	.halt_reg = 0x9d038,3899	.halt_check = BRANCH_HALT_SKIP,3900	.clkr = {3901		.enable_reg = 0x52018,3902		.enable_mask = BIT(22),3903		.hw.init = &(const struct clk_init_data) {3904			.name = "gcc_pcie_2a_pipediv2_clk",3905			.parent_hws = (const struct clk_hw*[]){3906				&gcc_pcie_2a_pipe_div_clk_src.clkr.hw,3907			},3908			.num_parents = 1,3909			.flags = CLK_SET_RATE_PARENT,3910			.ops = &clk_branch2_ops,3911		},3912	},3913};3914 3915static struct clk_branch gcc_pcie_2a_slv_axi_clk = {3916	.halt_reg = 0x9d014,3917	.halt_check = BRANCH_HALT_VOTED,3918	.hwcg_reg = 0x9d014,3919	.hwcg_bit = 1,3920	.clkr = {3921		.enable_reg = 0x52010,3922		.enable_mask = BIT(10),3923		.hw.init = &(const struct clk_init_data) {3924			.name = "gcc_pcie_2a_slv_axi_clk",3925			.ops = &clk_branch2_ops,3926		},3927	},3928};3929 3930static struct clk_branch gcc_pcie_2a_slv_q2a_axi_clk = {3931	.halt_reg = 0x9d010,3932	.halt_check = BRANCH_HALT_VOTED,3933	.clkr = {3934		.enable_reg = 0x52018,3935		.enable_mask = BIT(12),3936		.hw.init = &(const struct clk_init_data) {3937			.name = "gcc_pcie_2a_slv_q2a_axi_clk",3938			.ops = &clk_branch2_ops,3939		},3940	},3941};3942 3943static struct clk_branch gcc_pcie_2b_aux_clk = {3944	.halt_reg = 0x9e028,3945	.halt_check = BRANCH_HALT_VOTED,3946	.clkr = {3947		.enable_reg = 0x52010,3948		.enable_mask = BIT(20),3949		.hw.init = &(const struct clk_init_data) {3950			.name = "gcc_pcie_2b_aux_clk",3951			.parent_hws = (const struct clk_hw*[]){3952				&gcc_pcie_2b_aux_clk_src.clkr.hw,3953			},3954			.num_parents = 1,3955			.flags = CLK_SET_RATE_PARENT,3956			.ops = &clk_branch2_ops,3957		},3958	},3959};3960 3961static struct clk_branch gcc_pcie_2b_cfg_ahb_clk = {3962	.halt_reg = 0x9e024,3963	.halt_check = BRANCH_HALT_VOTED,3964	.hwcg_reg = 0x9e024,3965	.hwcg_bit = 1,3966	.clkr = {3967		.enable_reg = 0x52010,3968		.enable_mask = BIT(19),3969		.hw.init = &(const struct clk_init_data) {3970			.name = "gcc_pcie_2b_cfg_ahb_clk",3971			.ops = &clk_branch2_ops,3972		},3973	},3974};3975 3976static struct clk_branch gcc_pcie_2b_mstr_axi_clk = {3977	.halt_reg = 0x9e01c,3978	.halt_check = BRANCH_HALT_SKIP,3979	.hwcg_reg = 0x9e01c,3980	.hwcg_bit = 1,3981	.clkr = {3982		.enable_reg = 0x52010,3983		.enable_mask = BIT(18),3984		.hw.init = &(const struct clk_init_data) {3985			.name = "gcc_pcie_2b_mstr_axi_clk",3986			.ops = &clk_branch2_ops,3987		},3988	},3989};3990 3991static struct clk_branch gcc_pcie_2b_pipe_clk = {3992	.halt_reg = 0x9e030,3993	.halt_check = BRANCH_HALT_SKIP,3994	.clkr = {3995		.enable_reg = 0x52010,3996		.enable_mask = BIT(21),3997		.hw.init = &(const struct clk_init_data) {3998			.name = "gcc_pcie_2b_pipe_clk",3999			.parent_hws = (const struct clk_hw*[]){4000				&gcc_pcie_2b_pipe_clk_src.clkr.hw,4001			},4002			.num_parents = 1,4003			.flags = CLK_SET_RATE_PARENT,4004			.ops = &clk_branch2_ops,4005		},4006	},4007};4008 4009static struct clk_branch gcc_pcie_2b_pipediv2_clk = {4010	.halt_reg = 0x9e038,4011	.halt_check = BRANCH_HALT_SKIP,4012	.clkr = {4013		.enable_reg = 0x52018,4014		.enable_mask = BIT(23),4015		.hw.init = &(const struct clk_init_data) {4016			.name = "gcc_pcie_2b_pipediv2_clk",4017			.parent_hws = (const struct clk_hw*[]){4018				&gcc_pcie_2b_pipe_div_clk_src.clkr.hw,4019			},4020			.num_parents = 1,4021			.flags = CLK_SET_RATE_PARENT,4022			.ops = &clk_branch2_ops,4023		},4024	},4025};4026 4027static struct clk_branch gcc_pcie_2b_slv_axi_clk = {4028	.halt_reg = 0x9e014,4029	.halt_check = BRANCH_HALT_VOTED,4030	.hwcg_reg = 0x9e014,4031	.hwcg_bit = 1,4032	.clkr = {4033		.enable_reg = 0x52010,4034		.enable_mask = BIT(17),4035		.hw.init = &(const struct clk_init_data) {4036			.name = "gcc_pcie_2b_slv_axi_clk",4037			.ops = &clk_branch2_ops,4038		},4039	},4040};4041 4042static struct clk_branch gcc_pcie_2b_slv_q2a_axi_clk = {4043	.halt_reg = 0x9e010,4044	.halt_check = BRANCH_HALT_VOTED,4045	.clkr = {4046		.enable_reg = 0x52010,4047		.enable_mask = BIT(16),4048		.hw.init = &(const struct clk_init_data) {4049			.name = "gcc_pcie_2b_slv_q2a_axi_clk",4050			.ops = &clk_branch2_ops,4051		},4052	},4053};4054 4055static struct clk_branch gcc_pcie_3a3b_clkref_clk = {4056	.halt_reg = 0x8c038,4057	.halt_check = BRANCH_HALT,4058	.clkr = {4059		.enable_reg = 0x8c038,4060		.enable_mask = BIT(0),4061		.hw.init = &(const struct clk_init_data) {4062			.name = "gcc_pcie_3a3b_clkref_clk",4063			.ops = &clk_branch2_ops,4064		},4065	},4066};4067 4068static struct clk_branch gcc_pcie_3a_aux_clk = {4069	.halt_reg = 0xa0028,4070	.halt_check = BRANCH_HALT_VOTED,4071	.clkr = {4072		.enable_reg = 0x52010,4073		.enable_mask = BIT(27),4074		.hw.init = &(const struct clk_init_data) {4075			.name = "gcc_pcie_3a_aux_clk",4076			.parent_hws = (const struct clk_hw*[]){4077				&gcc_pcie_3a_aux_clk_src.clkr.hw,4078			},4079			.num_parents = 1,4080			.flags = CLK_SET_RATE_PARENT,4081			.ops = &clk_branch2_ops,4082		},4083	},4084};4085 4086static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = {4087	.halt_reg = 0xa0024,4088	.halt_check = BRANCH_HALT_VOTED,4089	.hwcg_reg = 0xa0024,4090	.hwcg_bit = 1,4091	.clkr = {4092		.enable_reg = 0x52010,4093		.enable_mask = BIT(26),4094		.hw.init = &(const struct clk_init_data) {4095			.name = "gcc_pcie_3a_cfg_ahb_clk",4096			.ops = &clk_branch2_ops,4097		},4098	},4099};4100 4101static struct clk_branch gcc_pcie_3a_mstr_axi_clk = {4102	.halt_reg = 0xa001c,4103	.halt_check = BRANCH_HALT_SKIP,4104	.hwcg_reg = 0xa001c,4105	.hwcg_bit = 1,4106	.clkr = {4107		.enable_reg = 0x52010,4108		.enable_mask = BIT(25),4109		.hw.init = &(const struct clk_init_data) {4110			.name = "gcc_pcie_3a_mstr_axi_clk",4111			.ops = &clk_branch2_ops,4112		},4113	},4114};4115 4116static struct clk_branch gcc_pcie_3a_pipe_clk = {4117	.halt_reg = 0xa0030,4118	.halt_check = BRANCH_HALT_SKIP,4119	.clkr = {4120		.enable_reg = 0x52010,4121		.enable_mask = BIT(28),4122		.hw.init = &(const struct clk_init_data) {4123			.name = "gcc_pcie_3a_pipe_clk",4124			.parent_hws = (const struct clk_hw*[]){4125				&gcc_pcie_3a_pipe_clk_src.clkr.hw,4126			},4127			.num_parents = 1,4128			.flags = CLK_SET_RATE_PARENT,4129			.ops = &clk_branch2_ops,4130		},4131	},4132};4133 4134static struct clk_branch gcc_pcie_3a_pipediv2_clk = {4135	.halt_reg = 0xa0038,4136	.halt_check = BRANCH_HALT_SKIP,4137	.clkr = {4138		.enable_reg = 0x52018,4139		.enable_mask = BIT(24),4140		.hw.init = &(const struct clk_init_data) {4141			.name = "gcc_pcie_3a_pipediv2_clk",4142			.parent_hws = (const struct clk_hw*[]){4143				&gcc_pcie_3a_pipe_div_clk_src.clkr.hw,4144			},4145			.num_parents = 1,4146			.flags = CLK_SET_RATE_PARENT,4147			.ops = &clk_branch2_ops,4148		},4149	},4150};4151 4152static struct clk_branch gcc_pcie_3a_slv_axi_clk = {4153	.halt_reg = 0xa0014,4154	.halt_check = BRANCH_HALT_VOTED,4155	.hwcg_reg = 0xa0014,4156	.hwcg_bit = 1,4157	.clkr = {4158		.enable_reg = 0x52010,4159		.enable_mask = BIT(24),4160		.hw.init = &(const struct clk_init_data) {4161			.name = "gcc_pcie_3a_slv_axi_clk",4162			.ops = &clk_branch2_ops,4163		},4164	},4165};4166 4167static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = {4168	.halt_reg = 0xa0010,4169	.halt_check = BRANCH_HALT_VOTED,4170	.clkr = {4171		.enable_reg = 0x52010,4172		.enable_mask = BIT(23),4173		.hw.init = &(const struct clk_init_data) {4174			.name = "gcc_pcie_3a_slv_q2a_axi_clk",4175			.ops = &clk_branch2_ops,4176		},4177	},4178};4179 4180static struct clk_branch gcc_pcie_3b_aux_clk = {4181	.halt_reg = 0xa2028,4182	.halt_check = BRANCH_HALT_VOTED,4183	.clkr = {4184		.enable_reg = 0x52018,4185		.enable_mask = BIT(2),4186		.hw.init = &(const struct clk_init_data) {4187			.name = "gcc_pcie_3b_aux_clk",4188			.parent_hws = (const struct clk_hw*[]){4189				&gcc_pcie_3b_aux_clk_src.clkr.hw,4190			},4191			.num_parents = 1,4192			.flags = CLK_SET_RATE_PARENT,4193			.ops = &clk_branch2_ops,4194		},4195	},4196};4197 4198static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = {4199	.halt_reg = 0xa2024,4200	.halt_check = BRANCH_HALT_VOTED,4201	.hwcg_reg = 0xa2024,4202	.hwcg_bit = 1,4203	.clkr = {4204		.enable_reg = 0x52018,4205		.enable_mask = BIT(1),4206		.hw.init = &(const struct clk_init_data) {4207			.name = "gcc_pcie_3b_cfg_ahb_clk",4208			.ops = &clk_branch2_ops,4209		},4210	},4211};4212 4213static struct clk_branch gcc_pcie_3b_mstr_axi_clk = {4214	.halt_reg = 0xa201c,4215	.halt_check = BRANCH_HALT_SKIP,4216	.hwcg_reg = 0xa201c,4217	.hwcg_bit = 1,4218	.clkr = {4219		.enable_reg = 0x52018,4220		.enable_mask = BIT(0),4221		.hw.init = &(const struct clk_init_data) {4222			.name = "gcc_pcie_3b_mstr_axi_clk",4223			.ops = &clk_branch2_ops,4224		},4225	},4226};4227 4228static struct clk_branch gcc_pcie_3b_pipe_clk = {4229	.halt_reg = 0xa2030,4230	.halt_check = BRANCH_HALT_SKIP,4231	.clkr = {4232		.enable_reg = 0x52018,4233		.enable_mask = BIT(3),4234		.hw.init = &(const struct clk_init_data) {4235			.name = "gcc_pcie_3b_pipe_clk",4236			.parent_hws = (const struct clk_hw*[]){4237				&gcc_pcie_3b_pipe_clk_src.clkr.hw,4238			},4239			.num_parents = 1,4240			.flags = CLK_SET_RATE_PARENT,4241			.ops = &clk_branch2_ops,4242		},4243	},4244};4245 4246static struct clk_branch gcc_pcie_3b_pipediv2_clk = {4247	.halt_reg = 0xa2038,4248	.halt_check = BRANCH_HALT_SKIP,4249	.clkr = {4250		.enable_reg = 0x52018,4251		.enable_mask = BIT(25),4252		.hw.init = &(const struct clk_init_data) {4253			.name = "gcc_pcie_3b_pipediv2_clk",4254			.parent_hws = (const struct clk_hw*[]){4255				&gcc_pcie_3b_pipe_div_clk_src.clkr.hw,4256			},4257			.num_parents = 1,4258			.flags = CLK_SET_RATE_PARENT,4259			.ops = &clk_branch2_ops,4260		},4261	},4262};4263 4264static struct clk_branch gcc_pcie_3b_slv_axi_clk = {4265	.halt_reg = 0xa2014,4266	.halt_check = BRANCH_HALT_VOTED,4267	.hwcg_reg = 0xa2014,4268	.hwcg_bit = 1,4269	.clkr = {4270		.enable_reg = 0x52010,4271		.enable_mask = BIT(31),4272		.hw.init = &(const struct clk_init_data) {4273			.name = "gcc_pcie_3b_slv_axi_clk",4274			.ops = &clk_branch2_ops,4275		},4276	},4277};4278 4279static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = {4280	.halt_reg = 0xa2010,4281	.halt_check = BRANCH_HALT_VOTED,4282	.clkr = {4283		.enable_reg = 0x52010,4284		.enable_mask = BIT(30),4285		.hw.init = &(const struct clk_init_data) {4286			.name = "gcc_pcie_3b_slv_q2a_axi_clk",4287			.ops = &clk_branch2_ops,4288		},4289	},4290};4291 4292static struct clk_branch gcc_pcie_4_aux_clk = {4293	.halt_reg = 0x6b028,4294	.halt_check = BRANCH_HALT_VOTED,4295	.clkr = {4296		.enable_reg = 0x52008,4297		.enable_mask = BIT(3),4298		.hw.init = &(const struct clk_init_data) {4299			.name = "gcc_pcie_4_aux_clk",4300			.parent_hws = (const struct clk_hw*[]){4301				&gcc_pcie_4_aux_clk_src.clkr.hw,4302			},4303			.num_parents = 1,4304			.flags = CLK_SET_RATE_PARENT,4305			.ops = &clk_branch2_ops,4306		},4307	},4308};4309 4310static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {4311	.halt_reg = 0x6b024,4312	.halt_check = BRANCH_HALT_VOTED,4313	.hwcg_reg = 0x6b024,4314	.hwcg_bit = 1,4315	.clkr = {4316		.enable_reg = 0x52008,4317		.enable_mask = BIT(2),4318		.hw.init = &(const struct clk_init_data) {4319			.name = "gcc_pcie_4_cfg_ahb_clk",4320			.ops = &clk_branch2_ops,4321		},4322	},4323};4324 4325static struct clk_branch gcc_pcie_4_clkref_clk = {4326	.halt_reg = 0x8c030,4327	.halt_check = BRANCH_HALT,4328	.clkr = {4329		.enable_reg = 0x8c030,4330		.enable_mask = BIT(0),4331		.hw.init = &(const struct clk_init_data) {4332			.name = "gcc_pcie_4_clkref_clk",4333			.ops = &clk_branch2_ops,4334		},4335	},4336};4337 4338static struct clk_branch gcc_pcie_4_mstr_axi_clk = {4339	.halt_reg = 0x6b01c,4340	.halt_check = BRANCH_HALT_SKIP,4341	.hwcg_reg = 0x6b01c,4342	.hwcg_bit = 1,4343	.clkr = {4344		.enable_reg = 0x52008,4345		.enable_mask = BIT(1),4346		.hw.init = &(const struct clk_init_data) {4347			.name = "gcc_pcie_4_mstr_axi_clk",4348			.ops = &clk_branch2_ops,4349		},4350	},4351};4352 4353static struct clk_branch gcc_pcie_4_pipe_clk = {4354	.halt_reg = 0x6b030,4355	.halt_check = BRANCH_HALT_SKIP,4356	.clkr = {4357		.enable_reg = 0x52008,4358		.enable_mask = BIT(4),4359		.hw.init = &(const struct clk_init_data) {4360			.name = "gcc_pcie_4_pipe_clk",4361			.parent_hws = (const struct clk_hw*[]){4362				&gcc_pcie_4_pipe_clk_src.clkr.hw,4363			},4364			.num_parents = 1,4365			.flags = CLK_SET_RATE_PARENT,4366			.ops = &clk_branch2_ops,4367		},4368	},4369};4370 4371static struct clk_branch gcc_pcie_4_pipediv2_clk = {4372	.halt_reg = 0x6b038,4373	.halt_check = BRANCH_HALT_SKIP,4374	.clkr = {4375		.enable_reg = 0x52018,4376		.enable_mask = BIT(16),4377		.hw.init = &(const struct clk_init_data) {4378			.name = "gcc_pcie_4_pipediv2_clk",4379			.parent_hws = (const struct clk_hw*[]){4380				&gcc_pcie_4_pipe_div_clk_src.clkr.hw,4381			},4382			.num_parents = 1,4383			.flags = CLK_SET_RATE_PARENT,4384			.ops = &clk_branch2_ops,4385		},4386	},4387};4388 4389static struct clk_branch gcc_pcie_4_slv_axi_clk = {4390	.halt_reg = 0x6b014,4391	.halt_check = BRANCH_HALT_VOTED,4392	.hwcg_reg = 0x6b014,4393	.hwcg_bit = 1,4394	.clkr = {4395		.enable_reg = 0x52008,4396		.enable_mask = BIT(0),4397		.hw.init = &(const struct clk_init_data) {4398			.name = "gcc_pcie_4_slv_axi_clk",4399			.ops = &clk_branch2_ops,4400		},4401	},4402};4403 4404static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {4405	.halt_reg = 0x6b010,4406	.halt_check = BRANCH_HALT_VOTED,4407	.clkr = {4408		.enable_reg = 0x52008,4409		.enable_mask = BIT(5),4410		.hw.init = &(const struct clk_init_data) {4411			.name = "gcc_pcie_4_slv_q2a_axi_clk",4412			.ops = &clk_branch2_ops,4413		},4414	},4415};4416 4417static struct clk_branch gcc_pcie_rscc_ahb_clk = {4418	.halt_reg = 0xae008,4419	.halt_check = BRANCH_HALT_VOTED,4420	.hwcg_reg = 0xae008,4421	.hwcg_bit = 1,4422	.clkr = {4423		.enable_reg = 0x52020,4424		.enable_mask = BIT(17),4425		.hw.init = &(const struct clk_init_data) {4426			.name = "gcc_pcie_rscc_ahb_clk",4427			.ops = &clk_branch2_ops,4428		},4429	},4430};4431 4432static struct clk_branch gcc_pcie_rscc_xo_clk = {4433	.halt_reg = 0xae004,4434	.halt_check = BRANCH_HALT_VOTED,4435	.clkr = {4436		.enable_reg = 0x52020,4437		.enable_mask = BIT(16),4438		.hw.init = &(const struct clk_init_data) {4439			.name = "gcc_pcie_rscc_xo_clk",4440			.parent_hws = (const struct clk_hw*[]){4441				&gcc_pcie_rscc_xo_clk_src.clkr.hw,4442			},4443			.num_parents = 1,4444			.flags = CLK_SET_RATE_PARENT,4445			.ops = &clk_branch2_ops,4446		},4447	},4448};4449 4450static struct clk_branch gcc_pcie_throttle_cfg_clk = {4451	.halt_reg = 0xa6028,4452	.halt_check = BRANCH_HALT_VOTED,4453	.clkr = {4454		.enable_reg = 0x52020,4455		.enable_mask = BIT(15),4456		.hw.init = &(const struct clk_init_data) {4457			.name = "gcc_pcie_throttle_cfg_clk",4458			.ops = &clk_branch2_ops,4459		},4460	},4461};4462 4463static struct clk_branch gcc_pdm2_clk = {4464	.halt_reg = 0x3300c,4465	.halt_check = BRANCH_HALT,4466	.clkr = {4467		.enable_reg = 0x3300c,4468		.enable_mask = BIT(0),4469		.hw.init = &(const struct clk_init_data) {4470			.name = "gcc_pdm2_clk",4471			.parent_hws = (const struct clk_hw*[]){4472				&gcc_pdm2_clk_src.clkr.hw,4473			},4474			.num_parents = 1,4475			.flags = CLK_SET_RATE_PARENT,4476			.ops = &clk_branch2_ops,4477		},4478	},4479};4480 4481static struct clk_branch gcc_pdm_ahb_clk = {4482	.halt_reg = 0x33004,4483	.halt_check = BRANCH_HALT_VOTED,4484	.hwcg_reg = 0x33004,4485	.hwcg_bit = 1,4486	.clkr = {4487		.enable_reg = 0x33004,4488		.enable_mask = BIT(0),4489		.hw.init = &(const struct clk_init_data) {4490			.name = "gcc_pdm_ahb_clk",4491			.ops = &clk_branch2_ops,4492		},4493	},4494};4495 4496static struct clk_branch gcc_pdm_xo4_clk = {4497	.halt_reg = 0x33008,4498	.halt_check = BRANCH_HALT,4499	.clkr = {4500		.enable_reg = 0x33008,4501		.enable_mask = BIT(0),4502		.hw.init = &(const struct clk_init_data) {4503			.name = "gcc_pdm_xo4_clk",4504			.ops = &clk_branch2_ops,4505		},4506	},4507};4508 4509static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {4510	.halt_reg = 0x26008,4511	.halt_check = BRANCH_HALT_VOTED,4512	.hwcg_reg = 0x26008,4513	.hwcg_bit = 1,4514	.clkr = {4515		.enable_reg = 0x26008,4516		.enable_mask = BIT(0),4517		.hw.init = &(const struct clk_init_data) {4518			.name = "gcc_qmip_camera_nrt_ahb_clk",4519			.ops = &clk_branch2_ops,4520		},4521	},4522};4523 4524static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {4525	.halt_reg = 0x2600c,4526	.halt_check = BRANCH_HALT_VOTED,4527	.hwcg_reg = 0x2600c,4528	.hwcg_bit = 1,4529	.clkr = {4530		.enable_reg = 0x2600c,4531		.enable_mask = BIT(0),4532		.hw.init = &(const struct clk_init_data) {4533			.name = "gcc_qmip_camera_rt_ahb_clk",4534			.ops = &clk_branch2_ops,4535		},4536	},4537};4538 4539static struct clk_branch gcc_qmip_disp1_ahb_clk = {4540	.halt_reg = 0xbb008,4541	.halt_check = BRANCH_HALT_VOTED,4542	.hwcg_reg = 0xbb008,4543	.hwcg_bit = 1,4544	.clkr = {4545		.enable_reg = 0xbb008,4546		.enable_mask = BIT(0),4547		.hw.init = &(const struct clk_init_data) {4548			.name = "gcc_qmip_disp1_ahb_clk",4549			.ops = &clk_branch2_ops,4550		},4551	},4552};4553 4554static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {4555	.halt_reg = 0xbb00c,4556	.halt_check = BRANCH_HALT_VOTED,4557	.hwcg_reg = 0xbb00c,4558	.hwcg_bit = 1,4559	.clkr = {4560		.enable_reg = 0xbb00c,4561		.enable_mask = BIT(0),4562		.hw.init = &(const struct clk_init_data) {4563			.name = "gcc_qmip_disp1_rot_ahb_clk",4564			.ops = &clk_branch2_ops,4565		},4566	},4567};4568 4569static struct clk_branch gcc_qmip_disp_ahb_clk = {4570	.halt_reg = 0x27008,4571	.halt_check = BRANCH_HALT_VOTED,4572	.hwcg_reg = 0x27008,4573	.hwcg_bit = 1,4574	.clkr = {4575		.enable_reg = 0x27008,4576		.enable_mask = BIT(0),4577		.hw.init = &(const struct clk_init_data) {4578			.name = "gcc_qmip_disp_ahb_clk",4579			.ops = &clk_branch2_ops,4580		},4581	},4582};4583 4584static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {4585	.halt_reg = 0x2700c,4586	.halt_check = BRANCH_HALT_VOTED,4587	.hwcg_reg = 0x2700c,4588	.hwcg_bit = 1,4589	.clkr = {4590		.enable_reg = 0x2700c,4591		.enable_mask = BIT(0),4592		.hw.init = &(const struct clk_init_data) {4593			.name = "gcc_qmip_disp_rot_ahb_clk",4594			.ops = &clk_branch2_ops,4595		},4596	},4597};4598 4599static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {4600	.halt_reg = 0x28008,4601	.halt_check = BRANCH_HALT_VOTED,4602	.hwcg_reg = 0x28008,4603	.hwcg_bit = 1,4604	.clkr = {4605		.enable_reg = 0x28008,4606		.enable_mask = BIT(0),4607		.hw.init = &(const struct clk_init_data) {4608			.name = "gcc_qmip_video_cvp_ahb_clk",4609			.ops = &clk_branch2_ops,4610		},4611	},4612};4613 4614static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {4615	.halt_reg = 0x2800c,4616	.halt_check = BRANCH_HALT_VOTED,4617	.hwcg_reg = 0x2800c,4618	.hwcg_bit = 1,4619	.clkr = {4620		.enable_reg = 0x2800c,4621		.enable_mask = BIT(0),4622		.hw.init = &(const struct clk_init_data) {4623			.name = "gcc_qmip_video_vcodec_ahb_clk",4624			.ops = &clk_branch2_ops,4625		},4626	},4627};4628 4629static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {4630	.halt_reg = 0x17014,4631	.halt_check = BRANCH_HALT_VOTED,4632	.clkr = {4633		.enable_reg = 0x52008,4634		.enable_mask = BIT(9),4635		.hw.init = &(const struct clk_init_data) {4636			.name = "gcc_qupv3_wrap0_core_2x_clk",4637			.ops = &clk_branch2_ops,4638		},4639	},4640};4641 4642static struct clk_branch gcc_qupv3_wrap0_core_clk = {4643	.halt_reg = 0x1700c,4644	.halt_check = BRANCH_HALT_VOTED,4645	.clkr = {4646		.enable_reg = 0x52008,4647		.enable_mask = BIT(8),4648		.hw.init = &(const struct clk_init_data) {4649			.name = "gcc_qupv3_wrap0_core_clk",4650			.ops = &clk_branch2_ops,4651		},4652	},4653};4654 4655static struct clk_branch gcc_qupv3_wrap0_qspi0_clk = {4656	.halt_reg = 0x17ac4,4657	.halt_check = BRANCH_HALT_VOTED,4658	.clkr = {4659		.enable_reg = 0x52020,4660		.enable_mask = BIT(0),4661		.hw.init = &(const struct clk_init_data) {4662			.name = "gcc_qupv3_wrap0_qspi0_clk",4663			.parent_hws = (const struct clk_hw*[]){4664				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,4665			},4666			.num_parents = 1,4667			.flags = CLK_SET_RATE_PARENT,4668			.ops = &clk_branch2_ops,4669		},4670	},4671};4672 4673static struct clk_branch gcc_qupv3_wrap0_s0_clk = {4674	.halt_reg = 0x17144,4675	.halt_check = BRANCH_HALT_VOTED,4676	.clkr = {4677		.enable_reg = 0x52008,4678		.enable_mask = BIT(10),4679		.hw.init = &(const struct clk_init_data) {4680			.name = "gcc_qupv3_wrap0_s0_clk",4681			.parent_hws = (const struct clk_hw*[]){4682				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,4683			},4684			.num_parents = 1,4685			.flags = CLK_SET_RATE_PARENT,4686			.ops = &clk_branch2_ops,4687		},4688	},4689};4690 4691static struct clk_branch gcc_qupv3_wrap0_s1_clk = {4692	.halt_reg = 0x17274,4693	.halt_check = BRANCH_HALT_VOTED,4694	.clkr = {4695		.enable_reg = 0x52008,4696		.enable_mask = BIT(11),4697		.hw.init = &(const struct clk_init_data) {4698			.name = "gcc_qupv3_wrap0_s1_clk",4699			.parent_hws = (const struct clk_hw*[]){4700				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,4701			},4702			.num_parents = 1,4703			.flags = CLK_SET_RATE_PARENT,4704			.ops = &clk_branch2_ops,4705		},4706	},4707};4708 4709static struct clk_branch gcc_qupv3_wrap0_s2_clk = {4710	.halt_reg = 0x173a4,4711	.halt_check = BRANCH_HALT_VOTED,4712	.clkr = {4713		.enable_reg = 0x52008,4714		.enable_mask = BIT(12),4715		.hw.init = &(const struct clk_init_data) {4716			.name = "gcc_qupv3_wrap0_s2_clk",4717			.parent_hws = (const struct clk_hw*[]){4718				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,4719			},4720			.num_parents = 1,4721			.flags = CLK_SET_RATE_PARENT,4722			.ops = &clk_branch2_ops,4723		},4724	},4725};4726 4727static struct clk_branch gcc_qupv3_wrap0_s3_clk = {4728	.halt_reg = 0x174d4,4729	.halt_check = BRANCH_HALT_VOTED,4730	.clkr = {4731		.enable_reg = 0x52008,4732		.enable_mask = BIT(13),4733		.hw.init = &(const struct clk_init_data) {4734			.name = "gcc_qupv3_wrap0_s3_clk",4735			.parent_hws = (const struct clk_hw*[]){4736				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,4737			},4738			.num_parents = 1,4739			.flags = CLK_SET_RATE_PARENT,4740			.ops = &clk_branch2_ops,4741		},4742	},4743};4744 4745static struct clk_branch gcc_qupv3_wrap0_s4_clk = {4746	.halt_reg = 0x17604,4747	.halt_check = BRANCH_HALT_VOTED,4748	.clkr = {4749		.enable_reg = 0x52008,4750		.enable_mask = BIT(14),4751		.hw.init = &(const struct clk_init_data) {4752			.name = "gcc_qupv3_wrap0_s4_clk",4753			.parent_hws = (const struct clk_hw*[]){4754				&gcc_qupv3_wrap0_s4_div_clk_src.clkr.hw,4755			},4756			.num_parents = 1,4757			.flags = CLK_SET_RATE_PARENT,4758			.ops = &clk_branch2_ops,4759		},4760	},4761};4762 4763static struct clk_branch gcc_qupv3_wrap0_s5_clk = {4764	.halt_reg = 0x17734,4765	.halt_check = BRANCH_HALT_VOTED,4766	.clkr = {4767		.enable_reg = 0x52008,4768		.enable_mask = BIT(15),4769		.hw.init = &(const struct clk_init_data) {4770			.name = "gcc_qupv3_wrap0_s5_clk",4771			.parent_hws = (const struct clk_hw*[]){4772				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,4773			},4774			.num_parents = 1,4775			.flags = CLK_SET_RATE_PARENT,4776			.ops = &clk_branch2_ops,4777		},4778	},4779};4780 4781static struct clk_branch gcc_qupv3_wrap0_s6_clk = {4782	.halt_reg = 0x17864,4783	.halt_check = BRANCH_HALT_VOTED,4784	.clkr = {4785		.enable_reg = 0x52008,4786		.enable_mask = BIT(16),4787		.hw.init = &(const struct clk_init_data) {4788			.name = "gcc_qupv3_wrap0_s6_clk",4789			.parent_hws = (const struct clk_hw*[]){4790				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,4791			},4792			.num_parents = 1,4793			.flags = CLK_SET_RATE_PARENT,4794			.ops = &clk_branch2_ops,4795		},4796	},4797};4798 4799static struct clk_branch gcc_qupv3_wrap0_s7_clk = {4800	.halt_reg = 0x17994,4801	.halt_check = BRANCH_HALT_VOTED,4802	.clkr = {4803		.enable_reg = 0x52008,4804		.enable_mask = BIT(17),4805		.hw.init = &(const struct clk_init_data) {4806			.name = "gcc_qupv3_wrap0_s7_clk",4807			.parent_hws = (const struct clk_hw*[]){4808				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,4809			},4810			.num_parents = 1,4811			.flags = CLK_SET_RATE_PARENT,4812			.ops = &clk_branch2_ops,4813		},4814	},4815};4816 4817static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {4818	.halt_reg = 0x18014,4819	.halt_check = BRANCH_HALT_VOTED,4820	.clkr = {4821		.enable_reg = 0x52008,4822		.enable_mask = BIT(18),4823		.hw.init = &(const struct clk_init_data) {4824			.name = "gcc_qupv3_wrap1_core_2x_clk",4825			.ops = &clk_branch2_ops,4826		},4827	},4828};4829 4830static struct clk_branch gcc_qupv3_wrap1_core_clk = {4831	.halt_reg = 0x1800c,4832	.halt_check = BRANCH_HALT_VOTED,4833	.clkr = {4834		.enable_reg = 0x52008,4835		.enable_mask = BIT(19),4836		.hw.init = &(const struct clk_init_data) {4837			.name = "gcc_qupv3_wrap1_core_clk",4838			.ops = &clk_branch2_ops,4839		},4840	},4841};4842 4843static struct clk_branch gcc_qupv3_wrap1_qspi0_clk = {4844	.halt_reg = 0x18ac4,4845	.halt_check = BRANCH_HALT_VOTED,4846	.clkr = {4847		.enable_reg = 0x52020,4848		.enable_mask = BIT(2),4849		.hw.init = &(const struct clk_init_data) {4850			.name = "gcc_qupv3_wrap1_qspi0_clk",4851			.parent_hws = (const struct clk_hw*[]){4852				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,4853			},4854			.num_parents = 1,4855			.flags = CLK_SET_RATE_PARENT,4856			.ops = &clk_branch2_ops,4857		},4858	},4859};4860 4861static struct clk_branch gcc_qupv3_wrap1_s0_clk = {4862	.halt_reg = 0x18144,4863	.halt_check = BRANCH_HALT_VOTED,4864	.clkr = {4865		.enable_reg = 0x52008,4866		.enable_mask = BIT(22),4867		.hw.init = &(const struct clk_init_data) {4868			.name = "gcc_qupv3_wrap1_s0_clk",4869			.parent_hws = (const struct clk_hw*[]){4870				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,4871			},4872			.num_parents = 1,4873			.flags = CLK_SET_RATE_PARENT,4874			.ops = &clk_branch2_ops,4875		},4876	},4877};4878 4879static struct clk_branch gcc_qupv3_wrap1_s1_clk = {4880	.halt_reg = 0x18274,4881	.halt_check = BRANCH_HALT_VOTED,4882	.clkr = {4883		.enable_reg = 0x52008,4884		.enable_mask = BIT(23),4885		.hw.init = &(const struct clk_init_data) {4886			.name = "gcc_qupv3_wrap1_s1_clk",4887			.parent_hws = (const struct clk_hw*[]){4888				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,4889			},4890			.num_parents = 1,4891			.flags = CLK_SET_RATE_PARENT,4892			.ops = &clk_branch2_ops,4893		},4894	},4895};4896 4897static struct clk_branch gcc_qupv3_wrap1_s2_clk = {4898	.halt_reg = 0x183a4,4899	.halt_check = BRANCH_HALT_VOTED,4900	.clkr = {4901		.enable_reg = 0x52008,4902		.enable_mask = BIT(24),4903		.hw.init = &(const struct clk_init_data) {4904			.name = "gcc_qupv3_wrap1_s2_clk",4905			.parent_hws = (const struct clk_hw*[]){4906				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,4907			},4908			.num_parents = 1,4909			.flags = CLK_SET_RATE_PARENT,4910			.ops = &clk_branch2_ops,4911		},4912	},4913};4914 4915static struct clk_branch gcc_qupv3_wrap1_s3_clk = {4916	.halt_reg = 0x184d4,4917	.halt_check = BRANCH_HALT_VOTED,4918	.clkr = {4919		.enable_reg = 0x52008,4920		.enable_mask = BIT(25),4921		.hw.init = &(const struct clk_init_data) {4922			.name = "gcc_qupv3_wrap1_s3_clk",4923			.parent_hws = (const struct clk_hw*[]){4924				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,4925			},4926			.num_parents = 1,4927			.flags = CLK_SET_RATE_PARENT,4928			.ops = &clk_branch2_ops,4929		},4930	},4931};4932 4933static struct clk_branch gcc_qupv3_wrap1_s4_clk = {4934	.halt_reg = 0x18604,4935	.halt_check = BRANCH_HALT_VOTED,4936	.clkr = {4937		.enable_reg = 0x52008,4938		.enable_mask = BIT(26),4939		.hw.init = &(const struct clk_init_data) {4940			.name = "gcc_qupv3_wrap1_s4_clk",4941			.parent_hws = (const struct clk_hw*[]){4942				&gcc_qupv3_wrap1_s4_div_clk_src.clkr.hw,4943			},4944			.num_parents = 1,4945			.flags = CLK_SET_RATE_PARENT,4946			.ops = &clk_branch2_ops,4947		},4948	},4949};4950 4951static struct clk_branch gcc_qupv3_wrap1_s5_clk = {4952	.halt_reg = 0x18734,4953	.halt_check = BRANCH_HALT_VOTED,4954	.clkr = {4955		.enable_reg = 0x52008,4956		.enable_mask = BIT(27),4957		.hw.init = &(const struct clk_init_data) {4958			.name = "gcc_qupv3_wrap1_s5_clk",4959			.parent_hws = (const struct clk_hw*[]){4960				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,4961			},4962			.num_parents = 1,4963			.flags = CLK_SET_RATE_PARENT,4964			.ops = &clk_branch2_ops,4965		},4966	},4967};4968 4969static struct clk_branch gcc_qupv3_wrap1_s6_clk = {4970	.halt_reg = 0x18864,4971	.halt_check = BRANCH_HALT_VOTED,4972	.clkr = {4973		.enable_reg = 0x52018,4974		.enable_mask = BIT(27),4975		.hw.init = &(const struct clk_init_data) {4976			.name = "gcc_qupv3_wrap1_s6_clk",4977			.parent_hws = (const struct clk_hw*[]){4978				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,4979			},4980			.num_parents = 1,4981			.flags = CLK_SET_RATE_PARENT,4982			.ops = &clk_branch2_ops,4983		},4984	},4985};4986 4987static struct clk_branch gcc_qupv3_wrap1_s7_clk = {4988	.halt_reg = 0x18994,4989	.halt_check = BRANCH_HALT_VOTED,4990	.clkr = {4991		.enable_reg = 0x52018,4992		.enable_mask = BIT(28),4993		.hw.init = &(const struct clk_init_data) {4994			.name = "gcc_qupv3_wrap1_s7_clk",4995			.parent_hws = (const struct clk_hw*[]){4996				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,4997			},4998			.num_parents = 1,4999			.flags = CLK_SET_RATE_PARENT,5000			.ops = &clk_branch2_ops,5001		},5002	},5003};5004 5005static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {5006	.halt_reg = 0x1e014,5007	.halt_check = BRANCH_HALT_VOTED,5008	.clkr = {5009		.enable_reg = 0x52010,5010		.enable_mask = BIT(3),5011		.hw.init = &(const struct clk_init_data) {5012			.name = "gcc_qupv3_wrap2_core_2x_clk",5013			.ops = &clk_branch2_ops,5014		},5015	},5016};5017 5018static struct clk_branch gcc_qupv3_wrap2_core_clk = {5019	.halt_reg = 0x1e00c,5020	.halt_check = BRANCH_HALT_VOTED,5021	.clkr = {5022		.enable_reg = 0x52010,5023		.enable_mask = BIT(0),5024		.hw.init = &(const struct clk_init_data) {5025			.name = "gcc_qupv3_wrap2_core_clk",5026			.ops = &clk_branch2_ops,5027		},5028	},5029};5030 5031static struct clk_branch gcc_qupv3_wrap2_qspi0_clk = {5032	.halt_reg = 0x1eac4,5033	.halt_check = BRANCH_HALT_VOTED,5034	.clkr = {5035		.enable_reg = 0x52020,5036		.enable_mask = BIT(4),5037		.hw.init = &(const struct clk_init_data) {5038			.name = "gcc_qupv3_wrap2_qspi0_clk",5039			.parent_hws = (const struct clk_hw*[]){5040				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,5041			},5042			.num_parents = 1,5043			.flags = CLK_SET_RATE_PARENT,5044			.ops = &clk_branch2_ops,5045		},5046	},5047};5048 5049static struct clk_branch gcc_qupv3_wrap2_s0_clk = {5050	.halt_reg = 0x1e144,5051	.halt_check = BRANCH_HALT_VOTED,5052	.clkr = {5053		.enable_reg = 0x52010,5054		.enable_mask = BIT(4),5055		.hw.init = &(const struct clk_init_data) {5056			.name = "gcc_qupv3_wrap2_s0_clk",5057			.parent_hws = (const struct clk_hw*[]){5058				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,5059			},5060			.num_parents = 1,5061			.flags = CLK_SET_RATE_PARENT,5062			.ops = &clk_branch2_ops,5063		},5064	},5065};5066 5067static struct clk_branch gcc_qupv3_wrap2_s1_clk = {5068	.halt_reg = 0x1e274,5069	.halt_check = BRANCH_HALT_VOTED,5070	.clkr = {5071		.enable_reg = 0x52010,5072		.enable_mask = BIT(5),5073		.hw.init = &(const struct clk_init_data) {5074			.name = "gcc_qupv3_wrap2_s1_clk",5075			.parent_hws = (const struct clk_hw*[]){5076				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,5077			},5078			.num_parents = 1,5079			.flags = CLK_SET_RATE_PARENT,5080			.ops = &clk_branch2_ops,5081		},5082	},5083};5084 5085static struct clk_branch gcc_qupv3_wrap2_s2_clk = {5086	.halt_reg = 0x1e3a4,5087	.halt_check = BRANCH_HALT_VOTED,5088	.clkr = {5089		.enable_reg = 0x52010,5090		.enable_mask = BIT(6),5091		.hw.init = &(const struct clk_init_data) {5092			.name = "gcc_qupv3_wrap2_s2_clk",5093			.parent_hws = (const struct clk_hw*[]){5094				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,5095			},5096			.num_parents = 1,5097			.flags = CLK_SET_RATE_PARENT,5098			.ops = &clk_branch2_ops,5099		},5100	},5101};5102 5103static struct clk_branch gcc_qupv3_wrap2_s3_clk = {5104	.halt_reg = 0x1e4d4,5105	.halt_check = BRANCH_HALT_VOTED,5106	.clkr = {5107		.enable_reg = 0x52010,5108		.enable_mask = BIT(7),5109		.hw.init = &(const struct clk_init_data) {5110			.name = "gcc_qupv3_wrap2_s3_clk",5111			.parent_hws = (const struct clk_hw*[]){5112				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,5113			},5114			.num_parents = 1,5115			.flags = CLK_SET_RATE_PARENT,5116			.ops = &clk_branch2_ops,5117		},5118	},5119};5120 5121static struct clk_branch gcc_qupv3_wrap2_s4_clk = {5122	.halt_reg = 0x1e604,5123	.halt_check = BRANCH_HALT_VOTED,5124	.clkr = {5125		.enable_reg = 0x52010,5126		.enable_mask = BIT(8),5127		.hw.init = &(const struct clk_init_data) {5128			.name = "gcc_qupv3_wrap2_s4_clk",5129			.parent_hws = (const struct clk_hw*[]){5130				&gcc_qupv3_wrap2_s4_div_clk_src.clkr.hw,5131			},5132			.num_parents = 1,5133			.flags = CLK_SET_RATE_PARENT,5134			.ops = &clk_branch2_ops,5135		},5136	},5137};5138 5139static struct clk_branch gcc_qupv3_wrap2_s5_clk = {5140	.halt_reg = 0x1e734,5141	.halt_check = BRANCH_HALT_VOTED,5142	.clkr = {5143		.enable_reg = 0x52010,5144		.enable_mask = BIT(9),5145		.hw.init = &(const struct clk_init_data) {5146			.name = "gcc_qupv3_wrap2_s5_clk",5147			.parent_hws = (const struct clk_hw*[]){5148				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,5149			},5150			.num_parents = 1,5151			.flags = CLK_SET_RATE_PARENT,5152			.ops = &clk_branch2_ops,5153		},5154	},5155};5156 5157static struct clk_branch gcc_qupv3_wrap2_s6_clk = {5158	.halt_reg = 0x1e864,5159	.halt_check = BRANCH_HALT_VOTED,5160	.clkr = {5161		.enable_reg = 0x52018,5162		.enable_mask = BIT(29),5163		.hw.init = &(const struct clk_init_data) {5164			.name = "gcc_qupv3_wrap2_s6_clk",5165			.parent_hws = (const struct clk_hw*[]){5166				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,5167			},5168			.num_parents = 1,5169			.flags = CLK_SET_RATE_PARENT,5170			.ops = &clk_branch2_ops,5171		},5172	},5173};5174 5175static struct clk_branch gcc_qupv3_wrap2_s7_clk = {5176	.halt_reg = 0x1e994,5177	.halt_check = BRANCH_HALT_VOTED,5178	.clkr = {5179		.enable_reg = 0x52018,5180		.enable_mask = BIT(30),5181		.hw.init = &(const struct clk_init_data) {5182			.name = "gcc_qupv3_wrap2_s7_clk",5183			.parent_hws = (const struct clk_hw*[]){5184				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,5185			},5186			.num_parents = 1,5187			.flags = CLK_SET_RATE_PARENT,5188			.ops = &clk_branch2_ops,5189		},5190	},5191};5192 5193static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {5194	.halt_reg = 0x17004,5195	.halt_check = BRANCH_HALT_VOTED,5196	.hwcg_reg = 0x17004,5197	.hwcg_bit = 1,5198	.clkr = {5199		.enable_reg = 0x52008,5200		.enable_mask = BIT(6),5201		.hw.init = &(const struct clk_init_data) {5202			.name = "gcc_qupv3_wrap_0_m_ahb_clk",5203			.ops = &clk_branch2_ops,5204		},5205	},5206};5207 5208static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {5209	.halt_reg = 0x17008,5210	.halt_check = BRANCH_HALT_VOTED,5211	.hwcg_reg = 0x17008,5212	.hwcg_bit = 1,5213	.clkr = {5214		.enable_reg = 0x52008,5215		.enable_mask = BIT(7),5216		.hw.init = &(const struct clk_init_data) {5217			.name = "gcc_qupv3_wrap_0_s_ahb_clk",5218			.ops = &clk_branch2_ops,5219		},5220	},5221};5222 5223static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {5224	.halt_reg = 0x18004,5225	.halt_check = BRANCH_HALT_VOTED,5226	.hwcg_reg = 0x18004,5227	.hwcg_bit = 1,5228	.clkr = {5229		.enable_reg = 0x52008,5230		.enable_mask = BIT(20),5231		.hw.init = &(const struct clk_init_data) {5232			.name = "gcc_qupv3_wrap_1_m_ahb_clk",5233			.ops = &clk_branch2_ops,5234		},5235	},5236};5237 5238static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {5239	.halt_reg = 0x18008,5240	.halt_check = BRANCH_HALT_VOTED,5241	.hwcg_reg = 0x18008,5242	.hwcg_bit = 1,5243	.clkr = {5244		.enable_reg = 0x52008,5245		.enable_mask = BIT(21),5246		.hw.init = &(const struct clk_init_data) {5247			.name = "gcc_qupv3_wrap_1_s_ahb_clk",5248			.ops = &clk_branch2_ops,5249		},5250	},5251};5252 5253static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {5254	.halt_reg = 0x1e004,5255	.halt_check = BRANCH_HALT_VOTED,5256	.hwcg_reg = 0x1e004,5257	.hwcg_bit = 1,5258	.clkr = {5259		.enable_reg = 0x52010,5260		.enable_mask = BIT(2),5261		.hw.init = &(const struct clk_init_data) {5262			.name = "gcc_qupv3_wrap_2_m_ahb_clk",5263			.ops = &clk_branch2_ops,5264		},5265	},5266};5267 5268static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {5269	.halt_reg = 0x1e008,5270	.halt_check = BRANCH_HALT_VOTED,5271	.hwcg_reg = 0x1e008,5272	.hwcg_bit = 1,5273	.clkr = {5274		.enable_reg = 0x52010,5275		.enable_mask = BIT(1),5276		.hw.init = &(const struct clk_init_data) {5277			.name = "gcc_qupv3_wrap_2_s_ahb_clk",5278			.ops = &clk_branch2_ops,5279		},5280	},5281};5282 5283static struct clk_branch gcc_sdcc2_ahb_clk = {5284	.halt_reg = 0x14008,5285	.halt_check = BRANCH_HALT,5286	.clkr = {5287		.enable_reg = 0x14008,5288		.enable_mask = BIT(0),5289		.hw.init = &(const struct clk_init_data) {5290			.name = "gcc_sdcc2_ahb_clk",5291			.ops = &clk_branch2_ops,5292		},5293	},5294};5295 5296static struct clk_branch gcc_sdcc2_apps_clk = {5297	.halt_reg = 0x14004,5298	.halt_check = BRANCH_HALT,5299	.clkr = {5300		.enable_reg = 0x14004,5301		.enable_mask = BIT(0),5302		.hw.init = &(const struct clk_init_data) {5303			.name = "gcc_sdcc2_apps_clk",5304			.parent_hws = (const struct clk_hw*[]){5305				&gcc_sdcc2_apps_clk_src.clkr.hw,5306			},5307			.num_parents = 1,5308			.flags = CLK_SET_RATE_PARENT,5309			.ops = &clk_branch2_ops,5310		},5311	},5312};5313 5314static struct clk_branch gcc_sdcc4_ahb_clk = {5315	.halt_reg = 0x16008,5316	.halt_check = BRANCH_HALT,5317	.clkr = {5318		.enable_reg = 0x16008,5319		.enable_mask = BIT(0),5320		.hw.init = &(const struct clk_init_data) {5321			.name = "gcc_sdcc4_ahb_clk",5322			.ops = &clk_branch2_ops,5323		},5324	},5325};5326 5327static struct clk_branch gcc_sdcc4_apps_clk = {5328	.halt_reg = 0x16004,5329	.halt_check = BRANCH_HALT,5330	.clkr = {5331		.enable_reg = 0x16004,5332		.enable_mask = BIT(0),5333		.hw.init = &(const struct clk_init_data) {5334			.name = "gcc_sdcc4_apps_clk",5335			.parent_hws = (const struct clk_hw*[]){5336				&gcc_sdcc4_apps_clk_src.clkr.hw,5337			},5338			.num_parents = 1,5339			.flags = CLK_SET_RATE_PARENT,5340			.ops = &clk_branch2_ops,5341		},5342	},5343};5344 5345static struct clk_branch gcc_sys_noc_usb_axi_clk = {5346	.halt_reg = 0x5d000,5347	.halt_check = BRANCH_HALT_VOTED,5348	.hwcg_reg = 0x5d000,5349	.hwcg_bit = 1,5350	.clkr = {5351		.enable_reg = 0x5d000,5352		.enable_mask = BIT(0),5353		.hw.init = &(const struct clk_init_data) {5354			.name = "gcc_sys_noc_usb_axi_clk",5355			.ops = &clk_branch2_ops,5356		},5357	},5358};5359 5360static struct clk_branch gcc_ufs_1_card_clkref_clk = {5361	.halt_reg = 0x8c000,5362	.halt_check = BRANCH_HALT,5363	.clkr = {5364		.enable_reg = 0x8c000,5365		.enable_mask = BIT(0),5366		.hw.init = &(const struct clk_init_data) {5367			.name = "gcc_ufs_1_card_clkref_clk",5368			.parent_data = &gcc_parent_data_tcxo,5369			.num_parents = 1,5370			.ops = &clk_branch2_ops,5371		},5372	},5373};5374 5375static struct clk_branch gcc_ufs_card_ahb_clk = {5376	.halt_reg = 0x75018,5377	.halt_check = BRANCH_HALT_VOTED,5378	.hwcg_reg = 0x75018,5379	.hwcg_bit = 1,5380	.clkr = {5381		.enable_reg = 0x75018,5382		.enable_mask = BIT(0),5383		.hw.init = &(const struct clk_init_data) {5384			.name = "gcc_ufs_card_ahb_clk",5385			.ops = &clk_branch2_ops,5386		},5387	},5388};5389 5390static struct clk_branch gcc_ufs_card_axi_clk = {5391	.halt_reg = 0x75010,5392	.halt_check = BRANCH_HALT_VOTED,5393	.hwcg_reg = 0x75010,5394	.hwcg_bit = 1,5395	.clkr = {5396		.enable_reg = 0x75010,5397		.enable_mask = BIT(0),5398		.hw.init = &(const struct clk_init_data) {5399			.name = "gcc_ufs_card_axi_clk",5400			.parent_hws = (const struct clk_hw*[]){5401				&gcc_ufs_card_axi_clk_src.clkr.hw,5402			},5403			.num_parents = 1,5404			.flags = CLK_SET_RATE_PARENT,5405			.ops = &clk_branch2_ops,5406		},5407	},5408};5409 5410static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {5411	.halt_reg = 0x75010,5412	.halt_check = BRANCH_HALT_VOTED,5413	.hwcg_reg = 0x75010,5414	.hwcg_bit = 1,5415	.clkr = {5416		.enable_reg = 0x75010,5417		.enable_mask = BIT(1),5418		.hw.init = &(const struct clk_init_data) {5419			.name = "gcc_ufs_card_axi_hw_ctl_clk",5420			.parent_hws = (const struct clk_hw*[]){5421				&gcc_ufs_card_axi_clk_src.clkr.hw,5422			},5423			.num_parents = 1,5424			.flags = CLK_SET_RATE_PARENT,5425			.ops = &clk_branch2_ops,5426		},5427	},5428};5429 5430static struct clk_branch gcc_ufs_card_clkref_clk = {5431	.halt_reg = 0x8c054,5432	.halt_check = BRANCH_HALT,5433	.clkr = {5434		.enable_reg = 0x8c054,5435		.enable_mask = BIT(0),5436		.hw.init = &(const struct clk_init_data) {5437			.name = "gcc_ufs_card_clkref_clk",5438			.parent_data = &gcc_parent_data_tcxo,5439			.num_parents = 1,5440			.ops = &clk_branch2_ops,5441		},5442	},5443};5444 5445static struct clk_branch gcc_ufs_card_ice_core_clk = {5446	.halt_reg = 0x75064,5447	.halt_check = BRANCH_HALT_VOTED,5448	.hwcg_reg = 0x75064,5449	.hwcg_bit = 1,5450	.clkr = {5451		.enable_reg = 0x75064,5452		.enable_mask = BIT(0),5453		.hw.init = &(const struct clk_init_data) {5454			.name = "gcc_ufs_card_ice_core_clk",5455			.parent_hws = (const struct clk_hw*[]){5456				&gcc_ufs_card_ice_core_clk_src.clkr.hw,5457			},5458			.num_parents = 1,5459			.flags = CLK_SET_RATE_PARENT,5460			.ops = &clk_branch2_ops,5461		},5462	},5463};5464 5465static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {5466	.halt_reg = 0x75064,5467	.halt_check = BRANCH_HALT_VOTED,5468	.hwcg_reg = 0x75064,5469	.hwcg_bit = 1,5470	.clkr = {5471		.enable_reg = 0x75064,5472		.enable_mask = BIT(1),5473		.hw.init = &(const struct clk_init_data) {5474			.name = "gcc_ufs_card_ice_core_hw_ctl_clk",5475			.parent_hws = (const struct clk_hw*[]){5476				&gcc_ufs_card_ice_core_clk_src.clkr.hw,5477			},5478			.num_parents = 1,5479			.flags = CLK_SET_RATE_PARENT,5480			.ops = &clk_branch2_ops,5481		},5482	},5483};5484 5485static struct clk_branch gcc_ufs_card_phy_aux_clk = {5486	.halt_reg = 0x7509c,5487	.halt_check = BRANCH_HALT_VOTED,5488	.hwcg_reg = 0x7509c,5489	.hwcg_bit = 1,5490	.clkr = {5491		.enable_reg = 0x7509c,5492		.enable_mask = BIT(0),5493		.hw.init = &(const struct clk_init_data) {5494			.name = "gcc_ufs_card_phy_aux_clk",5495			.parent_hws = (const struct clk_hw*[]){5496				&gcc_ufs_card_phy_aux_clk_src.clkr.hw,5497			},5498			.num_parents = 1,5499			.flags = CLK_SET_RATE_PARENT,5500			.ops = &clk_branch2_ops,5501		},5502	},5503};5504 5505static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {5506	.halt_reg = 0x7509c,5507	.halt_check = BRANCH_HALT_VOTED,5508	.hwcg_reg = 0x7509c,5509	.hwcg_bit = 1,5510	.clkr = {5511		.enable_reg = 0x7509c,5512		.enable_mask = BIT(1),5513		.hw.init = &(const struct clk_init_data) {5514			.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",5515			.parent_hws = (const struct clk_hw*[]){5516				&gcc_ufs_card_phy_aux_clk_src.clkr.hw,5517			},5518			.num_parents = 1,5519			.flags = CLK_SET_RATE_PARENT,5520			.ops = &clk_branch2_ops,5521		},5522	},5523};5524 5525static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {5526	.halt_reg = 0x75020,5527	.halt_check = BRANCH_HALT_DELAY,5528	.clkr = {5529		.enable_reg = 0x75020,5530		.enable_mask = BIT(0),5531		.hw.init = &(const struct clk_init_data) {5532			.name = "gcc_ufs_card_rx_symbol_0_clk",5533			.parent_hws = (const struct clk_hw*[]){5534				&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,5535			},5536			.num_parents = 1,5537			.flags = CLK_SET_RATE_PARENT,5538			.ops = &clk_branch2_ops,5539		},5540	},5541};5542 5543static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {5544	.halt_reg = 0x750b8,5545	.halt_check = BRANCH_HALT_DELAY,5546	.clkr = {5547		.enable_reg = 0x750b8,5548		.enable_mask = BIT(0),5549		.hw.init = &(const struct clk_init_data) {5550			.name = "gcc_ufs_card_rx_symbol_1_clk",5551			.parent_hws = (const struct clk_hw*[]){5552				&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,5553			},5554			.num_parents = 1,5555			.flags = CLK_SET_RATE_PARENT,5556			.ops = &clk_branch2_ops,5557		},5558	},5559};5560 5561static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {5562	.halt_reg = 0x7501c,5563	.halt_check = BRANCH_HALT_DELAY,5564	.clkr = {5565		.enable_reg = 0x7501c,5566		.enable_mask = BIT(0),5567		.hw.init = &(const struct clk_init_data) {5568			.name = "gcc_ufs_card_tx_symbol_0_clk",5569			.parent_hws = (const struct clk_hw*[]){5570				&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,5571			},5572			.num_parents = 1,5573			.flags = CLK_SET_RATE_PARENT,5574			.ops = &clk_branch2_ops,5575		},5576	},5577};5578 5579static struct clk_branch gcc_ufs_card_unipro_core_clk = {5580	.halt_reg = 0x7505c,5581	.halt_check = BRANCH_HALT_VOTED,5582	.hwcg_reg = 0x7505c,5583	.hwcg_bit = 1,5584	.clkr = {5585		.enable_reg = 0x7505c,5586		.enable_mask = BIT(0),5587		.hw.init = &(const struct clk_init_data) {5588			.name = "gcc_ufs_card_unipro_core_clk",5589			.parent_hws = (const struct clk_hw*[]){5590				&gcc_ufs_card_unipro_core_clk_src.clkr.hw,5591			},5592			.num_parents = 1,5593			.flags = CLK_SET_RATE_PARENT,5594			.ops = &clk_branch2_ops,5595		},5596	},5597};5598 5599static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {5600	.halt_reg = 0x7505c,5601	.halt_check = BRANCH_HALT_VOTED,5602	.hwcg_reg = 0x7505c,5603	.hwcg_bit = 1,5604	.clkr = {5605		.enable_reg = 0x7505c,5606		.enable_mask = BIT(1),5607		.hw.init = &(const struct clk_init_data) {5608			.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",5609			.parent_hws = (const struct clk_hw*[]){5610				&gcc_ufs_card_unipro_core_clk_src.clkr.hw,5611			},5612			.num_parents = 1,5613			.flags = CLK_SET_RATE_PARENT,5614			.ops = &clk_branch2_ops,5615		},5616	},5617};5618 5619static struct clk_branch gcc_ufs_phy_ahb_clk = {5620	.halt_reg = 0x77018,5621	.halt_check = BRANCH_HALT_VOTED,5622	.hwcg_reg = 0x77018,5623	.hwcg_bit = 1,5624	.clkr = {5625		.enable_reg = 0x77018,5626		.enable_mask = BIT(0),5627		.hw.init = &(const struct clk_init_data) {5628			.name = "gcc_ufs_phy_ahb_clk",5629			.ops = &clk_branch2_ops,5630		},5631	},5632};5633 5634static struct clk_branch gcc_ufs_phy_axi_clk = {5635	.halt_reg = 0x77010,5636	.halt_check = BRANCH_HALT_VOTED,5637	.hwcg_reg = 0x77010,5638	.hwcg_bit = 1,5639	.clkr = {5640		.enable_reg = 0x77010,5641		.enable_mask = BIT(0),5642		.hw.init = &(const struct clk_init_data) {5643			.name = "gcc_ufs_phy_axi_clk",5644			.parent_hws = (const struct clk_hw*[]){5645				&gcc_ufs_phy_axi_clk_src.clkr.hw,5646			},5647			.num_parents = 1,5648			.flags = CLK_SET_RATE_PARENT,5649			.ops = &clk_branch2_ops,5650		},5651	},5652};5653 5654static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {5655	.halt_reg = 0x77010,5656	.halt_check = BRANCH_HALT_VOTED,5657	.hwcg_reg = 0x77010,5658	.hwcg_bit = 1,5659	.clkr = {5660		.enable_reg = 0x77010,5661		.enable_mask = BIT(1),5662		.hw.init = &(const struct clk_init_data) {5663			.name = "gcc_ufs_phy_axi_hw_ctl_clk",5664			.parent_hws = (const struct clk_hw*[]){5665				&gcc_ufs_phy_axi_clk_src.clkr.hw,5666			},5667			.num_parents = 1,5668			.flags = CLK_SET_RATE_PARENT,5669			.ops = &clk_branch2_ops,5670		},5671	},5672};5673 5674static struct clk_branch gcc_ufs_phy_ice_core_clk = {5675	.halt_reg = 0x77064,5676	.halt_check = BRANCH_HALT_VOTED,5677	.hwcg_reg = 0x77064,5678	.hwcg_bit = 1,5679	.clkr = {5680		.enable_reg = 0x77064,5681		.enable_mask = BIT(0),5682		.hw.init = &(const struct clk_init_data) {5683			.name = "gcc_ufs_phy_ice_core_clk",5684			.parent_hws = (const struct clk_hw*[]){5685				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,5686			},5687			.num_parents = 1,5688			.flags = CLK_SET_RATE_PARENT,5689			.ops = &clk_branch2_ops,5690		},5691	},5692};5693 5694static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {5695	.halt_reg = 0x77064,5696	.halt_check = BRANCH_HALT_VOTED,5697	.hwcg_reg = 0x77064,5698	.hwcg_bit = 1,5699	.clkr = {5700		.enable_reg = 0x77064,5701		.enable_mask = BIT(1),5702		.hw.init = &(const struct clk_init_data) {5703			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",5704			.parent_hws = (const struct clk_hw*[]){5705				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,5706			},5707			.num_parents = 1,5708			.flags = CLK_SET_RATE_PARENT,5709			.ops = &clk_branch2_ops,5710		},5711	},5712};5713 5714static struct clk_branch gcc_ufs_phy_phy_aux_clk = {5715	.halt_reg = 0x7709c,5716	.halt_check = BRANCH_HALT_VOTED,5717	.hwcg_reg = 0x7709c,5718	.hwcg_bit = 1,5719	.clkr = {5720		.enable_reg = 0x7709c,5721		.enable_mask = BIT(0),5722		.hw.init = &(const struct clk_init_data) {5723			.name = "gcc_ufs_phy_phy_aux_clk",5724			.parent_hws = (const struct clk_hw*[]){5725				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,5726			},5727			.num_parents = 1,5728			.flags = CLK_SET_RATE_PARENT,5729			.ops = &clk_branch2_ops,5730		},5731	},5732};5733 5734static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {5735	.halt_reg = 0x7709c,5736	.halt_check = BRANCH_HALT_VOTED,5737	.hwcg_reg = 0x7709c,5738	.hwcg_bit = 1,5739	.clkr = {5740		.enable_reg = 0x7709c,5741		.enable_mask = BIT(1),5742		.hw.init = &(const struct clk_init_data) {5743			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",5744			.parent_hws = (const struct clk_hw*[]){5745				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,5746			},5747			.num_parents = 1,5748			.flags = CLK_SET_RATE_PARENT,5749			.ops = &clk_branch2_ops,5750		},5751	},5752};5753 5754static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {5755	.halt_reg = 0x77020,5756	.halt_check = BRANCH_HALT_DELAY,5757	.clkr = {5758		.enable_reg = 0x77020,5759		.enable_mask = BIT(0),5760		.hw.init = &(const struct clk_init_data) {5761			.name = "gcc_ufs_phy_rx_symbol_0_clk",5762			.parent_hws = (const struct clk_hw*[]){5763				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,5764			},5765			.num_parents = 1,5766			.flags = CLK_SET_RATE_PARENT,5767			.ops = &clk_branch2_ops,5768		},5769	},5770};5771 5772static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {5773	.halt_reg = 0x770b8,5774	.halt_check = BRANCH_HALT_DELAY,5775	.clkr = {5776		.enable_reg = 0x770b8,5777		.enable_mask = BIT(0),5778		.hw.init = &(const struct clk_init_data) {5779			.name = "gcc_ufs_phy_rx_symbol_1_clk",5780			.parent_hws = (const struct clk_hw*[]){5781				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,5782			},5783			.num_parents = 1,5784			.flags = CLK_SET_RATE_PARENT,5785			.ops = &clk_branch2_ops,5786		},5787	},5788};5789 5790static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {5791	.halt_reg = 0x7701c,5792	.halt_check = BRANCH_HALT_DELAY,5793	.clkr = {5794		.enable_reg = 0x7701c,5795		.enable_mask = BIT(0),5796		.hw.init = &(const struct clk_init_data) {5797			.name = "gcc_ufs_phy_tx_symbol_0_clk",5798			.parent_hws = (const struct clk_hw*[]){5799				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,5800			},5801			.num_parents = 1,5802			.flags = CLK_SET_RATE_PARENT,5803			.ops = &clk_branch2_ops,5804		},5805	},5806};5807 5808static struct clk_branch gcc_ufs_phy_unipro_core_clk = {5809	.halt_reg = 0x7705c,5810	.halt_check = BRANCH_HALT_VOTED,5811	.hwcg_reg = 0x7705c,5812	.hwcg_bit = 1,5813	.clkr = {5814		.enable_reg = 0x7705c,5815		.enable_mask = BIT(0),5816		.hw.init = &(const struct clk_init_data) {5817			.name = "gcc_ufs_phy_unipro_core_clk",5818			.parent_hws = (const struct clk_hw*[]){5819				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,5820			},5821			.num_parents = 1,5822			.flags = CLK_SET_RATE_PARENT,5823			.ops = &clk_branch2_ops,5824		},5825	},5826};5827 5828static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {5829	.halt_reg = 0x7705c,5830	.halt_check = BRANCH_HALT_VOTED,5831	.hwcg_reg = 0x7705c,5832	.hwcg_bit = 1,5833	.clkr = {5834		.enable_reg = 0x7705c,5835		.enable_mask = BIT(1),5836		.hw.init = &(const struct clk_init_data) {5837			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",5838			.parent_hws = (const struct clk_hw*[]){5839				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,5840			},5841			.num_parents = 1,5842			.flags = CLK_SET_RATE_PARENT,5843			.ops = &clk_branch2_ops,5844		},5845	},5846};5847 5848static struct clk_branch gcc_ufs_ref_clkref_clk = {5849	.halt_reg = 0x8c058,5850	.halt_check = BRANCH_HALT,5851	.clkr = {5852		.enable_reg = 0x8c058,5853		.enable_mask = BIT(0),5854		.hw.init = &(const struct clk_init_data) {5855			.name = "gcc_ufs_ref_clkref_clk",5856			.parent_data = &gcc_parent_data_tcxo,5857			.num_parents = 1,5858			.ops = &clk_branch2_ops,5859		},5860	},5861};5862 5863static struct clk_branch gcc_usb2_hs0_clkref_clk = {5864	.halt_reg = 0x8c044,5865	.halt_check = BRANCH_HALT,5866	.clkr = {5867		.enable_reg = 0x8c044,5868		.enable_mask = BIT(0),5869		.hw.init = &(const struct clk_init_data) {5870			.name = "gcc_usb2_hs0_clkref_clk",5871			.ops = &clk_branch2_ops,5872		},5873	},5874};5875 5876static struct clk_branch gcc_usb2_hs1_clkref_clk = {5877	.halt_reg = 0x8c048,5878	.halt_check = BRANCH_HALT,5879	.clkr = {5880		.enable_reg = 0x8c048,5881		.enable_mask = BIT(0),5882		.hw.init = &(const struct clk_init_data) {5883			.name = "gcc_usb2_hs1_clkref_clk",5884			.ops = &clk_branch2_ops,5885		},5886	},5887};5888 5889static struct clk_branch gcc_usb2_hs2_clkref_clk = {5890	.halt_reg = 0x8c04c,5891	.halt_check = BRANCH_HALT,5892	.clkr = {5893		.enable_reg = 0x8c04c,5894		.enable_mask = BIT(0),5895		.hw.init = &(const struct clk_init_data) {5896			.name = "gcc_usb2_hs2_clkref_clk",5897			.ops = &clk_branch2_ops,5898		},5899	},5900};5901 5902static struct clk_branch gcc_usb2_hs3_clkref_clk = {5903	.halt_reg = 0x8c050,5904	.halt_check = BRANCH_HALT,5905	.clkr = {5906		.enable_reg = 0x8c050,5907		.enable_mask = BIT(0),5908		.hw.init = &(const struct clk_init_data) {5909			.name = "gcc_usb2_hs3_clkref_clk",5910			.ops = &clk_branch2_ops,5911		},5912	},5913};5914 5915static struct clk_branch gcc_usb30_mp_master_clk = {5916	.halt_reg = 0xab010,5917	.halt_check = BRANCH_HALT,5918	.clkr = {5919		.enable_reg = 0xab010,5920		.enable_mask = BIT(0),5921		.hw.init = &(const struct clk_init_data) {5922			.name = "gcc_usb30_mp_master_clk",5923			.parent_hws = (const struct clk_hw*[]){5924				&gcc_usb30_mp_master_clk_src.clkr.hw,5925			},5926			.num_parents = 1,5927			.flags = CLK_SET_RATE_PARENT,5928			.ops = &clk_branch2_ops,5929		},5930	},5931};5932 5933static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {5934	.halt_reg = 0xab01c,5935	.halt_check = BRANCH_HALT,5936	.clkr = {5937		.enable_reg = 0xab01c,5938		.enable_mask = BIT(0),5939		.hw.init = &(const struct clk_init_data) {5940			.name = "gcc_usb30_mp_mock_utmi_clk",5941			.parent_hws = (const struct clk_hw*[]){5942				&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,5943			},5944			.num_parents = 1,5945			.flags = CLK_SET_RATE_PARENT,5946			.ops = &clk_branch2_ops,5947		},5948	},5949};5950 5951static struct clk_branch gcc_usb30_mp_sleep_clk = {5952	.halt_reg = 0xab018,5953	.halt_check = BRANCH_HALT,5954	.clkr = {5955		.enable_reg = 0xab018,5956		.enable_mask = BIT(0),5957		.hw.init = &(const struct clk_init_data) {5958			.name = "gcc_usb30_mp_sleep_clk",5959			.ops = &clk_branch2_ops,5960		},5961	},5962};5963 5964static struct clk_branch gcc_usb30_prim_master_clk = {5965	.halt_reg = 0xf010,5966	.halt_check = BRANCH_HALT,5967	.clkr = {5968		.enable_reg = 0xf010,5969		.enable_mask = BIT(0),5970		.hw.init = &(const struct clk_init_data) {5971			.name = "gcc_usb30_prim_master_clk",5972			.parent_hws = (const struct clk_hw*[]){5973				&gcc_usb30_prim_master_clk_src.clkr.hw,5974			},5975			.num_parents = 1,5976			.flags = CLK_SET_RATE_PARENT,5977			.ops = &clk_branch2_ops,5978		},5979	},5980};5981 5982static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {5983	.halt_reg = 0xf01c,5984	.halt_check = BRANCH_HALT,5985	.clkr = {5986		.enable_reg = 0xf01c,5987		.enable_mask = BIT(0),5988		.hw.init = &(const struct clk_init_data) {5989			.name = "gcc_usb30_prim_mock_utmi_clk",5990			.parent_hws = (const struct clk_hw*[]){5991				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,5992			},5993			.num_parents = 1,5994			.flags = CLK_SET_RATE_PARENT,5995			.ops = &clk_branch2_ops,5996		},5997	},5998};5999 6000static struct clk_branch gcc_usb30_prim_sleep_clk = {6001	.halt_reg = 0xf018,6002	.halt_check = BRANCH_HALT,6003	.clkr = {6004		.enable_reg = 0xf018,6005		.enable_mask = BIT(0),6006		.hw.init = &(const struct clk_init_data) {6007			.name = "gcc_usb30_prim_sleep_clk",6008			.ops = &clk_branch2_ops,6009		},6010	},6011};6012 6013static struct clk_branch gcc_usb30_sec_master_clk = {6014	.halt_reg = 0x10010,6015	.halt_check = BRANCH_HALT,6016	.clkr = {6017		.enable_reg = 0x10010,6018		.enable_mask = BIT(0),6019		.hw.init = &(const struct clk_init_data) {6020			.name = "gcc_usb30_sec_master_clk",6021			.parent_hws = (const struct clk_hw*[]){6022				&gcc_usb30_sec_master_clk_src.clkr.hw,6023			},6024			.num_parents = 1,6025			.flags = CLK_SET_RATE_PARENT,6026			.ops = &clk_branch2_ops,6027		},6028	},6029};6030 6031static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {6032	.halt_reg = 0x1001c,6033	.halt_check = BRANCH_HALT,6034	.clkr = {6035		.enable_reg = 0x1001c,6036		.enable_mask = BIT(0),6037		.hw.init = &(const struct clk_init_data) {6038			.name = "gcc_usb30_sec_mock_utmi_clk",6039			.parent_hws = (const struct clk_hw*[]){6040				&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,6041			},6042			.num_parents = 1,6043			.flags = CLK_SET_RATE_PARENT,6044			.ops = &clk_branch2_ops,6045		},6046	},6047};6048 6049static struct clk_branch gcc_usb30_sec_sleep_clk = {6050	.halt_reg = 0x10018,6051	.halt_check = BRANCH_HALT,6052	.clkr = {6053		.enable_reg = 0x10018,6054		.enable_mask = BIT(0),6055		.hw.init = &(const struct clk_init_data) {6056			.name = "gcc_usb30_sec_sleep_clk",6057			.ops = &clk_branch2_ops,6058		},6059	},6060};6061 6062static struct clk_branch gcc_usb3_mp0_clkref_clk = {6063	.halt_reg = 0x8c03c,6064	.halt_check = BRANCH_HALT,6065	.clkr = {6066		.enable_reg = 0x8c03c,6067		.enable_mask = BIT(0),6068		.hw.init = &(const struct clk_init_data) {6069			.name = "gcc_usb3_mp0_clkref_clk",6070			.ops = &clk_branch2_ops,6071		},6072	},6073};6074 6075static struct clk_branch gcc_usb3_mp1_clkref_clk = {6076	.halt_reg = 0x8c040,6077	.halt_check = BRANCH_HALT,6078	.clkr = {6079		.enable_reg = 0x8c040,6080		.enable_mask = BIT(0),6081		.hw.init = &(const struct clk_init_data) {6082			.name = "gcc_usb3_mp1_clkref_clk",6083			.ops = &clk_branch2_ops,6084		},6085	},6086};6087 6088static struct clk_branch gcc_usb3_mp_phy_aux_clk = {6089	.halt_reg = 0xab054,6090	.halt_check = BRANCH_HALT,6091	.clkr = {6092		.enable_reg = 0xab054,6093		.enable_mask = BIT(0),6094		.hw.init = &(const struct clk_init_data) {6095			.name = "gcc_usb3_mp_phy_aux_clk",6096			.parent_hws = (const struct clk_hw*[]){6097				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,6098			},6099			.num_parents = 1,6100			.flags = CLK_SET_RATE_PARENT,6101			.ops = &clk_branch2_ops,6102		},6103	},6104};6105 6106static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {6107	.halt_reg = 0xab058,6108	.halt_check = BRANCH_HALT,6109	.clkr = {6110		.enable_reg = 0xab058,6111		.enable_mask = BIT(0),6112		.hw.init = &(const struct clk_init_data) {6113			.name = "gcc_usb3_mp_phy_com_aux_clk",6114			.parent_hws = (const struct clk_hw*[]){6115				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,6116			},6117			.num_parents = 1,6118			.flags = CLK_SET_RATE_PARENT,6119			.ops = &clk_branch2_ops,6120		},6121	},6122};6123 6124static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {6125	.halt_reg = 0xab05c,6126	.halt_check = BRANCH_HALT_DELAY,6127	.clkr = {6128		.enable_reg = 0xab05c,6129		.enable_mask = BIT(0),6130		.hw.init = &(const struct clk_init_data) {6131			.name = "gcc_usb3_mp_phy_pipe_0_clk",6132			.parent_hws = (const struct clk_hw*[]){6133				&gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw,6134			},6135			.num_parents = 1,6136			.flags = CLK_SET_RATE_PARENT,6137			.ops = &clk_branch2_ops,6138		},6139	},6140};6141 6142static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {6143	.halt_reg = 0xab064,6144	.halt_check = BRANCH_HALT_DELAY,6145	.clkr = {6146		.enable_reg = 0xab064,6147		.enable_mask = BIT(0),6148		.hw.init = &(const struct clk_init_data) {6149			.name = "gcc_usb3_mp_phy_pipe_1_clk",6150			.parent_hws = (const struct clk_hw*[]){6151				&gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw,6152			},6153			.num_parents = 1,6154			.flags = CLK_SET_RATE_PARENT,6155			.ops = &clk_branch2_ops,6156		},6157	},6158};6159 6160static struct clk_branch gcc_usb3_prim_phy_aux_clk = {6161	.halt_reg = 0xf054,6162	.halt_check = BRANCH_HALT,6163	.clkr = {6164		.enable_reg = 0xf054,6165		.enable_mask = BIT(0),6166		.hw.init = &(const struct clk_init_data) {6167			.name = "gcc_usb3_prim_phy_aux_clk",6168			.parent_hws = (const struct clk_hw*[]){6169				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,6170			},6171			.num_parents = 1,6172			.flags = CLK_SET_RATE_PARENT,6173			.ops = &clk_branch2_ops,6174		},6175	},6176};6177 6178static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {6179	.halt_reg = 0xf058,6180	.halt_check = BRANCH_HALT,6181	.clkr = {6182		.enable_reg = 0xf058,6183		.enable_mask = BIT(0),6184		.hw.init = &(const struct clk_init_data) {6185			.name = "gcc_usb3_prim_phy_com_aux_clk",6186			.parent_hws = (const struct clk_hw*[]){6187				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,6188			},6189			.num_parents = 1,6190			.flags = CLK_SET_RATE_PARENT,6191			.ops = &clk_branch2_ops,6192		},6193	},6194};6195 6196static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {6197	.halt_reg = 0xf05c,6198	.halt_check = BRANCH_HALT_DELAY,6199	.hwcg_reg = 0xf05c,6200	.hwcg_bit = 1,6201	.clkr = {6202		.enable_reg = 0xf05c,6203		.enable_mask = BIT(0),6204		.hw.init = &(const struct clk_init_data) {6205			.name = "gcc_usb3_prim_phy_pipe_clk",6206			.parent_hws = (const struct clk_hw*[]){6207				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,6208			},6209			.num_parents = 1,6210			.flags = CLK_SET_RATE_PARENT,6211			.ops = &clk_branch2_ops,6212		},6213	},6214};6215 6216static struct clk_branch gcc_usb3_sec_phy_aux_clk = {6217	.halt_reg = 0x10054,6218	.halt_check = BRANCH_HALT,6219	.clkr = {6220		.enable_reg = 0x10054,6221		.enable_mask = BIT(0),6222		.hw.init = &(const struct clk_init_data) {6223			.name = "gcc_usb3_sec_phy_aux_clk",6224			.parent_hws = (const struct clk_hw*[]){6225				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,6226			},6227			.num_parents = 1,6228			.flags = CLK_SET_RATE_PARENT,6229			.ops = &clk_branch2_ops,6230		},6231	},6232};6233 6234static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {6235	.halt_reg = 0x10058,6236	.halt_check = BRANCH_HALT,6237	.clkr = {6238		.enable_reg = 0x10058,6239		.enable_mask = BIT(0),6240		.hw.init = &(const struct clk_init_data) {6241			.name = "gcc_usb3_sec_phy_com_aux_clk",6242			.parent_hws = (const struct clk_hw*[]){6243				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,6244			},6245			.num_parents = 1,6246			.flags = CLK_SET_RATE_PARENT,6247			.ops = &clk_branch2_ops,6248		},6249	},6250};6251 6252static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {6253	.halt_reg = 0x1005c,6254	.halt_check = BRANCH_HALT_DELAY,6255	.hwcg_reg = 0x1005c,6256	.hwcg_bit = 1,6257	.clkr = {6258		.enable_reg = 0x1005c,6259		.enable_mask = BIT(0),6260		.hw.init = &(const struct clk_init_data) {6261			.name = "gcc_usb3_sec_phy_pipe_clk",6262			.parent_hws = (const struct clk_hw*[]){6263				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,6264			},6265			.num_parents = 1,6266			.flags = CLK_SET_RATE_PARENT,6267			.ops = &clk_branch2_ops,6268		},6269	},6270};6271 6272static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {6273	.halt_reg = 0xb808c,6274	.halt_check = BRANCH_HALT_VOTED,6275	.hwcg_reg = 0xb808c,6276	.hwcg_bit = 1,6277	.clkr = {6278		.enable_reg = 0xb808c,6279		.enable_mask = BIT(0),6280		.hw.init = &(const struct clk_init_data) {6281			.name = "gcc_usb4_1_cfg_ahb_clk",6282			.ops = &clk_branch2_ops,6283		},6284	},6285};6286 6287static struct clk_branch gcc_usb4_1_dp_clk = {6288	.halt_reg = 0xb8048,6289	.halt_check = BRANCH_HALT,6290	.clkr = {6291		.enable_reg = 0xb8048,6292		.enable_mask = BIT(0),6293		.hw.init = &(const struct clk_init_data) {6294			.name = "gcc_usb4_1_dp_clk",6295			.parent_hws = (const struct clk_hw*[]){6296				&gcc_usb4_1_phy_dp_clk_src.clkr.hw,6297			},6298			.num_parents = 1,6299			.flags = CLK_SET_RATE_PARENT,6300			.ops = &clk_branch2_ops,6301		},6302	},6303};6304 6305static struct clk_branch gcc_usb4_1_master_clk = {6306	.halt_reg = 0xb8010,6307	.halt_check = BRANCH_HALT,6308	.clkr = {6309		.enable_reg = 0xb8010,6310		.enable_mask = BIT(0),6311		.hw.init = &(const struct clk_init_data) {6312			.name = "gcc_usb4_1_master_clk",6313			.parent_hws = (const struct clk_hw*[]){6314				&gcc_usb4_1_master_clk_src.clkr.hw,6315			},6316			.num_parents = 1,6317			.flags = CLK_SET_RATE_PARENT,6318			.ops = &clk_branch2_ops,6319		},6320	},6321};6322 6323static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {6324	.halt_reg = 0xb80b4,6325	.halt_check = BRANCH_HALT_DELAY,6326	.clkr = {6327		.enable_reg = 0xb80b4,6328		.enable_mask = BIT(0),6329		.hw.init = &(const struct clk_init_data) {6330			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",6331			.parent_hws = (const struct clk_hw*[]){6332				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,6333			},6334			.num_parents = 1,6335			.flags = CLK_SET_RATE_PARENT,6336			.ops = &clk_branch2_ops,6337		},6338	},6339};6340 6341static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {6342	.halt_reg = 0xb8038,6343	.halt_check = BRANCH_HALT_DELAY,6344	.clkr = {6345		.enable_reg = 0x52020,6346		.enable_mask = BIT(19),6347		.hw.init = &(const struct clk_init_data) {6348			.name = "gcc_usb4_1_phy_pcie_pipe_clk",6349			.parent_hws = (const struct clk_hw*[]){6350				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,6351			},6352			.num_parents = 1,6353			.flags = CLK_SET_RATE_PARENT,6354			.ops = &clk_branch2_ops,6355		},6356	},6357};6358 6359static struct clk_branch gcc_usb4_1_phy_rx0_clk = {6360	.halt_reg = 0xb8094,6361	.halt_check = BRANCH_HALT,6362	.clkr = {6363		.enable_reg = 0xb8094,6364		.enable_mask = BIT(0),6365		.hw.init = &(const struct clk_init_data) {6366			.name = "gcc_usb4_1_phy_rx0_clk",6367			.parent_hws = (const struct clk_hw*[]){6368				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,6369			},6370			.num_parents = 1,6371			.flags = CLK_SET_RATE_PARENT,6372			.ops = &clk_branch2_ops,6373		},6374	},6375};6376 6377static struct clk_branch gcc_usb4_1_phy_rx1_clk = {6378	.halt_reg = 0xb80a0,6379	.halt_check = BRANCH_HALT,6380	.clkr = {6381		.enable_reg = 0xb80a0,6382		.enable_mask = BIT(0),6383		.hw.init = &(const struct clk_init_data) {6384			.name = "gcc_usb4_1_phy_rx1_clk",6385			.parent_hws = (const struct clk_hw*[]){6386				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,6387			},6388			.num_parents = 1,6389			.flags = CLK_SET_RATE_PARENT,6390			.ops = &clk_branch2_ops,6391		},6392	},6393};6394 6395static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {6396	.halt_reg = 0xb8088,6397	.halt_check = BRANCH_HALT_DELAY,6398	.hwcg_reg = 0xb8088,6399	.hwcg_bit = 1,6400	.clkr = {6401		.enable_reg = 0xb8088,6402		.enable_mask = BIT(0),6403		.hw.init = &(const struct clk_init_data) {6404			.name = "gcc_usb4_1_phy_usb_pipe_clk",6405			.parent_hws = (const struct clk_hw*[]){6406				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,6407			},6408			.num_parents = 1,6409			.flags = CLK_SET_RATE_PARENT,6410			.ops = &clk_branch2_ops,6411		},6412	},6413};6414 6415static struct clk_branch gcc_usb4_1_sb_if_clk = {6416	.halt_reg = 0xb8034,6417	.halt_check = BRANCH_HALT,6418	.clkr = {6419		.enable_reg = 0xb8034,6420		.enable_mask = BIT(0),6421		.hw.init = &(const struct clk_init_data) {6422			.name = "gcc_usb4_1_sb_if_clk",6423			.parent_hws = (const struct clk_hw*[]){6424				&gcc_usb4_1_sb_if_clk_src.clkr.hw,6425			},6426			.num_parents = 1,6427			.flags = CLK_SET_RATE_PARENT,6428			.ops = &clk_branch2_ops,6429		},6430	},6431};6432 6433static struct clk_branch gcc_usb4_1_sys_clk = {6434	.halt_reg = 0xb8040,6435	.halt_check = BRANCH_HALT,6436	.clkr = {6437		.enable_reg = 0xb8040,6438		.enable_mask = BIT(0),6439		.hw.init = &(const struct clk_init_data) {6440			.name = "gcc_usb4_1_sys_clk",6441			.parent_hws = (const struct clk_hw*[]){6442				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,6443			},6444			.num_parents = 1,6445			.flags = CLK_SET_RATE_PARENT,6446			.ops = &clk_branch2_ops,6447		},6448	},6449};6450 6451static struct clk_branch gcc_usb4_1_tmu_clk = {6452	.halt_reg = 0xb806c,6453	.halt_check = BRANCH_HALT_VOTED,6454	.hwcg_reg = 0xb806c,6455	.hwcg_bit = 1,6456	.clkr = {6457		.enable_reg = 0xb806c,6458		.enable_mask = BIT(0),6459		.hw.init = &(const struct clk_init_data) {6460			.name = "gcc_usb4_1_tmu_clk",6461			.parent_hws = (const struct clk_hw*[]){6462				&gcc_usb4_1_tmu_clk_src.clkr.hw,6463			},6464			.num_parents = 1,6465			.flags = CLK_SET_RATE_PARENT,6466			.ops = &clk_branch2_ops,6467		},6468	},6469};6470 6471static struct clk_branch gcc_usb4_cfg_ahb_clk = {6472	.halt_reg = 0x2a08c,6473	.halt_check = BRANCH_HALT_VOTED,6474	.hwcg_reg = 0x2a08c,6475	.hwcg_bit = 1,6476	.clkr = {6477		.enable_reg = 0x2a08c,6478		.enable_mask = BIT(0),6479		.hw.init = &(const struct clk_init_data) {6480			.name = "gcc_usb4_cfg_ahb_clk",6481			.ops = &clk_branch2_ops,6482		},6483	},6484};6485 6486static struct clk_branch gcc_usb4_clkref_clk = {6487	.halt_reg = 0x8c010,6488	.halt_check = BRANCH_HALT,6489	.clkr = {6490		.enable_reg = 0x8c010,6491		.enable_mask = BIT(0),6492		.hw.init = &(const struct clk_init_data) {6493			.name = "gcc_usb4_clkref_clk",6494			.ops = &clk_branch2_ops,6495		},6496	},6497};6498 6499static struct clk_branch gcc_usb4_dp_clk = {6500	.halt_reg = 0x2a048,6501	.halt_check = BRANCH_HALT,6502	.clkr = {6503		.enable_reg = 0x2a048,6504		.enable_mask = BIT(0),6505		.hw.init = &(const struct clk_init_data) {6506			.name = "gcc_usb4_dp_clk",6507			.parent_hws = (const struct clk_hw*[]){6508				&gcc_usb4_phy_dp_clk_src.clkr.hw,6509			},6510			.num_parents = 1,6511			.flags = CLK_SET_RATE_PARENT,6512			.ops = &clk_branch2_ops,6513		},6514	},6515};6516 6517static struct clk_branch gcc_usb4_eud_clkref_clk = {6518	.halt_reg = 0x8c02c,6519	.halt_check = BRANCH_HALT,6520	.clkr = {6521		.enable_reg = 0x8c02c,6522		.enable_mask = BIT(0),6523		.hw.init = &(const struct clk_init_data) {6524			.name = "gcc_usb4_eud_clkref_clk",6525			.ops = &clk_branch2_ops,6526		},6527	},6528};6529 6530static struct clk_branch gcc_usb4_master_clk = {6531	.halt_reg = 0x2a010,6532	.halt_check = BRANCH_HALT,6533	.clkr = {6534		.enable_reg = 0x2a010,6535		.enable_mask = BIT(0),6536		.hw.init = &(const struct clk_init_data) {6537			.name = "gcc_usb4_master_clk",6538			.parent_hws = (const struct clk_hw*[]){6539				&gcc_usb4_master_clk_src.clkr.hw,6540			},6541			.num_parents = 1,6542			.flags = CLK_SET_RATE_PARENT,6543			.ops = &clk_branch2_ops,6544		},6545	},6546};6547 6548static struct clk_branch gcc_usb4_phy_p2rr2p_pipe_clk = {6549	.halt_reg = 0x2a0b4,6550	.halt_check = BRANCH_HALT_DELAY,6551	.clkr = {6552		.enable_reg = 0x2a0b4,6553		.enable_mask = BIT(0),6554		.hw.init = &(const struct clk_init_data) {6555			.name = "gcc_usb4_phy_p2rr2p_pipe_clk",6556			.parent_hws = (const struct clk_hw*[]){6557				&gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr.hw,6558			},6559			.num_parents = 1,6560			.flags = CLK_SET_RATE_PARENT,6561			.ops = &clk_branch2_ops,6562		},6563	},6564};6565 6566static struct clk_branch gcc_usb4_phy_pcie_pipe_clk = {6567	.halt_reg = 0x2a038,6568	.halt_check = BRANCH_HALT_DELAY,6569	.clkr = {6570		.enable_reg = 0x52020,6571		.enable_mask = BIT(18),6572		.hw.init = &(const struct clk_init_data) {6573			.name = "gcc_usb4_phy_pcie_pipe_clk",6574			.parent_hws = (const struct clk_hw*[]){6575				&gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr.hw,6576			},6577			.num_parents = 1,6578			.flags = CLK_SET_RATE_PARENT,6579			.ops = &clk_branch2_ops,6580		},6581	},6582};6583 6584static struct clk_branch gcc_usb4_phy_rx0_clk = {6585	.halt_reg = 0x2a094,6586	.halt_check = BRANCH_HALT,6587	.clkr = {6588		.enable_reg = 0x2a094,6589		.enable_mask = BIT(0),6590		.hw.init = &(const struct clk_init_data) {6591			.name = "gcc_usb4_phy_rx0_clk",6592			.parent_hws = (const struct clk_hw*[]){6593				&gcc_usb4_phy_rx0_clk_src.clkr.hw,6594			},6595			.num_parents = 1,6596			.flags = CLK_SET_RATE_PARENT,6597			.ops = &clk_branch2_ops,6598		},6599	},6600};6601 6602static struct clk_branch gcc_usb4_phy_rx1_clk = {6603	.halt_reg = 0x2a0a0,6604	.halt_check = BRANCH_HALT,6605	.clkr = {6606		.enable_reg = 0x2a0a0,6607		.enable_mask = BIT(0),6608		.hw.init = &(const struct clk_init_data) {6609			.name = "gcc_usb4_phy_rx1_clk",6610			.parent_hws = (const struct clk_hw*[]){6611				&gcc_usb4_phy_rx1_clk_src.clkr.hw,6612			},6613			.num_parents = 1,6614			.flags = CLK_SET_RATE_PARENT,6615			.ops = &clk_branch2_ops,6616		},6617	},6618};6619 6620static struct clk_branch gcc_usb4_phy_usb_pipe_clk = {6621	.halt_reg = 0x2a088,6622	.halt_check = BRANCH_HALT_DELAY,6623	.hwcg_reg = 0x2a088,6624	.hwcg_bit = 1,6625	.clkr = {6626		.enable_reg = 0x2a088,6627		.enable_mask = BIT(0),6628		.hw.init = &(const struct clk_init_data) {6629			.name = "gcc_usb4_phy_usb_pipe_clk",6630			.parent_hws = (const struct clk_hw*[]){6631				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,6632			},6633			.num_parents = 1,6634			.flags = CLK_SET_RATE_PARENT,6635			.ops = &clk_branch2_ops,6636		},6637	},6638};6639 6640static struct clk_branch gcc_usb4_sb_if_clk = {6641	.halt_reg = 0x2a034,6642	.halt_check = BRANCH_HALT,6643	.clkr = {6644		.enable_reg = 0x2a034,6645		.enable_mask = BIT(0),6646		.hw.init = &(const struct clk_init_data) {6647			.name = "gcc_usb4_sb_if_clk",6648			.parent_hws = (const struct clk_hw*[]){6649				&gcc_usb4_sb_if_clk_src.clkr.hw,6650			},6651			.num_parents = 1,6652			.flags = CLK_SET_RATE_PARENT,6653			.ops = &clk_branch2_ops,6654		},6655	},6656};6657 6658static struct clk_branch gcc_usb4_sys_clk = {6659	.halt_reg = 0x2a040,6660	.halt_check = BRANCH_HALT,6661	.clkr = {6662		.enable_reg = 0x2a040,6663		.enable_mask = BIT(0),6664		.hw.init = &(const struct clk_init_data) {6665			.name = "gcc_usb4_sys_clk",6666			.parent_hws = (const struct clk_hw*[]){6667				&gcc_usb4_phy_sys_clk_src.clkr.hw,6668			},6669			.num_parents = 1,6670			.flags = CLK_SET_RATE_PARENT,6671			.ops = &clk_branch2_ops,6672		},6673	},6674};6675 6676static struct clk_branch gcc_usb4_tmu_clk = {6677	.halt_reg = 0x2a06c,6678	.halt_check = BRANCH_HALT_VOTED,6679	.hwcg_reg = 0x2a06c,6680	.hwcg_bit = 1,6681	.clkr = {6682		.enable_reg = 0x2a06c,6683		.enable_mask = BIT(0),6684		.hw.init = &(const struct clk_init_data) {6685			.name = "gcc_usb4_tmu_clk",6686			.parent_hws = (const struct clk_hw*[]){6687				&gcc_usb4_tmu_clk_src.clkr.hw,6688			},6689			.num_parents = 1,6690			.flags = CLK_SET_RATE_PARENT,6691			.ops = &clk_branch2_ops,6692		},6693	},6694};6695 6696static struct clk_branch gcc_video_axi0_clk = {6697	.halt_reg = 0x28010,6698	.halt_check = BRANCH_HALT_SKIP,6699	.hwcg_reg = 0x28010,6700	.hwcg_bit = 1,6701	.clkr = {6702		.enable_reg = 0x28010,6703		.enable_mask = BIT(0),6704		.hw.init = &(const struct clk_init_data) {6705			.name = "gcc_video_axi0_clk",6706			.ops = &clk_branch2_ops,6707		},6708	},6709};6710 6711static struct clk_branch gcc_video_axi1_clk = {6712	.halt_reg = 0x28018,6713	.halt_check = BRANCH_HALT_SKIP,6714	.hwcg_reg = 0x28018,6715	.hwcg_bit = 1,6716	.clkr = {6717		.enable_reg = 0x28018,6718		.enable_mask = BIT(0),6719		.hw.init = &(const struct clk_init_data) {6720			.name = "gcc_video_axi1_clk",6721			.ops = &clk_branch2_ops,6722		},6723	},6724};6725 6726static struct clk_branch gcc_video_cvp_throttle_clk = {6727	.halt_reg = 0x28024,6728	.halt_check = BRANCH_HALT_SKIP,6729	.hwcg_reg = 0x28024,6730	.hwcg_bit = 1,6731	.clkr = {6732		.enable_reg = 0x28024,6733		.enable_mask = BIT(0),6734		.hw.init = &(const struct clk_init_data) {6735			.name = "gcc_video_cvp_throttle_clk",6736			.ops = &clk_branch2_ops,6737		},6738	},6739};6740 6741static struct clk_branch gcc_video_vcodec_throttle_clk = {6742	.halt_reg = 0x28020,6743	.halt_check = BRANCH_HALT_SKIP,6744	.hwcg_reg = 0x28020,6745	.hwcg_bit = 1,6746	.clkr = {6747		.enable_reg = 0x28020,6748		.enable_mask = BIT(0),6749		.hw.init = &(const struct clk_init_data) {6750			.name = "gcc_video_vcodec_throttle_clk",6751			.ops = &clk_branch2_ops,6752		},6753	},6754};6755 6756static struct gdsc pcie_0_tunnel_gdsc = {6757	.gdscr = 0xa4004,6758	.collapse_ctrl = 0x52128,6759	.collapse_mask = BIT(0),6760	.pd = {6761		.name = "pcie_0_tunnel_gdsc",6762	},6763	.pwrsts = PWRSTS_OFF_ON,6764	.flags = VOTABLE | RETAIN_FF_ENABLE,6765};6766 6767static struct gdsc pcie_1_tunnel_gdsc = {6768	.gdscr = 0x8d004,6769	.collapse_ctrl = 0x52128,6770	.collapse_mask = BIT(1),6771	.pd = {6772		.name = "pcie_1_tunnel_gdsc",6773	},6774	.pwrsts = PWRSTS_OFF_ON,6775	.flags = VOTABLE | RETAIN_FF_ENABLE,6776};6777 6778/*6779 * The Qualcomm PCIe driver does not yet implement suspend so to keep the6780 * PCIe power domains always-on for now.6781 */6782static struct gdsc pcie_2a_gdsc = {6783	.gdscr = 0x9d004,6784	.collapse_ctrl = 0x52128,6785	.collapse_mask = BIT(2),6786	.pd = {6787		.name = "pcie_2a_gdsc",6788	},6789	.pwrsts = PWRSTS_RET_ON,6790	.flags = VOTABLE | RETAIN_FF_ENABLE,6791};6792 6793static struct gdsc pcie_2b_gdsc = {6794	.gdscr = 0x9e004,6795	.collapse_ctrl = 0x52128,6796	.collapse_mask = BIT(3),6797	.pd = {6798		.name = "pcie_2b_gdsc",6799	},6800	.pwrsts = PWRSTS_RET_ON,6801	.flags = VOTABLE | RETAIN_FF_ENABLE,6802};6803 6804static struct gdsc pcie_3a_gdsc = {6805	.gdscr = 0xa0004,6806	.collapse_ctrl = 0x52128,6807	.collapse_mask = BIT(4),6808	.pd = {6809		.name = "pcie_3a_gdsc",6810	},6811	.pwrsts = PWRSTS_RET_ON,6812	.flags = VOTABLE | RETAIN_FF_ENABLE,6813};6814 6815static struct gdsc pcie_3b_gdsc = {6816	.gdscr = 0xa2004,6817	.collapse_ctrl = 0x52128,6818	.collapse_mask = BIT(5),6819	.pd = {6820		.name = "pcie_3b_gdsc",6821	},6822	.pwrsts = PWRSTS_RET_ON,6823	.flags = VOTABLE | RETAIN_FF_ENABLE,6824};6825 6826static struct gdsc pcie_4_gdsc = {6827	.gdscr = 0x6b004,6828	.collapse_ctrl = 0x52128,6829	.collapse_mask = BIT(6),6830	.pd = {6831		.name = "pcie_4_gdsc",6832	},6833	.pwrsts = PWRSTS_RET_ON,6834	.flags = VOTABLE | RETAIN_FF_ENABLE,6835};6836 6837static struct gdsc ufs_card_gdsc = {6838	.gdscr = 0x75004,6839	.pd = {6840		.name = "ufs_card_gdsc",6841	},6842	.pwrsts = PWRSTS_OFF_ON,6843	.flags = RETAIN_FF_ENABLE,6844};6845 6846static struct gdsc ufs_phy_gdsc = {6847	.gdscr = 0x77004,6848	.pd = {6849		.name = "ufs_phy_gdsc",6850	},6851	.pwrsts = PWRSTS_OFF_ON,6852	.flags = RETAIN_FF_ENABLE,6853};6854 6855static struct gdsc usb30_mp_gdsc = {6856	.gdscr = 0xab004,6857	.pd = {6858		.name = "usb30_mp_gdsc",6859	},6860	.pwrsts = PWRSTS_RET_ON,6861	.flags = RETAIN_FF_ENABLE,6862};6863 6864static struct gdsc usb30_prim_gdsc = {6865	.gdscr = 0xf004,6866	.pd = {6867		.name = "usb30_prim_gdsc",6868	},6869	.pwrsts = PWRSTS_RET_ON,6870	.flags = RETAIN_FF_ENABLE,6871};6872 6873static struct gdsc usb30_sec_gdsc = {6874	.gdscr = 0x10004,6875	.pd = {6876		.name = "usb30_sec_gdsc",6877	},6878	.pwrsts = PWRSTS_RET_ON,6879	.flags = RETAIN_FF_ENABLE,6880};6881 6882static struct gdsc emac_0_gdsc = {6883	.gdscr = 0xaa004,6884	.pd = {6885		.name = "emac_0_gdsc",6886	},6887	.pwrsts = PWRSTS_OFF_ON,6888	.flags = RETAIN_FF_ENABLE,6889};6890 6891static struct gdsc emac_1_gdsc = {6892	.gdscr = 0xba004,6893	.pd = {6894		.name = "emac_1_gdsc",6895	},6896	.pwrsts = PWRSTS_OFF_ON,6897	.flags = RETAIN_FF_ENABLE,6898};6899 6900static struct gdsc usb4_1_gdsc = {6901	.gdscr = 0xb8004,6902	.pd = {6903		.name = "usb4_1_gdsc",6904	},6905	.pwrsts = PWRSTS_OFF_ON,6906	.flags = RETAIN_FF_ENABLE,6907};6908 6909static struct gdsc usb4_gdsc = {6910	.gdscr = 0x2a004,6911	.pd = {6912		.name = "usb4_gdsc",6913	},6914	.pwrsts = PWRSTS_OFF_ON,6915	.flags = RETAIN_FF_ENABLE,6916};6917 6918static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {6919	.gdscr = 0x7d050,6920	.pd = {6921		.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",6922	},6923	.pwrsts = PWRSTS_OFF_ON,6924	.flags = VOTABLE,6925};6926 6927static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {6928	.gdscr = 0x7d058,6929	.pd = {6930		.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",6931	},6932	.pwrsts = PWRSTS_OFF_ON,6933	.flags = VOTABLE,6934};6935 6936static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {6937	.gdscr = 0x7d054,6938	.pd = {6939		.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",6940	},6941	.pwrsts = PWRSTS_OFF_ON,6942	.flags = VOTABLE,6943};6944 6945static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {6946	.gdscr = 0x7d06c,6947	.pd = {6948		.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",6949	},6950	.pwrsts = PWRSTS_OFF_ON,6951	.flags = VOTABLE,6952};6953 6954static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {6955	.gdscr = 0x7d05c,6956	.pd = {6957		.name = "hlos1_vote_turing_mmu_tbu0_gdsc",6958	},6959	.pwrsts = PWRSTS_OFF_ON,6960	.flags = VOTABLE,6961};6962 6963static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {6964	.gdscr = 0x7d060,6965	.pd = {6966		.name = "hlos1_vote_turing_mmu_tbu1_gdsc",6967	},6968	.pwrsts = PWRSTS_OFF_ON,6969	.flags = VOTABLE,6970};6971 6972static struct gdsc hlos1_vote_turing_mmu_tbu2_gdsc = {6973	.gdscr = 0x7d0a0,6974	.pd = {6975		.name = "hlos1_vote_turing_mmu_tbu2_gdsc",6976	},6977	.pwrsts = PWRSTS_OFF_ON,6978	.flags = VOTABLE,6979};6980 6981static struct gdsc hlos1_vote_turing_mmu_tbu3_gdsc = {6982	.gdscr = 0x7d0a4,6983	.pd = {6984		.name = "hlos1_vote_turing_mmu_tbu3_gdsc",6985	},6986	.pwrsts = PWRSTS_OFF_ON,6987	.flags = VOTABLE,6988};6989 6990static struct clk_regmap *gcc_sc8280xp_clocks[] = {6991	[GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr,6992	[GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr,6993	[GCC_AGGRE_NOC_PCIE_4_AXI_CLK] = &gcc_aggre_noc_pcie_4_axi_clk.clkr,6994	[GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_aggre_noc_pcie_south_sf_axi_clk.clkr,6995	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,6996	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,6997	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,6998	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,6999	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,7000	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,7001	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,7002	[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,7003	[GCC_AGGRE_USB4_AXI_CLK] = &gcc_aggre_usb4_axi_clk.clkr,7004	[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,7005	[GCC_AGGRE_USB_NOC_NORTH_AXI_CLK] = &gcc_aggre_usb_noc_north_axi_clk.clkr,7006	[GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK] = &gcc_aggre_usb_noc_south_axi_clk.clkr,7007	[GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,7008	[GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,7009	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,7010	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,7011	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,7012	[GCC_CAMERA_THROTTLE_NRT_AXI_CLK] = &gcc_camera_throttle_nrt_axi_clk.clkr,7013	[GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,7014	[GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,7015	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,7016	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,7017	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,7018	[GCC_CNOC_PCIE0_TUNNEL_CLK] = &gcc_cnoc_pcie0_tunnel_clk.clkr,7019	[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,7020	[GCC_CNOC_PCIE4_QX_CLK] = &gcc_cnoc_pcie4_qx_clk.clkr,7021	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,7022	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,7023	[GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,7024	[GCC_DISP1_SF_AXI_CLK] = &gcc_disp1_sf_axi_clk.clkr,7025	[GCC_DISP1_THROTTLE_NRT_AXI_CLK] = &gcc_disp1_throttle_nrt_axi_clk.clkr,7026	[GCC_DISP1_THROTTLE_RT_AXI_CLK] = &gcc_disp1_throttle_rt_axi_clk.clkr,7027	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,7028	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,7029	[GCC_DISP_THROTTLE_NRT_AXI_CLK] = &gcc_disp_throttle_nrt_axi_clk.clkr,7030	[GCC_DISP_THROTTLE_RT_AXI_CLK] = &gcc_disp_throttle_rt_axi_clk.clkr,7031	[GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,7032	[GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,7033	[GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,7034	[GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,7035	[GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,7036	[GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,7037	[GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,7038	[GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,7039	[GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,7040	[GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,7041	[GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,7042	[GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,7043	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,7044	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,7045	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,7046	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,7047	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,7048	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,7049	[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,7050	[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,7051	[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,7052	[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,7053	[GCC_GPLL0] = &gcc_gpll0.clkr,7054	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,7055	[GCC_GPLL2] = &gcc_gpll2.clkr,7056	[GCC_GPLL4] = &gcc_gpll4.clkr,7057	[GCC_GPLL7] = &gcc_gpll7.clkr,7058	[GCC_GPLL8] = &gcc_gpll8.clkr,7059	[GCC_GPLL9] = &gcc_gpll9.clkr,7060	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,7061	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,7062	[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,7063	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,7064	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,7065	[GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,7066	[GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,7067	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,7068	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,7069	[GCC_PCIE2A_PHY_RCHNG_CLK] = &gcc_pcie2a_phy_rchng_clk.clkr,7070	[GCC_PCIE2B_PHY_RCHNG_CLK] = &gcc_pcie2b_phy_rchng_clk.clkr,7071	[GCC_PCIE3A_PHY_RCHNG_CLK] = &gcc_pcie3a_phy_rchng_clk.clkr,7072	[GCC_PCIE3B_PHY_RCHNG_CLK] = &gcc_pcie3b_phy_rchng_clk.clkr,7073	[GCC_PCIE4_PHY_RCHNG_CLK] = &gcc_pcie4_phy_rchng_clk.clkr,7074	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,7075	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,7076	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,7077	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,7078	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,7079	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,7080	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,7081	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,7082	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,7083	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,7084	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,7085	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,7086	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,7087	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,7088	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,7089	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,7090	[GCC_PCIE_2A2B_CLKREF_CLK] = &gcc_pcie_2a2b_clkref_clk.clkr,7091	[GCC_PCIE_2A_AUX_CLK] = &gcc_pcie_2a_aux_clk.clkr,7092	[GCC_PCIE_2A_AUX_CLK_SRC] = &gcc_pcie_2a_aux_clk_src.clkr,7093	[GCC_PCIE_2A_CFG_AHB_CLK] = &gcc_pcie_2a_cfg_ahb_clk.clkr,7094	[GCC_PCIE_2A_MSTR_AXI_CLK] = &gcc_pcie_2a_mstr_axi_clk.clkr,7095	[GCC_PCIE_2A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2a_phy_rchng_clk_src.clkr,7096	[GCC_PCIE_2A_PIPE_CLK] = &gcc_pcie_2a_pipe_clk.clkr,7097	[GCC_PCIE_2A_PIPE_CLK_SRC] = &gcc_pcie_2a_pipe_clk_src.clkr,7098	[GCC_PCIE_2A_PIPE_DIV_CLK_SRC] = &gcc_pcie_2a_pipe_div_clk_src.clkr,7099	[GCC_PCIE_2A_PIPEDIV2_CLK] = &gcc_pcie_2a_pipediv2_clk.clkr,7100	[GCC_PCIE_2A_SLV_AXI_CLK] = &gcc_pcie_2a_slv_axi_clk.clkr,7101	[GCC_PCIE_2A_SLV_Q2A_AXI_CLK] = &gcc_pcie_2a_slv_q2a_axi_clk.clkr,7102	[GCC_PCIE_2B_AUX_CLK] = &gcc_pcie_2b_aux_clk.clkr,7103	[GCC_PCIE_2B_AUX_CLK_SRC] = &gcc_pcie_2b_aux_clk_src.clkr,7104	[GCC_PCIE_2B_CFG_AHB_CLK] = &gcc_pcie_2b_cfg_ahb_clk.clkr,7105	[GCC_PCIE_2B_MSTR_AXI_CLK] = &gcc_pcie_2b_mstr_axi_clk.clkr,7106	[GCC_PCIE_2B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2b_phy_rchng_clk_src.clkr,7107	[GCC_PCIE_2B_PIPE_CLK] = &gcc_pcie_2b_pipe_clk.clkr,7108	[GCC_PCIE_2B_PIPE_CLK_SRC] = &gcc_pcie_2b_pipe_clk_src.clkr,7109	[GCC_PCIE_2B_PIPE_DIV_CLK_SRC] = &gcc_pcie_2b_pipe_div_clk_src.clkr,7110	[GCC_PCIE_2B_PIPEDIV2_CLK] = &gcc_pcie_2b_pipediv2_clk.clkr,7111	[GCC_PCIE_2B_SLV_AXI_CLK] = &gcc_pcie_2b_slv_axi_clk.clkr,7112	[GCC_PCIE_2B_SLV_Q2A_AXI_CLK] = &gcc_pcie_2b_slv_q2a_axi_clk.clkr,7113	[GCC_PCIE_3A3B_CLKREF_CLK] = &gcc_pcie_3a3b_clkref_clk.clkr,7114	[GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr,7115	[GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr,7116	[GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr,7117	[GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr,7118	[GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr,7119	[GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr,7120	[GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr,7121	[GCC_PCIE_3A_PIPE_DIV_CLK_SRC] = &gcc_pcie_3a_pipe_div_clk_src.clkr,7122	[GCC_PCIE_3A_PIPEDIV2_CLK] = &gcc_pcie_3a_pipediv2_clk.clkr,7123	[GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr,7124	[GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr,7125	[GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr,7126	[GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr,7127	[GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr,7128	[GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr,7129	[GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr,7130	[GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr,7131	[GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr,7132	[GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr,7133	[GCC_PCIE_3B_PIPEDIV2_CLK] = &gcc_pcie_3b_pipediv2_clk.clkr,7134	[GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr,7135	[GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr,7136	[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,7137	[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,7138	[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,7139	[GCC_PCIE_4_CLKREF_CLK] = &gcc_pcie_4_clkref_clk.clkr,7140	[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,7141	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,7142	[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,7143	[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,7144	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,7145	[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,7146	[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,7147	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,7148	[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,7149	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,7150	[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,7151	[GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,7152	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,7153	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,7154	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,7155	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,7156	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,7157	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,7158	[GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,7159	[GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,7160	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,7161	[GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,7162	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,7163	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,7164	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,7165	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,7166	[GCC_QUPV3_WRAP0_QSPI0_CLK] = &gcc_qupv3_wrap0_qspi0_clk.clkr,7167	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,7168	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,7169	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,7170	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,7171	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,7172	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,7173	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,7174	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,7175	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,7176	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,7177	[GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s4_div_clk_src.clkr,7178	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,7179	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,7180	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,7181	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,7182	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,7183	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,7184	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,7185	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,7186	[GCC_QUPV3_WRAP1_QSPI0_CLK] = &gcc_qupv3_wrap1_qspi0_clk.clkr,7187	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,7188	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,7189	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,7190	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,7191	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,7192	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,7193	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,7194	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,7195	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,7196	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,7197	[GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s4_div_clk_src.clkr,7198	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,7199	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,7200	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,7201	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,7202	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,7203	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,7204	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,7205	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,7206	[GCC_QUPV3_WRAP2_QSPI0_CLK] = &gcc_qupv3_wrap2_qspi0_clk.clkr,7207	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,7208	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,7209	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,7210	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,7211	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,7212	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,7213	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,7214	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,7215	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,7216	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,7217	[GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s4_div_clk_src.clkr,7218	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,7219	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,7220	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,7221	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,7222	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,7223	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,7224	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,7225	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,7226	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,7227	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,7228	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,7229	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,7230	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,7231	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,7232	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,7233	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,7234	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,7235	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,7236	[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,7237	[GCC_UFS_1_CARD_CLKREF_CLK] = &gcc_ufs_1_card_clkref_clk.clkr,7238	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,7239	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,7240	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,7241	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,7242	[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,7243	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,7244	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,7245	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,7246	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,7247	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,7248	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,7249	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,7250	[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,7251	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,7252	[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,7253	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,7254	[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,7255	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,7256	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,7257	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,7258	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,7259	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,7260	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,7261	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,7262	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,7263	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,7264	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,7265	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,7266	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,7267	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,7268	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,7269	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,7270	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,7271	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,7272	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,7273	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,7274	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,7275	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,7276	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,7277	[GCC_UFS_REF_CLKREF_CLK] = &gcc_ufs_ref_clkref_clk.clkr,7278	[GCC_USB2_HS0_CLKREF_CLK] = &gcc_usb2_hs0_clkref_clk.clkr,7279	[GCC_USB2_HS1_CLKREF_CLK] = &gcc_usb2_hs1_clkref_clk.clkr,7280	[GCC_USB2_HS2_CLKREF_CLK] = &gcc_usb2_hs2_clkref_clk.clkr,7281	[GCC_USB2_HS3_CLKREF_CLK] = &gcc_usb2_hs3_clkref_clk.clkr,7282	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,7283	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,7284	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,7285	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,7286	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,7287	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,7288	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,7289	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,7290	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,7291	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,7292	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,7293	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,7294	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,7295	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,7296	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,7297	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,7298	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,7299	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,7300	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,7301	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,7302	[GCC_USB3_MP0_CLKREF_CLK] = &gcc_usb3_mp0_clkref_clk.clkr,7303	[GCC_USB3_MP1_CLKREF_CLK] = &gcc_usb3_mp1_clkref_clk.clkr,7304	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,7305	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,7306	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,7307	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,7308	[GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr,7309	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,7310	[GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr,7311	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,7312	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,7313	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,7314	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,7315	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,7316	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,7317	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,7318	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,7319	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,7320	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,7321	[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,7322	[GCC_USB4_1_DP_CLK] = &gcc_usb4_1_dp_clk.clkr,7323	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,7324	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,7325	[GCC_USB4_1_PHY_DP_CLK_SRC] = &gcc_usb4_1_phy_dp_clk_src.clkr,7326	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,7327	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,7328	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,7329	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,7330	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,7331	[GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipegmux_clk_src.clkr,7332	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,7333	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,7334	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,7335	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,7336	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,7337	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,7338	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,7339	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,7340	[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,7341	[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,7342	[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,7343	[GCC_USB4_CFG_AHB_CLK] = &gcc_usb4_cfg_ahb_clk.clkr,7344	[GCC_USB4_CLKREF_CLK] = &gcc_usb4_clkref_clk.clkr,7345	[GCC_USB4_DP_CLK] = &gcc_usb4_dp_clk.clkr,7346	[GCC_USB4_EUD_CLKREF_CLK] = &gcc_usb4_eud_clkref_clk.clkr,7347	[GCC_USB4_MASTER_CLK] = &gcc_usb4_master_clk.clkr,7348	[GCC_USB4_MASTER_CLK_SRC] = &gcc_usb4_master_clk_src.clkr,7349	[GCC_USB4_PHY_DP_CLK_SRC] = &gcc_usb4_phy_dp_clk_src.clkr,7350	[GCC_USB4_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_phy_p2rr2p_pipe_clk.clkr,7351	[GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_phy_p2rr2p_pipe_clk_src.clkr,7352	[GCC_USB4_PHY_PCIE_PIPE_CLK] = &gcc_usb4_phy_pcie_pipe_clk.clkr,7353	[GCC_USB4_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_clk_src.clkr,7354	[GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipe_mux_clk_src.clkr,7355	[GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC] = &gcc_usb4_phy_pcie_pipegmux_clk_src.clkr,7356	[GCC_USB4_PHY_RX0_CLK] = &gcc_usb4_phy_rx0_clk.clkr,7357	[GCC_USB4_PHY_RX0_CLK_SRC] = &gcc_usb4_phy_rx0_clk_src.clkr,7358	[GCC_USB4_PHY_RX1_CLK] = &gcc_usb4_phy_rx1_clk.clkr,7359	[GCC_USB4_PHY_RX1_CLK_SRC] = &gcc_usb4_phy_rx1_clk_src.clkr,7360	[GCC_USB4_PHY_SYS_CLK_SRC] = &gcc_usb4_phy_sys_clk_src.clkr,7361	[GCC_USB4_PHY_USB_PIPE_CLK] = &gcc_usb4_phy_usb_pipe_clk.clkr,7362	[GCC_USB4_SB_IF_CLK] = &gcc_usb4_sb_if_clk.clkr,7363	[GCC_USB4_SB_IF_CLK_SRC] = &gcc_usb4_sb_if_clk_src.clkr,7364	[GCC_USB4_SYS_CLK] = &gcc_usb4_sys_clk.clkr,7365	[GCC_USB4_TMU_CLK] = &gcc_usb4_tmu_clk.clkr,7366	[GCC_USB4_TMU_CLK_SRC] = &gcc_usb4_tmu_clk_src.clkr,7367	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,7368	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,7369	[GCC_VIDEO_CVP_THROTTLE_CLK] = &gcc_video_cvp_throttle_clk.clkr,7370	[GCC_VIDEO_VCODEC_THROTTLE_CLK] = &gcc_video_vcodec_throttle_clk.clkr,7371};7372 7373static const struct qcom_reset_map gcc_sc8280xp_resets[] = {7374	[GCC_EMAC0_BCR] = { 0xaa000 },7375	[GCC_EMAC1_BCR] = { 0xba000 },7376	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },7377	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },7378	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },7379	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },7380	[GCC_PCIE_0_TUNNEL_BCR] = { 0xa4000 },7381	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },7382	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },7383	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },7384	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },7385	[GCC_PCIE_1_TUNNEL_BCR] = { 0x8d000 },7386	[GCC_PCIE_2A_BCR] = { 0x9d000 },7387	[GCC_PCIE_2A_LINK_DOWN_BCR] = { 0x9d13c },7388	[GCC_PCIE_2A_NOCSR_COM_PHY_BCR] = { 0x9d148 },7389	[GCC_PCIE_2A_PHY_BCR] = { 0x9d144 },7390	[GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR] = { 0x9d14c },7391	[GCC_PCIE_2B_BCR] = { 0x9e000 },7392	[GCC_PCIE_2B_LINK_DOWN_BCR] = { 0x9e084 },7393	[GCC_PCIE_2B_NOCSR_COM_PHY_BCR] = { 0x9e090 },7394	[GCC_PCIE_2B_PHY_BCR] = { 0x9e08c },7395	[GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR] = { 0x9e094 },7396	[GCC_PCIE_3A_BCR] = { 0xa0000 },7397	[GCC_PCIE_3A_LINK_DOWN_BCR] = { 0xa00f0 },7398	[GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0xa00fc },7399	[GCC_PCIE_3A_PHY_BCR] = { 0xa00e0 },7400	[GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0xa00e4 },7401	[GCC_PCIE_3B_BCR] = { 0xa2000 },7402	[GCC_PCIE_3B_LINK_DOWN_BCR] = { 0xa20e0 },7403	[GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0xa20ec },7404	[GCC_PCIE_3B_PHY_BCR] = { 0xa20e8 },7405	[GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0xa20f0 },7406	[GCC_PCIE_4_BCR] = { 0x6b000 },7407	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0x6b300 },7408	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x6b30c },7409	[GCC_PCIE_4_PHY_BCR] = { 0x6b308 },7410	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x6b310 },7411	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },7412	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },7413	[GCC_PCIE_RSCC_BCR] = { 0xae000 },7414	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x12008 },7415	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x1200c },7416	[GCC_QUSB2PHY_HS2_MP_BCR] = { 0x12010 },7417	[GCC_QUSB2PHY_HS3_MP_BCR] = { 0x12014 },7418	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },7419	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },7420	[GCC_SDCC2_BCR] = { 0x14000 },7421	[GCC_SDCC4_BCR] = { 0x16000 },7422	[GCC_UFS_CARD_BCR] = { 0x75000 },7423	[GCC_UFS_PHY_BCR] = { 0x77000 },7424	[GCC_USB2_PHY_PRIM_BCR] = { 0x50028 },7425	[GCC_USB2_PHY_SEC_BCR] = { 0x5002c },7426	[GCC_USB30_MP_BCR] = { 0xab000 },7427	[GCC_USB30_PRIM_BCR] = { 0xf000 },7428	[GCC_USB30_SEC_BCR] = { 0x10000 },7429	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },7430	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },7431	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },7432	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },7433	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x50018 },7434	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5001c },7435	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },7436	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },7437	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x50020 },7438	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50024 },7439	[GCC_USB4_1_BCR] = { 0xb8000 },7440	[GCC_USB4_1_DP_PHY_PRIM_BCR] = { 0xb9020 },7441	[GCC_USB4_1_DPPHY_AUX_BCR] = { 0xb9024 },7442	[GCC_USB4_1_PHY_PRIM_BCR] = { 0xb9018 },7443	[GCC_USB4_BCR] = { 0x2a000 },7444	[GCC_USB4_DP_PHY_PRIM_BCR] = { 0x4a008 },7445	[GCC_USB4_DPPHY_AUX_BCR] = { 0x4a00c },7446	[GCC_USB4_PHY_PRIM_BCR] = { 0x4a000 },7447	[GCC_USB4PHY_1_PHY_PRIM_BCR] = { 0xb901c },7448	[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },7449	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },7450	[GCC_VIDEO_BCR] = { 0x28000 },7451	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },7452	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },7453};7454 7455static struct gdsc *gcc_sc8280xp_gdscs[] = {7456	[PCIE_0_TUNNEL_GDSC] = &pcie_0_tunnel_gdsc,7457	[PCIE_1_TUNNEL_GDSC] = &pcie_1_tunnel_gdsc,7458	[PCIE_2A_GDSC] = &pcie_2a_gdsc,7459	[PCIE_2B_GDSC] = &pcie_2b_gdsc,7460	[PCIE_3A_GDSC] = &pcie_3a_gdsc,7461	[PCIE_3B_GDSC] = &pcie_3b_gdsc,7462	[PCIE_4_GDSC] = &pcie_4_gdsc,7463	[UFS_CARD_GDSC] = &ufs_card_gdsc,7464	[UFS_PHY_GDSC] = &ufs_phy_gdsc,7465	[USB30_MP_GDSC] = &usb30_mp_gdsc,7466	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,7467	[USB30_SEC_GDSC] = &usb30_sec_gdsc,7468	[EMAC_0_GDSC] = &emac_0_gdsc,7469	[EMAC_1_GDSC] = &emac_1_gdsc,7470	[USB4_1_GDSC] = &usb4_1_gdsc,7471	[USB4_GDSC] = &usb4_gdsc,7472	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,7473	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,7474	[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,7475	[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,7476	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,7477	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,7478	[HLOS1_VOTE_TURING_MMU_TBU2_GDSC] = &hlos1_vote_turing_mmu_tbu2_gdsc,7479	[HLOS1_VOTE_TURING_MMU_TBU3_GDSC] = &hlos1_vote_turing_mmu_tbu3_gdsc,7480};7481 7482static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {7483	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),7484	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),7485	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),7486	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),7487	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),7488	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),7489	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),7490	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),7491	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),7492	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),7493	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),7494	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),7495	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),7496	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),7497	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),7498	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),7499	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),7500	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),7501	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),7502	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),7503	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),7504	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),7505	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),7506	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),7507};7508 7509static const struct regmap_config gcc_sc8280xp_regmap_config = {7510	.reg_bits = 32,7511	.reg_stride = 4,7512	.val_bits = 32,7513	.max_register = 0xc3014,7514	.fast_io = true,7515};7516 7517static const struct qcom_cc_desc gcc_sc8280xp_desc = {7518	.config = &gcc_sc8280xp_regmap_config,7519	.clks = gcc_sc8280xp_clocks,7520	.num_clks = ARRAY_SIZE(gcc_sc8280xp_clocks),7521	.resets = gcc_sc8280xp_resets,7522	.num_resets = ARRAY_SIZE(gcc_sc8280xp_resets),7523	.gdscs = gcc_sc8280xp_gdscs,7524	.num_gdscs = ARRAY_SIZE(gcc_sc8280xp_gdscs),7525};7526 7527static int gcc_sc8280xp_probe(struct platform_device *pdev)7528{7529	struct regmap *regmap;7530	int ret;7531 7532	ret = devm_pm_runtime_enable(&pdev->dev);7533	if (ret)7534		return ret;7535 7536	ret = pm_runtime_resume_and_get(&pdev->dev);7537	if (ret)7538		return ret;7539 7540	regmap = qcom_cc_map(pdev, &gcc_sc8280xp_desc);7541	if (IS_ERR(regmap)) {7542		ret = PTR_ERR(regmap);7543		goto err_put_rpm;7544	}7545 7546	/* Keep some clocks always-on */7547	qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */7548	qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */7549	qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */7550	qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */7551	qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */7552	qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */7553	qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */7554	qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */7555	qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */7556 7557	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));7558	if (ret)7559		goto err_put_rpm;7560 7561	ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap);7562	if (ret)7563		goto err_put_rpm;7564 7565	pm_runtime_put(&pdev->dev);7566 7567	return 0;7568 7569err_put_rpm:7570	pm_runtime_put_sync(&pdev->dev);7571 7572	return ret;7573}7574 7575static const struct of_device_id gcc_sc8280xp_match_table[] = {7576	{ .compatible = "qcom,gcc-sc8280xp" },7577	{ }7578};7579MODULE_DEVICE_TABLE(of, gcc_sc8280xp_match_table);7580 7581static struct platform_driver gcc_sc8280xp_driver = {7582	.probe = gcc_sc8280xp_probe,7583	.driver = {7584		.name = "gcc-sc8280xp",7585		.of_match_table = gcc_sc8280xp_match_table,7586	},7587};7588 7589static int __init gcc_sc8280xp_init(void)7590{7591	return platform_driver_register(&gcc_sc8280xp_driver);7592}7593subsys_initcall(gcc_sc8280xp_init);7594 7595static void __exit gcc_sc8280xp_exit(void)7596{7597	platform_driver_unregister(&gcc_sc8280xp_driver);7598}7599module_exit(gcc_sc8280xp_exit);7600 7601MODULE_DESCRIPTION("Qualcomm SC8280XP GCC driver");7602MODULE_LICENSE("GPL");7603