2502 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.4 * Copyright (c) 2018, Craig Tatlor.5 */6 7#include <linux/kernel.h>8#include <linux/bitops.h>9#include <linux/err.h>10#include <linux/platform_device.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/clk-provider.h>14#include <linux/regmap.h>15#include <linux/reset-controller.h>16 17#include <dt-bindings/clock/qcom,gcc-sdm660.h>18 19#include "common.h"20#include "clk-regmap.h"21#include "clk-alpha-pll.h"22#include "clk-rcg.h"23#include "clk-branch.h"24#include "reset.h"25#include "gdsc.h"26 27enum {28 P_XO,29 P_SLEEP_CLK,30 P_GPLL0,31 P_GPLL1,32 P_GPLL4,33 P_GPLL0_EARLY_DIV,34 P_GPLL1_EARLY_DIV,35};36 37static struct clk_fixed_factor xo = {38 .mult = 1,39 .div = 1,40 .hw.init = &(struct clk_init_data){41 .name = "xo",42 .parent_data = &(const struct clk_parent_data) {43 .fw_name = "xo"44 },45 .num_parents = 1,46 .ops = &clk_fixed_factor_ops,47 },48};49 50static struct clk_alpha_pll gpll0_early = {51 .offset = 0x0,52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],53 .clkr = {54 .enable_reg = 0x52000,55 .enable_mask = BIT(0),56 .hw.init = &(struct clk_init_data){57 .name = "gpll0_early",58 .parent_data = &(const struct clk_parent_data){59 .fw_name = "xo",60 },61 .num_parents = 1,62 .ops = &clk_alpha_pll_ops,63 },64 },65};66 67static struct clk_fixed_factor gpll0_early_div = {68 .mult = 1,69 .div = 2,70 .hw.init = &(struct clk_init_data){71 .name = "gpll0_early_div",72 .parent_hws = (const struct clk_hw*[]){73 &gpll0_early.clkr.hw,74 },75 .num_parents = 1,76 .ops = &clk_fixed_factor_ops,77 },78};79 80static struct clk_alpha_pll_postdiv gpll0 = {81 .offset = 0x00000,82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],83 .clkr.hw.init = &(struct clk_init_data){84 .name = "gpll0",85 .parent_hws = (const struct clk_hw*[]){86 &gpll0_early.clkr.hw,87 },88 .num_parents = 1,89 .ops = &clk_alpha_pll_postdiv_ops,90 },91};92 93static struct clk_alpha_pll gpll1_early = {94 .offset = 0x1000,95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],96 .clkr = {97 .enable_reg = 0x52000,98 .enable_mask = BIT(1),99 .hw.init = &(struct clk_init_data){100 .name = "gpll1_early",101 .parent_data = &(const struct clk_parent_data){102 .fw_name = "xo",103 },104 .num_parents = 1,105 .ops = &clk_alpha_pll_ops,106 },107 },108};109 110static struct clk_fixed_factor gpll1_early_div = {111 .mult = 1,112 .div = 2,113 .hw.init = &(struct clk_init_data){114 .name = "gpll1_early_div",115 .parent_hws = (const struct clk_hw*[]){116 &gpll1_early.clkr.hw,117 },118 .num_parents = 1,119 .ops = &clk_fixed_factor_ops,120 },121};122 123static struct clk_alpha_pll_postdiv gpll1 = {124 .offset = 0x1000,125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],126 .clkr.hw.init = &(struct clk_init_data){127 .name = "gpll1",128 .parent_hws = (const struct clk_hw*[]){129 &gpll1_early.clkr.hw,130 },131 .num_parents = 1,132 .ops = &clk_alpha_pll_postdiv_ops,133 },134};135 136static struct clk_alpha_pll gpll4_early = {137 .offset = 0x77000,138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],139 .clkr = {140 .enable_reg = 0x52000,141 .enable_mask = BIT(4),142 .hw.init = &(struct clk_init_data){143 .name = "gpll4_early",144 .parent_data = &(const struct clk_parent_data){145 .fw_name = "xo",146 },147 .num_parents = 1,148 .ops = &clk_alpha_pll_ops,149 },150 },151};152 153static struct clk_alpha_pll_postdiv gpll4 = {154 .offset = 0x77000,155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],156 .clkr.hw.init = &(struct clk_init_data)157 {158 .name = "gpll4",159 .parent_hws = (const struct clk_hw*[]){160 &gpll4_early.clkr.hw,161 },162 .num_parents = 1,163 .ops = &clk_alpha_pll_postdiv_ops,164 },165};166 167static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {168 { P_XO, 0 },169 { P_GPLL0, 1 },170 { P_GPLL0_EARLY_DIV, 6 },171};172 173static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = {174 { .fw_name = "xo" },175 { .hw = &gpll0.clkr.hw },176 { .hw = &gpll0_early_div.hw },177};178 179static const struct parent_map gcc_parent_map_xo_gpll0[] = {180 { P_XO, 0 },181 { P_GPLL0, 1 },182};183 184static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = {185 { .fw_name = "xo" },186 { .hw = &gpll0.clkr.hw },187};188 189static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {190 { P_XO, 0 },191 { P_GPLL0, 1 },192 { P_SLEEP_CLK, 5 },193 { P_GPLL0_EARLY_DIV, 6 },194};195 196static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = {197 { .fw_name = "xo" },198 { .hw = &gpll0.clkr.hw },199 { .fw_name = "sleep_clk" },200 { .hw = &gpll0_early_div.hw },201};202 203static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {204 { P_XO, 0 },205 { P_SLEEP_CLK, 5 },206};207 208static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = {209 { .fw_name = "xo" },210 { .fw_name = "sleep_clk" },211};212 213static const struct parent_map gcc_parent_map_xo_gpll4[] = {214 { P_XO, 0 },215 { P_GPLL4, 5 },216};217 218static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = {219 { .fw_name = "xo" },220 { .hw = &gpll4.clkr.hw },221};222 223static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {224 { P_XO, 0 },225 { P_GPLL0, 1 },226 { P_GPLL0_EARLY_DIV, 3 },227 { P_GPLL1, 4 },228 { P_GPLL4, 5 },229 { P_GPLL1_EARLY_DIV, 6 },230};231 232static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {233 { .fw_name = "xo" },234 { .hw = &gpll0.clkr.hw },235 { .hw = &gpll0_early_div.hw },236 { .hw = &gpll1.clkr.hw },237 { .hw = &gpll4.clkr.hw },238 { .hw = &gpll1_early_div.hw },239};240 241static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {242 { P_XO, 0 },243 { P_GPLL0, 1 },244 { P_GPLL4, 5 },245 { P_GPLL0_EARLY_DIV, 6 },246};247 248static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = {249 { .fw_name = "xo" },250 { .hw = &gpll0.clkr.hw },251 { .hw = &gpll4.clkr.hw },252 { .hw = &gpll0_early_div.hw },253};254 255static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {256 { P_XO, 0 },257 { P_GPLL0, 1 },258 { P_GPLL0_EARLY_DIV, 2 },259 { P_GPLL4, 5 },260};261 262static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = {263 { .fw_name = "xo" },264 { .hw = &gpll0.clkr.hw },265 { .hw = &gpll0_early_div.hw },266 { .hw = &gpll4.clkr.hw },267};268 269static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {270 F(19200000, P_XO, 1, 0, 0),271 F(50000000, P_GPLL0, 12, 0, 0),272 { }273};274 275static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {276 .cmd_rcgr = 0x19020,277 .mnd_width = 0,278 .hid_width = 5,279 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,280 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,281 .clkr.hw.init = &(struct clk_init_data){282 .name = "blsp1_qup1_i2c_apps_clk_src",283 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,284 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),285 .ops = &clk_rcg2_ops,286 },287};288 289static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {290 F(960000, P_XO, 10, 1, 2),291 F(4800000, P_XO, 4, 0, 0),292 F(9600000, P_XO, 2, 0, 0),293 F(15000000, P_GPLL0, 10, 1, 4),294 F(19200000, P_XO, 1, 0, 0),295 F(25000000, P_GPLL0, 12, 1, 2),296 F(50000000, P_GPLL0, 12, 0, 0),297 { }298};299 300static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {301 .cmd_rcgr = 0x1900c,302 .mnd_width = 8,303 .hid_width = 5,304 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,305 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,306 .clkr.hw.init = &(struct clk_init_data){307 .name = "blsp1_qup1_spi_apps_clk_src",308 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,309 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),310 .ops = &clk_rcg2_ops,311 },312};313 314static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {315 .cmd_rcgr = 0x1b020,316 .mnd_width = 0,317 .hid_width = 5,318 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,319 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,320 .clkr.hw.init = &(struct clk_init_data){321 .name = "blsp1_qup2_i2c_apps_clk_src",322 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,323 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),324 .ops = &clk_rcg2_ops,325 },326};327 328static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {329 .cmd_rcgr = 0x1b00c,330 .mnd_width = 8,331 .hid_width = 5,332 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,333 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,334 .clkr.hw.init = &(struct clk_init_data){335 .name = "blsp1_qup2_spi_apps_clk_src",336 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,337 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),338 .ops = &clk_rcg2_ops,339 },340};341 342static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {343 .cmd_rcgr = 0x1d020,344 .mnd_width = 0,345 .hid_width = 5,346 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,347 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,348 .clkr.hw.init = &(struct clk_init_data){349 .name = "blsp1_qup3_i2c_apps_clk_src",350 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,351 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),352 .ops = &clk_rcg2_ops,353 },354};355 356static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {357 .cmd_rcgr = 0x1d00c,358 .mnd_width = 8,359 .hid_width = 5,360 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,361 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,362 .clkr.hw.init = &(struct clk_init_data){363 .name = "blsp1_qup3_spi_apps_clk_src",364 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,365 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),366 .ops = &clk_rcg2_ops,367 },368};369 370static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {371 .cmd_rcgr = 0x1f020,372 .mnd_width = 0,373 .hid_width = 5,374 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,375 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,376 .clkr.hw.init = &(struct clk_init_data){377 .name = "blsp1_qup4_i2c_apps_clk_src",378 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,379 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),380 .ops = &clk_rcg2_ops,381 },382};383 384static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {385 .cmd_rcgr = 0x1f00c,386 .mnd_width = 8,387 .hid_width = 5,388 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,389 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,390 .clkr.hw.init = &(struct clk_init_data){391 .name = "blsp1_qup4_spi_apps_clk_src",392 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,393 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),394 .ops = &clk_rcg2_ops,395 },396};397 398static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {399 F(3686400, P_GPLL0, 1, 96, 15625),400 F(7372800, P_GPLL0, 1, 192, 15625),401 F(14745600, P_GPLL0, 1, 384, 15625),402 F(16000000, P_GPLL0, 5, 2, 15),403 F(19200000, P_XO, 1, 0, 0),404 F(24000000, P_GPLL0, 5, 1, 5),405 F(32000000, P_GPLL0, 1, 4, 75),406 F(40000000, P_GPLL0, 15, 0, 0),407 F(46400000, P_GPLL0, 1, 29, 375),408 F(48000000, P_GPLL0, 12.5, 0, 0),409 F(51200000, P_GPLL0, 1, 32, 375),410 F(56000000, P_GPLL0, 1, 7, 75),411 F(58982400, P_GPLL0, 1, 1536, 15625),412 F(60000000, P_GPLL0, 10, 0, 0),413 F(63157895, P_GPLL0, 9.5, 0, 0),414 { }415};416 417static struct clk_rcg2 blsp1_uart1_apps_clk_src = {418 .cmd_rcgr = 0x1a00c,419 .mnd_width = 16,420 .hid_width = 5,421 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,422 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,423 .clkr.hw.init = &(struct clk_init_data){424 .name = "blsp1_uart1_apps_clk_src",425 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,426 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),427 .ops = &clk_rcg2_ops,428 },429};430 431static struct clk_rcg2 blsp1_uart2_apps_clk_src = {432 .cmd_rcgr = 0x1c00c,433 .mnd_width = 16,434 .hid_width = 5,435 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,436 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,437 .clkr.hw.init = &(struct clk_init_data){438 .name = "blsp1_uart2_apps_clk_src",439 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,440 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),441 .ops = &clk_rcg2_ops,442 },443};444 445static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {446 .cmd_rcgr = 0x26020,447 .mnd_width = 0,448 .hid_width = 5,449 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,450 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,451 .clkr.hw.init = &(struct clk_init_data){452 .name = "blsp2_qup1_i2c_apps_clk_src",453 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,454 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),455 .ops = &clk_rcg2_ops,456 },457};458 459static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {460 .cmd_rcgr = 0x2600c,461 .mnd_width = 8,462 .hid_width = 5,463 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,464 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,465 .clkr.hw.init = &(struct clk_init_data){466 .name = "blsp2_qup1_spi_apps_clk_src",467 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,468 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),469 .ops = &clk_rcg2_ops,470 },471};472 473static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {474 .cmd_rcgr = 0x28020,475 .mnd_width = 0,476 .hid_width = 5,477 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,478 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,479 .clkr.hw.init = &(struct clk_init_data){480 .name = "blsp2_qup2_i2c_apps_clk_src",481 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,482 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),483 .ops = &clk_rcg2_ops,484 },485};486 487static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {488 .cmd_rcgr = 0x2800c,489 .mnd_width = 8,490 .hid_width = 5,491 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,492 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,493 .clkr.hw.init = &(struct clk_init_data){494 .name = "blsp2_qup2_spi_apps_clk_src",495 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,496 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),497 .ops = &clk_rcg2_ops,498 },499};500 501static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {502 .cmd_rcgr = 0x2a020,503 .mnd_width = 0,504 .hid_width = 5,505 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,506 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,507 .clkr.hw.init = &(struct clk_init_data){508 .name = "blsp2_qup3_i2c_apps_clk_src",509 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,510 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),511 .ops = &clk_rcg2_ops,512 },513};514 515static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {516 .cmd_rcgr = 0x2a00c,517 .mnd_width = 8,518 .hid_width = 5,519 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,520 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,521 .clkr.hw.init = &(struct clk_init_data){522 .name = "blsp2_qup3_spi_apps_clk_src",523 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,524 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),525 .ops = &clk_rcg2_ops,526 },527};528 529static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {530 .cmd_rcgr = 0x2c020,531 .mnd_width = 0,532 .hid_width = 5,533 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,534 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,535 .clkr.hw.init = &(struct clk_init_data){536 .name = "blsp2_qup4_i2c_apps_clk_src",537 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,538 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),539 .ops = &clk_rcg2_ops,540 },541};542 543static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {544 .cmd_rcgr = 0x2c00c,545 .mnd_width = 8,546 .hid_width = 5,547 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,548 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,549 .clkr.hw.init = &(struct clk_init_data){550 .name = "blsp2_qup4_spi_apps_clk_src",551 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,552 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),553 .ops = &clk_rcg2_ops,554 },555};556 557static struct clk_rcg2 blsp2_uart1_apps_clk_src = {558 .cmd_rcgr = 0x2700c,559 .mnd_width = 16,560 .hid_width = 5,561 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,562 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,563 .clkr.hw.init = &(struct clk_init_data){564 .name = "blsp2_uart1_apps_clk_src",565 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,566 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),567 .ops = &clk_rcg2_ops,568 },569};570 571static struct clk_rcg2 blsp2_uart2_apps_clk_src = {572 .cmd_rcgr = 0x2900c,573 .mnd_width = 16,574 .hid_width = 5,575 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,576 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,577 .clkr.hw.init = &(struct clk_init_data){578 .name = "blsp2_uart2_apps_clk_src",579 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,580 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),581 .ops = &clk_rcg2_ops,582 },583};584 585static const struct freq_tbl ftbl_gp1_clk_src[] = {586 F(19200000, P_XO, 1, 0, 0),587 F(100000000, P_GPLL0, 6, 0, 0),588 F(200000000, P_GPLL0, 3, 0, 0),589 { }590};591 592static struct clk_rcg2 gp1_clk_src = {593 .cmd_rcgr = 0x64004,594 .mnd_width = 8,595 .hid_width = 5,596 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,597 .freq_tbl = ftbl_gp1_clk_src,598 .clkr.hw.init = &(struct clk_init_data){599 .name = "gp1_clk_src",600 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,601 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),602 .ops = &clk_rcg2_ops,603 },604};605 606static struct clk_rcg2 gp2_clk_src = {607 .cmd_rcgr = 0x65004,608 .mnd_width = 8,609 .hid_width = 5,610 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,611 .freq_tbl = ftbl_gp1_clk_src,612 .clkr.hw.init = &(struct clk_init_data){613 .name = "gp2_clk_src",614 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,615 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),616 .ops = &clk_rcg2_ops,617 },618};619 620static struct clk_rcg2 gp3_clk_src = {621 .cmd_rcgr = 0x66004,622 .mnd_width = 8,623 .hid_width = 5,624 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,625 .freq_tbl = ftbl_gp1_clk_src,626 .clkr.hw.init = &(struct clk_init_data){627 .name = "gp3_clk_src",628 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,629 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),630 .ops = &clk_rcg2_ops,631 },632};633 634static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {635 F(300000000, P_GPLL0, 2, 0, 0),636 F(600000000, P_GPLL0, 1, 0, 0),637 { }638};639 640static struct clk_rcg2 hmss_gpll0_clk_src = {641 .cmd_rcgr = 0x4805c,642 .mnd_width = 0,643 .hid_width = 5,644 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,645 .freq_tbl = ftbl_hmss_gpll0_clk_src,646 .clkr.hw.init = &(struct clk_init_data){647 .name = "hmss_gpll0_clk_src",648 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,649 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),650 .ops = &clk_rcg2_ops,651 },652};653 654static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {655 F(384000000, P_GPLL4, 4, 0, 0),656 F(768000000, P_GPLL4, 2, 0, 0),657 F(1536000000, P_GPLL4, 1, 0, 0),658 { }659};660 661static struct clk_rcg2 hmss_gpll4_clk_src = {662 .cmd_rcgr = 0x48074,663 .mnd_width = 0,664 .hid_width = 5,665 .parent_map = gcc_parent_map_xo_gpll4,666 .freq_tbl = ftbl_hmss_gpll4_clk_src,667 .clkr.hw.init = &(struct clk_init_data){668 .name = "hmss_gpll4_clk_src",669 .parent_data = gcc_parent_data_xo_gpll4,670 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4),671 .ops = &clk_rcg2_ops,672 },673};674 675static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {676 F(19200000, P_XO, 1, 0, 0),677 { }678};679 680static struct clk_rcg2 hmss_rbcpr_clk_src = {681 .cmd_rcgr = 0x48044,682 .mnd_width = 0,683 .hid_width = 5,684 .parent_map = gcc_parent_map_xo_gpll0,685 .freq_tbl = ftbl_hmss_rbcpr_clk_src,686 .clkr.hw.init = &(struct clk_init_data){687 .name = "hmss_rbcpr_clk_src",688 .parent_data = gcc_parent_data_xo_gpll0,689 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0),690 .ops = &clk_rcg2_ops,691 },692};693 694static const struct freq_tbl ftbl_pdm2_clk_src[] = {695 F(60000000, P_GPLL0, 10, 0, 0),696 { }697};698 699static struct clk_rcg2 pdm2_clk_src = {700 .cmd_rcgr = 0x33010,701 .mnd_width = 0,702 .hid_width = 5,703 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,704 .freq_tbl = ftbl_pdm2_clk_src,705 .clkr.hw.init = &(struct clk_init_data){706 .name = "pdm2_clk_src",707 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,708 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),709 .ops = &clk_rcg2_ops,710 },711};712 713static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {714 F(19200000, P_XO, 1, 0, 0),715 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),716 F(160400000, P_GPLL1, 5, 0, 0),717 F(267333333, P_GPLL1, 3, 0, 0),718 { }719};720 721static struct clk_rcg2 qspi_ser_clk_src = {722 .cmd_rcgr = 0x4d00c,723 .mnd_width = 0,724 .hid_width = 5,725 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,726 .freq_tbl = ftbl_qspi_ser_clk_src,727 .clkr.hw.init = &(struct clk_init_data){728 .name = "qspi_ser_clk_src",729 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,730 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div),731 .ops = &clk_rcg2_ops,732 },733};734 735static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {736 F(144000, P_XO, 16, 3, 25),737 F(400000, P_XO, 12, 1, 4),738 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),739 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),740 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),741 F(100000000, P_GPLL0, 6, 0, 0),742 F(192000000, P_GPLL4, 8, 0, 0),743 F(384000000, P_GPLL4, 4, 0, 0),744 { }745};746 747static struct clk_rcg2 sdcc1_apps_clk_src = {748 .cmd_rcgr = 0x1602c,749 .mnd_width = 8,750 .hid_width = 5,751 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,752 .freq_tbl = ftbl_sdcc1_apps_clk_src,753 .clkr.hw.init = &(struct clk_init_data){754 .name = "sdcc1_apps_clk_src",755 .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,756 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),757 .ops = &clk_rcg2_floor_ops,758 },759};760 761static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {762 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),763 F(150000000, P_GPLL0, 4, 0, 0),764 F(200000000, P_GPLL0, 3, 0, 0),765 F(300000000, P_GPLL0, 2, 0, 0),766 { }767};768 769static struct clk_rcg2 sdcc1_ice_core_clk_src = {770 .cmd_rcgr = 0x16010,771 .mnd_width = 0,772 .hid_width = 5,773 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,774 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,775 .clkr.hw.init = &(struct clk_init_data){776 .name = "sdcc1_ice_core_clk_src",777 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,778 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),779 .ops = &clk_rcg2_ops,780 },781};782 783static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {784 F(144000, P_XO, 16, 3, 25),785 F(400000, P_XO, 12, 1, 4),786 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),787 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),788 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),789 F(100000000, P_GPLL0, 6, 0, 0),790 F(192000000, P_GPLL4, 8, 0, 0),791 F(200000000, P_GPLL0, 3, 0, 0),792 { }793};794 795static struct clk_rcg2 sdcc2_apps_clk_src = {796 .cmd_rcgr = 0x14010,797 .mnd_width = 8,798 .hid_width = 5,799 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,800 .freq_tbl = ftbl_sdcc2_apps_clk_src,801 .clkr.hw.init = &(struct clk_init_data){802 .name = "sdcc2_apps_clk_src",803 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,804 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4),805 .ops = &clk_rcg2_floor_ops,806 },807};808 809static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {810 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),811 F(100000000, P_GPLL0, 6, 0, 0),812 F(150000000, P_GPLL0, 4, 0, 0),813 F(200000000, P_GPLL0, 3, 0, 0),814 F(240000000, P_GPLL0, 2.5, 0, 0),815 { }816};817 818static struct clk_rcg2 ufs_axi_clk_src = {819 .cmd_rcgr = 0x75018,820 .mnd_width = 8,821 .hid_width = 5,822 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,823 .freq_tbl = ftbl_ufs_axi_clk_src,824 .clkr.hw.init = &(struct clk_init_data){825 .name = "ufs_axi_clk_src",826 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,827 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),828 .ops = &clk_rcg2_ops,829 },830};831 832static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {833 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),834 F(150000000, P_GPLL0, 4, 0, 0),835 F(300000000, P_GPLL0, 2, 0, 0),836 { }837};838 839static struct clk_rcg2 ufs_ice_core_clk_src = {840 .cmd_rcgr = 0x76010,841 .mnd_width = 0,842 .hid_width = 5,843 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,844 .freq_tbl = ftbl_ufs_ice_core_clk_src,845 .clkr.hw.init = &(struct clk_init_data){846 .name = "ufs_ice_core_clk_src",847 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,848 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),849 .ops = &clk_rcg2_ops,850 },851};852 853static struct clk_rcg2 ufs_phy_aux_clk_src = {854 .cmd_rcgr = 0x76044,855 .mnd_width = 0,856 .hid_width = 5,857 .parent_map = gcc_parent_map_xo_sleep_clk,858 .freq_tbl = ftbl_hmss_rbcpr_clk_src,859 .clkr.hw.init = &(struct clk_init_data){860 .name = "ufs_phy_aux_clk_src",861 .parent_data = gcc_parent_data_xo_sleep_clk,862 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),863 .ops = &clk_rcg2_ops,864 },865};866 867static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {868 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),869 F(75000000, P_GPLL0, 8, 0, 0),870 F(150000000, P_GPLL0, 4, 0, 0),871 { }872};873 874static struct clk_rcg2 ufs_unipro_core_clk_src = {875 .cmd_rcgr = 0x76028,876 .mnd_width = 0,877 .hid_width = 5,878 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,879 .freq_tbl = ftbl_ufs_unipro_core_clk_src,880 .clkr.hw.init = &(struct clk_init_data){881 .name = "ufs_unipro_core_clk_src",882 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,883 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),884 .ops = &clk_rcg2_ops,885 },886};887 888static const struct freq_tbl ftbl_usb20_master_clk_src[] = {889 F(19200000, P_XO, 1, 0, 0),890 F(60000000, P_GPLL0, 10, 0, 0),891 F(120000000, P_GPLL0, 5, 0, 0),892 { }893};894 895static struct clk_rcg2 usb20_master_clk_src = {896 .cmd_rcgr = 0x2f010,897 .mnd_width = 8,898 .hid_width = 5,899 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,900 .freq_tbl = ftbl_usb20_master_clk_src,901 .clkr.hw.init = &(struct clk_init_data){902 .name = "usb20_master_clk_src",903 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,904 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),905 .ops = &clk_rcg2_ops,906 },907};908 909static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {910 F(19200000, P_XO, 1, 0, 0),911 F(60000000, P_GPLL0, 10, 0, 0),912 { }913};914 915static struct clk_rcg2 usb20_mock_utmi_clk_src = {916 .cmd_rcgr = 0x2f024,917 .mnd_width = 0,918 .hid_width = 5,919 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,920 .freq_tbl = ftbl_usb20_mock_utmi_clk_src,921 .clkr.hw.init = &(struct clk_init_data){922 .name = "usb20_mock_utmi_clk_src",923 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,924 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),925 .ops = &clk_rcg2_ops,926 },927};928 929static const struct freq_tbl ftbl_usb30_master_clk_src[] = {930 F(19200000, P_XO, 1, 0, 0),931 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),932 F(120000000, P_GPLL0, 5, 0, 0),933 F(133333333, P_GPLL0, 4.5, 0, 0),934 F(150000000, P_GPLL0, 4, 0, 0),935 F(200000000, P_GPLL0, 3, 0, 0),936 F(240000000, P_GPLL0, 2.5, 0, 0),937 { }938};939 940static struct clk_rcg2 usb30_master_clk_src = {941 .cmd_rcgr = 0xf014,942 .mnd_width = 8,943 .hid_width = 5,944 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,945 .freq_tbl = ftbl_usb30_master_clk_src,946 .clkr.hw.init = &(struct clk_init_data){947 .name = "usb30_master_clk_src",948 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,949 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),950 .ops = &clk_rcg2_ops,951 },952};953 954static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {955 F(19200000, P_XO, 1, 0, 0),956 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),957 F(60000000, P_GPLL0, 10, 0, 0),958 { }959};960 961static struct clk_rcg2 usb30_mock_utmi_clk_src = {962 .cmd_rcgr = 0xf028,963 .mnd_width = 0,964 .hid_width = 5,965 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,966 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,967 .clkr.hw.init = &(struct clk_init_data){968 .name = "usb30_mock_utmi_clk_src",969 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,970 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),971 .ops = &clk_rcg2_ops,972 },973};974 975static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {976 F(1200000, P_XO, 16, 0, 0),977 F(19200000, P_XO, 1, 0, 0),978 { }979};980 981static struct clk_rcg2 usb3_phy_aux_clk_src = {982 .cmd_rcgr = 0x5000c,983 .mnd_width = 0,984 .hid_width = 5,985 .parent_map = gcc_parent_map_xo_sleep_clk,986 .freq_tbl = ftbl_usb3_phy_aux_clk_src,987 .clkr.hw.init = &(struct clk_init_data){988 .name = "usb3_phy_aux_clk_src",989 .parent_data = gcc_parent_data_xo_sleep_clk,990 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),991 .ops = &clk_rcg2_ops,992 },993};994 995static struct clk_branch gcc_aggre2_ufs_axi_clk = {996 .halt_reg = 0x75034,997 .halt_check = BRANCH_HALT,998 .clkr = {999 .enable_reg = 0x75034,1000 .enable_mask = BIT(0),1001 .hw.init = &(struct clk_init_data){1002 .name = "gcc_aggre2_ufs_axi_clk",1003 .parent_hws = (const struct clk_hw*[]) {1004 &ufs_axi_clk_src.clkr.hw,1005 },1006 .num_parents = 1,1007 .ops = &clk_branch2_ops,1008 },1009 },1010};1011 1012static struct clk_branch gcc_aggre2_usb3_axi_clk = {1013 .halt_reg = 0xf03c,1014 .halt_check = BRANCH_HALT,1015 .clkr = {1016 .enable_reg = 0xf03c,1017 .enable_mask = BIT(0),1018 .hw.init = &(struct clk_init_data){1019 .name = "gcc_aggre2_usb3_axi_clk",1020 .parent_hws = (const struct clk_hw*[]) {1021 &usb30_master_clk_src.clkr.hw,1022 },1023 .num_parents = 1,1024 .ops = &clk_branch2_ops,1025 },1026 },1027};1028 1029static struct clk_branch gcc_bimc_gfx_clk = {1030 .halt_reg = 0x7106c,1031 .halt_check = BRANCH_VOTED,1032 .clkr = {1033 .enable_reg = 0x7106c,1034 .enable_mask = BIT(0),1035 .hw.init = &(struct clk_init_data){1036 .name = "gcc_bimc_gfx_clk",1037 .ops = &clk_branch2_ops,1038 },1039 },1040};1041 1042static struct clk_branch gcc_bimc_hmss_axi_clk = {1043 .halt_reg = 0x48004,1044 .halt_check = BRANCH_HALT_VOTED,1045 .clkr = {1046 .enable_reg = 0x52004,1047 .enable_mask = BIT(22),1048 .hw.init = &(struct clk_init_data){1049 .name = "gcc_bimc_hmss_axi_clk",1050 .ops = &clk_branch2_ops,1051 },1052 },1053};1054 1055static struct clk_branch gcc_bimc_mss_q6_axi_clk = {1056 .halt_reg = 0x4401c,1057 .halt_check = BRANCH_HALT,1058 .clkr = {1059 .enable_reg = 0x4401c,1060 .enable_mask = BIT(0),1061 .hw.init = &(struct clk_init_data){1062 .name = "gcc_bimc_mss_q6_axi_clk",1063 .ops = &clk_branch2_ops,1064 },1065 },1066};1067 1068static struct clk_branch gcc_blsp1_ahb_clk = {1069 .halt_reg = 0x17004,1070 .halt_check = BRANCH_HALT_VOTED,1071 .clkr = {1072 .enable_reg = 0x52004,1073 .enable_mask = BIT(17),1074 .hw.init = &(struct clk_init_data){1075 .name = "gcc_blsp1_ahb_clk",1076 .ops = &clk_branch2_ops,1077 },1078 },1079};1080 1081static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {1082 .halt_reg = 0x19008,1083 .halt_check = BRANCH_HALT,1084 .clkr = {1085 .enable_reg = 0x19008,1086 .enable_mask = BIT(0),1087 .hw.init = &(struct clk_init_data){1088 .name = "gcc_blsp1_qup1_i2c_apps_clk",1089 .parent_hws = (const struct clk_hw*[]) {1090 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,1091 },1092 .num_parents = 1,1093 .flags = CLK_SET_RATE_PARENT,1094 .ops = &clk_branch2_ops,1095 },1096 },1097};1098 1099static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {1100 .halt_reg = 0x19004,1101 .halt_check = BRANCH_HALT,1102 .clkr = {1103 .enable_reg = 0x19004,1104 .enable_mask = BIT(0),1105 .hw.init = &(struct clk_init_data){1106 .name = "gcc_blsp1_qup1_spi_apps_clk",1107 .parent_hws = (const struct clk_hw*[]) {1108 &blsp1_qup1_spi_apps_clk_src.clkr.hw,1109 },1110 .num_parents = 1,1111 .flags = CLK_SET_RATE_PARENT,1112 .ops = &clk_branch2_ops,1113 },1114 },1115};1116 1117static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {1118 .halt_reg = 0x1b008,1119 .halt_check = BRANCH_HALT,1120 .clkr = {1121 .enable_reg = 0x1b008,1122 .enable_mask = BIT(0),1123 .hw.init = &(struct clk_init_data){1124 .name = "gcc_blsp1_qup2_i2c_apps_clk",1125 .parent_hws = (const struct clk_hw*[]) {1126 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,1127 },1128 .num_parents = 1,1129 .flags = CLK_SET_RATE_PARENT,1130 .ops = &clk_branch2_ops,1131 },1132 },1133};1134 1135static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {1136 .halt_reg = 0x1b004,1137 .halt_check = BRANCH_HALT,1138 .clkr = {1139 .enable_reg = 0x1b004,1140 .enable_mask = BIT(0),1141 .hw.init = &(struct clk_init_data){1142 .name = "gcc_blsp1_qup2_spi_apps_clk",1143 .parent_hws = (const struct clk_hw*[]) {1144 &blsp1_qup2_spi_apps_clk_src.clkr.hw,1145 },1146 .num_parents = 1,1147 .flags = CLK_SET_RATE_PARENT,1148 .ops = &clk_branch2_ops,1149 },1150 },1151};1152 1153static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {1154 .halt_reg = 0x1d008,1155 .halt_check = BRANCH_HALT,1156 .clkr = {1157 .enable_reg = 0x1d008,1158 .enable_mask = BIT(0),1159 .hw.init = &(struct clk_init_data){1160 .name = "gcc_blsp1_qup3_i2c_apps_clk",1161 .parent_hws = (const struct clk_hw*[]) {1162 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,1163 },1164 .num_parents = 1,1165 .flags = CLK_SET_RATE_PARENT,1166 .ops = &clk_branch2_ops,1167 },1168 },1169};1170 1171static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {1172 .halt_reg = 0x1d004,1173 .halt_check = BRANCH_HALT,1174 .clkr = {1175 .enable_reg = 0x1d004,1176 .enable_mask = BIT(0),1177 .hw.init = &(struct clk_init_data){1178 .name = "gcc_blsp1_qup3_spi_apps_clk",1179 .parent_hws = (const struct clk_hw*[]) {1180 &blsp1_qup3_spi_apps_clk_src.clkr.hw,1181 },1182 .num_parents = 1,1183 .flags = CLK_SET_RATE_PARENT,1184 .ops = &clk_branch2_ops,1185 },1186 },1187};1188 1189static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {1190 .halt_reg = 0x1f008,1191 .halt_check = BRANCH_HALT,1192 .clkr = {1193 .enable_reg = 0x1f008,1194 .enable_mask = BIT(0),1195 .hw.init = &(struct clk_init_data){1196 .name = "gcc_blsp1_qup4_i2c_apps_clk",1197 .parent_hws = (const struct clk_hw*[]) {1198 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,1199 },1200 .num_parents = 1,1201 .flags = CLK_SET_RATE_PARENT,1202 .ops = &clk_branch2_ops,1203 },1204 },1205};1206 1207static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {1208 .halt_reg = 0x1f004,1209 .halt_check = BRANCH_HALT,1210 .clkr = {1211 .enable_reg = 0x1f004,1212 .enable_mask = BIT(0),1213 .hw.init = &(struct clk_init_data){1214 .name = "gcc_blsp1_qup4_spi_apps_clk",1215 .parent_hws = (const struct clk_hw*[]) {1216 &blsp1_qup4_spi_apps_clk_src.clkr.hw,1217 },1218 .num_parents = 1,1219 .flags = CLK_SET_RATE_PARENT,1220 .ops = &clk_branch2_ops,1221 },1222 },1223};1224 1225static struct clk_branch gcc_blsp1_uart1_apps_clk = {1226 .halt_reg = 0x1a004,1227 .halt_check = BRANCH_HALT,1228 .clkr = {1229 .enable_reg = 0x1a004,1230 .enable_mask = BIT(0),1231 .hw.init = &(struct clk_init_data){1232 .name = "gcc_blsp1_uart1_apps_clk",1233 .parent_hws = (const struct clk_hw*[]) {1234 &blsp1_uart1_apps_clk_src.clkr.hw,1235 },1236 .num_parents = 1,1237 .flags = CLK_SET_RATE_PARENT,1238 .ops = &clk_branch2_ops,1239 },1240 },1241};1242 1243static struct clk_branch gcc_blsp1_uart2_apps_clk = {1244 .halt_reg = 0x1c004,1245 .halt_check = BRANCH_HALT,1246 .clkr = {1247 .enable_reg = 0x1c004,1248 .enable_mask = BIT(0),1249 .hw.init = &(struct clk_init_data){1250 .name = "gcc_blsp1_uart2_apps_clk",1251 .parent_hws = (const struct clk_hw*[]) {1252 &blsp1_uart2_apps_clk_src.clkr.hw,1253 },1254 .num_parents = 1,1255 .flags = CLK_SET_RATE_PARENT,1256 .ops = &clk_branch2_ops,1257 },1258 },1259};1260 1261static struct clk_branch gcc_blsp2_ahb_clk = {1262 .halt_reg = 0x25004,1263 .halt_check = BRANCH_HALT_VOTED,1264 .clkr = {1265 .enable_reg = 0x52004,1266 .enable_mask = BIT(15),1267 .hw.init = &(struct clk_init_data){1268 .name = "gcc_blsp2_ahb_clk",1269 .ops = &clk_branch2_ops,1270 },1271 },1272};1273 1274static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {1275 .halt_reg = 0x26008,1276 .halt_check = BRANCH_HALT,1277 .clkr = {1278 .enable_reg = 0x26008,1279 .enable_mask = BIT(0),1280 .hw.init = &(struct clk_init_data){1281 .name = "gcc_blsp2_qup1_i2c_apps_clk",1282 .parent_hws = (const struct clk_hw*[]) {1283 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,1284 },1285 .num_parents = 1,1286 .flags = CLK_SET_RATE_PARENT,1287 .ops = &clk_branch2_ops,1288 },1289 },1290};1291 1292static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {1293 .halt_reg = 0x26004,1294 .halt_check = BRANCH_HALT,1295 .clkr = {1296 .enable_reg = 0x26004,1297 .enable_mask = BIT(0),1298 .hw.init = &(struct clk_init_data){1299 .name = "gcc_blsp2_qup1_spi_apps_clk",1300 .parent_hws = (const struct clk_hw*[]) {1301 &blsp2_qup1_spi_apps_clk_src.clkr.hw,1302 },1303 .num_parents = 1,1304 .flags = CLK_SET_RATE_PARENT,1305 .ops = &clk_branch2_ops,1306 },1307 },1308};1309 1310static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {1311 .halt_reg = 0x28008,1312 .halt_check = BRANCH_HALT,1313 .clkr = {1314 .enable_reg = 0x28008,1315 .enable_mask = BIT(0),1316 .hw.init = &(struct clk_init_data){1317 .name = "gcc_blsp2_qup2_i2c_apps_clk",1318 .parent_hws = (const struct clk_hw*[]) {1319 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,1320 },1321 .num_parents = 1,1322 .flags = CLK_SET_RATE_PARENT,1323 .ops = &clk_branch2_ops,1324 },1325 },1326};1327 1328static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {1329 .halt_reg = 0x28004,1330 .halt_check = BRANCH_HALT,1331 .clkr = {1332 .enable_reg = 0x28004,1333 .enable_mask = BIT(0),1334 .hw.init = &(struct clk_init_data){1335 .name = "gcc_blsp2_qup2_spi_apps_clk",1336 .parent_hws = (const struct clk_hw*[]) {1337 &blsp2_qup2_spi_apps_clk_src.clkr.hw,1338 },1339 .num_parents = 1,1340 .flags = CLK_SET_RATE_PARENT,1341 .ops = &clk_branch2_ops,1342 },1343 },1344};1345 1346static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {1347 .halt_reg = 0x2a008,1348 .halt_check = BRANCH_HALT,1349 .clkr = {1350 .enable_reg = 0x2a008,1351 .enable_mask = BIT(0),1352 .hw.init = &(struct clk_init_data){1353 .name = "gcc_blsp2_qup3_i2c_apps_clk",1354 .parent_hws = (const struct clk_hw*[]) {1355 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,1356 },1357 .num_parents = 1,1358 .flags = CLK_SET_RATE_PARENT,1359 .ops = &clk_branch2_ops,1360 },1361 },1362};1363 1364static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {1365 .halt_reg = 0x2a004,1366 .halt_check = BRANCH_HALT,1367 .clkr = {1368 .enable_reg = 0x2a004,1369 .enable_mask = BIT(0),1370 .hw.init = &(struct clk_init_data){1371 .name = "gcc_blsp2_qup3_spi_apps_clk",1372 .parent_hws = (const struct clk_hw*[]) {1373 &blsp2_qup3_spi_apps_clk_src.clkr.hw,1374 },1375 .num_parents = 1,1376 .flags = CLK_SET_RATE_PARENT,1377 .ops = &clk_branch2_ops,1378 },1379 },1380};1381 1382static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {1383 .halt_reg = 0x2c008,1384 .halt_check = BRANCH_HALT,1385 .clkr = {1386 .enable_reg = 0x2c008,1387 .enable_mask = BIT(0),1388 .hw.init = &(struct clk_init_data){1389 .name = "gcc_blsp2_qup4_i2c_apps_clk",1390 .parent_hws = (const struct clk_hw*[]) {1391 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,1392 },1393 .num_parents = 1,1394 .flags = CLK_SET_RATE_PARENT,1395 .ops = &clk_branch2_ops,1396 },1397 },1398};1399 1400static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {1401 .halt_reg = 0x2c004,1402 .halt_check = BRANCH_HALT,1403 .clkr = {1404 .enable_reg = 0x2c004,1405 .enable_mask = BIT(0),1406 .hw.init = &(struct clk_init_data){1407 .name = "gcc_blsp2_qup4_spi_apps_clk",1408 .parent_hws = (const struct clk_hw*[]) {1409 &blsp2_qup4_spi_apps_clk_src.clkr.hw,1410 },1411 .num_parents = 1,1412 .flags = CLK_SET_RATE_PARENT,1413 .ops = &clk_branch2_ops,1414 },1415 },1416};1417 1418static struct clk_branch gcc_blsp2_uart1_apps_clk = {1419 .halt_reg = 0x27004,1420 .halt_check = BRANCH_HALT,1421 .clkr = {1422 .enable_reg = 0x27004,1423 .enable_mask = BIT(0),1424 .hw.init = &(struct clk_init_data){1425 .name = "gcc_blsp2_uart1_apps_clk",1426 .parent_hws = (const struct clk_hw*[]) {1427 &blsp2_uart1_apps_clk_src.clkr.hw,1428 },1429 .num_parents = 1,1430 .flags = CLK_SET_RATE_PARENT,1431 .ops = &clk_branch2_ops,1432 },1433 },1434};1435 1436static struct clk_branch gcc_blsp2_uart2_apps_clk = {1437 .halt_reg = 0x29004,1438 .halt_check = BRANCH_HALT,1439 .clkr = {1440 .enable_reg = 0x29004,1441 .enable_mask = BIT(0),1442 .hw.init = &(struct clk_init_data){1443 .name = "gcc_blsp2_uart2_apps_clk",1444 .parent_hws = (const struct clk_hw*[]) {1445 &blsp2_uart2_apps_clk_src.clkr.hw,1446 },1447 .num_parents = 1,1448 .flags = CLK_SET_RATE_PARENT,1449 .ops = &clk_branch2_ops,1450 },1451 },1452};1453 1454static struct clk_branch gcc_boot_rom_ahb_clk = {1455 .halt_reg = 0x38004,1456 .halt_check = BRANCH_HALT_VOTED,1457 .clkr = {1458 .enable_reg = 0x52004,1459 .enable_mask = BIT(10),1460 .hw.init = &(struct clk_init_data){1461 .name = "gcc_boot_rom_ahb_clk",1462 .ops = &clk_branch2_ops,1463 },1464 },1465};1466 1467static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {1468 .halt_reg = 0x5058,1469 .halt_check = BRANCH_HALT,1470 .clkr = {1471 .enable_reg = 0x5058,1472 .enable_mask = BIT(0),1473 .hw.init = &(struct clk_init_data){1474 .name = "gcc_cfg_noc_usb2_axi_clk",1475 .parent_hws = (const struct clk_hw*[]) {1476 &usb20_master_clk_src.clkr.hw,1477 },1478 .num_parents = 1,1479 .ops = &clk_branch2_ops,1480 },1481 },1482};1483 1484static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {1485 .halt_reg = 0x5018,1486 .halt_check = BRANCH_HALT,1487 .clkr = {1488 .enable_reg = 0x5018,1489 .enable_mask = BIT(0),1490 .hw.init = &(struct clk_init_data){1491 .name = "gcc_cfg_noc_usb3_axi_clk",1492 .parent_hws = (const struct clk_hw*[]) {1493 &usb30_master_clk_src.clkr.hw,1494 },1495 .num_parents = 1,1496 .ops = &clk_branch2_ops,1497 },1498 },1499};1500 1501static struct clk_branch gcc_dcc_ahb_clk = {1502 .halt_reg = 0x84004,1503 .clkr = {1504 .enable_reg = 0x84004,1505 .enable_mask = BIT(0),1506 .hw.init = &(struct clk_init_data){1507 .name = "gcc_dcc_ahb_clk",1508 .ops = &clk_branch2_ops,1509 },1510 },1511};1512 1513static struct clk_branch gcc_gp1_clk = {1514 .halt_reg = 0x64000,1515 .halt_check = BRANCH_HALT,1516 .clkr = {1517 .enable_reg = 0x64000,1518 .enable_mask = BIT(0),1519 .hw.init = &(struct clk_init_data){1520 .name = "gcc_gp1_clk",1521 .parent_hws = (const struct clk_hw*[]) {1522 &gp1_clk_src.clkr.hw,1523 },1524 .num_parents = 1,1525 .flags = CLK_SET_RATE_PARENT,1526 .ops = &clk_branch2_ops,1527 },1528 },1529};1530 1531static struct clk_branch gcc_gp2_clk = {1532 .halt_reg = 0x65000,1533 .halt_check = BRANCH_HALT,1534 .clkr = {1535 .enable_reg = 0x65000,1536 .enable_mask = BIT(0),1537 .hw.init = &(struct clk_init_data){1538 .name = "gcc_gp2_clk",1539 .parent_hws = (const struct clk_hw*[]) {1540 &gp2_clk_src.clkr.hw,1541 },1542 .num_parents = 1,1543 .flags = CLK_SET_RATE_PARENT,1544 .ops = &clk_branch2_ops,1545 },1546 },1547};1548 1549static struct clk_branch gcc_gp3_clk = {1550 .halt_reg = 0x66000,1551 .halt_check = BRANCH_HALT,1552 .clkr = {1553 .enable_reg = 0x66000,1554 .enable_mask = BIT(0),1555 .hw.init = &(struct clk_init_data){1556 .name = "gcc_gp3_clk",1557 .parent_hws = (const struct clk_hw*[]) {1558 &gp3_clk_src.clkr.hw,1559 },1560 .num_parents = 1,1561 .flags = CLK_SET_RATE_PARENT,1562 .ops = &clk_branch2_ops,1563 },1564 },1565};1566 1567static struct clk_branch gcc_gpu_bimc_gfx_clk = {1568 .halt_reg = 0x71010,1569 .halt_check = BRANCH_VOTED,1570 .clkr = {1571 .enable_reg = 0x71010,1572 .enable_mask = BIT(0),1573 .hw.init = &(struct clk_init_data){1574 .name = "gcc_gpu_bimc_gfx_clk",1575 .ops = &clk_branch2_ops,1576 },1577 },1578};1579 1580static struct clk_branch gcc_gpu_cfg_ahb_clk = {1581 .halt_reg = 0x71004,1582 .halt_check = BRANCH_VOTED,1583 .clkr = {1584 .enable_reg = 0x71004,1585 .enable_mask = BIT(0),1586 .hw.init = &(struct clk_init_data){1587 .name = "gcc_gpu_cfg_ahb_clk",1588 .ops = &clk_branch2_ops,1589 .flags = CLK_IS_CRITICAL,1590 },1591 },1592};1593 1594static struct clk_branch gcc_gpu_gpll0_clk = {1595 .halt_reg = 0x5200c,1596 .halt_check = BRANCH_HALT_DELAY,1597 .clkr = {1598 .enable_reg = 0x5200c,1599 .enable_mask = BIT(4),1600 .hw.init = &(struct clk_init_data){1601 .name = "gcc_gpu_gpll0_clk",1602 .parent_hws = (const struct clk_hw*[]) {1603 &gpll0.clkr.hw,1604 },1605 .num_parents = 1,1606 .ops = &clk_branch2_ops,1607 },1608 },1609};1610 1611static struct clk_branch gcc_gpu_gpll0_div_clk = {1612 .halt_reg = 0x5200c,1613 .halt_check = BRANCH_HALT_DELAY,1614 .clkr = {1615 .enable_reg = 0x5200c,1616 .enable_mask = BIT(3),1617 .hw.init = &(struct clk_init_data){1618 .name = "gcc_gpu_gpll0_div_clk",1619 .parent_hws = (const struct clk_hw*[]) {1620 &gpll0_early_div.hw,1621 },1622 .num_parents = 1,1623 .ops = &clk_branch2_ops,1624 },1625 },1626};1627 1628static struct clk_branch gcc_hmss_dvm_bus_clk = {1629 .halt_reg = 0x4808c,1630 .halt_check = BRANCH_HALT,1631 .clkr = {1632 .enable_reg = 0x4808c,1633 .enable_mask = BIT(0),1634 .hw.init = &(struct clk_init_data){1635 .name = "gcc_hmss_dvm_bus_clk",1636 .ops = &clk_branch2_ops,1637 .flags = CLK_IGNORE_UNUSED,1638 },1639 },1640};1641 1642static struct clk_branch gcc_hmss_rbcpr_clk = {1643 .halt_reg = 0x48008,1644 .halt_check = BRANCH_HALT,1645 .clkr = {1646 .enable_reg = 0x48008,1647 .enable_mask = BIT(0),1648 .hw.init = &(struct clk_init_data){1649 .name = "gcc_hmss_rbcpr_clk",1650 .parent_hws = (const struct clk_hw*[]) {1651 &hmss_rbcpr_clk_src.clkr.hw,1652 },1653 .num_parents = 1,1654 .flags = CLK_SET_RATE_PARENT,1655 .ops = &clk_branch2_ops,1656 },1657 },1658};1659 1660static struct clk_branch gcc_mmss_gpll0_clk = {1661 .halt_reg = 0x5200c,1662 .halt_check = BRANCH_HALT_DELAY,1663 .clkr = {1664 .enable_reg = 0x5200c,1665 .enable_mask = BIT(1),1666 .hw.init = &(struct clk_init_data){1667 .name = "gcc_mmss_gpll0_clk",1668 .parent_hws = (const struct clk_hw*[]) {1669 &gpll0.clkr.hw,1670 },1671 .num_parents = 1,1672 .ops = &clk_branch2_ops,1673 },1674 },1675};1676 1677static struct clk_branch gcc_mmss_gpll0_div_clk = {1678 .halt_reg = 0x5200c,1679 .halt_check = BRANCH_HALT_DELAY,1680 .clkr = {1681 .enable_reg = 0x5200c,1682 .enable_mask = BIT(0),1683 .hw.init = &(struct clk_init_data){1684 .name = "gcc_mmss_gpll0_div_clk",1685 .parent_hws = (const struct clk_hw*[]) {1686 &gpll0_early_div.hw,1687 },1688 .num_parents = 1,1689 .ops = &clk_branch2_ops,1690 },1691 },1692};1693 1694static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {1695 .halt_reg = 0x9004,1696 .halt_check = BRANCH_HALT,1697 .clkr = {1698 .enable_reg = 0x9004,1699 .enable_mask = BIT(0),1700 .hw.init = &(struct clk_init_data){1701 .name = "gcc_mmss_noc_cfg_ahb_clk",1702 .ops = &clk_branch2_ops,1703 /*1704 * Any access to mmss depends on this clock.1705 * Gating this clock has been shown to crash the system1706 * when mmssnoc_axi_rpm_clk is inited in rpmcc.1707 */1708 .flags = CLK_IS_CRITICAL,1709 },1710 },1711};1712 1713static struct clk_branch gcc_mmss_sys_noc_axi_clk = {1714 .halt_reg = 0x9000,1715 .halt_check = BRANCH_HALT,1716 .clkr = {1717 .enable_reg = 0x9000,1718 .enable_mask = BIT(0),1719 .hw.init = &(struct clk_init_data){1720 .name = "gcc_mmss_sys_noc_axi_clk",1721 .ops = &clk_branch2_ops,1722 },1723 },1724};1725 1726static struct clk_branch gcc_mss_cfg_ahb_clk = {1727 .halt_reg = 0x8a000,1728 .clkr = {1729 .enable_reg = 0x8a000,1730 .enable_mask = BIT(0),1731 .hw.init = &(struct clk_init_data){1732 .name = "gcc_mss_cfg_ahb_clk",1733 .ops = &clk_branch2_ops,1734 },1735 },1736};1737 1738static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {1739 .halt_reg = 0x8a004,1740 .halt_check = BRANCH_HALT,1741 .hwcg_reg = 0x8a004,1742 .hwcg_bit = 1,1743 .clkr = {1744 .enable_reg = 0x8a004,1745 .enable_mask = BIT(0),1746 .hw.init = &(struct clk_init_data){1747 .name = "gcc_mss_mnoc_bimc_axi_clk",1748 .ops = &clk_branch2_ops,1749 },1750 },1751};1752 1753static struct clk_branch gcc_mss_q6_bimc_axi_clk = {1754 .halt_reg = 0x8a040,1755 .clkr = {1756 .enable_reg = 0x8a040,1757 .enable_mask = BIT(0),1758 .hw.init = &(struct clk_init_data){1759 .name = "gcc_mss_q6_bimc_axi_clk",1760 .ops = &clk_branch2_ops,1761 },1762 },1763};1764 1765static struct clk_branch gcc_mss_snoc_axi_clk = {1766 .halt_reg = 0x8a03c,1767 .clkr = {1768 .enable_reg = 0x8a03c,1769 .enable_mask = BIT(0),1770 .hw.init = &(struct clk_init_data){1771 .name = "gcc_mss_snoc_axi_clk",1772 .ops = &clk_branch2_ops,1773 },1774 },1775};1776 1777static struct clk_branch gcc_pdm2_clk = {1778 .halt_reg = 0x3300c,1779 .halt_check = BRANCH_HALT,1780 .clkr = {1781 .enable_reg = 0x3300c,1782 .enable_mask = BIT(0),1783 .hw.init = &(struct clk_init_data){1784 .name = "gcc_pdm2_clk",1785 .parent_hws = (const struct clk_hw*[]) {1786 &pdm2_clk_src.clkr.hw,1787 },1788 .num_parents = 1,1789 .flags = CLK_SET_RATE_PARENT,1790 .ops = &clk_branch2_ops,1791 },1792 },1793};1794 1795static struct clk_branch gcc_pdm_ahb_clk = {1796 .halt_reg = 0x33004,1797 .halt_check = BRANCH_HALT,1798 .clkr = {1799 .enable_reg = 0x33004,1800 .enable_mask = BIT(0),1801 .hw.init = &(struct clk_init_data){1802 .name = "gcc_pdm_ahb_clk",1803 .ops = &clk_branch2_ops,1804 },1805 },1806};1807 1808static struct clk_branch gcc_prng_ahb_clk = {1809 .halt_reg = 0x34004,1810 .halt_check = BRANCH_HALT_VOTED,1811 .clkr = {1812 .enable_reg = 0x52004,1813 .enable_mask = BIT(13),1814 .hw.init = &(struct clk_init_data){1815 .name = "gcc_prng_ahb_clk",1816 .ops = &clk_branch2_ops,1817 },1818 },1819};1820 1821static struct clk_branch gcc_qspi_ahb_clk = {1822 .halt_reg = 0x4d004,1823 .halt_check = BRANCH_HALT,1824 .clkr = {1825 .enable_reg = 0x4d004,1826 .enable_mask = BIT(0),1827 .hw.init = &(struct clk_init_data){1828 .name = "gcc_qspi_ahb_clk",1829 .ops = &clk_branch2_ops,1830 },1831 },1832};1833 1834static struct clk_branch gcc_qspi_ser_clk = {1835 .halt_reg = 0x4d008,1836 .halt_check = BRANCH_HALT,1837 .clkr = {1838 .enable_reg = 0x4d008,1839 .enable_mask = BIT(0),1840 .hw.init = &(struct clk_init_data){1841 .name = "gcc_qspi_ser_clk",1842 .parent_hws = (const struct clk_hw*[]) {1843 &qspi_ser_clk_src.clkr.hw,1844 },1845 .num_parents = 1,1846 .flags = CLK_SET_RATE_PARENT,1847 .ops = &clk_branch2_ops,1848 },1849 },1850};1851 1852static struct clk_branch gcc_rx0_usb2_clkref_clk = {1853 .halt_reg = 0x88018,1854 .halt_check = BRANCH_HALT_VOTED,1855 .clkr = {1856 .enable_reg = 0x88018,1857 .enable_mask = BIT(0),1858 .hw.init = &(struct clk_init_data){1859 .name = "gcc_rx0_usb2_clkref_clk",1860 .ops = &clk_branch2_ops,1861 },1862 },1863};1864 1865static struct clk_branch gcc_rx1_usb2_clkref_clk = {1866 .halt_reg = 0x88014,1867 .halt_check = BRANCH_HALT_VOTED,1868 .clkr = {1869 .enable_reg = 0x88014,1870 .enable_mask = BIT(0),1871 .hw.init = &(struct clk_init_data){1872 .name = "gcc_rx1_usb2_clkref_clk",1873 .ops = &clk_branch2_ops,1874 },1875 },1876};1877 1878static struct clk_branch gcc_sdcc1_ahb_clk = {1879 .halt_reg = 0x16008,1880 .halt_check = BRANCH_HALT,1881 .clkr = {1882 .enable_reg = 0x16008,1883 .enable_mask = BIT(0),1884 .hw.init = &(struct clk_init_data){1885 .name = "gcc_sdcc1_ahb_clk",1886 .ops = &clk_branch2_ops,1887 },1888 },1889};1890 1891static struct clk_branch gcc_sdcc1_apps_clk = {1892 .halt_reg = 0x16004,1893 .halt_check = BRANCH_HALT,1894 .clkr = {1895 .enable_reg = 0x16004,1896 .enable_mask = BIT(0),1897 .hw.init = &(struct clk_init_data){1898 .name = "gcc_sdcc1_apps_clk",1899 .parent_hws = (const struct clk_hw*[]) {1900 &sdcc1_apps_clk_src.clkr.hw,1901 },1902 .num_parents = 1,1903 .flags = CLK_SET_RATE_PARENT,1904 .ops = &clk_branch2_ops,1905 },1906 },1907};1908 1909static struct clk_branch gcc_sdcc1_ice_core_clk = {1910 .halt_reg = 0x1600c,1911 .halt_check = BRANCH_HALT,1912 .clkr = {1913 .enable_reg = 0x1600c,1914 .enable_mask = BIT(0),1915 .hw.init = &(struct clk_init_data){1916 .name = "gcc_sdcc1_ice_core_clk",1917 .parent_hws = (const struct clk_hw*[]) {1918 &sdcc1_ice_core_clk_src.clkr.hw,1919 },1920 .num_parents = 1,1921 .flags = CLK_SET_RATE_PARENT,1922 .ops = &clk_branch2_ops,1923 },1924 },1925};1926 1927static struct clk_branch gcc_sdcc2_ahb_clk = {1928 .halt_reg = 0x14008,1929 .halt_check = BRANCH_HALT,1930 .clkr = {1931 .enable_reg = 0x14008,1932 .enable_mask = BIT(0),1933 .hw.init = &(struct clk_init_data){1934 .name = "gcc_sdcc2_ahb_clk",1935 .ops = &clk_branch2_ops,1936 },1937 },1938};1939 1940static struct clk_branch gcc_sdcc2_apps_clk = {1941 .halt_reg = 0x14004,1942 .halt_check = BRANCH_HALT,1943 .clkr = {1944 .enable_reg = 0x14004,1945 .enable_mask = BIT(0),1946 .hw.init = &(struct clk_init_data){1947 .name = "gcc_sdcc2_apps_clk",1948 .parent_hws = (const struct clk_hw*[]) {1949 &sdcc2_apps_clk_src.clkr.hw,1950 },1951 .num_parents = 1,1952 .flags = CLK_SET_RATE_PARENT,1953 .ops = &clk_branch2_ops,1954 },1955 },1956};1957 1958static struct clk_branch gcc_ufs_ahb_clk = {1959 .halt_reg = 0x7500c,1960 .halt_check = BRANCH_HALT,1961 .clkr = {1962 .enable_reg = 0x7500c,1963 .enable_mask = BIT(0),1964 .hw.init = &(struct clk_init_data){1965 .name = "gcc_ufs_ahb_clk",1966 .ops = &clk_branch2_ops,1967 },1968 },1969};1970 1971static struct clk_branch gcc_ufs_axi_clk = {1972 .halt_reg = 0x75008,1973 .halt_check = BRANCH_HALT,1974 .clkr = {1975 .enable_reg = 0x75008,1976 .enable_mask = BIT(0),1977 .hw.init = &(struct clk_init_data){1978 .name = "gcc_ufs_axi_clk",1979 .parent_hws = (const struct clk_hw*[]) {1980 &ufs_axi_clk_src.clkr.hw,1981 },1982 .num_parents = 1,1983 .flags = CLK_SET_RATE_PARENT,1984 .ops = &clk_branch2_ops,1985 },1986 },1987};1988 1989static struct clk_branch gcc_ufs_clkref_clk = {1990 .halt_reg = 0x88008,1991 .halt_check = BRANCH_HALT,1992 .clkr = {1993 .enable_reg = 0x88008,1994 .enable_mask = BIT(0),1995 .hw.init = &(struct clk_init_data){1996 .name = "gcc_ufs_clkref_clk",1997 .ops = &clk_branch2_ops,1998 },1999 },2000};2001 2002static struct clk_branch gcc_ufs_ice_core_clk = {2003 .halt_reg = 0x7600c,2004 .halt_check = BRANCH_HALT,2005 .clkr = {2006 .enable_reg = 0x7600c,2007 .enable_mask = BIT(0),2008 .hw.init = &(struct clk_init_data){2009 .name = "gcc_ufs_ice_core_clk",2010 .parent_hws = (const struct clk_hw*[]) {2011 &ufs_ice_core_clk_src.clkr.hw,2012 },2013 .num_parents = 1,2014 .flags = CLK_SET_RATE_PARENT,2015 .ops = &clk_branch2_ops,2016 },2017 },2018};2019 2020static struct clk_branch gcc_ufs_phy_aux_clk = {2021 .halt_reg = 0x76040,2022 .halt_check = BRANCH_HALT,2023 .clkr = {2024 .enable_reg = 0x76040,2025 .enable_mask = BIT(0),2026 .hw.init = &(struct clk_init_data){2027 .name = "gcc_ufs_phy_aux_clk",2028 .parent_hws = (const struct clk_hw*[]) {2029 &ufs_phy_aux_clk_src.clkr.hw,2030 },2031 .num_parents = 1,2032 .flags = CLK_SET_RATE_PARENT,2033 .ops = &clk_branch2_ops,2034 },2035 },2036};2037 2038static struct clk_branch gcc_ufs_rx_symbol_0_clk = {2039 .halt_reg = 0x75014,2040 .halt_check = BRANCH_HALT_SKIP,2041 .clkr = {2042 .enable_reg = 0x75014,2043 .enable_mask = BIT(0),2044 .hw.init = &(struct clk_init_data){2045 .name = "gcc_ufs_rx_symbol_0_clk",2046 .ops = &clk_branch2_ops,2047 },2048 },2049};2050 2051static struct clk_branch gcc_ufs_rx_symbol_1_clk = {2052 .halt_reg = 0x7605c,2053 .halt_check = BRANCH_HALT_SKIP,2054 .clkr = {2055 .enable_reg = 0x7605c,2056 .enable_mask = BIT(0),2057 .hw.init = &(struct clk_init_data){2058 .name = "gcc_ufs_rx_symbol_1_clk",2059 .ops = &clk_branch2_ops,2060 },2061 },2062};2063 2064static struct clk_branch gcc_ufs_tx_symbol_0_clk = {2065 .halt_reg = 0x75010,2066 .halt_check = BRANCH_HALT_SKIP,2067 .clkr = {2068 .enable_reg = 0x75010,2069 .enable_mask = BIT(0),2070 .hw.init = &(struct clk_init_data){2071 .name = "gcc_ufs_tx_symbol_0_clk",2072 .ops = &clk_branch2_ops,2073 },2074 },2075};2076 2077static struct clk_branch gcc_ufs_unipro_core_clk = {2078 .halt_reg = 0x76008,2079 .halt_check = BRANCH_HALT,2080 .clkr = {2081 .enable_reg = 0x76008,2082 .enable_mask = BIT(0),2083 .hw.init = &(struct clk_init_data){2084 .name = "gcc_ufs_unipro_core_clk",2085 .parent_hws = (const struct clk_hw*[]) {2086 &ufs_unipro_core_clk_src.clkr.hw,2087 },2088 .flags = CLK_SET_RATE_PARENT,2089 .num_parents = 1,2090 .ops = &clk_branch2_ops,2091 },2092 },2093};2094 2095static struct clk_branch gcc_usb20_master_clk = {2096 .halt_reg = 0x2f004,2097 .halt_check = BRANCH_HALT,2098 .clkr = {2099 .enable_reg = 0x2f004,2100 .enable_mask = BIT(0),2101 .hw.init = &(struct clk_init_data){2102 .name = "gcc_usb20_master_clk",2103 .parent_hws = (const struct clk_hw*[]) {2104 &usb20_master_clk_src.clkr.hw,2105 },2106 .flags = CLK_SET_RATE_PARENT,2107 .num_parents = 1,2108 .ops = &clk_branch2_ops,2109 },2110 },2111};2112 2113static struct clk_branch gcc_usb20_mock_utmi_clk = {2114 .halt_reg = 0x2f00c,2115 .halt_check = BRANCH_HALT,2116 .clkr = {2117 .enable_reg = 0x2f00c,2118 .enable_mask = BIT(0),2119 .hw.init = &(struct clk_init_data){2120 .name = "gcc_usb20_mock_utmi_clk",2121 .parent_hws = (const struct clk_hw*[]) {2122 &usb20_mock_utmi_clk_src.clkr.hw,2123 },2124 .num_parents = 1,2125 .flags = CLK_SET_RATE_PARENT,2126 .ops = &clk_branch2_ops,2127 },2128 },2129};2130 2131static struct clk_branch gcc_usb20_sleep_clk = {2132 .halt_reg = 0x2f008,2133 .halt_check = BRANCH_HALT,2134 .clkr = {2135 .enable_reg = 0x2f008,2136 .enable_mask = BIT(0),2137 .hw.init = &(struct clk_init_data){2138 .name = "gcc_usb20_sleep_clk",2139 .ops = &clk_branch2_ops,2140 },2141 },2142};2143 2144static struct clk_branch gcc_usb30_master_clk = {2145 .halt_reg = 0xf008,2146 .halt_check = BRANCH_HALT,2147 .clkr = {2148 .enable_reg = 0xf008,2149 .enable_mask = BIT(0),2150 .hw.init = &(struct clk_init_data){2151 .name = "gcc_usb30_master_clk",2152 .parent_hws = (const struct clk_hw*[]) {2153 &usb30_master_clk_src.clkr.hw,2154 },2155 .num_parents = 1,2156 .flags = CLK_SET_RATE_PARENT,2157 .ops = &clk_branch2_ops,2158 },2159 },2160};2161 2162static struct clk_branch gcc_usb30_mock_utmi_clk = {2163 .halt_reg = 0xf010,2164 .halt_check = BRANCH_HALT,2165 .clkr = {2166 .enable_reg = 0xf010,2167 .enable_mask = BIT(0),2168 .hw.init = &(struct clk_init_data){2169 .name = "gcc_usb30_mock_utmi_clk",2170 .parent_hws = (const struct clk_hw*[]) {2171 &usb30_mock_utmi_clk_src.clkr.hw,2172 },2173 .num_parents = 1,2174 .flags = CLK_SET_RATE_PARENT,2175 .ops = &clk_branch2_ops,2176 },2177 },2178};2179 2180static struct clk_branch gcc_usb30_sleep_clk = {2181 .halt_reg = 0xf00c,2182 .halt_check = BRANCH_HALT,2183 .clkr = {2184 .enable_reg = 0xf00c,2185 .enable_mask = BIT(0),2186 .hw.init = &(struct clk_init_data){2187 .name = "gcc_usb30_sleep_clk",2188 .ops = &clk_branch2_ops,2189 },2190 },2191};2192 2193static struct clk_branch gcc_usb3_clkref_clk = {2194 .halt_reg = 0x8800c,2195 .halt_check = BRANCH_HALT,2196 .clkr = {2197 .enable_reg = 0x8800c,2198 .enable_mask = BIT(0),2199 .hw.init = &(struct clk_init_data){2200 .name = "gcc_usb3_clkref_clk",2201 .ops = &clk_branch2_ops,2202 },2203 },2204};2205 2206static struct clk_branch gcc_usb3_phy_aux_clk = {2207 .halt_reg = 0x50000,2208 .halt_check = BRANCH_HALT,2209 .clkr = {2210 .enable_reg = 0x50000,2211 .enable_mask = BIT(0),2212 .hw.init = &(struct clk_init_data){2213 .name = "gcc_usb3_phy_aux_clk",2214 .parent_hws = (const struct clk_hw*[]) {2215 &usb3_phy_aux_clk_src.clkr.hw,2216 },2217 .num_parents = 1,2218 .flags = CLK_SET_RATE_PARENT,2219 .ops = &clk_branch2_ops,2220 },2221 },2222};2223 2224static struct clk_branch gcc_usb3_phy_pipe_clk = {2225 .halt_reg = 0x50004,2226 .halt_check = BRANCH_HALT_DELAY,2227 .clkr = {2228 .enable_reg = 0x50004,2229 .enable_mask = BIT(0),2230 .hw.init = &(struct clk_init_data){2231 .name = "gcc_usb3_phy_pipe_clk",2232 .ops = &clk_branch2_ops,2233 },2234 },2235};2236 2237static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {2238 .halt_reg = 0x6a004,2239 .halt_check = BRANCH_HALT,2240 .clkr = {2241 .enable_reg = 0x6a004,2242 .enable_mask = BIT(0),2243 .hw.init = &(struct clk_init_data){2244 .name = "gcc_usb_phy_cfg_ahb2phy_clk",2245 .ops = &clk_branch2_ops,2246 },2247 },2248};2249 2250static struct gdsc ufs_gdsc = {2251 .gdscr = 0x75004,2252 .gds_hw_ctrl = 0x0,2253 .pd = {2254 .name = "ufs_gdsc",2255 },2256 .pwrsts = PWRSTS_OFF_ON,2257 .flags = VOTABLE,2258};2259 2260static struct gdsc usb_30_gdsc = {2261 .gdscr = 0xf004,2262 .gds_hw_ctrl = 0x0,2263 .pd = {2264 .name = "usb_30_gdsc",2265 },2266 .pwrsts = PWRSTS_OFF_ON,2267 .flags = VOTABLE,2268};2269 2270static struct gdsc pcie_0_gdsc = {2271 .gdscr = 0x6b004,2272 .gds_hw_ctrl = 0x0,2273 .pd = {2274 .name = "pcie_0_gdsc",2275 },2276 .pwrsts = PWRSTS_OFF_ON,2277 .flags = VOTABLE,2278};2279 2280static struct clk_hw *gcc_sdm660_hws[] = {2281 &xo.hw,2282 &gpll0_early_div.hw,2283 &gpll1_early_div.hw,2284};2285 2286static struct clk_regmap *gcc_sdm660_clocks[] = {2287 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,2288 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,2289 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,2290 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,2291 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,2292 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,2293 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,2294 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,2295 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,2296 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,2297 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,2298 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,2299 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,2300 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,2301 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,2302 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,2303 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,2304 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,2305 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,2306 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,2307 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,2308 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,2309 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,2310 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,2311 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,2312 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,2313 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,2314 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,2315 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,2316 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,2317 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,2318 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,2319 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,2320 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,2321 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,2322 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,2323 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,2324 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,2325 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,2326 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,2327 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,2328 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,2329 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,2330 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,2331 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,2332 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,2333 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,2334 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,2335 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,2336 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,2337 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,2338 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,2339 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,2340 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,2341 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,2342 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,2343 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,2344 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,2345 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,2346 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,2347 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,2348 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,2349 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,2350 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,2351 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,2352 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,2353 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,2354 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,2355 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,2356 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,2357 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,2358 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,2359 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,2360 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,2361 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,2362 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,2363 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,2364 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,2365 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,2366 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,2367 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,2368 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,2369 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,2370 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,2371 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,2372 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,2373 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,2374 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,2375 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,2376 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,2377 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,2378 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,2379 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,2380 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,2381 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,2382 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,2383 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,2384 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,2385 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,2386 [GP1_CLK_SRC] = &gp1_clk_src.clkr,2387 [GP2_CLK_SRC] = &gp2_clk_src.clkr,2388 [GP3_CLK_SRC] = &gp3_clk_src.clkr,2389 [GPLL0] = &gpll0.clkr,2390 [GPLL0_EARLY] = &gpll0_early.clkr,2391 [GPLL1] = &gpll1.clkr,2392 [GPLL1_EARLY] = &gpll1_early.clkr,2393 [GPLL4] = &gpll4.clkr,2394 [GPLL4_EARLY] = &gpll4_early.clkr,2395 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,2396 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,2397 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,2398 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,2399 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,2400 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,2401 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,2402 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,2403 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,2404 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,2405 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,2406 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,2407 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,2408 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,2409 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,2410 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,2411 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,2412};2413 2414static struct gdsc *gcc_sdm660_gdscs[] = {2415 [UFS_GDSC] = &ufs_gdsc,2416 [USB_30_GDSC] = &usb_30_gdsc,2417 [PCIE_0_GDSC] = &pcie_0_gdsc,2418};2419 2420static const struct qcom_reset_map gcc_sdm660_resets[] = {2421 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },2422 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },2423 [GCC_UFS_BCR] = { 0x75000 },2424 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },2425 [GCC_USB3_PHY_BCR] = { 0x50020 },2426 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },2427 [GCC_USB_20_BCR] = { 0x2f000 },2428 [GCC_USB_30_BCR] = { 0xf000 },2429 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },2430 [GCC_MSS_RESTART] = { 0x79000 },2431};2432 2433static const struct regmap_config gcc_sdm660_regmap_config = {2434 .reg_bits = 32,2435 .reg_stride = 4,2436 .val_bits = 32,2437 .max_register = 0x94000,2438 .fast_io = true,2439};2440 2441static const struct qcom_cc_desc gcc_sdm660_desc = {2442 .config = &gcc_sdm660_regmap_config,2443 .clks = gcc_sdm660_clocks,2444 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),2445 .resets = gcc_sdm660_resets,2446 .num_resets = ARRAY_SIZE(gcc_sdm660_resets),2447 .gdscs = gcc_sdm660_gdscs,2448 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),2449 .clk_hws = gcc_sdm660_hws,2450 .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),2451};2452 2453static const struct of_device_id gcc_sdm660_match_table[] = {2454 { .compatible = "qcom,gcc-sdm630" },2455 { .compatible = "qcom,gcc-sdm660" },2456 { }2457};2458MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);2459 2460static int gcc_sdm660_probe(struct platform_device *pdev)2461{2462 int ret;2463 struct regmap *regmap;2464 2465 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);2466 if (IS_ERR(regmap))2467 return PTR_ERR(regmap);2468 2469 /*2470 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be2471 * turned off by hardware during certain apps low power modes.2472 */2473 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));2474 if (ret)2475 return ret;2476 2477 return qcom_cc_really_probe(&pdev->dev, &gcc_sdm660_desc, regmap);2478}2479 2480static struct platform_driver gcc_sdm660_driver = {2481 .probe = gcc_sdm660_probe,2482 .driver = {2483 .name = "gcc-sdm660",2484 .of_match_table = gcc_sdm660_match_table,2485 },2486};2487 2488static int __init gcc_sdm660_init(void)2489{2490 return platform_driver_register(&gcc_sdm660_driver);2491}2492core_initcall_sync(gcc_sdm660_init);2493 2494static void __exit gcc_sdm660_exit(void)2495{2496 platform_driver_unregister(&gcc_sdm660_driver);2497}2498module_exit(gcc_sdm660_exit);2499 2500MODULE_LICENSE("GPL v2");2501MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");2502