2968 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/regmap.h>11 12#include <dt-bindings/clock/qcom,sdx75-gcc.h>13 14#include "clk-alpha-pll.h"15#include "clk-branch.h"16#include "clk-rcg.h"17#include "clk-regmap.h"18#include "clk-regmap-divider.h"19#include "clk-regmap-mux.h"20#include "clk-regmap-phy-mux.h"21#include "gdsc.h"22#include "reset.h"23 24enum {25 DT_BI_TCXO,26 DT_SLEEP_CLK,27 DT_EMAC0_SGMIIPHY_MAC_RCLK,28 DT_EMAC0_SGMIIPHY_MAC_TCLK,29 DT_EMAC0_SGMIIPHY_RCLK,30 DT_EMAC0_SGMIIPHY_TCLK,31 DT_EMAC1_SGMIIPHY_MAC_RCLK,32 DT_EMAC1_SGMIIPHY_MAC_TCLK,33 DT_EMAC1_SGMIIPHY_RCLK,34 DT_EMAC1_SGMIIPHY_TCLK,35 DT_PCIE20_PHY_AUX_CLK,36 DT_PCIE_1_PIPE_CLK,37 DT_PCIE_2_PIPE_CLK,38 DT_PCIE_PIPE_CLK,39 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,40};41 42enum {43 P_BI_TCXO,44 P_EMAC0_SGMIIPHY_MAC_RCLK,45 P_EMAC0_SGMIIPHY_MAC_TCLK,46 P_EMAC0_SGMIIPHY_RCLK,47 P_EMAC0_SGMIIPHY_TCLK,48 P_EMAC1_SGMIIPHY_MAC_RCLK,49 P_EMAC1_SGMIIPHY_MAC_TCLK,50 P_EMAC1_SGMIIPHY_RCLK,51 P_EMAC1_SGMIIPHY_TCLK,52 P_GPLL0_OUT_EVEN,53 P_GPLL0_OUT_MAIN,54 P_GPLL4_OUT_MAIN,55 P_GPLL5_OUT_MAIN,56 P_GPLL6_OUT_MAIN,57 P_GPLL8_OUT_MAIN,58 P_PCIE20_PHY_AUX_CLK,59 P_PCIE_1_PIPE_CLK,60 P_PCIE_2_PIPE_CLK,61 P_PCIE_PIPE_CLK,62 P_SLEEP_CLK,63 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,64};65 66static struct clk_alpha_pll gpll0 = {67 .offset = 0x0,68 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],69 .clkr = {70 .enable_reg = 0x7d000,71 .enable_mask = BIT(0),72 .hw.init = &(const struct clk_init_data) {73 .name = "gpll0",74 .parent_data = &(const struct clk_parent_data) {75 .index = DT_BI_TCXO,76 },77 .num_parents = 1,78 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,79 },80 },81};82 83static const struct clk_div_table post_div_table_gpll0_out_even[] = {84 { 0x1, 2 },85 { }86};87 88static struct clk_alpha_pll_postdiv gpll0_out_even = {89 .offset = 0x0,90 .post_div_shift = 10,91 .post_div_table = post_div_table_gpll0_out_even,92 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),93 .width = 4,94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],95 .clkr.hw.init = &(const struct clk_init_data) {96 .name = "gpll0_out_even",97 .parent_hws = (const struct clk_hw*[]) {98 &gpll0.clkr.hw,99 },100 .num_parents = 1,101 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops,102 },103};104 105static struct clk_alpha_pll gpll4 = {106 .offset = 0x4000,107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],108 .clkr = {109 .enable_reg = 0x7d000,110 .enable_mask = BIT(4),111 .hw.init = &(const struct clk_init_data) {112 .name = "gpll4",113 .parent_data = &(const struct clk_parent_data) {114 .index = DT_BI_TCXO,115 },116 .num_parents = 1,117 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,118 },119 },120};121 122static struct clk_alpha_pll gpll5 = {123 .offset = 0x5000,124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],125 .clkr = {126 .enable_reg = 0x7d000,127 .enable_mask = BIT(5),128 .hw.init = &(const struct clk_init_data) {129 .name = "gpll5",130 .parent_data = &(const struct clk_parent_data) {131 .index = DT_BI_TCXO,132 },133 .num_parents = 1,134 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,135 },136 },137};138 139static struct clk_alpha_pll gpll6 = {140 .offset = 0x6000,141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],142 .clkr = {143 .enable_reg = 0x7d000,144 .enable_mask = BIT(6),145 .hw.init = &(const struct clk_init_data) {146 .name = "gpll6",147 .parent_data = &(const struct clk_parent_data) {148 .index = DT_BI_TCXO,149 },150 .num_parents = 1,151 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,152 },153 },154};155 156static struct clk_alpha_pll gpll8 = {157 .offset = 0x8000,158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],159 .clkr = {160 .enable_reg = 0x7d000,161 .enable_mask = BIT(8),162 .hw.init = &(const struct clk_init_data) {163 .name = "gpll8",164 .parent_data = &(const struct clk_parent_data) {165 .index = DT_BI_TCXO,166 },167 .num_parents = 1,168 .ops = &clk_alpha_pll_fixed_lucid_ole_ops,169 },170 },171};172 173static const struct parent_map gcc_parent_map_0[] = {174 { P_BI_TCXO, 0 },175 { P_GPLL0_OUT_MAIN, 1 },176 { P_GPLL0_OUT_EVEN, 6 },177};178 179static const struct clk_parent_data gcc_parent_data_0[] = {180 { .index = DT_BI_TCXO },181 { .hw = &gpll0.clkr.hw },182 { .hw = &gpll0_out_even.clkr.hw },183};184 185static const struct parent_map gcc_parent_map_1[] = {186 { P_BI_TCXO, 0 },187 { P_GPLL0_OUT_MAIN, 1 },188 { P_GPLL4_OUT_MAIN, 2 },189 { P_GPLL5_OUT_MAIN, 5 },190 { P_GPLL0_OUT_EVEN, 6 },191};192 193static const struct clk_parent_data gcc_parent_data_1[] = {194 { .index = DT_BI_TCXO },195 { .hw = &gpll0.clkr.hw },196 { .hw = &gpll4.clkr.hw },197 { .hw = &gpll5.clkr.hw },198 { .hw = &gpll0_out_even.clkr.hw },199};200 201static const struct parent_map gcc_parent_map_2[] = {202 { P_BI_TCXO, 0 },203 { P_GPLL0_OUT_MAIN, 1 },204 { P_SLEEP_CLK, 5 },205 { P_GPLL0_OUT_EVEN, 6 },206};207 208static const struct clk_parent_data gcc_parent_data_2[] = {209 { .index = DT_BI_TCXO },210 { .hw = &gpll0.clkr.hw },211 { .index = DT_SLEEP_CLK },212 { .hw = &gpll0_out_even.clkr.hw },213};214 215static const struct parent_map gcc_parent_map_3[] = {216 { P_BI_TCXO, 0 },217 { P_SLEEP_CLK, 5 },218};219 220static const struct clk_parent_data gcc_parent_data_3[] = {221 { .index = DT_BI_TCXO },222 { .index = DT_SLEEP_CLK },223};224 225static const struct parent_map gcc_parent_map_4[] = {226 { P_BI_TCXO, 0 },227 { P_GPLL0_OUT_MAIN, 1 },228 { P_SLEEP_CLK, 5 },229};230 231static const struct clk_parent_data gcc_parent_data_4[] = {232 { .index = DT_BI_TCXO },233 { .hw = &gpll0.clkr.hw },234 { .index = DT_SLEEP_CLK },235};236 237static const struct parent_map gcc_parent_map_5[] = {238 { P_EMAC0_SGMIIPHY_RCLK, 0 },239 { P_BI_TCXO, 2 },240};241 242static const struct clk_parent_data gcc_parent_data_5[] = {243 { .index = DT_EMAC0_SGMIIPHY_RCLK },244 { .index = DT_BI_TCXO },245};246 247static const struct parent_map gcc_parent_map_6[] = {248 { P_EMAC0_SGMIIPHY_TCLK, 0 },249 { P_BI_TCXO, 2 },250};251 252static const struct clk_parent_data gcc_parent_data_6[] = {253 { .index = DT_EMAC0_SGMIIPHY_TCLK },254 { .index = DT_BI_TCXO },255};256 257static const struct parent_map gcc_parent_map_7[] = {258 { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 },259 { P_BI_TCXO, 2 },260};261 262static const struct clk_parent_data gcc_parent_data_7[] = {263 { .index = DT_EMAC0_SGMIIPHY_MAC_RCLK },264 { .index = DT_BI_TCXO },265};266 267static const struct parent_map gcc_parent_map_8[] = {268 { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 },269 { P_BI_TCXO, 2 },270};271 272static const struct clk_parent_data gcc_parent_data_8[] = {273 { .index = DT_EMAC0_SGMIIPHY_MAC_TCLK },274 { .index = DT_BI_TCXO },275};276 277static const struct parent_map gcc_parent_map_9[] = {278 { P_EMAC1_SGMIIPHY_RCLK, 0 },279 { P_BI_TCXO, 2 },280};281 282static const struct clk_parent_data gcc_parent_data_9[] = {283 { .index = DT_EMAC1_SGMIIPHY_RCLK },284 { .index = DT_BI_TCXO },285};286 287static const struct parent_map gcc_parent_map_10[] = {288 { P_EMAC1_SGMIIPHY_TCLK, 0 },289 { P_BI_TCXO, 2 },290};291 292static const struct clk_parent_data gcc_parent_data_10[] = {293 { .index = DT_EMAC1_SGMIIPHY_TCLK },294 { .index = DT_BI_TCXO },295};296 297static const struct parent_map gcc_parent_map_11[] = {298 { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 },299 { P_BI_TCXO, 2 },300};301 302static const struct clk_parent_data gcc_parent_data_11[] = {303 { .index = DT_EMAC1_SGMIIPHY_MAC_RCLK },304 { .index = DT_BI_TCXO },305};306 307static const struct parent_map gcc_parent_map_12[] = {308 { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 },309 { P_BI_TCXO, 2 },310};311 312static const struct clk_parent_data gcc_parent_data_12[] = {313 { .index = DT_EMAC1_SGMIIPHY_MAC_TCLK },314 { .index = DT_BI_TCXO },315};316 317static const struct parent_map gcc_parent_map_15[] = {318 { P_PCIE20_PHY_AUX_CLK, 0 },319 { P_BI_TCXO, 2 },320};321 322static const struct clk_parent_data gcc_parent_data_15[] = {323 { .index = DT_PCIE20_PHY_AUX_CLK },324 { .index = DT_BI_TCXO },325};326 327static const struct parent_map gcc_parent_map_17[] = {328 { P_BI_TCXO, 0 },329 { P_GPLL0_OUT_MAIN, 1 },330 { P_GPLL6_OUT_MAIN, 2 },331 { P_GPLL0_OUT_EVEN, 6 },332};333 334static const struct clk_parent_data gcc_parent_data_17[] = {335 { .index = DT_BI_TCXO },336 { .hw = &gpll0.clkr.hw },337 { .hw = &gpll6.clkr.hw },338 { .hw = &gpll0_out_even.clkr.hw },339};340 341static const struct parent_map gcc_parent_map_18[] = {342 { P_BI_TCXO, 0 },343 { P_GPLL0_OUT_MAIN, 1 },344 { P_GPLL8_OUT_MAIN, 2 },345 { P_GPLL0_OUT_EVEN, 6 },346};347 348static const struct clk_parent_data gcc_parent_data_18[] = {349 { .index = DT_BI_TCXO },350 { .hw = &gpll0.clkr.hw },351 { .hw = &gpll8.clkr.hw },352 { .hw = &gpll0_out_even.clkr.hw },353};354 355static const struct parent_map gcc_parent_map_19[] = {356 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },357 { P_BI_TCXO, 2 },358};359 360static const struct clk_parent_data gcc_parent_data_19[] = {361 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },362 { .index = DT_BI_TCXO },363};364 365static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src = {366 .reg = 0x71060,367 .shift = 0,368 .width = 2,369 .parent_map = gcc_parent_map_5,370 .clkr = {371 .hw.init = &(const struct clk_init_data) {372 .name = "gcc_emac0_cc_sgmiiphy_rx_clk_src",373 .parent_data = gcc_parent_data_5,374 .num_parents = ARRAY_SIZE(gcc_parent_data_5),375 .ops = &clk_regmap_mux_closest_ops,376 },377 },378};379 380static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src = {381 .reg = 0x71058,382 .shift = 0,383 .width = 2,384 .parent_map = gcc_parent_map_6,385 .clkr = {386 .hw.init = &(const struct clk_init_data) {387 .name = "gcc_emac0_cc_sgmiiphy_tx_clk_src",388 .parent_data = gcc_parent_data_6,389 .num_parents = ARRAY_SIZE(gcc_parent_data_6),390 .ops = &clk_regmap_mux_closest_ops,391 },392 },393};394 395static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src = {396 .reg = 0x71098,397 .shift = 0,398 .width = 2,399 .parent_map = gcc_parent_map_7,400 .clkr = {401 .hw.init = &(const struct clk_init_data) {402 .name = "gcc_emac0_sgmiiphy_mac_rclk_src",403 .parent_data = gcc_parent_data_7,404 .num_parents = ARRAY_SIZE(gcc_parent_data_7),405 .ops = &clk_regmap_mux_closest_ops,406 },407 },408};409 410static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src = {411 .reg = 0x71094,412 .shift = 0,413 .width = 2,414 .parent_map = gcc_parent_map_8,415 .clkr = {416 .hw.init = &(const struct clk_init_data) {417 .name = "gcc_emac0_sgmiiphy_mac_tclk_src",418 .parent_data = gcc_parent_data_8,419 .num_parents = ARRAY_SIZE(gcc_parent_data_8),420 .ops = &clk_regmap_mux_closest_ops,421 },422 },423};424 425static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src = {426 .reg = 0x72060,427 .shift = 0,428 .width = 2,429 .parent_map = gcc_parent_map_9,430 .clkr = {431 .hw.init = &(const struct clk_init_data) {432 .name = "gcc_emac1_cc_sgmiiphy_rx_clk_src",433 .parent_data = gcc_parent_data_9,434 .num_parents = ARRAY_SIZE(gcc_parent_data_9),435 .ops = &clk_regmap_mux_closest_ops,436 },437 },438};439 440static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src = {441 .reg = 0x72058,442 .shift = 0,443 .width = 2,444 .parent_map = gcc_parent_map_10,445 .clkr = {446 .hw.init = &(const struct clk_init_data) {447 .name = "gcc_emac1_cc_sgmiiphy_tx_clk_src",448 .parent_data = gcc_parent_data_10,449 .num_parents = ARRAY_SIZE(gcc_parent_data_10),450 .ops = &clk_regmap_mux_closest_ops,451 },452 },453};454 455static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src = {456 .reg = 0x72098,457 .shift = 0,458 .width = 2,459 .parent_map = gcc_parent_map_11,460 .clkr = {461 .hw.init = &(const struct clk_init_data) {462 .name = "gcc_emac1_sgmiiphy_mac_rclk_src",463 .parent_data = gcc_parent_data_11,464 .num_parents = ARRAY_SIZE(gcc_parent_data_11),465 .ops = &clk_regmap_mux_closest_ops,466 },467 },468};469 470static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src = {471 .reg = 0x72094,472 .shift = 0,473 .width = 2,474 .parent_map = gcc_parent_map_12,475 .clkr = {476 .hw.init = &(const struct clk_init_data) {477 .name = "gcc_emac1_sgmiiphy_mac_tclk_src",478 .parent_data = gcc_parent_data_12,479 .num_parents = ARRAY_SIZE(gcc_parent_data_12),480 .ops = &clk_regmap_mux_closest_ops,481 },482 },483};484 485static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {486 .reg = 0x67084,487 .clkr = {488 .hw.init = &(const struct clk_init_data) {489 .name = "gcc_pcie_1_pipe_clk_src",490 .parent_data = &(const struct clk_parent_data) {491 .index = DT_PCIE_1_PIPE_CLK,492 },493 .num_parents = 1,494 .ops = &clk_regmap_phy_mux_ops,495 },496 },497};498 499static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src = {500 .reg = 0x68050,501 .clkr = {502 .hw.init = &(const struct clk_init_data) {503 .name = "gcc_pcie_2_pipe_clk_src",504 .parent_data = &(const struct clk_parent_data) {505 .index = DT_PCIE_2_PIPE_CLK,506 },507 .num_parents = 1,508 .ops = &clk_regmap_phy_mux_ops,509 },510 },511};512 513static struct clk_regmap_mux gcc_pcie_aux_clk_src = {514 .reg = 0x53074,515 .shift = 0,516 .width = 2,517 .parent_map = gcc_parent_map_15,518 .clkr = {519 .hw.init = &(const struct clk_init_data) {520 .name = "gcc_pcie_aux_clk_src",521 .parent_data = gcc_parent_data_15,522 .num_parents = ARRAY_SIZE(gcc_parent_data_15),523 .ops = &clk_regmap_mux_closest_ops,524 },525 },526};527 528static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src = {529 .reg = 0x53058,530 .clkr = {531 .hw.init = &(const struct clk_init_data) {532 .name = "gcc_pcie_pipe_clk_src",533 .parent_data = &(const struct clk_parent_data) {534 .index = DT_PCIE_PIPE_CLK,535 },536 .num_parents = 1,537 .ops = &clk_regmap_phy_mux_ops,538 },539 },540};541 542static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {543 .reg = 0x27070,544 .shift = 0,545 .width = 2,546 .parent_map = gcc_parent_map_19,547 .clkr = {548 .hw.init = &(const struct clk_init_data) {549 .name = "gcc_usb3_phy_pipe_clk_src",550 .parent_data = gcc_parent_data_19,551 .num_parents = ARRAY_SIZE(gcc_parent_data_19),552 .ops = &clk_regmap_mux_closest_ops,553 },554 },555};556 557static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] = {558 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),559 { }560};561 562static struct clk_rcg2 gcc_eee_emac0_clk_src = {563 .cmd_rcgr = 0x710b0,564 .mnd_width = 16,565 .hid_width = 5,566 .parent_map = gcc_parent_map_2,567 .freq_tbl = ftbl_gcc_eee_emac0_clk_src,568 .clkr.hw.init = &(const struct clk_init_data) {569 .name = "gcc_eee_emac0_clk_src",570 .parent_data = gcc_parent_data_2,571 .num_parents = ARRAY_SIZE(gcc_parent_data_2),572 .ops = &clk_rcg2_shared_ops,573 },574};575 576static struct clk_rcg2 gcc_eee_emac1_clk_src = {577 .cmd_rcgr = 0x720b0,578 .mnd_width = 16,579 .hid_width = 5,580 .parent_map = gcc_parent_map_2,581 .freq_tbl = ftbl_gcc_eee_emac0_clk_src,582 .clkr.hw.init = &(const struct clk_init_data) {583 .name = "gcc_eee_emac1_clk_src",584 .parent_data = gcc_parent_data_2,585 .num_parents = ARRAY_SIZE(gcc_parent_data_2),586 .ops = &clk_rcg2_shared_ops,587 },588};589 590static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {591 F(19200000, P_BI_TCXO, 1, 0, 0),592 { }593};594 595static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {596 .cmd_rcgr = 0x7102c,597 .mnd_width = 0,598 .hid_width = 5,599 .parent_map = gcc_parent_map_4,600 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,601 .clkr.hw.init = &(const struct clk_init_data) {602 .name = "gcc_emac0_phy_aux_clk_src",603 .parent_data = gcc_parent_data_4,604 .num_parents = ARRAY_SIZE(gcc_parent_data_4),605 .ops = &clk_rcg2_shared_ops,606 },607};608 609static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {610 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),611 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),612 F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0),613 { }614};615 616static struct clk_rcg2 gcc_emac0_ptp_clk_src = {617 .cmd_rcgr = 0x7107c,618 .mnd_width = 16,619 .hid_width = 5,620 .parent_map = gcc_parent_map_1,621 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src,622 .clkr.hw.init = &(const struct clk_init_data) {623 .name = "gcc_emac0_ptp_clk_src",624 .parent_data = gcc_parent_data_1,625 .num_parents = ARRAY_SIZE(gcc_parent_data_1),626 .ops = &clk_rcg2_shared_ops,627 },628};629 630static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {631 F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6),632 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),633 F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0),634 F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0),635 { }636};637 638static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {639 .cmd_rcgr = 0x71064,640 .mnd_width = 16,641 .hid_width = 5,642 .parent_map = gcc_parent_map_1,643 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,644 .clkr.hw.init = &(const struct clk_init_data) {645 .name = "gcc_emac0_rgmii_clk_src",646 .parent_data = gcc_parent_data_1,647 .num_parents = ARRAY_SIZE(gcc_parent_data_1),648 .ops = &clk_rcg2_shared_ops,649 },650};651 652static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {653 .cmd_rcgr = 0x7202c,654 .mnd_width = 0,655 .hid_width = 5,656 .parent_map = gcc_parent_map_4,657 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,658 .clkr.hw.init = &(const struct clk_init_data) {659 .name = "gcc_emac1_phy_aux_clk_src",660 .parent_data = gcc_parent_data_4,661 .num_parents = ARRAY_SIZE(gcc_parent_data_4),662 .ops = &clk_rcg2_shared_ops,663 },664};665 666static struct clk_rcg2 gcc_emac1_ptp_clk_src = {667 .cmd_rcgr = 0x7207c,668 .mnd_width = 16,669 .hid_width = 5,670 .parent_map = gcc_parent_map_1,671 .freq_tbl = ftbl_gcc_emac0_ptp_clk_src,672 .clkr.hw.init = &(const struct clk_init_data) {673 .name = "gcc_emac1_ptp_clk_src",674 .parent_data = gcc_parent_data_1,675 .num_parents = ARRAY_SIZE(gcc_parent_data_1),676 .ops = &clk_rcg2_shared_ops,677 },678};679 680static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {681 .cmd_rcgr = 0x72064,682 .mnd_width = 16,683 .hid_width = 5,684 .parent_map = gcc_parent_map_1,685 .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,686 .clkr.hw.init = &(const struct clk_init_data) {687 .name = "gcc_emac1_rgmii_clk_src",688 .parent_data = gcc_parent_data_1,689 .num_parents = ARRAY_SIZE(gcc_parent_data_1),690 .ops = &clk_rcg2_shared_ops,691 },692};693 694static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {695 F(19200000, P_BI_TCXO, 1, 0, 0),696 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),697 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),698 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),699 { }700};701 702static struct clk_rcg2 gcc_gp1_clk_src = {703 .cmd_rcgr = 0x47004,704 .mnd_width = 16,705 .hid_width = 5,706 .parent_map = gcc_parent_map_2,707 .freq_tbl = ftbl_gcc_gp1_clk_src,708 .clkr.hw.init = &(const struct clk_init_data) {709 .name = "gcc_gp1_clk_src",710 .parent_data = gcc_parent_data_2,711 .num_parents = ARRAY_SIZE(gcc_parent_data_2),712 .ops = &clk_rcg2_shared_ops,713 },714};715 716static struct clk_rcg2 gcc_gp2_clk_src = {717 .cmd_rcgr = 0x48004,718 .mnd_width = 16,719 .hid_width = 5,720 .parent_map = gcc_parent_map_2,721 .freq_tbl = ftbl_gcc_gp1_clk_src,722 .clkr.hw.init = &(const struct clk_init_data) {723 .name = "gcc_gp2_clk_src",724 .parent_data = gcc_parent_data_2,725 .num_parents = ARRAY_SIZE(gcc_parent_data_2),726 .ops = &clk_rcg2_shared_ops,727 },728};729 730static struct clk_rcg2 gcc_gp3_clk_src = {731 .cmd_rcgr = 0x49004,732 .mnd_width = 16,733 .hid_width = 5,734 .parent_map = gcc_parent_map_2,735 .freq_tbl = ftbl_gcc_gp1_clk_src,736 .clkr.hw.init = &(const struct clk_init_data) {737 .name = "gcc_gp3_clk_src",738 .parent_data = gcc_parent_data_2,739 .num_parents = ARRAY_SIZE(gcc_parent_data_2),740 .ops = &clk_rcg2_shared_ops,741 },742};743 744static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src = {745 .cmd_rcgr = 0x67044,746 .mnd_width = 16,747 .hid_width = 5,748 .parent_map = gcc_parent_map_3,749 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,750 .clkr.hw.init = &(const struct clk_init_data) {751 .name = "gcc_pcie_1_aux_phy_clk_src",752 .parent_data = gcc_parent_data_3,753 .num_parents = ARRAY_SIZE(gcc_parent_data_3),754 .ops = &clk_rcg2_shared_ops,755 },756};757 758static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] = {759 F(19200000, P_BI_TCXO, 1, 0, 0),760 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),761 { }762};763 764static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {765 .cmd_rcgr = 0x6706c,766 .mnd_width = 0,767 .hid_width = 5,768 .parent_map = gcc_parent_map_2,769 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,770 .clkr.hw.init = &(const struct clk_init_data) {771 .name = "gcc_pcie_1_phy_rchng_clk_src",772 .parent_data = gcc_parent_data_2,773 .num_parents = ARRAY_SIZE(gcc_parent_data_2),774 .ops = &clk_rcg2_shared_ops,775 },776};777 778static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src = {779 .cmd_rcgr = 0x68064,780 .mnd_width = 16,781 .hid_width = 5,782 .parent_map = gcc_parent_map_3,783 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,784 .clkr.hw.init = &(const struct clk_init_data) {785 .name = "gcc_pcie_2_aux_phy_clk_src",786 .parent_data = gcc_parent_data_3,787 .num_parents = ARRAY_SIZE(gcc_parent_data_3),788 .ops = &clk_rcg2_shared_ops,789 },790};791 792static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {793 .cmd_rcgr = 0x68038,794 .mnd_width = 0,795 .hid_width = 5,796 .parent_map = gcc_parent_map_2,797 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,798 .clkr.hw.init = &(const struct clk_init_data) {799 .name = "gcc_pcie_2_phy_rchng_clk_src",800 .parent_data = gcc_parent_data_2,801 .num_parents = ARRAY_SIZE(gcc_parent_data_2),802 .ops = &clk_rcg2_shared_ops,803 },804};805 806static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {807 .cmd_rcgr = 0x5305c,808 .mnd_width = 16,809 .hid_width = 5,810 .parent_map = gcc_parent_map_3,811 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,812 .clkr.hw.init = &(const struct clk_init_data) {813 .name = "gcc_pcie_aux_phy_clk_src",814 .parent_data = gcc_parent_data_3,815 .num_parents = ARRAY_SIZE(gcc_parent_data_3),816 .ops = &clk_rcg2_shared_ops,817 },818};819 820static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {821 .cmd_rcgr = 0x53078,822 .mnd_width = 0,823 .hid_width = 5,824 .parent_map = gcc_parent_map_2,825 .freq_tbl = ftbl_gcc_pcie_1_phy_rchng_clk_src,826 .clkr.hw.init = &(const struct clk_init_data) {827 .name = "gcc_pcie_rchng_phy_clk_src",828 .parent_data = gcc_parent_data_2,829 .num_parents = ARRAY_SIZE(gcc_parent_data_2),830 .ops = &clk_rcg2_shared_ops,831 },832};833 834static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {835 F(19200000, P_BI_TCXO, 1, 0, 0),836 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),837 { }838};839 840static struct clk_rcg2 gcc_pdm2_clk_src = {841 .cmd_rcgr = 0x34010,842 .mnd_width = 0,843 .hid_width = 5,844 .parent_map = gcc_parent_map_0,845 .freq_tbl = ftbl_gcc_pdm2_clk_src,846 .clkr.hw.init = &(const struct clk_init_data) {847 .name = "gcc_pdm2_clk_src",848 .parent_data = gcc_parent_data_0,849 .num_parents = ARRAY_SIZE(gcc_parent_data_0),850 .ops = &clk_rcg2_shared_ops,851 },852};853 854static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {855 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),856 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),857 F(19200000, P_BI_TCXO, 1, 0, 0),858 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),859 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),860 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),861 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),862 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),863 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),864 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),865 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),866 { }867};868 869static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {870 .name = "gcc_qupv3_wrap0_s0_clk_src",871 .parent_data = gcc_parent_data_0,872 .num_parents = ARRAY_SIZE(gcc_parent_data_0),873 .ops = &clk_rcg2_shared_ops,874};875 876static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {877 .cmd_rcgr = 0x6c010,878 .mnd_width = 16,879 .hid_width = 5,880 .parent_map = gcc_parent_map_0,881 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,882 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,883};884 885static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {886 .name = "gcc_qupv3_wrap0_s1_clk_src",887 .parent_data = gcc_parent_data_0,888 .num_parents = ARRAY_SIZE(gcc_parent_data_0),889 .ops = &clk_rcg2_shared_ops,890};891 892static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {893 .cmd_rcgr = 0x6c148,894 .mnd_width = 16,895 .hid_width = 5,896 .parent_map = gcc_parent_map_0,897 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,898 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,899};900 901static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {902 .name = "gcc_qupv3_wrap0_s2_clk_src",903 .parent_data = gcc_parent_data_0,904 .num_parents = ARRAY_SIZE(gcc_parent_data_0),905 .ops = &clk_rcg2_shared_ops,906};907 908static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {909 .cmd_rcgr = 0x6c280,910 .mnd_width = 16,911 .hid_width = 5,912 .parent_map = gcc_parent_map_0,913 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,914 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,915};916 917static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {918 .name = "gcc_qupv3_wrap0_s3_clk_src",919 .parent_data = gcc_parent_data_0,920 .num_parents = ARRAY_SIZE(gcc_parent_data_0),921 .ops = &clk_rcg2_shared_ops,922};923 924static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {925 .cmd_rcgr = 0x6c3b8,926 .mnd_width = 16,927 .hid_width = 5,928 .parent_map = gcc_parent_map_0,929 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,930 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,931};932 933static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {934 .name = "gcc_qupv3_wrap0_s4_clk_src",935 .parent_data = gcc_parent_data_0,936 .num_parents = ARRAY_SIZE(gcc_parent_data_0),937 .ops = &clk_rcg2_shared_ops,938};939 940static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {941 .cmd_rcgr = 0x6c4f0,942 .mnd_width = 16,943 .hid_width = 5,944 .parent_map = gcc_parent_map_0,945 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,946 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,947};948 949static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {950 .name = "gcc_qupv3_wrap0_s5_clk_src",951 .parent_data = gcc_parent_data_0,952 .num_parents = ARRAY_SIZE(gcc_parent_data_0),953 .ops = &clk_rcg2_shared_ops,954};955 956static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {957 .cmd_rcgr = 0x6c628,958 .mnd_width = 16,959 .hid_width = 5,960 .parent_map = gcc_parent_map_0,961 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,962 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,963};964 965static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {966 .name = "gcc_qupv3_wrap0_s6_clk_src",967 .parent_data = gcc_parent_data_0,968 .num_parents = ARRAY_SIZE(gcc_parent_data_0),969 .ops = &clk_rcg2_shared_ops,970};971 972static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {973 .cmd_rcgr = 0x6c760,974 .mnd_width = 16,975 .hid_width = 5,976 .parent_map = gcc_parent_map_0,977 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,978 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,979};980 981static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {982 .name = "gcc_qupv3_wrap0_s7_clk_src",983 .parent_data = gcc_parent_data_0,984 .num_parents = ARRAY_SIZE(gcc_parent_data_0),985 .ops = &clk_rcg2_shared_ops,986};987 988static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {989 .cmd_rcgr = 0x6c898,990 .mnd_width = 16,991 .hid_width = 5,992 .parent_map = gcc_parent_map_0,993 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,994 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,995};996 997static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init = {998 .name = "gcc_qupv3_wrap0_s8_clk_src",999 .parent_data = gcc_parent_data_0,1000 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1001 .ops = &clk_rcg2_shared_ops,1002};1003 1004static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src = {1005 .cmd_rcgr = 0x6c9d0,1006 .mnd_width = 16,1007 .hid_width = 5,1008 .parent_map = gcc_parent_map_0,1009 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1010 .clkr.hw.init = &gcc_qupv3_wrap0_s8_clk_src_init,1011};1012 1013static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {1014 F(144000, P_BI_TCXO, 16, 3, 25),1015 F(400000, P_BI_TCXO, 12, 1, 4),1016 F(19200000, P_BI_TCXO, 1, 0, 0),1017 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),1018 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),1019 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),1020 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),1021 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),1022 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),1023 { }1024};1025 1026static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {1027 .cmd_rcgr = 0x6b014,1028 .mnd_width = 8,1029 .hid_width = 5,1030 .parent_map = gcc_parent_map_17,1031 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,1032 .clkr.hw.init = &(const struct clk_init_data) {1033 .name = "gcc_sdcc1_apps_clk_src",1034 .parent_data = gcc_parent_data_17,1035 .num_parents = ARRAY_SIZE(gcc_parent_data_17),1036 .ops = &clk_rcg2_floor_ops,1037 },1038};1039 1040static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {1041 F(400000, P_BI_TCXO, 12, 1, 4),1042 F(19200000, P_BI_TCXO, 1, 0, 0),1043 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),1044 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),1045 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),1046 F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0),1047 { }1048};1049 1050static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {1051 .cmd_rcgr = 0x6a018,1052 .mnd_width = 8,1053 .hid_width = 5,1054 .parent_map = gcc_parent_map_18,1055 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,1056 .clkr.hw.init = &(const struct clk_init_data) {1057 .name = "gcc_sdcc2_apps_clk_src",1058 .parent_data = gcc_parent_data_18,1059 .num_parents = ARRAY_SIZE(gcc_parent_data_18),1060 .ops = &clk_rcg2_floor_ops,1061 },1062};1063 1064static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {1065 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),1066 { }1067};1068 1069static struct clk_rcg2 gcc_usb30_master_clk_src = {1070 .cmd_rcgr = 0x27034,1071 .mnd_width = 8,1072 .hid_width = 5,1073 .parent_map = gcc_parent_map_0,1074 .freq_tbl = ftbl_gcc_usb30_master_clk_src,1075 .clkr.hw.init = &(const struct clk_init_data) {1076 .name = "gcc_usb30_master_clk_src",1077 .parent_data = gcc_parent_data_0,1078 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1079 .ops = &clk_rcg2_shared_ops,1080 },1081};1082 1083static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {1084 .cmd_rcgr = 0x2704c,1085 .mnd_width = 0,1086 .hid_width = 5,1087 .parent_map = gcc_parent_map_0,1088 .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,1089 .clkr.hw.init = &(const struct clk_init_data) {1090 .name = "gcc_usb30_mock_utmi_clk_src",1091 .parent_data = gcc_parent_data_0,1092 .num_parents = ARRAY_SIZE(gcc_parent_data_0),1093 .ops = &clk_rcg2_shared_ops,1094 },1095};1096 1097static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {1098 F(1000000, P_BI_TCXO, 1, 5, 96),1099 F(19200000, P_BI_TCXO, 1, 0, 0),1100 { }1101};1102 1103static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {1104 .cmd_rcgr = 0x27074,1105 .mnd_width = 16,1106 .hid_width = 5,1107 .parent_map = gcc_parent_map_3,1108 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,1109 .clkr.hw.init = &(const struct clk_init_data) {1110 .name = "gcc_usb3_phy_aux_clk_src",1111 .parent_data = gcc_parent_data_3,1112 .num_parents = ARRAY_SIZE(gcc_parent_data_3),1113 .ops = &clk_rcg2_shared_ops,1114 },1115};1116 1117static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {1118 .reg = 0x67088,1119 .shift = 0,1120 .width = 4,1121 .clkr.hw.init = &(const struct clk_init_data) {1122 .name = "gcc_pcie_1_pipe_div2_clk_src",1123 .parent_hws = (const struct clk_hw*[]) {1124 &gcc_pcie_1_pipe_clk_src.clkr.hw,1125 },1126 .num_parents = 1,1127 .flags = CLK_SET_RATE_PARENT,1128 .ops = &clk_regmap_div_ro_ops,1129 },1130};1131 1132static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src = {1133 .reg = 0x68088,1134 .shift = 0,1135 .width = 4,1136 .clkr.hw.init = &(const struct clk_init_data) {1137 .name = "gcc_pcie_2_pipe_div2_clk_src",1138 .parent_hws = (const struct clk_hw*[]) {1139 &gcc_pcie_2_pipe_clk_src.clkr.hw,1140 },1141 .num_parents = 1,1142 .flags = CLK_SET_RATE_PARENT,1143 .ops = &clk_regmap_div_ro_ops,1144 },1145};1146 1147static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {1148 .reg = 0x27064,1149 .shift = 0,1150 .width = 4,1151 .clkr.hw.init = &(const struct clk_init_data) {1152 .name = "gcc_usb30_mock_utmi_postdiv_clk_src",1153 .parent_hws = (const struct clk_hw*[]) {1154 &gcc_usb30_mock_utmi_clk_src.clkr.hw,1155 },1156 .num_parents = 1,1157 .flags = CLK_SET_RATE_PARENT,1158 .ops = &clk_regmap_div_ro_ops,1159 },1160};1161 1162static struct clk_branch gcc_boot_rom_ahb_clk = {1163 .halt_reg = 0x37004,1164 .halt_check = BRANCH_HALT_VOTED,1165 .hwcg_reg = 0x37004,1166 .hwcg_bit = 1,1167 .clkr = {1168 .enable_reg = 0x7d008,1169 .enable_mask = BIT(26),1170 .hw.init = &(const struct clk_init_data) {1171 .name = "gcc_boot_rom_ahb_clk",1172 .ops = &clk_branch2_ops,1173 },1174 },1175};1176 1177static struct clk_branch gcc_eee_emac0_clk = {1178 .halt_reg = 0x710ac,1179 .halt_check = BRANCH_HALT,1180 .clkr = {1181 .enable_reg = 0x710ac,1182 .enable_mask = BIT(0),1183 .hw.init = &(const struct clk_init_data) {1184 .name = "gcc_eee_emac0_clk",1185 .parent_hws = (const struct clk_hw*[]) {1186 &gcc_eee_emac0_clk_src.clkr.hw,1187 },1188 .num_parents = 1,1189 .flags = CLK_SET_RATE_PARENT,1190 .ops = &clk_branch2_ops,1191 },1192 },1193};1194 1195static struct clk_branch gcc_eee_emac1_clk = {1196 .halt_reg = 0x720ac,1197 .halt_check = BRANCH_HALT,1198 .clkr = {1199 .enable_reg = 0x720ac,1200 .enable_mask = BIT(0),1201 .hw.init = &(const struct clk_init_data) {1202 .name = "gcc_eee_emac1_clk",1203 .parent_hws = (const struct clk_hw*[]) {1204 &gcc_eee_emac1_clk_src.clkr.hw,1205 },1206 .num_parents = 1,1207 .flags = CLK_SET_RATE_PARENT,1208 .ops = &clk_branch2_ops,1209 },1210 },1211};1212 1213static struct clk_branch gcc_emac0_axi_clk = {1214 .halt_reg = 0x71018,1215 .halt_check = BRANCH_HALT_VOTED,1216 .hwcg_reg = 0x71018,1217 .hwcg_bit = 1,1218 .clkr = {1219 .enable_reg = 0x71018,1220 .enable_mask = BIT(0),1221 .hw.init = &(const struct clk_init_data) {1222 .name = "gcc_emac0_axi_clk",1223 .ops = &clk_branch2_ops,1224 },1225 },1226};1227 1228static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk = {1229 .halt_reg = 0x7105c,1230 .halt_check = BRANCH_HALT_DELAY,1231 .clkr = {1232 .enable_reg = 0x7105c,1233 .enable_mask = BIT(0),1234 .hw.init = &(const struct clk_init_data) {1235 .name = "gcc_emac0_cc_sgmiiphy_rx_clk",1236 .parent_hws = (const struct clk_hw*[]) {1237 &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw,1238 },1239 .num_parents = 1,1240 .flags = CLK_SET_RATE_PARENT,1241 .ops = &clk_branch2_ops,1242 },1243 },1244};1245 1246static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk = {1247 .halt_reg = 0x71054,1248 .halt_check = BRANCH_HALT_DELAY,1249 .clkr = {1250 .enable_reg = 0x71054,1251 .enable_mask = BIT(0),1252 .hw.init = &(const struct clk_init_data) {1253 .name = "gcc_emac0_cc_sgmiiphy_tx_clk",1254 .parent_hws = (const struct clk_hw*[]) {1255 &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw,1256 },1257 .num_parents = 1,1258 .flags = CLK_SET_RATE_PARENT,1259 .ops = &clk_branch2_ops,1260 },1261 },1262};1263 1264static struct clk_branch gcc_emac0_phy_aux_clk = {1265 .halt_reg = 0x71028,1266 .halt_check = BRANCH_HALT,1267 .clkr = {1268 .enable_reg = 0x71028,1269 .enable_mask = BIT(0),1270 .hw.init = &(const struct clk_init_data) {1271 .name = "gcc_emac0_phy_aux_clk",1272 .parent_hws = (const struct clk_hw*[]) {1273 &gcc_emac0_phy_aux_clk_src.clkr.hw,1274 },1275 .num_parents = 1,1276 .flags = CLK_SET_RATE_PARENT,1277 .ops = &clk_branch2_ops,1278 },1279 },1280};1281 1282static struct clk_branch gcc_emac0_ptp_clk = {1283 .halt_reg = 0x71044,1284 .halt_check = BRANCH_HALT,1285 .clkr = {1286 .enable_reg = 0x71044,1287 .enable_mask = BIT(0),1288 .hw.init = &(const struct clk_init_data) {1289 .name = "gcc_emac0_ptp_clk",1290 .parent_hws = (const struct clk_hw*[]) {1291 &gcc_emac0_ptp_clk_src.clkr.hw,1292 },1293 .num_parents = 1,1294 .flags = CLK_SET_RATE_PARENT,1295 .ops = &clk_branch2_ops,1296 },1297 },1298};1299 1300static struct clk_branch gcc_emac0_rgmii_clk = {1301 .halt_reg = 0x71050,1302 .halt_check = BRANCH_HALT,1303 .clkr = {1304 .enable_reg = 0x71050,1305 .enable_mask = BIT(0),1306 .hw.init = &(const struct clk_init_data) {1307 .name = "gcc_emac0_rgmii_clk",1308 .parent_hws = (const struct clk_hw*[]) {1309 &gcc_emac0_rgmii_clk_src.clkr.hw,1310 },1311 .num_parents = 1,1312 .flags = CLK_SET_RATE_PARENT,1313 .ops = &clk_branch2_ops,1314 },1315 },1316};1317 1318static struct clk_branch gcc_emac0_rpcs_rx_clk = {1319 .halt_reg = 0x710a0,1320 .halt_check = BRANCH_HALT_DELAY,1321 .clkr = {1322 .enable_reg = 0x710a0,1323 .enable_mask = BIT(0),1324 .hw.init = &(const struct clk_init_data) {1325 .name = "gcc_emac0_rpcs_rx_clk",1326 .parent_hws = (const struct clk_hw*[]) {1327 &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,1328 },1329 .num_parents = 1,1330 .flags = CLK_SET_RATE_PARENT,1331 .ops = &clk_branch2_ops,1332 },1333 },1334};1335 1336static struct clk_branch gcc_emac0_rpcs_tx_clk = {1337 .halt_reg = 0x7109c,1338 .halt_check = BRANCH_HALT_DELAY,1339 .clkr = {1340 .enable_reg = 0x7109c,1341 .enable_mask = BIT(0),1342 .hw.init = &(const struct clk_init_data) {1343 .name = "gcc_emac0_rpcs_tx_clk",1344 .parent_hws = (const struct clk_hw*[]) {1345 &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,1346 },1347 .num_parents = 1,1348 .flags = CLK_SET_RATE_PARENT,1349 .ops = &clk_branch2_ops,1350 },1351 },1352};1353 1354static struct clk_branch gcc_emac0_slv_ahb_clk = {1355 .halt_reg = 0x71024,1356 .halt_check = BRANCH_HALT_VOTED,1357 .hwcg_reg = 0x71024,1358 .hwcg_bit = 1,1359 .clkr = {1360 .enable_reg = 0x71024,1361 .enable_mask = BIT(0),1362 .hw.init = &(const struct clk_init_data) {1363 .name = "gcc_emac0_slv_ahb_clk",1364 .ops = &clk_branch2_ops,1365 },1366 },1367};1368 1369static struct clk_branch gcc_emac0_xgxs_rx_clk = {1370 .halt_reg = 0x710a8,1371 .halt_check = BRANCH_HALT_DELAY,1372 .clkr = {1373 .enable_reg = 0x710a8,1374 .enable_mask = BIT(0),1375 .hw.init = &(const struct clk_init_data) {1376 .name = "gcc_emac0_xgxs_rx_clk",1377 .parent_hws = (const struct clk_hw*[]) {1378 &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw,1379 },1380 .num_parents = 1,1381 .flags = CLK_SET_RATE_PARENT,1382 .ops = &clk_branch2_ops,1383 },1384 },1385};1386 1387static struct clk_branch gcc_emac0_xgxs_tx_clk = {1388 .halt_reg = 0x710a4,1389 .halt_check = BRANCH_HALT_DELAY,1390 .clkr = {1391 .enable_reg = 0x710a4,1392 .enable_mask = BIT(0),1393 .hw.init = &(const struct clk_init_data) {1394 .name = "gcc_emac0_xgxs_tx_clk",1395 .parent_hws = (const struct clk_hw*[]) {1396 &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw,1397 },1398 .num_parents = 1,1399 .flags = CLK_SET_RATE_PARENT,1400 .ops = &clk_branch2_ops,1401 },1402 },1403};1404 1405static struct clk_branch gcc_emac1_axi_clk = {1406 .halt_reg = 0x72018,1407 .halt_check = BRANCH_HALT_VOTED,1408 .hwcg_reg = 0x72018,1409 .hwcg_bit = 1,1410 .clkr = {1411 .enable_reg = 0x72018,1412 .enable_mask = BIT(0),1413 .hw.init = &(const struct clk_init_data) {1414 .name = "gcc_emac1_axi_clk",1415 .ops = &clk_branch2_ops,1416 },1417 },1418};1419 1420static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk = {1421 .halt_reg = 0x7205c,1422 .halt_check = BRANCH_HALT_DELAY,1423 .clkr = {1424 .enable_reg = 0x7205c,1425 .enable_mask = BIT(0),1426 .hw.init = &(const struct clk_init_data) {1427 .name = "gcc_emac1_cc_sgmiiphy_rx_clk",1428 .parent_hws = (const struct clk_hw*[]) {1429 &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw,1430 },1431 .num_parents = 1,1432 .flags = CLK_SET_RATE_PARENT,1433 .ops = &clk_branch2_ops,1434 },1435 },1436};1437 1438static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk = {1439 .halt_reg = 0x72054,1440 .halt_check = BRANCH_HALT_DELAY,1441 .clkr = {1442 .enable_reg = 0x72054,1443 .enable_mask = BIT(0),1444 .hw.init = &(const struct clk_init_data) {1445 .name = "gcc_emac1_cc_sgmiiphy_tx_clk",1446 .parent_hws = (const struct clk_hw*[]) {1447 &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw,1448 },1449 .num_parents = 1,1450 .flags = CLK_SET_RATE_PARENT,1451 .ops = &clk_branch2_ops,1452 },1453 },1454};1455 1456static struct clk_branch gcc_emac1_phy_aux_clk = {1457 .halt_reg = 0x72028,1458 .halt_check = BRANCH_HALT,1459 .clkr = {1460 .enable_reg = 0x72028,1461 .enable_mask = BIT(0),1462 .hw.init = &(const struct clk_init_data) {1463 .name = "gcc_emac1_phy_aux_clk",1464 .parent_hws = (const struct clk_hw*[]) {1465 &gcc_emac1_phy_aux_clk_src.clkr.hw,1466 },1467 .num_parents = 1,1468 .flags = CLK_SET_RATE_PARENT,1469 .ops = &clk_branch2_ops,1470 },1471 },1472};1473 1474static struct clk_branch gcc_emac1_ptp_clk = {1475 .halt_reg = 0x72044,1476 .halt_check = BRANCH_HALT,1477 .clkr = {1478 .enable_reg = 0x72044,1479 .enable_mask = BIT(0),1480 .hw.init = &(const struct clk_init_data) {1481 .name = "gcc_emac1_ptp_clk",1482 .parent_hws = (const struct clk_hw*[]) {1483 &gcc_emac1_ptp_clk_src.clkr.hw,1484 },1485 .num_parents = 1,1486 .flags = CLK_SET_RATE_PARENT,1487 .ops = &clk_branch2_ops,1488 },1489 },1490};1491 1492static struct clk_branch gcc_emac1_rgmii_clk = {1493 .halt_reg = 0x72050,1494 .halt_check = BRANCH_HALT,1495 .clkr = {1496 .enable_reg = 0x72050,1497 .enable_mask = BIT(0),1498 .hw.init = &(const struct clk_init_data) {1499 .name = "gcc_emac1_rgmii_clk",1500 .parent_hws = (const struct clk_hw*[]) {1501 &gcc_emac1_rgmii_clk_src.clkr.hw,1502 },1503 .num_parents = 1,1504 .flags = CLK_SET_RATE_PARENT,1505 .ops = &clk_branch2_ops,1506 },1507 },1508};1509 1510static struct clk_branch gcc_emac1_rpcs_rx_clk = {1511 .halt_reg = 0x720a0,1512 .halt_check = BRANCH_HALT_DELAY,1513 .clkr = {1514 .enable_reg = 0x720a0,1515 .enable_mask = BIT(0),1516 .hw.init = &(const struct clk_init_data) {1517 .name = "gcc_emac1_rpcs_rx_clk",1518 .parent_hws = (const struct clk_hw*[]) {1519 &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,1520 },1521 .num_parents = 1,1522 .flags = CLK_SET_RATE_PARENT,1523 .ops = &clk_branch2_ops,1524 },1525 },1526};1527 1528static struct clk_branch gcc_emac1_rpcs_tx_clk = {1529 .halt_reg = 0x7209c,1530 .halt_check = BRANCH_HALT_DELAY,1531 .clkr = {1532 .enable_reg = 0x7209c,1533 .enable_mask = BIT(0),1534 .hw.init = &(const struct clk_init_data) {1535 .name = "gcc_emac1_rpcs_tx_clk",1536 .parent_hws = (const struct clk_hw*[]) {1537 &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,1538 },1539 .num_parents = 1,1540 .flags = CLK_SET_RATE_PARENT,1541 .ops = &clk_branch2_ops,1542 },1543 },1544};1545 1546static struct clk_branch gcc_emac1_slv_ahb_clk = {1547 .halt_reg = 0x72024,1548 .halt_check = BRANCH_HALT_VOTED,1549 .hwcg_reg = 0x72024,1550 .hwcg_bit = 1,1551 .clkr = {1552 .enable_reg = 0x72024,1553 .enable_mask = BIT(0),1554 .hw.init = &(const struct clk_init_data) {1555 .name = "gcc_emac1_slv_ahb_clk",1556 .ops = &clk_branch2_ops,1557 },1558 },1559};1560 1561static struct clk_branch gcc_emac1_xgxs_rx_clk = {1562 .halt_reg = 0x720a8,1563 .halt_check = BRANCH_HALT_DELAY,1564 .clkr = {1565 .enable_reg = 0x720a8,1566 .enable_mask = BIT(0),1567 .hw.init = &(const struct clk_init_data) {1568 .name = "gcc_emac1_xgxs_rx_clk",1569 .parent_hws = (const struct clk_hw*[]) {1570 &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw,1571 },1572 .num_parents = 1,1573 .flags = CLK_SET_RATE_PARENT,1574 .ops = &clk_branch2_ops,1575 },1576 },1577};1578 1579static struct clk_branch gcc_emac1_xgxs_tx_clk = {1580 .halt_reg = 0x720a4,1581 .halt_check = BRANCH_HALT_DELAY,1582 .clkr = {1583 .enable_reg = 0x720a4,1584 .enable_mask = BIT(0),1585 .hw.init = &(const struct clk_init_data) {1586 .name = "gcc_emac1_xgxs_tx_clk",1587 .parent_hws = (const struct clk_hw*[]) {1588 &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw,1589 },1590 .num_parents = 1,1591 .flags = CLK_SET_RATE_PARENT,1592 .ops = &clk_branch2_ops,1593 },1594 },1595};1596 1597static struct clk_branch gcc_emac_0_clkref_en = {1598 .halt_reg = 0x98108,1599 .halt_check = BRANCH_HALT_ENABLE,1600 .clkr = {1601 .enable_reg = 0x98108,1602 .enable_mask = BIT(0),1603 .hw.init = &(const struct clk_init_data) {1604 .name = "gcc_emac_0_clkref_en",1605 .ops = &clk_branch2_ops,1606 },1607 },1608};1609 1610static struct clk_branch gcc_emac_1_clkref_en = {1611 .halt_reg = 0x9810c,1612 .halt_check = BRANCH_HALT_ENABLE,1613 .clkr = {1614 .enable_reg = 0x9810c,1615 .enable_mask = BIT(0),1616 .hw.init = &(const struct clk_init_data) {1617 .name = "gcc_emac_1_clkref_en",1618 .ops = &clk_branch2_ops,1619 },1620 },1621};1622 1623static struct clk_branch gcc_gp1_clk = {1624 .halt_reg = 0x47000,1625 .halt_check = BRANCH_HALT,1626 .clkr = {1627 .enable_reg = 0x47000,1628 .enable_mask = BIT(0),1629 .hw.init = &(const struct clk_init_data) {1630 .name = "gcc_gp1_clk",1631 .parent_hws = (const struct clk_hw*[]) {1632 &gcc_gp1_clk_src.clkr.hw,1633 },1634 .num_parents = 1,1635 .flags = CLK_SET_RATE_PARENT,1636 .ops = &clk_branch2_ops,1637 },1638 },1639};1640 1641static struct clk_branch gcc_gp2_clk = {1642 .halt_reg = 0x48000,1643 .halt_check = BRANCH_HALT,1644 .clkr = {1645 .enable_reg = 0x48000,1646 .enable_mask = BIT(0),1647 .hw.init = &(const struct clk_init_data) {1648 .name = "gcc_gp2_clk",1649 .parent_hws = (const struct clk_hw*[]) {1650 &gcc_gp2_clk_src.clkr.hw,1651 },1652 .num_parents = 1,1653 .flags = CLK_SET_RATE_PARENT,1654 .ops = &clk_branch2_ops,1655 },1656 },1657};1658 1659static struct clk_branch gcc_gp3_clk = {1660 .halt_reg = 0x49000,1661 .halt_check = BRANCH_HALT,1662 .clkr = {1663 .enable_reg = 0x49000,1664 .enable_mask = BIT(0),1665 .hw.init = &(const struct clk_init_data) {1666 .name = "gcc_gp3_clk",1667 .parent_hws = (const struct clk_hw*[]) {1668 &gcc_gp3_clk_src.clkr.hw,1669 },1670 .num_parents = 1,1671 .flags = CLK_SET_RATE_PARENT,1672 .ops = &clk_branch2_ops,1673 },1674 },1675};1676 1677static struct clk_branch gcc_pcie_0_clkref_en = {1678 .halt_reg = 0x98004,1679 .halt_check = BRANCH_HALT_ENABLE,1680 .clkr = {1681 .enable_reg = 0x98004,1682 .enable_mask = BIT(0),1683 .hw.init = &(const struct clk_init_data) {1684 .name = "gcc_pcie_0_clkref_en",1685 .ops = &clk_branch2_ops,1686 },1687 },1688};1689 1690static struct clk_branch gcc_pcie_1_aux_clk = {1691 .halt_reg = 0x67038,1692 .halt_check = BRANCH_HALT_DELAY,1693 .clkr = {1694 .enable_reg = 0x7d010,1695 .enable_mask = BIT(22),1696 .hw.init = &(const struct clk_init_data) {1697 .name = "gcc_pcie_1_aux_clk",1698 .parent_hws = (const struct clk_hw*[]) {1699 &gcc_pcie_1_aux_phy_clk_src.clkr.hw,1700 },1701 .num_parents = 1,1702 .flags = CLK_SET_RATE_PARENT,1703 .ops = &clk_branch2_ops,1704 },1705 },1706};1707 1708static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {1709 .halt_reg = 0x67034,1710 .halt_check = BRANCH_HALT_VOTED,1711 .hwcg_reg = 0x67034,1712 .hwcg_bit = 1,1713 .clkr = {1714 .enable_reg = 0x7d010,1715 .enable_mask = BIT(21),1716 .hw.init = &(const struct clk_init_data) {1717 .name = "gcc_pcie_1_cfg_ahb_clk",1718 .ops = &clk_branch2_ops,1719 },1720 },1721};1722 1723static struct clk_branch gcc_pcie_1_clkref_en = {1724 .halt_reg = 0x98114,1725 .halt_check = BRANCH_HALT_ENABLE,1726 .clkr = {1727 .enable_reg = 0x98114,1728 .enable_mask = BIT(0),1729 .hw.init = &(const struct clk_init_data) {1730 .name = "gcc_pcie_1_clkref_en",1731 .ops = &clk_branch2_ops,1732 },1733 },1734};1735 1736static struct clk_branch gcc_pcie_1_mstr_axi_clk = {1737 .halt_reg = 0x67028,1738 .halt_check = BRANCH_HALT_VOTED,1739 .clkr = {1740 .enable_reg = 0x7d010,1741 .enable_mask = BIT(20),1742 .hw.init = &(const struct clk_init_data) {1743 .name = "gcc_pcie_1_mstr_axi_clk",1744 .ops = &clk_branch2_ops,1745 },1746 },1747};1748 1749static struct clk_branch gcc_pcie_1_phy_rchng_clk = {1750 .halt_reg = 0x67068,1751 .halt_check = BRANCH_HALT_VOTED,1752 .clkr = {1753 .enable_reg = 0x7d010,1754 .enable_mask = BIT(24),1755 .hw.init = &(const struct clk_init_data) {1756 .name = "gcc_pcie_1_phy_rchng_clk",1757 .parent_hws = (const struct clk_hw*[]) {1758 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,1759 },1760 .num_parents = 1,1761 .flags = CLK_SET_RATE_PARENT,1762 .ops = &clk_branch2_ops,1763 },1764 },1765};1766 1767static struct clk_branch gcc_pcie_1_pipe_clk = {1768 .halt_reg = 0x6705c,1769 .halt_check = BRANCH_HALT_DELAY,1770 .clkr = {1771 .enable_reg = 0x7d010,1772 .enable_mask = BIT(23),1773 .hw.init = &(const struct clk_init_data) {1774 .name = "gcc_pcie_1_pipe_clk",1775 .parent_hws = (const struct clk_hw*[]) {1776 &gcc_pcie_1_pipe_clk_src.clkr.hw,1777 },1778 .num_parents = 1,1779 .flags = CLK_SET_RATE_PARENT,1780 .ops = &clk_branch2_ops,1781 },1782 },1783};1784 1785static struct clk_branch gcc_pcie_1_pipe_div2_clk = {1786 .halt_reg = 0x6708c,1787 .halt_check = BRANCH_HALT_DELAY,1788 .clkr = {1789 .enable_reg = 0x7d020,1790 .enable_mask = BIT(3),1791 .hw.init = &(const struct clk_init_data) {1792 .name = "gcc_pcie_1_pipe_div2_clk",1793 .parent_hws = (const struct clk_hw*[]) {1794 &gcc_pcie_1_pipe_div2_clk_src.clkr.hw,1795 },1796 .num_parents = 1,1797 .flags = CLK_SET_RATE_PARENT,1798 .ops = &clk_branch2_ops,1799 },1800 },1801};1802 1803static struct clk_branch gcc_pcie_1_slv_axi_clk = {1804 .halt_reg = 0x6701c,1805 .halt_check = BRANCH_HALT_VOTED,1806 .clkr = {1807 .enable_reg = 0x7d010,1808 .enable_mask = BIT(19),1809 .hw.init = &(const struct clk_init_data) {1810 .name = "gcc_pcie_1_slv_axi_clk",1811 .ops = &clk_branch2_ops,1812 },1813 },1814};1815 1816static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {1817 .halt_reg = 0x67018,1818 .halt_check = BRANCH_HALT_VOTED,1819 .clkr = {1820 .enable_reg = 0x7d010,1821 .enable_mask = BIT(18),1822 .hw.init = &(const struct clk_init_data) {1823 .name = "gcc_pcie_1_slv_q2a_axi_clk",1824 .ops = &clk_branch2_ops,1825 },1826 },1827};1828 1829static struct clk_branch gcc_pcie_2_aux_clk = {1830 .halt_reg = 0x68058,1831 .halt_check = BRANCH_HALT_DELAY,1832 .clkr = {1833 .enable_reg = 0x7d010,1834 .enable_mask = BIT(29),1835 .hw.init = &(const struct clk_init_data) {1836 .name = "gcc_pcie_2_aux_clk",1837 .parent_hws = (const struct clk_hw*[]) {1838 &gcc_pcie_2_aux_phy_clk_src.clkr.hw,1839 },1840 .num_parents = 1,1841 .flags = CLK_SET_RATE_PARENT,1842 .ops = &clk_branch2_ops,1843 },1844 },1845};1846 1847static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {1848 .halt_reg = 0x68034,1849 .halt_check = BRANCH_HALT_VOTED,1850 .hwcg_reg = 0x68034,1851 .hwcg_bit = 1,1852 .clkr = {1853 .enable_reg = 0x7d010,1854 .enable_mask = BIT(28),1855 .hw.init = &(const struct clk_init_data) {1856 .name = "gcc_pcie_2_cfg_ahb_clk",1857 .ops = &clk_branch2_ops,1858 },1859 },1860};1861 1862static struct clk_branch gcc_pcie_2_clkref_en = {1863 .halt_reg = 0x98110,1864 .halt_check = BRANCH_HALT_ENABLE,1865 .clkr = {1866 .enable_reg = 0x98110,1867 .enable_mask = BIT(0),1868 .hw.init = &(const struct clk_init_data) {1869 .name = "gcc_pcie_2_clkref_en",1870 .ops = &clk_branch2_ops,1871 },1872 },1873};1874 1875static struct clk_branch gcc_pcie_2_mstr_axi_clk = {1876 .halt_reg = 0x68028,1877 .halt_check = BRANCH_HALT_VOTED,1878 .clkr = {1879 .enable_reg = 0x7d008,1880 .enable_mask = BIT(8),1881 .hw.init = &(const struct clk_init_data) {1882 .name = "gcc_pcie_2_mstr_axi_clk",1883 .ops = &clk_branch2_ops,1884 },1885 },1886};1887 1888static struct clk_branch gcc_pcie_2_phy_rchng_clk = {1889 .halt_reg = 0x68098,1890 .halt_check = BRANCH_HALT_VOTED,1891 .clkr = {1892 .enable_reg = 0x7d010,1893 .enable_mask = BIT(31),1894 .hw.init = &(const struct clk_init_data) {1895 .name = "gcc_pcie_2_phy_rchng_clk",1896 .parent_hws = (const struct clk_hw*[]) {1897 &gcc_pcie_2_phy_rchng_clk_src.clkr.hw,1898 },1899 .num_parents = 1,1900 .flags = CLK_SET_RATE_PARENT,1901 .ops = &clk_branch2_ops,1902 },1903 },1904};1905 1906static struct clk_branch gcc_pcie_2_pipe_clk = {1907 .halt_reg = 0x6807c,1908 .halt_check = BRANCH_HALT_DELAY,1909 .clkr = {1910 .enable_reg = 0x7d010,1911 .enable_mask = BIT(30),1912 .hw.init = &(const struct clk_init_data) {1913 .name = "gcc_pcie_2_pipe_clk",1914 .parent_hws = (const struct clk_hw*[]) {1915 &gcc_pcie_2_pipe_clk_src.clkr.hw,1916 },1917 .num_parents = 1,1918 .flags = CLK_SET_RATE_PARENT,1919 .ops = &clk_branch2_ops,1920 },1921 },1922};1923 1924static struct clk_branch gcc_pcie_2_pipe_div2_clk = {1925 .halt_reg = 0x6808c,1926 .halt_check = BRANCH_HALT_DELAY,1927 .clkr = {1928 .enable_reg = 0x7d020,1929 .enable_mask = BIT(4),1930 .hw.init = &(const struct clk_init_data) {1931 .name = "gcc_pcie_2_pipe_div2_clk",1932 .parent_hws = (const struct clk_hw*[]) {1933 &gcc_pcie_2_pipe_div2_clk_src.clkr.hw,1934 },1935 .num_parents = 1,1936 .flags = CLK_SET_RATE_PARENT,1937 .ops = &clk_branch2_ops,1938 },1939 },1940};1941 1942static struct clk_branch gcc_pcie_2_slv_axi_clk = {1943 .halt_reg = 0x6801c,1944 .halt_check = BRANCH_HALT_VOTED,1945 .clkr = {1946 .enable_reg = 0x7d010,1947 .enable_mask = BIT(26),1948 .hw.init = &(const struct clk_init_data) {1949 .name = "gcc_pcie_2_slv_axi_clk",1950 .ops = &clk_branch2_ops,1951 },1952 },1953};1954 1955static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {1956 .halt_reg = 0x68018,1957 .halt_check = BRANCH_HALT_VOTED,1958 .clkr = {1959 .enable_reg = 0x7d010,1960 .enable_mask = BIT(25),1961 .hw.init = &(const struct clk_init_data) {1962 .name = "gcc_pcie_2_slv_q2a_axi_clk",1963 .ops = &clk_branch2_ops,1964 },1965 },1966};1967 1968static struct clk_branch gcc_pcie_aux_clk = {1969 .halt_reg = 0x5303c,1970 .halt_check = BRANCH_HALT_DELAY,1971 .hwcg_reg = 0x5303c,1972 .hwcg_bit = 1,1973 .clkr = {1974 .enable_reg = 0x7d010,1975 .enable_mask = BIT(15),1976 .hw.init = &(const struct clk_init_data) {1977 .name = "gcc_pcie_aux_clk",1978 .parent_hws = (const struct clk_hw*[]) {1979 &gcc_pcie_aux_clk_src.clkr.hw,1980 },1981 .num_parents = 1,1982 .flags = CLK_SET_RATE_PARENT,1983 .ops = &clk_branch2_ops,1984 },1985 },1986};1987 1988static struct clk_branch gcc_pcie_cfg_ahb_clk = {1989 .halt_reg = 0x53034,1990 .halt_check = BRANCH_HALT_VOTED,1991 .hwcg_reg = 0x53034,1992 .hwcg_bit = 1,1993 .clkr = {1994 .enable_reg = 0x7d010,1995 .enable_mask = BIT(13),1996 .hw.init = &(const struct clk_init_data) {1997 .name = "gcc_pcie_cfg_ahb_clk",1998 .ops = &clk_branch2_ops,1999 },2000 },2001};2002 2003static struct clk_branch gcc_pcie_mstr_axi_clk = {2004 .halt_reg = 0x53028,2005 .halt_check = BRANCH_HALT_VOTED,2006 .hwcg_reg = 0x53028,2007 .hwcg_bit = 1,2008 .clkr = {2009 .enable_reg = 0x7d010,2010 .enable_mask = BIT(12),2011 .hw.init = &(const struct clk_init_data) {2012 .name = "gcc_pcie_mstr_axi_clk",2013 .ops = &clk_branch2_ops,2014 },2015 },2016};2017 2018static struct clk_branch gcc_pcie_pipe_clk = {2019 .halt_reg = 0x5304c,2020 .halt_check = BRANCH_HALT_DELAY,2021 .hwcg_reg = 0x5304c,2022 .hwcg_bit = 1,2023 .clkr = {2024 .enable_reg = 0x7d010,2025 .enable_mask = BIT(17),2026 .hw.init = &(const struct clk_init_data) {2027 .name = "gcc_pcie_pipe_clk",2028 .parent_hws = (const struct clk_hw*[]) {2029 &gcc_pcie_pipe_clk_src.clkr.hw,2030 },2031 .num_parents = 1,2032 .flags = CLK_SET_RATE_PARENT,2033 .ops = &clk_branch2_ops,2034 },2035 },2036};2037 2038static struct clk_branch gcc_pcie_rchng_phy_clk = {2039 .halt_reg = 0x53038,2040 .halt_check = BRANCH_HALT_VOTED,2041 .hwcg_reg = 0x53038,2042 .hwcg_bit = 1,2043 .clkr = {2044 .enable_reg = 0x7d010,2045 .enable_mask = BIT(14),2046 .hw.init = &(const struct clk_init_data) {2047 .name = "gcc_pcie_rchng_phy_clk",2048 .parent_hws = (const struct clk_hw*[]) {2049 &gcc_pcie_rchng_phy_clk_src.clkr.hw,2050 },2051 .num_parents = 1,2052 .flags = CLK_SET_RATE_PARENT,2053 .ops = &clk_branch2_ops,2054 },2055 },2056};2057 2058static struct clk_branch gcc_pcie_sleep_clk = {2059 .halt_reg = 0x53048,2060 .halt_check = BRANCH_HALT_VOTED,2061 .hwcg_reg = 0x53048,2062 .hwcg_bit = 1,2063 .clkr = {2064 .enable_reg = 0x7d010,2065 .enable_mask = BIT(16),2066 .hw.init = &(const struct clk_init_data) {2067 .name = "gcc_pcie_sleep_clk",2068 .parent_hws = (const struct clk_hw*[]) {2069 &gcc_pcie_aux_phy_clk_src.clkr.hw,2070 },2071 .num_parents = 1,2072 .flags = CLK_SET_RATE_PARENT,2073 .ops = &clk_branch2_ops,2074 },2075 },2076};2077 2078static struct clk_branch gcc_pcie_slv_axi_clk = {2079 .halt_reg = 0x5301c,2080 .halt_check = BRANCH_HALT_VOTED,2081 .clkr = {2082 .enable_reg = 0x7d010,2083 .enable_mask = BIT(11),2084 .hw.init = &(const struct clk_init_data) {2085 .name = "gcc_pcie_slv_axi_clk",2086 .ops = &clk_branch2_ops,2087 },2088 },2089};2090 2091static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {2092 .halt_reg = 0x53018,2093 .halt_check = BRANCH_HALT_VOTED,2094 .hwcg_reg = 0x53018,2095 .hwcg_bit = 1,2096 .clkr = {2097 .enable_reg = 0x7d010,2098 .enable_mask = BIT(10),2099 .hw.init = &(const struct clk_init_data) {2100 .name = "gcc_pcie_slv_q2a_axi_clk",2101 .ops = &clk_branch2_ops,2102 },2103 },2104};2105 2106static struct clk_branch gcc_pdm2_clk = {2107 .halt_reg = 0x3400c,2108 .halt_check = BRANCH_HALT,2109 .clkr = {2110 .enable_reg = 0x3400c,2111 .enable_mask = BIT(0),2112 .hw.init = &(const struct clk_init_data) {2113 .name = "gcc_pdm2_clk",2114 .parent_hws = (const struct clk_hw*[]) {2115 &gcc_pdm2_clk_src.clkr.hw,2116 },2117 .num_parents = 1,2118 .flags = CLK_SET_RATE_PARENT,2119 .ops = &clk_branch2_ops,2120 },2121 },2122};2123 2124static struct clk_branch gcc_pdm_ahb_clk = {2125 .halt_reg = 0x34004,2126 .halt_check = BRANCH_HALT,2127 .clkr = {2128 .enable_reg = 0x34004,2129 .enable_mask = BIT(0),2130 .hw.init = &(const struct clk_init_data) {2131 .name = "gcc_pdm_ahb_clk",2132 .ops = &clk_branch2_ops,2133 },2134 },2135};2136 2137static struct clk_branch gcc_pdm_xo4_clk = {2138 .halt_reg = 0x34008,2139 .halt_check = BRANCH_HALT,2140 .clkr = {2141 .enable_reg = 0x34008,2142 .enable_mask = BIT(0),2143 .hw.init = &(const struct clk_init_data) {2144 .name = "gcc_pdm_xo4_clk",2145 .ops = &clk_branch2_ops,2146 },2147 },2148};2149 2150static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {2151 .halt_reg = 0x2d018,2152 .halt_check = BRANCH_HALT_VOTED,2153 .clkr = {2154 .enable_reg = 0x7d008,2155 .enable_mask = BIT(15),2156 .hw.init = &(const struct clk_init_data) {2157 .name = "gcc_qupv3_wrap0_core_2x_clk",2158 .ops = &clk_branch2_ops,2159 },2160 },2161};2162 2163static struct clk_branch gcc_qupv3_wrap0_core_clk = {2164 .halt_reg = 0x2d008,2165 .halt_check = BRANCH_HALT_VOTED,2166 .clkr = {2167 .enable_reg = 0x7d008,2168 .enable_mask = BIT(14),2169 .hw.init = &(const struct clk_init_data) {2170 .name = "gcc_qupv3_wrap0_core_clk",2171 .ops = &clk_branch2_ops,2172 },2173 },2174};2175 2176static struct clk_branch gcc_qupv3_wrap0_s0_clk = {2177 .halt_reg = 0x6c004,2178 .halt_check = BRANCH_HALT_VOTED,2179 .clkr = {2180 .enable_reg = 0x7d008,2181 .enable_mask = BIT(16),2182 .hw.init = &(const struct clk_init_data) {2183 .name = "gcc_qupv3_wrap0_s0_clk",2184 .parent_hws = (const struct clk_hw*[]) {2185 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,2186 },2187 .num_parents = 1,2188 .flags = CLK_SET_RATE_PARENT,2189 .ops = &clk_branch2_ops,2190 },2191 },2192};2193 2194static struct clk_branch gcc_qupv3_wrap0_s1_clk = {2195 .halt_reg = 0x6c13c,2196 .halt_check = BRANCH_HALT_VOTED,2197 .clkr = {2198 .enable_reg = 0x7d008,2199 .enable_mask = BIT(17),2200 .hw.init = &(const struct clk_init_data) {2201 .name = "gcc_qupv3_wrap0_s1_clk",2202 .parent_hws = (const struct clk_hw*[]) {2203 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,2204 },2205 .num_parents = 1,2206 .flags = CLK_SET_RATE_PARENT,2207 .ops = &clk_branch2_ops,2208 },2209 },2210};2211 2212static struct clk_branch gcc_qupv3_wrap0_s2_clk = {2213 .halt_reg = 0x6c274,2214 .halt_check = BRANCH_HALT_VOTED,2215 .clkr = {2216 .enable_reg = 0x7d008,2217 .enable_mask = BIT(18),2218 .hw.init = &(const struct clk_init_data) {2219 .name = "gcc_qupv3_wrap0_s2_clk",2220 .parent_hws = (const struct clk_hw*[]) {2221 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,2222 },2223 .num_parents = 1,2224 .flags = CLK_SET_RATE_PARENT,2225 .ops = &clk_branch2_ops,2226 },2227 },2228};2229 2230static struct clk_branch gcc_qupv3_wrap0_s3_clk = {2231 .halt_reg = 0x6c3ac,2232 .halt_check = BRANCH_HALT_VOTED,2233 .clkr = {2234 .enable_reg = 0x7d008,2235 .enable_mask = BIT(19),2236 .hw.init = &(const struct clk_init_data) {2237 .name = "gcc_qupv3_wrap0_s3_clk",2238 .parent_hws = (const struct clk_hw*[]) {2239 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,2240 },2241 .num_parents = 1,2242 .flags = CLK_SET_RATE_PARENT,2243 .ops = &clk_branch2_ops,2244 },2245 },2246};2247 2248static struct clk_branch gcc_qupv3_wrap0_s4_clk = {2249 .halt_reg = 0x6c4e4,2250 .halt_check = BRANCH_HALT_VOTED,2251 .clkr = {2252 .enable_reg = 0x7d008,2253 .enable_mask = BIT(20),2254 .hw.init = &(const struct clk_init_data) {2255 .name = "gcc_qupv3_wrap0_s4_clk",2256 .parent_hws = (const struct clk_hw*[]) {2257 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,2258 },2259 .num_parents = 1,2260 .flags = CLK_SET_RATE_PARENT,2261 .ops = &clk_branch2_ops,2262 },2263 },2264};2265 2266static struct clk_branch gcc_qupv3_wrap0_s5_clk = {2267 .halt_reg = 0x6c61c,2268 .halt_check = BRANCH_HALT_VOTED,2269 .clkr = {2270 .enable_reg = 0x7d008,2271 .enable_mask = BIT(21),2272 .hw.init = &(const struct clk_init_data) {2273 .name = "gcc_qupv3_wrap0_s5_clk",2274 .parent_hws = (const struct clk_hw*[]) {2275 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,2276 },2277 .num_parents = 1,2278 .flags = CLK_SET_RATE_PARENT,2279 .ops = &clk_branch2_ops,2280 },2281 },2282};2283 2284static struct clk_branch gcc_qupv3_wrap0_s6_clk = {2285 .halt_reg = 0x6c754,2286 .halt_check = BRANCH_HALT_VOTED,2287 .clkr = {2288 .enable_reg = 0x7d008,2289 .enable_mask = BIT(22),2290 .hw.init = &(const struct clk_init_data) {2291 .name = "gcc_qupv3_wrap0_s6_clk",2292 .parent_hws = (const struct clk_hw*[]) {2293 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,2294 },2295 .num_parents = 1,2296 .flags = CLK_SET_RATE_PARENT,2297 .ops = &clk_branch2_ops,2298 },2299 },2300};2301 2302static struct clk_branch gcc_qupv3_wrap0_s7_clk = {2303 .halt_reg = 0x6c88c,2304 .halt_check = BRANCH_HALT_VOTED,2305 .clkr = {2306 .enable_reg = 0x7d008,2307 .enable_mask = BIT(23),2308 .hw.init = &(const struct clk_init_data) {2309 .name = "gcc_qupv3_wrap0_s7_clk",2310 .parent_hws = (const struct clk_hw*[]) {2311 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,2312 },2313 .num_parents = 1,2314 .flags = CLK_SET_RATE_PARENT,2315 .ops = &clk_branch2_ops,2316 },2317 },2318};2319 2320static struct clk_branch gcc_qupv3_wrap0_s8_clk = {2321 .halt_reg = 0x6c9c4,2322 .halt_check = BRANCH_HALT_VOTED,2323 .clkr = {2324 .enable_reg = 0x7d020,2325 .enable_mask = BIT(7),2326 .hw.init = &(const struct clk_init_data) {2327 .name = "gcc_qupv3_wrap0_s8_clk",2328 .parent_hws = (const struct clk_hw*[]) {2329 &gcc_qupv3_wrap0_s8_clk_src.clkr.hw,2330 },2331 .num_parents = 1,2332 .flags = CLK_SET_RATE_PARENT,2333 .ops = &clk_branch2_ops,2334 },2335 },2336};2337 2338static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {2339 .halt_reg = 0x2d000,2340 .halt_check = BRANCH_HALT_VOTED,2341 .hwcg_reg = 0x2d000,2342 .hwcg_bit = 1,2343 .clkr = {2344 .enable_reg = 0x7d008,2345 .enable_mask = BIT(12),2346 .hw.init = &(const struct clk_init_data) {2347 .name = "gcc_qupv3_wrap_0_m_ahb_clk",2348 .ops = &clk_branch2_ops,2349 },2350 },2351};2352 2353static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {2354 .halt_reg = 0x2d004,2355 .halt_check = BRANCH_HALT_VOTED,2356 .hwcg_reg = 0x2d004,2357 .hwcg_bit = 1,2358 .clkr = {2359 .enable_reg = 0x7d008,2360 .enable_mask = BIT(13),2361 .hw.init = &(const struct clk_init_data) {2362 .name = "gcc_qupv3_wrap_0_s_ahb_clk",2363 .ops = &clk_branch2_ops,2364 },2365 },2366};2367 2368static struct clk_branch gcc_sdcc1_ahb_clk = {2369 .halt_reg = 0x6b004,2370 .halt_check = BRANCH_HALT,2371 .clkr = {2372 .enable_reg = 0x6b004,2373 .enable_mask = BIT(0),2374 .hw.init = &(const struct clk_init_data) {2375 .name = "gcc_sdcc1_ahb_clk",2376 .ops = &clk_branch2_ops,2377 },2378 },2379};2380 2381static struct clk_branch gcc_sdcc1_apps_clk = {2382 .halt_reg = 0x6b008,2383 .halt_check = BRANCH_HALT,2384 .clkr = {2385 .enable_reg = 0x6b008,2386 .enable_mask = BIT(0),2387 .hw.init = &(const struct clk_init_data) {2388 .name = "gcc_sdcc1_apps_clk",2389 .parent_hws = (const struct clk_hw*[]) {2390 &gcc_sdcc1_apps_clk_src.clkr.hw,2391 },2392 .num_parents = 1,2393 .flags = CLK_SET_RATE_PARENT,2394 .ops = &clk_branch2_ops,2395 },2396 },2397};2398 2399static struct clk_branch gcc_sdcc2_ahb_clk = {2400 .halt_reg = 0x6a010,2401 .halt_check = BRANCH_HALT,2402 .clkr = {2403 .enable_reg = 0x6a010,2404 .enable_mask = BIT(0),2405 .hw.init = &(const struct clk_init_data) {2406 .name = "gcc_sdcc2_ahb_clk",2407 .ops = &clk_branch2_ops,2408 },2409 },2410};2411 2412static struct clk_branch gcc_sdcc2_apps_clk = {2413 .halt_reg = 0x6a004,2414 .halt_check = BRANCH_HALT,2415 .clkr = {2416 .enable_reg = 0x6a004,2417 .enable_mask = BIT(0),2418 .hw.init = &(const struct clk_init_data) {2419 .name = "gcc_sdcc2_apps_clk",2420 .parent_hws = (const struct clk_hw*[]) {2421 &gcc_sdcc2_apps_clk_src.clkr.hw,2422 },2423 .num_parents = 1,2424 .flags = CLK_SET_RATE_PARENT,2425 .ops = &clk_branch2_ops,2426 },2427 },2428};2429 2430static struct clk_branch gcc_usb2_clkref_en = {2431 .halt_reg = 0x98008,2432 .halt_check = BRANCH_HALT_ENABLE,2433 .clkr = {2434 .enable_reg = 0x98008,2435 .enable_mask = BIT(0),2436 .hw.init = &(const struct clk_init_data) {2437 .name = "gcc_usb2_clkref_en",2438 .ops = &clk_branch2_ops,2439 },2440 },2441};2442 2443static struct clk_branch gcc_usb30_master_clk = {2444 .halt_reg = 0x27018,2445 .halt_check = BRANCH_HALT,2446 .clkr = {2447 .enable_reg = 0x27018,2448 .enable_mask = BIT(0),2449 .hw.init = &(const struct clk_init_data) {2450 .name = "gcc_usb30_master_clk",2451 .parent_hws = (const struct clk_hw*[]) {2452 &gcc_usb30_master_clk_src.clkr.hw,2453 },2454 .num_parents = 1,2455 .flags = CLK_SET_RATE_PARENT,2456 .ops = &clk_branch2_ops,2457 },2458 },2459};2460 2461static struct clk_branch gcc_usb30_mock_utmi_clk = {2462 .halt_reg = 0x27030,2463 .halt_check = BRANCH_HALT,2464 .clkr = {2465 .enable_reg = 0x27030,2466 .enable_mask = BIT(0),2467 .hw.init = &(const struct clk_init_data) {2468 .name = "gcc_usb30_mock_utmi_clk",2469 .parent_hws = (const struct clk_hw*[]) {2470 &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,2471 },2472 .num_parents = 1,2473 .flags = CLK_SET_RATE_PARENT,2474 .ops = &clk_branch2_ops,2475 },2476 },2477};2478 2479static struct clk_branch gcc_usb30_mstr_axi_clk = {2480 .halt_reg = 0x27024,2481 .halt_check = BRANCH_HALT,2482 .clkr = {2483 .enable_reg = 0x27024,2484 .enable_mask = BIT(0),2485 .hw.init = &(const struct clk_init_data) {2486 .name = "gcc_usb30_mstr_axi_clk",2487 .ops = &clk_branch2_ops,2488 },2489 },2490};2491 2492static struct clk_branch gcc_usb30_sleep_clk = {2493 .halt_reg = 0x2702c,2494 .halt_check = BRANCH_HALT,2495 .clkr = {2496 .enable_reg = 0x2702c,2497 .enable_mask = BIT(0),2498 .hw.init = &(const struct clk_init_data) {2499 .name = "gcc_usb30_sleep_clk",2500 .ops = &clk_branch2_ops,2501 },2502 },2503};2504 2505static struct clk_branch gcc_usb30_slv_ahb_clk = {2506 .halt_reg = 0x27028,2507 .halt_check = BRANCH_HALT,2508 .clkr = {2509 .enable_reg = 0x27028,2510 .enable_mask = BIT(0),2511 .hw.init = &(const struct clk_init_data) {2512 .name = "gcc_usb30_slv_ahb_clk",2513 .ops = &clk_branch2_ops,2514 },2515 },2516};2517 2518static struct clk_branch gcc_usb3_phy_aux_clk = {2519 .halt_reg = 0x27068,2520 .halt_check = BRANCH_HALT,2521 .clkr = {2522 .enable_reg = 0x27068,2523 .enable_mask = BIT(0),2524 .hw.init = &(const struct clk_init_data) {2525 .name = "gcc_usb3_phy_aux_clk",2526 .parent_hws = (const struct clk_hw*[]) {2527 &gcc_usb3_phy_aux_clk_src.clkr.hw,2528 },2529 .num_parents = 1,2530 .flags = CLK_SET_RATE_PARENT,2531 .ops = &clk_branch2_ops,2532 },2533 },2534};2535 2536static struct clk_branch gcc_usb3_phy_pipe_clk = {2537 .halt_reg = 0x2706c,2538 .halt_check = BRANCH_HALT_DELAY,2539 .hwcg_reg = 0x2706c,2540 .hwcg_bit = 1,2541 .clkr = {2542 .enable_reg = 0x2706c,2543 .enable_mask = BIT(0),2544 .hw.init = &(const struct clk_init_data) {2545 .name = "gcc_usb3_phy_pipe_clk",2546 .parent_hws = (const struct clk_hw*[]) {2547 &gcc_usb3_phy_pipe_clk_src.clkr.hw,2548 },2549 .num_parents = 1,2550 .flags = CLK_SET_RATE_PARENT,2551 .ops = &clk_branch2_ops,2552 },2553 },2554};2555 2556static struct clk_branch gcc_usb3_prim_clkref_en = {2557 .halt_reg = 0x98000,2558 .halt_check = BRANCH_HALT_ENABLE,2559 .clkr = {2560 .enable_reg = 0x98000,2561 .enable_mask = BIT(0),2562 .hw.init = &(const struct clk_init_data) {2563 .name = "gcc_usb3_prim_clkref_en",2564 .ops = &clk_branch2_ops,2565 },2566 },2567};2568 2569static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {2570 .halt_reg = 0x29004,2571 .halt_check = BRANCH_HALT,2572 .hwcg_reg = 0x29004,2573 .hwcg_bit = 1,2574 .clkr = {2575 .enable_reg = 0x29004,2576 .enable_mask = BIT(0),2577 .hw.init = &(const struct clk_init_data) {2578 .name = "gcc_usb_phy_cfg_ahb2phy_clk",2579 .ops = &clk_branch2_aon_ops,2580 },2581 },2582};2583 2584static struct gdsc gcc_emac0_gdsc = {2585 .gdscr = 0x71004,2586 .en_rest_wait_val = 0x2,2587 .en_few_wait_val = 0x2,2588 .clk_dis_wait_val = 0xf,2589 .pd = {2590 .name = "gcc_emac0_gdsc",2591 },2592 .pwrsts = PWRSTS_OFF_ON,2593 .flags = RETAIN_FF_ENABLE,2594};2595 2596static struct gdsc gcc_emac1_gdsc = {2597 .gdscr = 0x72004,2598 .en_rest_wait_val = 0x2,2599 .en_few_wait_val = 0x2,2600 .clk_dis_wait_val = 0xf,2601 .pd = {2602 .name = "gcc_emac1_gdsc",2603 },2604 .pwrsts = PWRSTS_OFF_ON,2605 .flags = RETAIN_FF_ENABLE,2606};2607 2608static struct gdsc gcc_pcie_1_gdsc = {2609 .gdscr = 0x67004,2610 .en_rest_wait_val = 0x2,2611 .en_few_wait_val = 0x2,2612 .clk_dis_wait_val = 0xf,2613 .pd = {2614 .name = "gcc_pcie_1_gdsc",2615 },2616 .pwrsts = PWRSTS_OFF_ON,2617 .flags = RETAIN_FF_ENABLE,2618};2619 2620static struct gdsc gcc_pcie_1_phy_gdsc = {2621 .gdscr = 0x56004,2622 .en_rest_wait_val = 0x2,2623 .en_few_wait_val = 0x2,2624 .clk_dis_wait_val = 0x2,2625 .pd = {2626 .name = "gcc_pcie_1_phy_gdsc",2627 },2628 .pwrsts = PWRSTS_OFF_ON,2629 .flags = RETAIN_FF_ENABLE,2630};2631 2632static struct gdsc gcc_pcie_2_gdsc = {2633 .gdscr = 0x68004,2634 .en_rest_wait_val = 0x2,2635 .en_few_wait_val = 0x2,2636 .clk_dis_wait_val = 0xf,2637 .pd = {2638 .name = "gcc_pcie_2_gdsc",2639 },2640 .pwrsts = PWRSTS_OFF_ON,2641 .flags = RETAIN_FF_ENABLE,2642};2643 2644static struct gdsc gcc_pcie_2_phy_gdsc = {2645 .gdscr = 0x6e004,2646 .en_rest_wait_val = 0x2,2647 .en_few_wait_val = 0x2,2648 .clk_dis_wait_val = 0x2,2649 .pd = {2650 .name = "gcc_pcie_2_phy_gdsc",2651 },2652 .pwrsts = PWRSTS_OFF_ON,2653 .flags = RETAIN_FF_ENABLE,2654};2655 2656static struct gdsc gcc_pcie_gdsc = {2657 .gdscr = 0x53004,2658 .en_rest_wait_val = 0x2,2659 .en_few_wait_val = 0x2,2660 .clk_dis_wait_val = 0xf,2661 .pd = {2662 .name = "gcc_pcie_gdsc",2663 },2664 .pwrsts = PWRSTS_OFF_ON,2665 .flags = RETAIN_FF_ENABLE,2666};2667 2668static struct gdsc gcc_pcie_phy_gdsc = {2669 .gdscr = 0x54004,2670 .en_rest_wait_val = 0x2,2671 .en_few_wait_val = 0x2,2672 .clk_dis_wait_val = 0x2,2673 .pd = {2674 .name = "gcc_pcie_phy_gdsc",2675 },2676 .pwrsts = PWRSTS_OFF_ON,2677 .flags = RETAIN_FF_ENABLE,2678};2679 2680static struct gdsc gcc_usb30_gdsc = {2681 .gdscr = 0x27004,2682 .en_rest_wait_val = 0x2,2683 .en_few_wait_val = 0x2,2684 .clk_dis_wait_val = 0xf,2685 .pd = {2686 .name = "gcc_usb30_gdsc",2687 },2688 .pwrsts = PWRSTS_OFF_ON,2689 .flags = RETAIN_FF_ENABLE,2690};2691 2692static struct gdsc gcc_usb3_phy_gdsc = {2693 .gdscr = 0x28008,2694 .en_rest_wait_val = 0x2,2695 .en_few_wait_val = 0x2,2696 .clk_dis_wait_val = 0x2,2697 .pd = {2698 .name = "gcc_usb3_phy_gdsc",2699 },2700 .pwrsts = PWRSTS_OFF_ON,2701 .flags = RETAIN_FF_ENABLE,2702};2703 2704static struct clk_regmap *gcc_sdx75_clocks[] = {2705 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,2706 [GCC_EEE_EMAC0_CLK] = &gcc_eee_emac0_clk.clkr,2707 [GCC_EEE_EMAC0_CLK_SRC] = &gcc_eee_emac0_clk_src.clkr,2708 [GCC_EEE_EMAC1_CLK] = &gcc_eee_emac1_clk.clkr,2709 [GCC_EEE_EMAC1_CLK_SRC] = &gcc_eee_emac1_clk_src.clkr,2710 [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,2711 [GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &gcc_emac0_cc_sgmiiphy_rx_clk.clkr,2712 [GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr,2713 [GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &gcc_emac0_cc_sgmiiphy_tx_clk.clkr,2714 [GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr,2715 [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,2716 [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,2717 [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,2718 [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,2719 [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,2720 [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,2721 [GCC_EMAC0_RPCS_RX_CLK] = &gcc_emac0_rpcs_rx_clk.clkr,2722 [GCC_EMAC0_RPCS_TX_CLK] = &gcc_emac0_rpcs_tx_clk.clkr,2723 [GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac0_sgmiiphy_mac_rclk_src.clkr,2724 [GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac0_sgmiiphy_mac_tclk_src.clkr,2725 [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,2726 [GCC_EMAC0_XGXS_RX_CLK] = &gcc_emac0_xgxs_rx_clk.clkr,2727 [GCC_EMAC0_XGXS_TX_CLK] = &gcc_emac0_xgxs_tx_clk.clkr,2728 [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,2729 [GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &gcc_emac1_cc_sgmiiphy_rx_clk.clkr,2730 [GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr,2731 [GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &gcc_emac1_cc_sgmiiphy_tx_clk.clkr,2732 [GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] = &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr,2733 [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,2734 [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,2735 [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,2736 [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,2737 [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,2738 [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,2739 [GCC_EMAC1_RPCS_RX_CLK] = &gcc_emac1_rpcs_rx_clk.clkr,2740 [GCC_EMAC1_RPCS_TX_CLK] = &gcc_emac1_rpcs_tx_clk.clkr,2741 [GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] = &gcc_emac1_sgmiiphy_mac_rclk_src.clkr,2742 [GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] = &gcc_emac1_sgmiiphy_mac_tclk_src.clkr,2743 [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,2744 [GCC_EMAC1_XGXS_RX_CLK] = &gcc_emac1_xgxs_rx_clk.clkr,2745 [GCC_EMAC1_XGXS_TX_CLK] = &gcc_emac1_xgxs_tx_clk.clkr,2746 [GCC_EMAC_0_CLKREF_EN] = &gcc_emac_0_clkref_en.clkr,2747 [GCC_EMAC_1_CLKREF_EN] = &gcc_emac_1_clkref_en.clkr,2748 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,2749 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,2750 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,2751 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,2752 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,2753 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,2754 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,2755 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,2756 [GCC_PCIE_1_AUX_PHY_CLK_SRC] = &gcc_pcie_1_aux_phy_clk_src.clkr,2757 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,2758 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,2759 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,2760 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,2761 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,2762 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,2763 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,2764 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,2765 [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,2766 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,2767 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,2768 [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,2769 [GCC_PCIE_2_AUX_PHY_CLK_SRC] = &gcc_pcie_2_aux_phy_clk_src.clkr,2770 [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,2771 [GCC_PCIE_2_CLKREF_EN] = &gcc_pcie_2_clkref_en.clkr,2772 [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,2773 [GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr,2774 [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,2775 [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,2776 [GCC_PCIE_2_PIPE_CLK_SRC] = &gcc_pcie_2_pipe_clk_src.clkr,2777 [GCC_PCIE_2_PIPE_DIV2_CLK] = &gcc_pcie_2_pipe_div2_clk.clkr,2778 [GCC_PCIE_2_PIPE_DIV2_CLK_SRC] = &gcc_pcie_2_pipe_div2_clk_src.clkr,2779 [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,2780 [GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,2781 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,2782 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,2783 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,2784 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,2785 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,2786 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,2787 [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,2788 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,2789 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,2790 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,2791 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,2792 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,2793 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,2794 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,2795 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,2796 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,2797 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,2798 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,2799 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,2800 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,2801 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,2802 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,2803 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,2804 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,2805 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,2806 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,2807 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,2808 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,2809 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,2810 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,2811 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,2812 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,2813 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,2814 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,2815 [GCC_QUPV3_WRAP0_S8_CLK] = &gcc_qupv3_wrap0_s8_clk.clkr,2816 [GCC_QUPV3_WRAP0_S8_CLK_SRC] = &gcc_qupv3_wrap0_s8_clk_src.clkr,2817 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,2818 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,2819 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,2820 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,2821 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,2822 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,2823 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,2824 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,2825 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,2826 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,2827 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,2828 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,2829 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,2830 [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,2831 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,2832 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,2833 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,2834 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,2835 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,2836 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,2837 [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,2838 [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,2839 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,2840 [GPLL0] = &gpll0.clkr,2841 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,2842 [GPLL4] = &gpll4.clkr,2843 [GPLL5] = &gpll5.clkr,2844 [GPLL6] = &gpll6.clkr,2845 [GPLL8] = &gpll8.clkr,2846};2847 2848static struct gdsc *gcc_sdx75_gdscs[] = {2849 [GCC_EMAC0_GDSC] = &gcc_emac0_gdsc,2850 [GCC_EMAC1_GDSC] = &gcc_emac1_gdsc,2851 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,2852 [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc,2853 [GCC_PCIE_2_GDSC] = &gcc_pcie_2_gdsc,2854 [GCC_PCIE_2_PHY_GDSC] = &gcc_pcie_2_phy_gdsc,2855 [GCC_PCIE_GDSC] = &gcc_pcie_gdsc,2856 [GCC_PCIE_PHY_GDSC] = &gcc_pcie_phy_gdsc,2857 [GCC_USB30_GDSC] = &gcc_usb30_gdsc,2858 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,2859};2860 2861static const struct qcom_reset_map gcc_sdx75_resets[] = {2862 [GCC_EMAC0_BCR] = { 0x71000 },2863 [GCC_EMAC0_RGMII_CLK_ARES] = { 0x71050, 2 },2864 [GCC_EMAC1_BCR] = { 0x72000 },2865 [GCC_EMMC_BCR] = { 0x6b000 },2866 [GCC_PCIE_1_BCR] = { 0x67000 },2867 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e700 },2868 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x56120 },2869 [GCC_PCIE_1_PHY_BCR] = { 0x56000 },2870 [GCC_PCIE_2_BCR] = { 0x68000 },2871 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x9f700 },2872 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x6e130 },2873 [GCC_PCIE_2_PHY_BCR] = { 0x6e000 },2874 [GCC_PCIE_BCR] = { 0x53000 },2875 [GCC_PCIE_LINK_DOWN_BCR] = { 0x87000 },2876 [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x88008 },2877 [GCC_PCIE_PHY_BCR] = { 0x54000 },2878 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x88000 },2879 [GCC_PCIE_PHY_COM_BCR] = { 0x88004 },2880 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x8800c },2881 [GCC_QUSB2PHY_BCR] = { 0x2a000 },2882 [GCC_TCSR_PCIE_BCR] = { 0x84000 },2883 [GCC_USB30_BCR] = { 0x27000 },2884 [GCC_USB3_PHY_BCR] = { 0x28000 },2885 [GCC_USB3PHY_PHY_BCR] = { 0x28004 },2886 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x29000 },2887};2888 2889static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {2890 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),2891 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),2892 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),2893 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),2894 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),2895 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),2896 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),2897 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),2898 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src),2899};2900 2901static const struct regmap_config gcc_sdx75_regmap_config = {2902 .reg_bits = 32,2903 .reg_stride = 4,2904 .val_bits = 32,2905 .max_register = 0x1f41f0,2906 .fast_io = true,2907};2908 2909static const struct qcom_cc_desc gcc_sdx75_desc = {2910 .config = &gcc_sdx75_regmap_config,2911 .clks = gcc_sdx75_clocks,2912 .num_clks = ARRAY_SIZE(gcc_sdx75_clocks),2913 .resets = gcc_sdx75_resets,2914 .num_resets = ARRAY_SIZE(gcc_sdx75_resets),2915 .gdscs = gcc_sdx75_gdscs,2916 .num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),2917};2918 2919static const struct of_device_id gcc_sdx75_match_table[] = {2920 { .compatible = "qcom,sdx75-gcc" },2921 { }2922};2923MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table);2924 2925static int gcc_sdx75_probe(struct platform_device *pdev)2926{2927 struct regmap *regmap;2928 int ret;2929 2930 regmap = qcom_cc_map(pdev, &gcc_sdx75_desc);2931 if (IS_ERR(regmap))2932 return PTR_ERR(regmap);2933 2934 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,2935 ARRAY_SIZE(gcc_dfs_clocks));2936 if (ret)2937 return ret;2938 2939 /* Keep some clocks always-on */2940 qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */2941 qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */2942 2943 return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap);2944}2945 2946static struct platform_driver gcc_sdx75_driver = {2947 .probe = gcc_sdx75_probe,2948 .driver = {2949 .name = "gcc-sdx75",2950 .of_match_table = gcc_sdx75_match_table,2951 },2952};2953 2954static int __init gcc_sdx75_init(void)2955{2956 return platform_driver_register(&gcc_sdx75_driver);2957}2958subsys_initcall(gcc_sdx75_init);2959 2960static void __exit gcc_sdx75_exit(void)2961{2962 platform_driver_unregister(&gcc_sdx75_driver);2963}2964module_exit(gcc_sdx75_exit);2965 2966MODULE_DESCRIPTION("QTI GCC SDX75 Driver");2967MODULE_LICENSE("GPL");2968