2889 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/regmap.h>11 12#include <dt-bindings/clock/qcom,sm4450-gcc.h>13 14#include "clk-alpha-pll.h"15#include "clk-branch.h"16#include "clk-rcg.h"17#include "clk-regmap.h"18#include "clk-regmap-divider.h"19#include "clk-regmap-mux.h"20#include "clk-regmap-phy-mux.h"21#include "gdsc.h"22#include "reset.h"23 24enum {25 DT_BI_TCXO,26 DT_SLEEP_CLK,27 DT_PCIE_0_PIPE_CLK,28 DT_UFS_PHY_RX_SYMBOL_0_CLK,29 DT_UFS_PHY_RX_SYMBOL_1_CLK,30 DT_UFS_PHY_TX_SYMBOL_0_CLK,31 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,32};33 34enum {35 P_BI_TCXO,36 P_GCC_GPLL0_OUT_EVEN,37 P_GCC_GPLL0_OUT_MAIN,38 P_GCC_GPLL0_OUT_ODD,39 P_GCC_GPLL1_OUT_MAIN,40 P_GCC_GPLL3_OUT_MAIN,41 P_GCC_GPLL4_OUT_MAIN,42 P_GCC_GPLL9_OUT_MAIN,43 P_GCC_GPLL10_OUT_MAIN,44 P_SLEEP_CLK,45 P_UFS_PHY_RX_SYMBOL_0_CLK,46 P_UFS_PHY_RX_SYMBOL_1_CLK,47 P_UFS_PHY_TX_SYMBOL_0_CLK,48 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,49};50 51static const struct pll_vco lucid_evo_vco[] = {52 { 249600000, 2020000000, 0 },53};54 55static struct clk_alpha_pll gcc_gpll0 = {56 .offset = 0x0,57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],58 .clkr = {59 .enable_reg = 0x62018,60 .enable_mask = BIT(0),61 .hw.init = &(const struct clk_init_data) {62 .name = "gcc_gpll0",63 .parent_data = &(const struct clk_parent_data) {64 .index = DT_BI_TCXO,65 },66 .num_parents = 1,67 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,68 },69 },70};71 72static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {73 { 0x1, 2 },74 { }75};76 77static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {78 .offset = 0x0,79 .post_div_shift = 10,80 .post_div_table = post_div_table_gcc_gpll0_out_even,81 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),82 .width = 4,83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],84 .clkr.hw.init = &(const struct clk_init_data) {85 .name = "gcc_gpll0_out_even",86 .parent_hws = (const struct clk_hw*[]) {87 &gcc_gpll0.clkr.hw,88 },89 .num_parents = 1,90 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,91 },92};93 94static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {95 { 0x2, 3 },96 { }97};98 99static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {100 .offset = 0x0,101 .post_div_shift = 14,102 .post_div_table = post_div_table_gcc_gpll0_out_odd,103 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),104 .width = 4,105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],106 .clkr.hw.init = &(const struct clk_init_data) {107 .name = "gcc_gpll0_out_odd",108 .parent_hws = (const struct clk_hw*[]) {109 &gcc_gpll0.clkr.hw,110 },111 .num_parents = 1,112 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,113 },114};115 116static struct clk_alpha_pll gcc_gpll1 = {117 .offset = 0x1000,118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],119 .clkr = {120 .enable_reg = 0x62018,121 .enable_mask = BIT(1),122 .hw.init = &(const struct clk_init_data) {123 .name = "gcc_gpll1",124 .parent_data = &(const struct clk_parent_data) {125 .index = DT_BI_TCXO,126 },127 .num_parents = 1,128 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,129 },130 },131};132 133static const struct alpha_pll_config gcc_gpll3_config = {134 .l = 0x14,135 .alpha = 0xd555,136 .config_ctl_val = 0x20485699,137 .config_ctl_hi_val = 0x00182261,138 .config_ctl_hi1_val = 0x32aa299c,139 .user_ctl_val = 0x00000000,140 .user_ctl_hi_val = 0x00000805,141};142 143static struct clk_alpha_pll gcc_gpll3 = {144 .offset = 0x3000,145 .vco_table = lucid_evo_vco,146 .num_vco = ARRAY_SIZE(lucid_evo_vco),147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],148 .clkr = {149 .enable_reg = 0x62018,150 .enable_mask = BIT(3),151 .hw.init = &(const struct clk_init_data) {152 .name = "gcc_gpll3",153 .parent_data = &(const struct clk_parent_data) {154 .index = DT_BI_TCXO,155 },156 .num_parents = 1,157 .ops = &clk_alpha_pll_lucid_evo_ops,158 },159 },160};161 162static struct clk_alpha_pll gcc_gpll4 = {163 .offset = 0x4000,164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],165 .clkr = {166 .enable_reg = 0x62018,167 .enable_mask = BIT(4),168 .hw.init = &(const struct clk_init_data) {169 .name = "gcc_gpll4",170 .parent_data = &(const struct clk_parent_data) {171 .index = DT_BI_TCXO,172 },173 .num_parents = 1,174 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,175 },176 },177};178 179static struct clk_alpha_pll gcc_gpll9 = {180 .offset = 0x9000,181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],182 .clkr = {183 .enable_reg = 0x62018,184 .enable_mask = BIT(9),185 .hw.init = &(const struct clk_init_data) {186 .name = "gcc_gpll9",187 .parent_data = &(const struct clk_parent_data) {188 .index = DT_BI_TCXO,189 },190 .num_parents = 1,191 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,192 },193 },194};195 196static struct clk_alpha_pll gcc_gpll10 = {197 .offset = 0xa000,198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],199 .clkr = {200 .enable_reg = 0x62018,201 .enable_mask = BIT(10),202 .hw.init = &(const struct clk_init_data) {203 .name = "gcc_gpll10",204 .parent_data = &(const struct clk_parent_data) {205 .index = DT_BI_TCXO,206 },207 .num_parents = 1,208 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,209 },210 },211};212 213static const struct parent_map gcc_parent_map_0[] = {214 { P_BI_TCXO, 0 },215 { P_GCC_GPLL0_OUT_MAIN, 1 },216 { P_GCC_GPLL0_OUT_EVEN, 6 },217};218 219static const struct clk_parent_data gcc_parent_data_0[] = {220 { .index = DT_BI_TCXO },221 { .hw = &gcc_gpll0.clkr.hw },222 { .hw = &gcc_gpll0_out_even.clkr.hw },223};224 225static const struct parent_map gcc_parent_map_1[] = {226 { P_BI_TCXO, 0 },227 { P_GCC_GPLL0_OUT_MAIN, 1 },228 { P_SLEEP_CLK, 5 },229 { P_GCC_GPLL0_OUT_EVEN, 6 },230};231 232static const struct clk_parent_data gcc_parent_data_1[] = {233 { .index = DT_BI_TCXO },234 { .hw = &gcc_gpll0.clkr.hw },235 { .index = DT_SLEEP_CLK },236 { .hw = &gcc_gpll0_out_even.clkr.hw },237};238 239static const struct parent_map gcc_parent_map_2[] = {240 { P_BI_TCXO, 0 },241 { P_GCC_GPLL0_OUT_MAIN, 1 },242 { P_GCC_GPLL1_OUT_MAIN, 4 },243 { P_GCC_GPLL4_OUT_MAIN, 5 },244 { P_GCC_GPLL0_OUT_EVEN, 6 },245};246 247static const struct clk_parent_data gcc_parent_data_2[] = {248 { .index = DT_BI_TCXO },249 { .hw = &gcc_gpll0.clkr.hw },250 { .hw = &gcc_gpll1.clkr.hw },251 { .hw = &gcc_gpll4.clkr.hw },252 { .hw = &gcc_gpll0_out_even.clkr.hw },253};254 255static const struct parent_map gcc_parent_map_3[] = {256 { P_BI_TCXO, 0 },257 { P_SLEEP_CLK, 5 },258};259 260static const struct clk_parent_data gcc_parent_data_3[] = {261 { .index = DT_BI_TCXO },262 { .index = DT_SLEEP_CLK },263};264 265static const struct parent_map gcc_parent_map_4[] = {266 { P_BI_TCXO, 0 },267 { P_GCC_GPLL0_OUT_MAIN, 1 },268 { P_GCC_GPLL0_OUT_ODD, 2 },269 { P_GCC_GPLL10_OUT_MAIN, 3 },270 { P_GCC_GPLL0_OUT_EVEN, 6 },271};272 273static const struct clk_parent_data gcc_parent_data_4[] = {274 { .index = DT_BI_TCXO },275 { .hw = &gcc_gpll0.clkr.hw },276 { .hw = &gcc_gpll0_out_odd.clkr.hw },277 { .hw = &gcc_gpll10.clkr.hw },278 { .hw = &gcc_gpll0_out_even.clkr.hw },279};280 281static const struct parent_map gcc_parent_map_5[] = {282 { P_BI_TCXO, 0 },283};284 285static const struct clk_parent_data gcc_parent_data_5[] = {286 { .index = DT_BI_TCXO },287};288 289static const struct parent_map gcc_parent_map_6[] = {290 { P_BI_TCXO, 0 },291 { P_GCC_GPLL0_OUT_MAIN, 1 },292 { P_GCC_GPLL9_OUT_MAIN, 2 },293 { P_GCC_GPLL4_OUT_MAIN, 5 },294 { P_GCC_GPLL0_OUT_EVEN, 6 },295};296 297static const struct clk_parent_data gcc_parent_data_6[] = {298 { .index = DT_BI_TCXO },299 { .hw = &gcc_gpll0.clkr.hw },300 { .hw = &gcc_gpll9.clkr.hw },301 { .hw = &gcc_gpll4.clkr.hw },302 { .hw = &gcc_gpll0_out_even.clkr.hw },303};304 305static const struct parent_map gcc_parent_map_7[] = {306 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },307 { P_BI_TCXO, 2 },308};309 310static const struct clk_parent_data gcc_parent_data_7[] = {311 { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },312 { .index = DT_BI_TCXO },313};314 315static const struct parent_map gcc_parent_map_8[] = {316 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },317 { P_BI_TCXO, 2 },318};319 320static const struct clk_parent_data gcc_parent_data_8[] = {321 { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },322 { .index = DT_BI_TCXO },323};324 325static const struct parent_map gcc_parent_map_9[] = {326 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },327 { P_BI_TCXO, 2 },328};329 330static const struct clk_parent_data gcc_parent_data_9[] = {331 { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },332 { .index = DT_BI_TCXO },333};334 335static const struct parent_map gcc_parent_map_10[] = {336 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },337 { P_BI_TCXO, 2 },338};339 340static const struct clk_parent_data gcc_parent_data_10[] = {341 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },342 { .index = DT_BI_TCXO },343};344 345static const struct parent_map gcc_parent_map_11[] = {346 { P_BI_TCXO, 0 },347 { P_GCC_GPLL0_OUT_MAIN, 1 },348 { P_GCC_GPLL3_OUT_MAIN, 5 },349};350 351static const struct clk_parent_data gcc_parent_data_11[] = {352 { .index = DT_BI_TCXO },353 { .hw = &gcc_gpll0.clkr.hw },354 { .hw = &gcc_gpll3.clkr.hw },355};356 357static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {358 .reg = 0x7b060,359 .clkr = {360 .hw.init = &(const struct clk_init_data) {361 .name = "gcc_pcie_0_pipe_clk_src",362 .parent_data = &(const struct clk_parent_data) {363 .index = DT_PCIE_0_PIPE_CLK,364 },365 .num_parents = 1,366 .ops = &clk_regmap_phy_mux_ops,367 },368 },369};370 371static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {372 .reg = 0x87060,373 .shift = 0,374 .width = 2,375 .parent_map = gcc_parent_map_7,376 .clkr = {377 .hw.init = &(const struct clk_init_data) {378 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",379 .parent_data = gcc_parent_data_7,380 .num_parents = ARRAY_SIZE(gcc_parent_data_7),381 .ops = &clk_regmap_mux_closest_ops,382 },383 },384};385 386static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {387 .reg = 0x870d0,388 .shift = 0,389 .width = 2,390 .parent_map = gcc_parent_map_8,391 .clkr = {392 .hw.init = &(const struct clk_init_data) {393 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",394 .parent_data = gcc_parent_data_8,395 .num_parents = ARRAY_SIZE(gcc_parent_data_8),396 .ops = &clk_regmap_mux_closest_ops,397 },398 },399};400 401static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {402 .reg = 0x87050,403 .shift = 0,404 .width = 2,405 .parent_map = gcc_parent_map_9,406 .clkr = {407 .hw.init = &(const struct clk_init_data) {408 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",409 .parent_data = gcc_parent_data_9,410 .num_parents = ARRAY_SIZE(gcc_parent_data_9),411 .ops = &clk_regmap_mux_closest_ops,412 },413 },414};415 416static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {417 .reg = 0x49068,418 .shift = 0,419 .width = 2,420 .parent_map = gcc_parent_map_10,421 .clkr = {422 .hw.init = &(const struct clk_init_data) {423 .name = "gcc_usb3_prim_phy_pipe_clk_src",424 .parent_data = gcc_parent_data_10,425 .num_parents = ARRAY_SIZE(gcc_parent_data_10),426 .ops = &clk_regmap_mux_closest_ops,427 },428 },429};430 431static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {432 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),433 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),434 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),435 { }436};437 438static struct clk_rcg2 gcc_gp1_clk_src = {439 .cmd_rcgr = 0x74004,440 .mnd_width = 16,441 .hid_width = 5,442 .parent_map = gcc_parent_map_1,443 .freq_tbl = ftbl_gcc_gp1_clk_src,444 .clkr.hw.init = &(const struct clk_init_data) {445 .name = "gcc_gp1_clk_src",446 .parent_data = gcc_parent_data_1,447 .num_parents = ARRAY_SIZE(gcc_parent_data_1),448 .flags = CLK_SET_RATE_PARENT,449 .ops = &clk_rcg2_shared_ops,450 },451};452 453static struct clk_rcg2 gcc_gp2_clk_src = {454 .cmd_rcgr = 0x75004,455 .mnd_width = 16,456 .hid_width = 5,457 .parent_map = gcc_parent_map_1,458 .freq_tbl = ftbl_gcc_gp1_clk_src,459 .clkr.hw.init = &(const struct clk_init_data) {460 .name = "gcc_gp2_clk_src",461 .parent_data = gcc_parent_data_1,462 .num_parents = ARRAY_SIZE(gcc_parent_data_1),463 .flags = CLK_SET_RATE_PARENT,464 .ops = &clk_rcg2_shared_ops,465 },466};467 468static struct clk_rcg2 gcc_gp3_clk_src = {469 .cmd_rcgr = 0x76004,470 .mnd_width = 16,471 .hid_width = 5,472 .parent_map = gcc_parent_map_1,473 .freq_tbl = ftbl_gcc_gp1_clk_src,474 .clkr.hw.init = &(const struct clk_init_data) {475 .name = "gcc_gp3_clk_src",476 .parent_data = gcc_parent_data_1,477 .num_parents = ARRAY_SIZE(gcc_parent_data_1),478 .flags = CLK_SET_RATE_PARENT,479 .ops = &clk_rcg2_shared_ops,480 },481};482 483static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {484 F(9600000, P_BI_TCXO, 2, 0, 0),485 F(19200000, P_BI_TCXO, 1, 0, 0),486 { }487};488 489static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {490 .cmd_rcgr = 0x7b064,491 .mnd_width = 16,492 .hid_width = 5,493 .parent_map = gcc_parent_map_3,494 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,495 .clkr.hw.init = &(const struct clk_init_data) {496 .name = "gcc_pcie_0_aux_clk_src",497 .parent_data = gcc_parent_data_3,498 .num_parents = ARRAY_SIZE(gcc_parent_data_3),499 .flags = CLK_SET_RATE_PARENT,500 .ops = &clk_rcg2_shared_ops,501 },502};503 504static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {505 F(19200000, P_BI_TCXO, 1, 0, 0),506 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),507 { }508};509 510static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {511 .cmd_rcgr = 0x7b048,512 .mnd_width = 0,513 .hid_width = 5,514 .parent_map = gcc_parent_map_0,515 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,516 .clkr.hw.init = &(const struct clk_init_data) {517 .name = "gcc_pcie_0_phy_rchng_clk_src",518 .parent_data = gcc_parent_data_0,519 .num_parents = ARRAY_SIZE(gcc_parent_data_0),520 .flags = CLK_SET_RATE_PARENT,521 .ops = &clk_rcg2_shared_ops,522 },523};524 525static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {526 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),527 { }528};529 530static struct clk_rcg2 gcc_pdm2_clk_src = {531 .cmd_rcgr = 0x43010,532 .mnd_width = 0,533 .hid_width = 5,534 .parent_map = gcc_parent_map_0,535 .freq_tbl = ftbl_gcc_pdm2_clk_src,536 .clkr.hw.init = &(const struct clk_init_data) {537 .name = "gcc_pdm2_clk_src",538 .parent_data = gcc_parent_data_0,539 .num_parents = ARRAY_SIZE(gcc_parent_data_0),540 .flags = CLK_SET_RATE_PARENT,541 .ops = &clk_rcg2_shared_ops,542 },543};544 545static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {546 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),547 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),548 F(19200000, P_BI_TCXO, 1, 0, 0),549 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),550 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),551 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),552 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),553 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),554 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),555 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),556 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),557 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),558 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),559 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),560 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),561 { }562};563 564static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {565 .name = "gcc_qupv3_wrap0_s0_clk_src",566 .parent_data = gcc_parent_data_0,567 .num_parents = ARRAY_SIZE(gcc_parent_data_0),568 .flags = CLK_SET_RATE_PARENT,569 .ops = &clk_rcg2_shared_ops,570};571 572static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {573 .cmd_rcgr = 0x27014,574 .mnd_width = 16,575 .hid_width = 5,576 .parent_map = gcc_parent_map_0,577 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,578 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,579};580 581static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s1_clk_src[] = {582 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),583 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),584 F(19200000, P_BI_TCXO, 1, 0, 0),585 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),586 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),587 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),588 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),589 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),590 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),591 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),592 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),593 { }594};595 596static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {597 .name = "gcc_qupv3_wrap0_s1_clk_src",598 .parent_data = gcc_parent_data_0,599 .num_parents = ARRAY_SIZE(gcc_parent_data_0),600 .flags = CLK_SET_RATE_PARENT,601 .ops = &clk_rcg2_shared_ops,602};603 604static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {605 .cmd_rcgr = 0x27148,606 .mnd_width = 16,607 .hid_width = 5,608 .parent_map = gcc_parent_map_0,609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,610 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,611};612 613static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {614 .name = "gcc_qupv3_wrap0_s2_clk_src",615 .parent_data = gcc_parent_data_0,616 .num_parents = ARRAY_SIZE(gcc_parent_data_0),617 .flags = CLK_SET_RATE_PARENT,618 .ops = &clk_rcg2_shared_ops,619};620 621static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {622 .cmd_rcgr = 0x2727c,623 .mnd_width = 16,624 .hid_width = 5,625 .parent_map = gcc_parent_map_0,626 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,627 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,628};629 630static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {631 .name = "gcc_qupv3_wrap0_s3_clk_src",632 .parent_data = gcc_parent_data_0,633 .num_parents = ARRAY_SIZE(gcc_parent_data_0),634 .flags = CLK_SET_RATE_PARENT,635 .ops = &clk_rcg2_shared_ops,636};637 638static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {639 .cmd_rcgr = 0x273b0,640 .mnd_width = 16,641 .hid_width = 5,642 .parent_map = gcc_parent_map_0,643 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,644 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,645};646 647static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {648 .name = "gcc_qupv3_wrap0_s4_clk_src",649 .parent_data = gcc_parent_data_0,650 .num_parents = ARRAY_SIZE(gcc_parent_data_0),651 .flags = CLK_SET_RATE_PARENT,652 .ops = &clk_rcg2_shared_ops,653};654 655static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {656 .cmd_rcgr = 0x274e4,657 .mnd_width = 16,658 .hid_width = 5,659 .parent_map = gcc_parent_map_0,660 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,661 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,662};663 664static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {665 .name = "gcc_qupv3_wrap1_s0_clk_src",666 .parent_data = gcc_parent_data_0,667 .num_parents = ARRAY_SIZE(gcc_parent_data_0),668 .flags = CLK_SET_RATE_PARENT,669 .ops = &clk_rcg2_shared_ops,670};671 672static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {673 .cmd_rcgr = 0x28014,674 .mnd_width = 16,675 .hid_width = 5,676 .parent_map = gcc_parent_map_0,677 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,678 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,679};680 681static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {682 .name = "gcc_qupv3_wrap1_s1_clk_src",683 .parent_data = gcc_parent_data_0,684 .num_parents = ARRAY_SIZE(gcc_parent_data_0),685 .flags = CLK_SET_RATE_PARENT,686 .ops = &clk_rcg2_shared_ops,687};688 689static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {690 .cmd_rcgr = 0x28148,691 .mnd_width = 16,692 .hid_width = 5,693 .parent_map = gcc_parent_map_0,694 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,695 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,696};697 698static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {699 .name = "gcc_qupv3_wrap1_s2_clk_src",700 .parent_data = gcc_parent_data_0,701 .num_parents = ARRAY_SIZE(gcc_parent_data_0),702 .flags = CLK_SET_RATE_PARENT,703 .ops = &clk_rcg2_shared_ops,704};705 706static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {707 .cmd_rcgr = 0x2827c,708 .mnd_width = 16,709 .hid_width = 5,710 .parent_map = gcc_parent_map_0,711 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,712 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,713};714 715static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {716 .name = "gcc_qupv3_wrap1_s3_clk_src",717 .parent_data = gcc_parent_data_0,718 .num_parents = ARRAY_SIZE(gcc_parent_data_0),719 .flags = CLK_SET_RATE_PARENT,720 .ops = &clk_rcg2_shared_ops,721};722 723static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {724 .cmd_rcgr = 0x283b0,725 .mnd_width = 16,726 .hid_width = 5,727 .parent_map = gcc_parent_map_0,728 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,729 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,730};731 732static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {733 .name = "gcc_qupv3_wrap1_s4_clk_src",734 .parent_data = gcc_parent_data_0,735 .num_parents = ARRAY_SIZE(gcc_parent_data_0),736 .flags = CLK_SET_RATE_PARENT,737 .ops = &clk_rcg2_shared_ops,738};739 740static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {741 .cmd_rcgr = 0x284e4,742 .mnd_width = 16,743 .hid_width = 5,744 .parent_map = gcc_parent_map_0,745 .freq_tbl = ftbl_gcc_qupv3_wrap0_s1_clk_src,746 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,747};748 749static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {750 F(144000, P_BI_TCXO, 16, 3, 25),751 F(400000, P_BI_TCXO, 12, 1, 4),752 F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),753 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),754 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),755 F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),756 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),757 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),758 { }759};760 761static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {762 .cmd_rcgr = 0xb3010,763 .mnd_width = 8,764 .hid_width = 5,765 .parent_map = gcc_parent_map_4,766 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,767 .clkr.hw.init = &(const struct clk_init_data) {768 .name = "gcc_sdcc1_apps_clk_src",769 .parent_data = gcc_parent_data_4,770 .num_parents = ARRAY_SIZE(gcc_parent_data_4),771 .flags = CLK_SET_RATE_PARENT,772 .ops = &clk_rcg2_floor_ops,773 },774};775 776static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {777 F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),778 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),779 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),780 { }781};782 783static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {784 .cmd_rcgr = 0xb3030,785 .mnd_width = 0,786 .hid_width = 5,787 .parent_map = gcc_parent_map_4,788 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,789 .clkr.hw.init = &(const struct clk_init_data) {790 .name = "gcc_sdcc1_ice_core_clk_src",791 .parent_data = gcc_parent_data_4,792 .num_parents = ARRAY_SIZE(gcc_parent_data_4),793 .flags = CLK_SET_RATE_PARENT,794 .ops = &clk_rcg2_floor_ops,795 },796};797 798static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {799 F(400000, P_BI_TCXO, 12, 1, 4),800 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),801 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),802 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),803 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),804 { }805};806 807static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {808 .cmd_rcgr = 0x24014,809 .mnd_width = 8,810 .hid_width = 5,811 .parent_map = gcc_parent_map_6,812 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,813 .clkr.hw.init = &(const struct clk_init_data) {814 .name = "gcc_sdcc2_apps_clk_src",815 .parent_data = gcc_parent_data_6,816 .num_parents = ARRAY_SIZE(gcc_parent_data_6),817 .flags = CLK_SET_RATE_PARENT,818 .ops = &clk_rcg2_floor_ops,819 },820};821 822static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {823 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),824 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),825 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),826 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),827 { }828};829 830static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {831 .cmd_rcgr = 0x8702c,832 .mnd_width = 8,833 .hid_width = 5,834 .parent_map = gcc_parent_map_0,835 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,836 .clkr.hw.init = &(const struct clk_init_data) {837 .name = "gcc_ufs_phy_axi_clk_src",838 .parent_data = gcc_parent_data_0,839 .num_parents = ARRAY_SIZE(gcc_parent_data_0),840 .flags = CLK_SET_RATE_PARENT,841 .ops = &clk_rcg2_shared_ops,842 },843};844 845static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {846 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),847 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),848 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),849 { }850};851 852static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {853 .cmd_rcgr = 0x87074,854 .mnd_width = 0,855 .hid_width = 5,856 .parent_map = gcc_parent_map_2,857 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,858 .clkr.hw.init = &(const struct clk_init_data) {859 .name = "gcc_ufs_phy_ice_core_clk_src",860 .parent_data = gcc_parent_data_2,861 .num_parents = ARRAY_SIZE(gcc_parent_data_2),862 .flags = CLK_SET_RATE_PARENT,863 .ops = &clk_rcg2_shared_ops,864 },865};866 867static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {868 .cmd_rcgr = 0x870a8,869 .mnd_width = 0,870 .hid_width = 5,871 .parent_map = gcc_parent_map_5,872 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,873 .clkr.hw.init = &(const struct clk_init_data) {874 .name = "gcc_ufs_phy_phy_aux_clk_src",875 .parent_data = gcc_parent_data_5,876 .num_parents = ARRAY_SIZE(gcc_parent_data_5),877 .flags = CLK_SET_RATE_PARENT,878 .ops = &clk_rcg2_shared_ops,879 },880};881 882static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {883 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),884 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),885 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),886 { }887};888 889static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {890 .cmd_rcgr = 0x8708c,891 .mnd_width = 0,892 .hid_width = 5,893 .parent_map = gcc_parent_map_0,894 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,895 .clkr.hw.init = &(const struct clk_init_data) {896 .name = "gcc_ufs_phy_unipro_core_clk_src",897 .parent_data = gcc_parent_data_0,898 .num_parents = ARRAY_SIZE(gcc_parent_data_0),899 .flags = CLK_SET_RATE_PARENT,900 .ops = &clk_rcg2_shared_ops,901 },902};903 904static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {905 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),906 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),907 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),908 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),909 { }910};911 912static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {913 .cmd_rcgr = 0x49028,914 .mnd_width = 8,915 .hid_width = 5,916 .parent_map = gcc_parent_map_0,917 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,918 .clkr.hw.init = &(const struct clk_init_data) {919 .name = "gcc_usb30_prim_master_clk_src",920 .parent_data = gcc_parent_data_0,921 .num_parents = ARRAY_SIZE(gcc_parent_data_0),922 .flags = CLK_SET_RATE_PARENT,923 .ops = &clk_rcg2_shared_ops,924 },925};926 927static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {928 F(19200000, P_BI_TCXO, 1, 0, 0),929 { }930};931 932static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {933 .cmd_rcgr = 0x49040,934 .mnd_width = 0,935 .hid_width = 5,936 .parent_map = gcc_parent_map_0,937 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,938 .clkr.hw.init = &(const struct clk_init_data) {939 .name = "gcc_usb30_prim_mock_utmi_clk_src",940 .parent_data = gcc_parent_data_0,941 .num_parents = ARRAY_SIZE(gcc_parent_data_0),942 .flags = CLK_SET_RATE_PARENT,943 .ops = &clk_rcg2_shared_ops,944 },945};946 947static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {948 .cmd_rcgr = 0x4906c,949 .mnd_width = 0,950 .hid_width = 5,951 .parent_map = gcc_parent_map_3,952 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,953 .clkr.hw.init = &(const struct clk_init_data) {954 .name = "gcc_usb3_prim_phy_aux_clk_src",955 .parent_data = gcc_parent_data_3,956 .num_parents = ARRAY_SIZE(gcc_parent_data_3),957 .flags = CLK_SET_RATE_PARENT,958 .ops = &clk_rcg2_shared_ops,959 },960};961 962static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {963 F(133333333, P_GCC_GPLL3_OUT_MAIN, 3, 0, 0),964 F(240000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),965 F(365000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),966 F(384000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),967 { }968};969 970static struct clk_rcg2 gcc_video_venus_clk_src = {971 .cmd_rcgr = 0xb6004,972 .mnd_width = 0,973 .hid_width = 5,974 .parent_map = gcc_parent_map_11,975 .freq_tbl = ftbl_gcc_video_venus_clk_src,976 .clkr.hw.init = &(const struct clk_init_data) {977 .name = "gcc_video_venus_clk_src",978 .parent_data = gcc_parent_data_11,979 .num_parents = ARRAY_SIZE(gcc_parent_data_11),980 .flags = CLK_SET_RATE_PARENT,981 .ops = &clk_rcg2_shared_ops,982 },983};984 985static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = {986 .reg = 0x7b084,987 .shift = 0,988 .width = 4,989 .clkr.hw.init = &(const struct clk_init_data) {990 .name = "gcc_pcie_0_pipe_div2_clk_src",991 .parent_hws = (const struct clk_hw*[]) {992 &gcc_pcie_0_pipe_clk_src.clkr.hw,993 },994 .num_parents = 1,995 .flags = CLK_SET_RATE_PARENT,996 .ops = &clk_regmap_div_ro_ops,997 },998};999 1000static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {1001 .reg = 0x49058,1002 .shift = 0,1003 .width = 4,1004 .clkr.hw.init = &(const struct clk_init_data) {1005 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",1006 .parent_hws = (const struct clk_hw*[]) {1007 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,1008 },1009 .num_parents = 1,1010 .flags = CLK_SET_RATE_PARENT,1011 .ops = &clk_regmap_div_ro_ops,1012 },1013};1014 1015static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {1016 .halt_reg = 0x7b08c,1017 .halt_check = BRANCH_HALT_SKIP,1018 .hwcg_reg = 0x7b08c,1019 .hwcg_bit = 1,1020 .clkr = {1021 .enable_reg = 0x62000,1022 .enable_mask = BIT(12),1023 .hw.init = &(const struct clk_init_data) {1024 .name = "gcc_aggre_noc_pcie_0_axi_clk",1025 .ops = &clk_branch2_ops,1026 },1027 },1028};1029 1030static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {1031 .halt_reg = 0x870d4,1032 .halt_check = BRANCH_HALT_VOTED,1033 .hwcg_reg = 0x870d4,1034 .hwcg_bit = 1,1035 .clkr = {1036 .enable_reg = 0x870d4,1037 .enable_mask = BIT(0),1038 .hw.init = &(const struct clk_init_data) {1039 .name = "gcc_aggre_ufs_phy_axi_clk",1040 .parent_hws = (const struct clk_hw*[]) {1041 &gcc_ufs_phy_axi_clk_src.clkr.hw,1042 },1043 .num_parents = 1,1044 .flags = CLK_SET_RATE_PARENT,1045 .ops = &clk_branch2_ops,1046 },1047 },1048};1049 1050static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {1051 .halt_reg = 0x870d4,1052 .halt_check = BRANCH_HALT_VOTED,1053 .hwcg_reg = 0x870d4,1054 .hwcg_bit = 1,1055 .clkr = {1056 .enable_reg = 0x870d4,1057 .enable_mask = BIT(1),1058 .hw.init = &(const struct clk_init_data) {1059 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",1060 .parent_hws = (const struct clk_hw*[]) {1061 &gcc_ufs_phy_axi_clk_src.clkr.hw,1062 },1063 .num_parents = 1,1064 .flags = CLK_SET_RATE_PARENT,1065 .ops = &clk_branch2_ops,1066 },1067 },1068};1069 1070static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {1071 .halt_reg = 0x49088,1072 .halt_check = BRANCH_HALT_VOTED,1073 .hwcg_reg = 0x49088,1074 .hwcg_bit = 1,1075 .clkr = {1076 .enable_reg = 0x49088,1077 .enable_mask = BIT(0),1078 .hw.init = &(const struct clk_init_data) {1079 .name = "gcc_aggre_usb3_prim_axi_clk",1080 .parent_hws = (const struct clk_hw*[]) {1081 &gcc_usb30_prim_master_clk_src.clkr.hw,1082 },1083 .num_parents = 1,1084 .flags = CLK_SET_RATE_PARENT,1085 .ops = &clk_branch2_ops,1086 },1087 },1088};1089 1090static struct clk_branch gcc_boot_rom_ahb_clk = {1091 .halt_reg = 0x48004,1092 .halt_check = BRANCH_HALT_VOTED,1093 .hwcg_reg = 0x48004,1094 .hwcg_bit = 1,1095 .clkr = {1096 .enable_reg = 0x62000,1097 .enable_mask = BIT(10),1098 .hw.init = &(const struct clk_init_data) {1099 .name = "gcc_boot_rom_ahb_clk",1100 .ops = &clk_branch2_ops,1101 },1102 },1103};1104 1105static struct clk_branch gcc_camera_hf_axi_clk = {1106 .halt_reg = 0x36010,1107 .halt_check = BRANCH_HALT_SKIP,1108 .hwcg_reg = 0x36010,1109 .hwcg_bit = 1,1110 .clkr = {1111 .enable_reg = 0x36010,1112 .enable_mask = BIT(0),1113 .hw.init = &(const struct clk_init_data) {1114 .name = "gcc_camera_hf_axi_clk",1115 .ops = &clk_branch2_ops,1116 },1117 },1118};1119 1120static struct clk_branch gcc_camera_sf_axi_clk = {1121 .halt_reg = 0x36014,1122 .halt_check = BRANCH_HALT_SKIP,1123 .hwcg_reg = 0x36014,1124 .hwcg_bit = 1,1125 .clkr = {1126 .enable_reg = 0x36014,1127 .enable_mask = BIT(0),1128 .hw.init = &(const struct clk_init_data) {1129 .name = "gcc_camera_sf_axi_clk",1130 .ops = &clk_branch2_ops,1131 },1132 },1133};1134 1135static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {1136 .halt_reg = 0x20030,1137 .halt_check = BRANCH_HALT_VOTED,1138 .hwcg_reg = 0x20030,1139 .hwcg_bit = 1,1140 .clkr = {1141 .enable_reg = 0x62000,1142 .enable_mask = BIT(20),1143 .hw.init = &(const struct clk_init_data) {1144 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",1145 .ops = &clk_branch2_ops,1146 },1147 },1148};1149 1150static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {1151 .halt_reg = 0x49084,1152 .halt_check = BRANCH_HALT_VOTED,1153 .hwcg_reg = 0x49084,1154 .hwcg_bit = 1,1155 .clkr = {1156 .enable_reg = 0x49084,1157 .enable_mask = BIT(0),1158 .hw.init = &(const struct clk_init_data) {1159 .name = "gcc_cfg_noc_usb3_prim_axi_clk",1160 .parent_hws = (const struct clk_hw*[]) {1161 &gcc_usb30_prim_master_clk_src.clkr.hw,1162 },1163 .num_parents = 1,1164 .flags = CLK_SET_RATE_PARENT,1165 .ops = &clk_branch2_ops,1166 },1167 },1168};1169 1170static struct clk_branch gcc_ddrss_gpu_axi_clk = {1171 .halt_reg = 0x81154,1172 .halt_check = BRANCH_HALT_SKIP,1173 .hwcg_reg = 0x81154,1174 .hwcg_bit = 1,1175 .clkr = {1176 .enable_reg = 0x81154,1177 .enable_mask = BIT(0),1178 .hw.init = &(const struct clk_init_data) {1179 .name = "gcc_ddrss_gpu_axi_clk",1180 .ops = &clk_branch2_aon_ops,1181 },1182 },1183};1184 1185static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {1186 .halt_reg = 0x7b090,1187 .halt_check = BRANCH_HALT_SKIP,1188 .hwcg_reg = 0x7b090,1189 .hwcg_bit = 1,1190 .clkr = {1191 .enable_reg = 0x62000,1192 .enable_mask = BIT(19),1193 .hw.init = &(const struct clk_init_data) {1194 .name = "gcc_ddrss_pcie_sf_tbu_clk",1195 .ops = &clk_branch2_ops,1196 },1197 },1198};1199 1200static struct clk_branch gcc_disp_hf_axi_clk = {1201 .halt_reg = 0x3700c,1202 .halt_check = BRANCH_HALT_SKIP,1203 .hwcg_reg = 0x3700c,1204 .hwcg_bit = 1,1205 .clkr = {1206 .enable_reg = 0x3700c,1207 .enable_mask = BIT(0),1208 .hw.init = &(const struct clk_init_data) {1209 .name = "gcc_disp_hf_axi_clk",1210 .ops = &clk_branch2_ops,1211 },1212 },1213};1214 1215static struct clk_branch gcc_eusb3_0_clkref_en = {1216 .halt_reg = 0x9c00c,1217 .halt_check = BRANCH_HALT_DELAY,1218 .clkr = {1219 .enable_reg = 0x9c00c,1220 .enable_mask = BIT(0),1221 .hw.init = &(const struct clk_init_data) {1222 .name = "gcc_eusb3_0_clkref_en",1223 .ops = &clk_branch2_ops,1224 },1225 },1226};1227 1228static struct clk_branch gcc_gp1_clk = {1229 .halt_reg = 0x74000,1230 .halt_check = BRANCH_HALT,1231 .clkr = {1232 .enable_reg = 0x74000,1233 .enable_mask = BIT(0),1234 .hw.init = &(const struct clk_init_data) {1235 .name = "gcc_gp1_clk",1236 .parent_hws = (const struct clk_hw*[]) {1237 &gcc_gp1_clk_src.clkr.hw,1238 },1239 .num_parents = 1,1240 .flags = CLK_SET_RATE_PARENT,1241 .ops = &clk_branch2_ops,1242 },1243 },1244};1245 1246static struct clk_branch gcc_gp2_clk = {1247 .halt_reg = 0x75000,1248 .halt_check = BRANCH_HALT,1249 .clkr = {1250 .enable_reg = 0x75000,1251 .enable_mask = BIT(0),1252 .hw.init = &(const struct clk_init_data) {1253 .name = "gcc_gp2_clk",1254 .parent_hws = (const struct clk_hw*[]) {1255 &gcc_gp2_clk_src.clkr.hw,1256 },1257 .num_parents = 1,1258 .flags = CLK_SET_RATE_PARENT,1259 .ops = &clk_branch2_ops,1260 },1261 },1262};1263 1264static struct clk_branch gcc_gp3_clk = {1265 .halt_reg = 0x76000,1266 .halt_check = BRANCH_HALT,1267 .clkr = {1268 .enable_reg = 0x76000,1269 .enable_mask = BIT(0),1270 .hw.init = &(const struct clk_init_data) {1271 .name = "gcc_gp3_clk",1272 .parent_hws = (const struct clk_hw*[]) {1273 &gcc_gp3_clk_src.clkr.hw,1274 },1275 .num_parents = 1,1276 .flags = CLK_SET_RATE_PARENT,1277 .ops = &clk_branch2_ops,1278 },1279 },1280};1281 1282static struct clk_branch gcc_gpu_gpll0_clk_src = {1283 .halt_check = BRANCH_HALT_DELAY,1284 .clkr = {1285 .enable_reg = 0x62000,1286 .enable_mask = BIT(15),1287 .hw.init = &(const struct clk_init_data) {1288 .name = "gcc_gpu_gpll0_clk_src",1289 .parent_hws = (const struct clk_hw*[]) {1290 &gcc_gpll0.clkr.hw,1291 },1292 .num_parents = 1,1293 .flags = CLK_SET_RATE_PARENT,1294 .ops = &clk_branch2_ops,1295 },1296 },1297};1298 1299static struct clk_branch gcc_gpu_gpll0_div_clk_src = {1300 .halt_check = BRANCH_HALT_DELAY,1301 .clkr = {1302 .enable_reg = 0x62000,1303 .enable_mask = BIT(16),1304 .hw.init = &(const struct clk_init_data) {1305 .name = "gcc_gpu_gpll0_div_clk_src",1306 .parent_hws = (const struct clk_hw*[]) {1307 &gcc_gpll0_out_even.clkr.hw,1308 },1309 .num_parents = 1,1310 .flags = CLK_SET_RATE_PARENT,1311 .ops = &clk_branch2_ops,1312 },1313 },1314};1315 1316static struct clk_branch gcc_gpu_memnoc_gfx_clk = {1317 .halt_reg = 0x81010,1318 .halt_check = BRANCH_HALT_VOTED,1319 .hwcg_reg = 0x81010,1320 .hwcg_bit = 1,1321 .clkr = {1322 .enable_reg = 0x81010,1323 .enable_mask = BIT(0),1324 .hw.init = &(const struct clk_init_data) {1325 .name = "gcc_gpu_memnoc_gfx_clk",1326 .ops = &clk_branch2_ops,1327 },1328 },1329};1330 1331static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {1332 .halt_reg = 0x81018,1333 .halt_check = BRANCH_HALT_DELAY,1334 .clkr = {1335 .enable_reg = 0x81018,1336 .enable_mask = BIT(0),1337 .hw.init = &(const struct clk_init_data) {1338 .name = "gcc_gpu_snoc_dvm_gfx_clk",1339 .ops = &clk_branch2_ops,1340 },1341 },1342};1343 1344static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk = {1345 .halt_reg = 0x8d004,1346 .halt_check = BRANCH_HALT_VOTED,1347 .clkr = {1348 .enable_reg = 0x8d004,1349 .enable_mask = BIT(0),1350 .hw.init = &(const struct clk_init_data){1351 .name = "gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk",1352 .ops = &clk_branch2_ops,1353 },1354 },1355};1356 1357static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk = {1358 .halt_reg = 0x8d010,1359 .halt_check = BRANCH_HALT_VOTED,1360 .clkr = {1361 .enable_reg = 0x8d010,1362 .enable_mask = BIT(0),1363 .hw.init = &(const struct clk_init_data){1364 .name = "gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk",1365 .ops = &clk_branch2_ops,1366 },1367 },1368};1369 1370static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk = {1371 .halt_reg = 0x8d008,1372 .halt_check = BRANCH_HALT_VOTED,1373 .clkr = {1374 .enable_reg = 0x8d008,1375 .enable_mask = BIT(0),1376 .hw.init = &(const struct clk_init_data){1377 .name = "gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk",1378 .ops = &clk_branch2_ops,1379 },1380 },1381};1382 1383static struct clk_branch gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk = {1384 .halt_reg = 0x8d00c,1385 .halt_check = BRANCH_HALT_VOTED,1386 .clkr = {1387 .enable_reg = 0x8d00c,1388 .enable_mask = BIT(0),1389 .hw.init = &(const struct clk_init_data){1390 .name = "gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk",1391 .ops = &clk_branch2_ops,1392 },1393 },1394};1395 1396static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk = {1397 .halt_reg = 0x8d018,1398 .halt_check = BRANCH_HALT_VOTED,1399 .clkr = {1400 .enable_reg = 0x8d018,1401 .enable_mask = BIT(0),1402 .hw.init = &(const struct clk_init_data){1403 .name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk",1404 .ops = &clk_branch2_ops,1405 },1406 },1407};1408 1409static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk = {1410 .halt_reg = 0x8d01c,1411 .halt_check = BRANCH_HALT_VOTED,1412 .clkr = {1413 .enable_reg = 0x8d01c,1414 .enable_mask = BIT(0),1415 .hw.init = &(const struct clk_init_data){1416 .name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk",1417 .ops = &clk_branch2_ops,1418 },1419 },1420};1421 1422static struct clk_branch gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk = {1423 .halt_reg = 0x8d014,1424 .halt_check = BRANCH_HALT_VOTED,1425 .clkr = {1426 .enable_reg = 0x8d014,1427 .enable_mask = BIT(0),1428 .hw.init = &(const struct clk_init_data){1429 .name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk",1430 .ops = &clk_branch2_ops,1431 },1432 },1433};1434 1435static struct clk_branch gcc_hlos1_vote_mmu_tcu_clk = {1436 .halt_reg = 0x8d02c,1437 .halt_check = BRANCH_HALT_VOTED,1438 .clkr = {1439 .enable_reg = 0x8d02c,1440 .enable_mask = BIT(0),1441 .hw.init = &(const struct clk_init_data){1442 .name = "gcc_hlos1_vote_mmu_tcu_clk",1443 .ops = &clk_branch2_ops,1444 },1445 },1446};1447 1448static struct clk_branch gcc_pcie_0_aux_clk = {1449 .halt_reg = 0x7b034,1450 .halt_check = BRANCH_HALT_VOTED,1451 .clkr = {1452 .enable_reg = 0x62008,1453 .enable_mask = BIT(3),1454 .hw.init = &(const struct clk_init_data) {1455 .name = "gcc_pcie_0_aux_clk",1456 .parent_hws = (const struct clk_hw*[]) {1457 &gcc_pcie_0_aux_clk_src.clkr.hw,1458 },1459 .num_parents = 1,1460 .flags = CLK_SET_RATE_PARENT,1461 .ops = &clk_branch2_ops,1462 },1463 },1464};1465 1466static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {1467 .halt_reg = 0x7b030,1468 .halt_check = BRANCH_HALT_VOTED,1469 .hwcg_reg = 0x7b030,1470 .hwcg_bit = 1,1471 .clkr = {1472 .enable_reg = 0x62008,1473 .enable_mask = BIT(2),1474 .hw.init = &(const struct clk_init_data) {1475 .name = "gcc_pcie_0_cfg_ahb_clk",1476 .ops = &clk_branch2_ops,1477 },1478 },1479};1480 1481static struct clk_branch gcc_pcie_0_clkref_en = {1482 .halt_reg = 0x9c004,1483 .halt_check = BRANCH_HALT_DELAY,1484 .clkr = {1485 .enable_reg = 0x9c004,1486 .enable_mask = BIT(0),1487 .hw.init = &(const struct clk_init_data) {1488 .name = "gcc_pcie_0_clkref_en",1489 .ops = &clk_branch2_ops,1490 },1491 },1492};1493 1494static struct clk_branch gcc_pcie_0_mstr_axi_clk = {1495 .halt_reg = 0x7b028,1496 .halt_check = BRANCH_HALT_SKIP,1497 .clkr = {1498 .enable_reg = 0x62008,1499 .enable_mask = BIT(1),1500 .hw.init = &(const struct clk_init_data) {1501 .name = "gcc_pcie_0_mstr_axi_clk",1502 .ops = &clk_branch2_ops,1503 },1504 },1505};1506 1507static struct clk_branch gcc_pcie_0_phy_rchng_clk = {1508 .halt_reg = 0x7b044,1509 .halt_check = BRANCH_HALT_VOTED,1510 .clkr = {1511 .enable_reg = 0x62000,1512 .enable_mask = BIT(22),1513 .hw.init = &(const struct clk_init_data) {1514 .name = "gcc_pcie_0_phy_rchng_clk",1515 .parent_hws = (const struct clk_hw*[]) {1516 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,1517 },1518 .num_parents = 1,1519 .flags = CLK_SET_RATE_PARENT,1520 .ops = &clk_branch2_ops,1521 },1522 },1523};1524 1525static struct clk_branch gcc_pcie_0_pipe_clk = {1526 .halt_reg = 0x7b03c,1527 .halt_check = BRANCH_HALT_SKIP,1528 .clkr = {1529 .enable_reg = 0x62008,1530 .enable_mask = BIT(4),1531 .hw.init = &(const struct clk_init_data) {1532 .name = "gcc_pcie_0_pipe_clk",1533 .parent_hws = (const struct clk_hw*[]) {1534 &gcc_pcie_0_pipe_clk_src.clkr.hw,1535 },1536 .num_parents = 1,1537 .flags = CLK_SET_RATE_PARENT,1538 .ops = &clk_branch2_ops,1539 },1540 },1541};1542 1543static struct clk_branch gcc_pcie_0_pipe_div2_clk = {1544 .halt_reg = 0x7b094,1545 .halt_check = BRANCH_HALT_SKIP,1546 .clkr = {1547 .enable_reg = 0x62010,1548 .enable_mask = BIT(26),1549 .hw.init = &(const struct clk_init_data) {1550 .name = "gcc_pcie_0_pipe_div2_clk",1551 .parent_hws = (const struct clk_hw*[]) {1552 &gcc_pcie_0_pipe_div2_clk_src.clkr.hw,1553 },1554 .num_parents = 1,1555 .flags = CLK_SET_RATE_PARENT,1556 .ops = &clk_branch2_ops,1557 },1558 },1559};1560 1561static struct clk_branch gcc_pcie_0_slv_axi_clk = {1562 .halt_reg = 0x7b020,1563 .halt_check = BRANCH_HALT_VOTED,1564 .hwcg_reg = 0x7b020,1565 .hwcg_bit = 1,1566 .clkr = {1567 .enable_reg = 0x62008,1568 .enable_mask = BIT(0),1569 .hw.init = &(const struct clk_init_data) {1570 .name = "gcc_pcie_0_slv_axi_clk",1571 .ops = &clk_branch2_ops,1572 },1573 },1574};1575 1576static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {1577 .halt_reg = 0x7b01c,1578 .halt_check = BRANCH_HALT_VOTED,1579 .clkr = {1580 .enable_reg = 0x62008,1581 .enable_mask = BIT(5),1582 .hw.init = &(const struct clk_init_data) {1583 .name = "gcc_pcie_0_slv_q2a_axi_clk",1584 .ops = &clk_branch2_ops,1585 },1586 },1587};1588 1589static struct clk_branch gcc_pdm2_clk = {1590 .halt_reg = 0x4300c,1591 .halt_check = BRANCH_HALT,1592 .clkr = {1593 .enable_reg = 0x4300c,1594 .enable_mask = BIT(0),1595 .hw.init = &(const struct clk_init_data) {1596 .name = "gcc_pdm2_clk",1597 .parent_hws = (const struct clk_hw*[]) {1598 &gcc_pdm2_clk_src.clkr.hw,1599 },1600 .num_parents = 1,1601 .flags = CLK_SET_RATE_PARENT,1602 .ops = &clk_branch2_ops,1603 },1604 },1605};1606 1607static struct clk_branch gcc_pdm_ahb_clk = {1608 .halt_reg = 0x43004,1609 .halt_check = BRANCH_HALT_VOTED,1610 .hwcg_reg = 0x43004,1611 .hwcg_bit = 1,1612 .clkr = {1613 .enable_reg = 0x43004,1614 .enable_mask = BIT(0),1615 .hw.init = &(const struct clk_init_data) {1616 .name = "gcc_pdm_ahb_clk",1617 .ops = &clk_branch2_ops,1618 },1619 },1620};1621 1622static struct clk_branch gcc_pdm_xo4_clk = {1623 .halt_reg = 0x43008,1624 .halt_check = BRANCH_HALT,1625 .clkr = {1626 .enable_reg = 0x43008,1627 .enable_mask = BIT(0),1628 .hw.init = &(const struct clk_init_data) {1629 .name = "gcc_pdm_xo4_clk",1630 .ops = &clk_branch2_ops,1631 },1632 },1633};1634 1635static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {1636 .halt_reg = 0x36008,1637 .halt_check = BRANCH_HALT_VOTED,1638 .hwcg_reg = 0x36008,1639 .hwcg_bit = 1,1640 .clkr = {1641 .enable_reg = 0x36008,1642 .enable_mask = BIT(0),1643 .hw.init = &(const struct clk_init_data) {1644 .name = "gcc_qmip_camera_nrt_ahb_clk",1645 .ops = &clk_branch2_ops,1646 },1647 },1648};1649 1650static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {1651 .halt_reg = 0x3600c,1652 .halt_check = BRANCH_HALT_VOTED,1653 .hwcg_reg = 0x3600c,1654 .hwcg_bit = 1,1655 .clkr = {1656 .enable_reg = 0x3600c,1657 .enable_mask = BIT(0),1658 .hw.init = &(const struct clk_init_data) {1659 .name = "gcc_qmip_camera_rt_ahb_clk",1660 .ops = &clk_branch2_ops,1661 },1662 },1663};1664 1665static struct clk_branch gcc_qmip_disp_ahb_clk = {1666 .halt_reg = 0x37008,1667 .halt_check = BRANCH_HALT_VOTED,1668 .hwcg_reg = 0x37008,1669 .hwcg_bit = 1,1670 .clkr = {1671 .enable_reg = 0x37008,1672 .enable_mask = BIT(0),1673 .hw.init = &(const struct clk_init_data) {1674 .name = "gcc_qmip_disp_ahb_clk",1675 .ops = &clk_branch2_ops,1676 },1677 },1678};1679 1680static struct clk_branch gcc_qmip_gpu_ahb_clk = {1681 .halt_reg = 0x81008,1682 .halt_check = BRANCH_HALT_VOTED,1683 .hwcg_reg = 0x81008,1684 .hwcg_bit = 1,1685 .clkr = {1686 .enable_reg = 0x81008,1687 .enable_mask = BIT(0),1688 .hw.init = &(const struct clk_init_data) {1689 .name = "gcc_qmip_gpu_ahb_clk",1690 .ops = &clk_branch2_ops,1691 },1692 },1693};1694 1695static struct clk_branch gcc_qmip_pcie_ahb_clk = {1696 .halt_reg = 0x7b018,1697 .halt_check = BRANCH_HALT_VOTED,1698 .hwcg_reg = 0x7b018,1699 .hwcg_bit = 1,1700 .clkr = {1701 .enable_reg = 0x7b018,1702 .enable_mask = BIT(0),1703 .hw.init = &(const struct clk_init_data) {1704 .name = "gcc_qmip_pcie_ahb_clk",1705 .ops = &clk_branch2_ops,1706 },1707 },1708};1709 1710static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {1711 .halt_reg = 0x42008,1712 .halt_check = BRANCH_HALT_VOTED,1713 .hwcg_reg = 0x42008,1714 .hwcg_bit = 1,1715 .clkr = {1716 .enable_reg = 0x42008,1717 .enable_mask = BIT(0),1718 .hw.init = &(const struct clk_init_data) {1719 .name = "gcc_qmip_video_vcodec_ahb_clk",1720 .ops = &clk_branch2_ops,1721 },1722 },1723};1724 1725static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {1726 .halt_reg = 0x3300c,1727 .halt_check = BRANCH_HALT_VOTED,1728 .clkr = {1729 .enable_reg = 0x62008,1730 .enable_mask = BIT(9),1731 .hw.init = &(const struct clk_init_data) {1732 .name = "gcc_qupv3_wrap0_core_2x_clk",1733 .ops = &clk_branch2_ops,1734 },1735 },1736};1737 1738static struct clk_branch gcc_qupv3_wrap0_core_clk = {1739 .halt_reg = 0x33000,1740 .halt_check = BRANCH_HALT_VOTED,1741 .clkr = {1742 .enable_reg = 0x62008,1743 .enable_mask = BIT(8),1744 .hw.init = &(const struct clk_init_data) {1745 .name = "gcc_qupv3_wrap0_core_clk",1746 .ops = &clk_branch2_ops,1747 },1748 },1749};1750 1751static struct clk_branch gcc_qupv3_wrap0_s0_clk = {1752 .halt_reg = 0x2700c,1753 .halt_check = BRANCH_HALT_VOTED,1754 .clkr = {1755 .enable_reg = 0x62008,1756 .enable_mask = BIT(10),1757 .hw.init = &(const struct clk_init_data) {1758 .name = "gcc_qupv3_wrap0_s0_clk",1759 .parent_hws = (const struct clk_hw*[]) {1760 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,1761 },1762 .num_parents = 1,1763 .flags = CLK_SET_RATE_PARENT,1764 .ops = &clk_branch2_ops,1765 },1766 },1767};1768 1769static struct clk_branch gcc_qupv3_wrap0_s1_clk = {1770 .halt_reg = 0x27140,1771 .halt_check = BRANCH_HALT_VOTED,1772 .clkr = {1773 .enable_reg = 0x62008,1774 .enable_mask = BIT(11),1775 .hw.init = &(const struct clk_init_data) {1776 .name = "gcc_qupv3_wrap0_s1_clk",1777 .parent_hws = (const struct clk_hw*[]) {1778 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,1779 },1780 .num_parents = 1,1781 .flags = CLK_SET_RATE_PARENT,1782 .ops = &clk_branch2_ops,1783 },1784 },1785};1786 1787static struct clk_branch gcc_qupv3_wrap0_s2_clk = {1788 .halt_reg = 0x27274,1789 .halt_check = BRANCH_HALT_VOTED,1790 .clkr = {1791 .enable_reg = 0x62008,1792 .enable_mask = BIT(12),1793 .hw.init = &(const struct clk_init_data) {1794 .name = "gcc_qupv3_wrap0_s2_clk",1795 .parent_hws = (const struct clk_hw*[]) {1796 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,1797 },1798 .num_parents = 1,1799 .flags = CLK_SET_RATE_PARENT,1800 .ops = &clk_branch2_ops,1801 },1802 },1803};1804 1805static struct clk_branch gcc_qupv3_wrap0_s3_clk = {1806 .halt_reg = 0x273a8,1807 .halt_check = BRANCH_HALT_VOTED,1808 .clkr = {1809 .enable_reg = 0x62008,1810 .enable_mask = BIT(13),1811 .hw.init = &(const struct clk_init_data) {1812 .name = "gcc_qupv3_wrap0_s3_clk",1813 .parent_hws = (const struct clk_hw*[]) {1814 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,1815 },1816 .num_parents = 1,1817 .flags = CLK_SET_RATE_PARENT,1818 .ops = &clk_branch2_ops,1819 },1820 },1821};1822 1823static struct clk_branch gcc_qupv3_wrap0_s4_clk = {1824 .halt_reg = 0x274dc,1825 .halt_check = BRANCH_HALT_VOTED,1826 .clkr = {1827 .enable_reg = 0x62008,1828 .enable_mask = BIT(14),1829 .hw.init = &(const struct clk_init_data) {1830 .name = "gcc_qupv3_wrap0_s4_clk",1831 .parent_hws = (const struct clk_hw*[]) {1832 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,1833 },1834 .num_parents = 1,1835 .flags = CLK_SET_RATE_PARENT,1836 .ops = &clk_branch2_ops,1837 },1838 },1839};1840 1841static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {1842 .halt_reg = 0x3314c,1843 .halt_check = BRANCH_HALT_VOTED,1844 .clkr = {1845 .enable_reg = 0x62008,1846 .enable_mask = BIT(18),1847 .hw.init = &(const struct clk_init_data) {1848 .name = "gcc_qupv3_wrap1_core_2x_clk",1849 .ops = &clk_branch2_ops,1850 },1851 },1852};1853 1854static struct clk_branch gcc_qupv3_wrap1_core_clk = {1855 .halt_reg = 0x33140,1856 .halt_check = BRANCH_HALT_VOTED,1857 .clkr = {1858 .enable_reg = 0x62008,1859 .enable_mask = BIT(19),1860 .hw.init = &(const struct clk_init_data) {1861 .name = "gcc_qupv3_wrap1_core_clk",1862 .ops = &clk_branch2_ops,1863 },1864 },1865};1866 1867static struct clk_branch gcc_qupv3_wrap1_s0_clk = {1868 .halt_reg = 0x2800c,1869 .halt_check = BRANCH_HALT_VOTED,1870 .clkr = {1871 .enable_reg = 0x62008,1872 .enable_mask = BIT(22),1873 .hw.init = &(const struct clk_init_data) {1874 .name = "gcc_qupv3_wrap1_s0_clk",1875 .parent_hws = (const struct clk_hw*[]) {1876 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,1877 },1878 .num_parents = 1,1879 .flags = CLK_SET_RATE_PARENT,1880 .ops = &clk_branch2_ops,1881 },1882 },1883};1884 1885static struct clk_branch gcc_qupv3_wrap1_s1_clk = {1886 .halt_reg = 0x28140,1887 .halt_check = BRANCH_HALT_VOTED,1888 .clkr = {1889 .enable_reg = 0x62008,1890 .enable_mask = BIT(23),1891 .hw.init = &(const struct clk_init_data) {1892 .name = "gcc_qupv3_wrap1_s1_clk",1893 .parent_hws = (const struct clk_hw*[]) {1894 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,1895 },1896 .num_parents = 1,1897 .flags = CLK_SET_RATE_PARENT,1898 .ops = &clk_branch2_ops,1899 },1900 },1901};1902 1903static struct clk_branch gcc_qupv3_wrap1_s2_clk = {1904 .halt_reg = 0x28274,1905 .halt_check = BRANCH_HALT_VOTED,1906 .clkr = {1907 .enable_reg = 0x62008,1908 .enable_mask = BIT(24),1909 .hw.init = &(const struct clk_init_data) {1910 .name = "gcc_qupv3_wrap1_s2_clk",1911 .parent_hws = (const struct clk_hw*[]) {1912 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,1913 },1914 .num_parents = 1,1915 .flags = CLK_SET_RATE_PARENT,1916 .ops = &clk_branch2_ops,1917 },1918 },1919};1920 1921static struct clk_branch gcc_qupv3_wrap1_s3_clk = {1922 .halt_reg = 0x283a8,1923 .halt_check = BRANCH_HALT_VOTED,1924 .clkr = {1925 .enable_reg = 0x62008,1926 .enable_mask = BIT(25),1927 .hw.init = &(const struct clk_init_data) {1928 .name = "gcc_qupv3_wrap1_s3_clk",1929 .parent_hws = (const struct clk_hw*[]) {1930 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,1931 },1932 .num_parents = 1,1933 .flags = CLK_SET_RATE_PARENT,1934 .ops = &clk_branch2_ops,1935 },1936 },1937};1938 1939static struct clk_branch gcc_qupv3_wrap1_s4_clk = {1940 .halt_reg = 0x284dc,1941 .halt_check = BRANCH_HALT_VOTED,1942 .clkr = {1943 .enable_reg = 0x62008,1944 .enable_mask = BIT(26),1945 .hw.init = &(const struct clk_init_data) {1946 .name = "gcc_qupv3_wrap1_s4_clk",1947 .parent_hws = (const struct clk_hw*[]) {1948 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,1949 },1950 .num_parents = 1,1951 .flags = CLK_SET_RATE_PARENT,1952 .ops = &clk_branch2_ops,1953 },1954 },1955};1956 1957static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {1958 .halt_reg = 0x27004,1959 .halt_check = BRANCH_HALT_VOTED,1960 .hwcg_reg = 0x27004,1961 .hwcg_bit = 1,1962 .clkr = {1963 .enable_reg = 0x62008,1964 .enable_mask = BIT(6),1965 .hw.init = &(const struct clk_init_data) {1966 .name = "gcc_qupv3_wrap_0_m_ahb_clk",1967 .ops = &clk_branch2_ops,1968 },1969 },1970};1971 1972static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {1973 .halt_reg = 0x27008,1974 .halt_check = BRANCH_HALT_VOTED,1975 .hwcg_reg = 0x27008,1976 .hwcg_bit = 1,1977 .clkr = {1978 .enable_reg = 0x62008,1979 .enable_mask = BIT(7),1980 .hw.init = &(const struct clk_init_data) {1981 .name = "gcc_qupv3_wrap_0_s_ahb_clk",1982 .ops = &clk_branch2_ops,1983 },1984 },1985};1986 1987static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {1988 .halt_reg = 0x28004,1989 .halt_check = BRANCH_HALT_VOTED,1990 .hwcg_reg = 0x28004,1991 .hwcg_bit = 1,1992 .clkr = {1993 .enable_reg = 0x62008,1994 .enable_mask = BIT(20),1995 .hw.init = &(const struct clk_init_data) {1996 .name = "gcc_qupv3_wrap_1_m_ahb_clk",1997 .ops = &clk_branch2_ops,1998 },1999 },2000};2001 2002static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {2003 .halt_reg = 0x28008,2004 .halt_check = BRANCH_HALT_VOTED,2005 .hwcg_reg = 0x28008,2006 .hwcg_bit = 1,2007 .clkr = {2008 .enable_reg = 0x62008,2009 .enable_mask = BIT(21),2010 .hw.init = &(const struct clk_init_data) {2011 .name = "gcc_qupv3_wrap_1_s_ahb_clk",2012 .ops = &clk_branch2_ops,2013 },2014 },2015};2016 2017static struct clk_branch gcc_sdcc1_ahb_clk = {2018 .halt_reg = 0xb3004,2019 .halt_check = BRANCH_HALT,2020 .clkr = {2021 .enable_reg = 0xb3004,2022 .enable_mask = BIT(0),2023 .hw.init = &(const struct clk_init_data) {2024 .name = "gcc_sdcc1_ahb_clk",2025 .ops = &clk_branch2_ops,2026 },2027 },2028};2029 2030static struct clk_branch gcc_sdcc1_apps_clk = {2031 .halt_reg = 0xb3008,2032 .halt_check = BRANCH_HALT,2033 .clkr = {2034 .enable_reg = 0xb3008,2035 .enable_mask = BIT(0),2036 .hw.init = &(const struct clk_init_data) {2037 .name = "gcc_sdcc1_apps_clk",2038 .parent_hws = (const struct clk_hw*[]) {2039 &gcc_sdcc1_apps_clk_src.clkr.hw,2040 },2041 .num_parents = 1,2042 .flags = CLK_SET_RATE_PARENT,2043 .ops = &clk_branch2_ops,2044 },2045 },2046};2047 2048static struct clk_branch gcc_sdcc1_ice_core_clk = {2049 .halt_reg = 0xb3028,2050 .halt_check = BRANCH_HALT_VOTED,2051 .hwcg_reg = 0xb3028,2052 .hwcg_bit = 1,2053 .clkr = {2054 .enable_reg = 0xb3028,2055 .enable_mask = BIT(0),2056 .hw.init = &(const struct clk_init_data) {2057 .name = "gcc_sdcc1_ice_core_clk",2058 .parent_hws = (const struct clk_hw*[]) {2059 &gcc_sdcc1_ice_core_clk_src.clkr.hw,2060 },2061 .num_parents = 1,2062 .flags = CLK_SET_RATE_PARENT,2063 .ops = &clk_branch2_ops,2064 },2065 },2066};2067 2068static struct clk_branch gcc_sdcc2_ahb_clk = {2069 .halt_reg = 0x2400c,2070 .halt_check = BRANCH_HALT,2071 .clkr = {2072 .enable_reg = 0x2400c,2073 .enable_mask = BIT(0),2074 .hw.init = &(const struct clk_init_data) {2075 .name = "gcc_sdcc2_ahb_clk",2076 .ops = &clk_branch2_ops,2077 },2078 },2079};2080 2081static struct clk_branch gcc_sdcc2_apps_clk = {2082 .halt_reg = 0x24004,2083 .halt_check = BRANCH_HALT,2084 .clkr = {2085 .enable_reg = 0x24004,2086 .enable_mask = BIT(0),2087 .hw.init = &(const struct clk_init_data) {2088 .name = "gcc_sdcc2_apps_clk",2089 .parent_hws = (const struct clk_hw*[]) {2090 &gcc_sdcc2_apps_clk_src.clkr.hw,2091 },2092 .num_parents = 1,2093 .flags = CLK_SET_RATE_PARENT,2094 .ops = &clk_branch2_ops,2095 },2096 },2097};2098 2099static struct clk_branch gcc_ufs_0_clkref_en = {2100 .halt_reg = 0x9c000,2101 .halt_check = BRANCH_HALT_DELAY,2102 .clkr = {2103 .enable_reg = 0x9c000,2104 .enable_mask = BIT(0),2105 .hw.init = &(const struct clk_init_data) {2106 .name = "gcc_ufs_0_clkref_en",2107 .ops = &clk_branch2_ops,2108 },2109 },2110};2111 2112static struct clk_branch gcc_ufs_pad_clkref_en = {2113 .halt_reg = 0x9c024,2114 .halt_check = BRANCH_HALT_DELAY,2115 .clkr = {2116 .enable_reg = 0x9c024,2117 .enable_mask = BIT(0),2118 .hw.init = &(const struct clk_init_data) {2119 .name = "gcc_ufs_pad_clkref_en",2120 .ops = &clk_branch2_ops,2121 },2122 },2123};2124 2125static struct clk_branch gcc_ufs_phy_ahb_clk = {2126 .halt_reg = 0x87020,2127 .halt_check = BRANCH_HALT_VOTED,2128 .hwcg_reg = 0x87020,2129 .hwcg_bit = 1,2130 .clkr = {2131 .enable_reg = 0x87020,2132 .enable_mask = BIT(0),2133 .hw.init = &(const struct clk_init_data) {2134 .name = "gcc_ufs_phy_ahb_clk",2135 .ops = &clk_branch2_ops,2136 },2137 },2138};2139 2140static struct clk_branch gcc_ufs_phy_axi_clk = {2141 .halt_reg = 0x87018,2142 .halt_check = BRANCH_HALT_VOTED,2143 .hwcg_reg = 0x87018,2144 .hwcg_bit = 1,2145 .clkr = {2146 .enable_reg = 0x87018,2147 .enable_mask = BIT(0),2148 .hw.init = &(const struct clk_init_data) {2149 .name = "gcc_ufs_phy_axi_clk",2150 .parent_hws = (const struct clk_hw*[]) {2151 &gcc_ufs_phy_axi_clk_src.clkr.hw,2152 },2153 .num_parents = 1,2154 .flags = CLK_SET_RATE_PARENT,2155 .ops = &clk_branch2_ops,2156 },2157 },2158};2159 2160static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {2161 .halt_reg = 0x87018,2162 .halt_check = BRANCH_HALT_VOTED,2163 .hwcg_reg = 0x87018,2164 .hwcg_bit = 1,2165 .clkr = {2166 .enable_reg = 0x87018,2167 .enable_mask = BIT(1),2168 .hw.init = &(const struct clk_init_data) {2169 .name = "gcc_ufs_phy_axi_hw_ctl_clk",2170 .parent_hws = (const struct clk_hw*[]) {2171 &gcc_ufs_phy_axi_clk_src.clkr.hw,2172 },2173 .num_parents = 1,2174 .flags = CLK_SET_RATE_PARENT,2175 .ops = &clk_branch2_ops,2176 },2177 },2178};2179 2180static struct clk_branch gcc_ufs_phy_ice_core_clk = {2181 .halt_reg = 0x8706c,2182 .halt_check = BRANCH_HALT_VOTED,2183 .hwcg_reg = 0x8706c,2184 .hwcg_bit = 1,2185 .clkr = {2186 .enable_reg = 0x8706c,2187 .enable_mask = BIT(0),2188 .hw.init = &(const struct clk_init_data) {2189 .name = "gcc_ufs_phy_ice_core_clk",2190 .parent_hws = (const struct clk_hw*[]) {2191 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,2192 },2193 .num_parents = 1,2194 .flags = CLK_SET_RATE_PARENT,2195 .ops = &clk_branch2_ops,2196 },2197 },2198};2199 2200static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {2201 .halt_reg = 0x8706c,2202 .halt_check = BRANCH_HALT_VOTED,2203 .hwcg_reg = 0x8706c,2204 .hwcg_bit = 1,2205 .clkr = {2206 .enable_reg = 0x8706c,2207 .enable_mask = BIT(1),2208 .hw.init = &(const struct clk_init_data) {2209 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",2210 .parent_hws = (const struct clk_hw*[]) {2211 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,2212 },2213 .num_parents = 1,2214 .flags = CLK_SET_RATE_PARENT,2215 .ops = &clk_branch2_ops,2216 },2217 },2218};2219 2220static struct clk_branch gcc_ufs_phy_phy_aux_clk = {2221 .halt_reg = 0x870a4,2222 .halt_check = BRANCH_HALT_VOTED,2223 .hwcg_reg = 0x870a4,2224 .hwcg_bit = 1,2225 .clkr = {2226 .enable_reg = 0x870a4,2227 .enable_mask = BIT(0),2228 .hw.init = &(const struct clk_init_data) {2229 .name = "gcc_ufs_phy_phy_aux_clk",2230 .parent_hws = (const struct clk_hw*[]) {2231 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,2232 },2233 .num_parents = 1,2234 .flags = CLK_SET_RATE_PARENT,2235 .ops = &clk_branch2_ops,2236 },2237 },2238};2239 2240static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {2241 .halt_reg = 0x870a4,2242 .halt_check = BRANCH_HALT_VOTED,2243 .hwcg_reg = 0x870a4,2244 .hwcg_bit = 1,2245 .clkr = {2246 .enable_reg = 0x870a4,2247 .enable_mask = BIT(1),2248 .hw.init = &(const struct clk_init_data) {2249 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",2250 .parent_hws = (const struct clk_hw*[]) {2251 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,2252 },2253 .num_parents = 1,2254 .flags = CLK_SET_RATE_PARENT,2255 .ops = &clk_branch2_ops,2256 },2257 },2258};2259 2260static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {2261 .halt_reg = 0x87028,2262 .halt_check = BRANCH_HALT_DELAY,2263 .clkr = {2264 .enable_reg = 0x87028,2265 .enable_mask = BIT(0),2266 .hw.init = &(const struct clk_init_data) {2267 .name = "gcc_ufs_phy_rx_symbol_0_clk",2268 .parent_hws = (const struct clk_hw*[]) {2269 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,2270 },2271 .num_parents = 1,2272 .flags = CLK_SET_RATE_PARENT,2273 .ops = &clk_branch2_ops,2274 },2275 },2276};2277 2278static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {2279 .halt_reg = 0x870c0,2280 .halt_check = BRANCH_HALT_DELAY,2281 .clkr = {2282 .enable_reg = 0x870c0,2283 .enable_mask = BIT(0),2284 .hw.init = &(const struct clk_init_data) {2285 .name = "gcc_ufs_phy_rx_symbol_1_clk",2286 .parent_hws = (const struct clk_hw*[]) {2287 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,2288 },2289 .num_parents = 1,2290 .flags = CLK_SET_RATE_PARENT,2291 .ops = &clk_branch2_ops,2292 },2293 },2294};2295 2296static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {2297 .halt_reg = 0x87024,2298 .halt_check = BRANCH_HALT_DELAY,2299 .clkr = {2300 .enable_reg = 0x87024,2301 .enable_mask = BIT(0),2302 .hw.init = &(const struct clk_init_data) {2303 .name = "gcc_ufs_phy_tx_symbol_0_clk",2304 .parent_hws = (const struct clk_hw*[]) {2305 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,2306 },2307 .num_parents = 1,2308 .flags = CLK_SET_RATE_PARENT,2309 .ops = &clk_branch2_ops,2310 },2311 },2312};2313 2314static struct clk_branch gcc_ufs_phy_unipro_core_clk = {2315 .halt_reg = 0x87064,2316 .halt_check = BRANCH_HALT_VOTED,2317 .hwcg_reg = 0x87064,2318 .hwcg_bit = 1,2319 .clkr = {2320 .enable_reg = 0x87064,2321 .enable_mask = BIT(0),2322 .hw.init = &(const struct clk_init_data) {2323 .name = "gcc_ufs_phy_unipro_core_clk",2324 .parent_hws = (const struct clk_hw*[]) {2325 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,2326 },2327 .num_parents = 1,2328 .flags = CLK_SET_RATE_PARENT,2329 .ops = &clk_branch2_ops,2330 },2331 },2332};2333 2334static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {2335 .halt_reg = 0x87064,2336 .halt_check = BRANCH_HALT_VOTED,2337 .hwcg_reg = 0x87064,2338 .hwcg_bit = 1,2339 .clkr = {2340 .enable_reg = 0x87064,2341 .enable_mask = BIT(1),2342 .hw.init = &(const struct clk_init_data) {2343 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",2344 .parent_hws = (const struct clk_hw*[]) {2345 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,2346 },2347 .num_parents = 1,2348 .flags = CLK_SET_RATE_PARENT,2349 .ops = &clk_branch2_ops,2350 },2351 },2352};2353 2354static struct clk_branch gcc_usb30_prim_master_clk = {2355 .halt_reg = 0x49018,2356 .halt_check = BRANCH_HALT,2357 .clkr = {2358 .enable_reg = 0x49018,2359 .enable_mask = BIT(0),2360 .hw.init = &(const struct clk_init_data) {2361 .name = "gcc_usb30_prim_master_clk",2362 .parent_hws = (const struct clk_hw*[]) {2363 &gcc_usb30_prim_master_clk_src.clkr.hw,2364 },2365 .num_parents = 1,2366 .flags = CLK_SET_RATE_PARENT,2367 .ops = &clk_branch2_ops,2368 },2369 },2370};2371 2372static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {2373 .halt_reg = 0x49024,2374 .halt_check = BRANCH_HALT,2375 .clkr = {2376 .enable_reg = 0x49024,2377 .enable_mask = BIT(0),2378 .hw.init = &(const struct clk_init_data) {2379 .name = "gcc_usb30_prim_mock_utmi_clk",2380 .parent_hws = (const struct clk_hw*[]) {2381 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,2382 },2383 .num_parents = 1,2384 .flags = CLK_SET_RATE_PARENT,2385 .ops = &clk_branch2_ops,2386 },2387 },2388};2389 2390static struct clk_branch gcc_usb30_prim_sleep_clk = {2391 .halt_reg = 0x49020,2392 .halt_check = BRANCH_HALT,2393 .clkr = {2394 .enable_reg = 0x49020,2395 .enable_mask = BIT(0),2396 .hw.init = &(const struct clk_init_data) {2397 .name = "gcc_usb30_prim_sleep_clk",2398 .ops = &clk_branch2_ops,2399 },2400 },2401};2402 2403static struct clk_branch gcc_usb3_0_clkref_en = {2404 .halt_reg = 0x9c010,2405 .halt_check = BRANCH_HALT_DELAY,2406 .clkr = {2407 .enable_reg = 0x9c010,2408 .enable_mask = BIT(0),2409 .hw.init = &(const struct clk_init_data) {2410 .name = "gcc_usb3_0_clkref_en",2411 .ops = &clk_branch2_ops,2412 },2413 },2414};2415 2416static struct clk_branch gcc_usb3_prim_phy_aux_clk = {2417 .halt_reg = 0x4905c,2418 .halt_check = BRANCH_HALT,2419 .clkr = {2420 .enable_reg = 0x4905c,2421 .enable_mask = BIT(0),2422 .hw.init = &(const struct clk_init_data) {2423 .name = "gcc_usb3_prim_phy_aux_clk",2424 .parent_hws = (const struct clk_hw*[]) {2425 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,2426 },2427 .num_parents = 1,2428 .flags = CLK_SET_RATE_PARENT,2429 .ops = &clk_branch2_ops,2430 },2431 },2432};2433 2434static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {2435 .halt_reg = 0x49060,2436 .halt_check = BRANCH_HALT,2437 .clkr = {2438 .enable_reg = 0x49060,2439 .enable_mask = BIT(0),2440 .hw.init = &(const struct clk_init_data) {2441 .name = "gcc_usb3_prim_phy_com_aux_clk",2442 .parent_hws = (const struct clk_hw*[]) {2443 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,2444 },2445 .num_parents = 1,2446 .flags = CLK_SET_RATE_PARENT,2447 .ops = &clk_branch2_ops,2448 },2449 },2450};2451 2452static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {2453 .halt_reg = 0x49064,2454 .halt_check = BRANCH_HALT_DELAY,2455 .hwcg_reg = 0x49064,2456 .hwcg_bit = 1,2457 .clkr = {2458 .enable_reg = 0x49064,2459 .enable_mask = BIT(0),2460 .hw.init = &(const struct clk_init_data) {2461 .name = "gcc_usb3_prim_phy_pipe_clk",2462 .parent_hws = (const struct clk_hw*[]) {2463 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,2464 },2465 .num_parents = 1,2466 .flags = CLK_SET_RATE_PARENT,2467 .ops = &clk_branch2_ops,2468 },2469 },2470};2471 2472static struct clk_branch gcc_vcodec0_axi_clk = {2473 .halt_reg = 0x42020,2474 .halt_check = BRANCH_HALT_SKIP,2475 .hwcg_reg = 0x42020,2476 .hwcg_bit = 1,2477 .clkr = {2478 .enable_reg = 0x42020,2479 .enable_mask = BIT(0),2480 .hw.init = &(const struct clk_init_data) {2481 .name = "gcc_vcodec0_axi_clk",2482 .ops = &clk_branch2_ops,2483 },2484 },2485};2486 2487static struct clk_branch gcc_venus_ctl_axi_clk = {2488 .halt_reg = 0x4201c,2489 .halt_check = BRANCH_HALT_SKIP,2490 .clkr = {2491 .enable_reg = 0x4201c,2492 .enable_mask = BIT(0),2493 .hw.init = &(const struct clk_init_data) {2494 .name = "gcc_venus_ctl_axi_clk",2495 .ops = &clk_branch2_ops,2496 },2497 },2498};2499 2500static struct clk_branch gcc_video_throttle_core_clk = {2501 .halt_reg = 0x42014,2502 .halt_check = BRANCH_HALT_SKIP,2503 .hwcg_reg = 0x42014,2504 .hwcg_bit = 1,2505 .clkr = {2506 .enable_reg = 0x42014,2507 .enable_mask = BIT(0),2508 .hw.init = &(const struct clk_init_data) {2509 .name = "gcc_video_throttle_core_clk",2510 .ops = &clk_branch2_ops,2511 },2512 },2513};2514 2515static struct clk_branch gcc_video_vcodec0_sys_clk = {2516 .halt_reg = 0xb6058,2517 .halt_check = BRANCH_HALT_VOTED,2518 .hwcg_reg = 0xb6058,2519 .hwcg_bit = 1,2520 .clkr = {2521 .enable_reg = 0xb6058,2522 .enable_mask = BIT(0),2523 .hw.init = &(const struct clk_init_data) {2524 .name = "gcc_video_vcodec0_sys_clk",2525 .parent_hws = (const struct clk_hw*[]) {2526 &gcc_video_venus_clk_src.clkr.hw,2527 },2528 .num_parents = 1,2529 .flags = CLK_SET_RATE_PARENT,2530 .ops = &clk_branch2_ops,2531 },2532 },2533};2534 2535static struct clk_branch gcc_video_venus_ctl_clk = {2536 .halt_reg = 0xb6038,2537 .halt_check = BRANCH_HALT,2538 .clkr = {2539 .enable_reg = 0xb6038,2540 .enable_mask = BIT(0),2541 .hw.init = &(const struct clk_init_data) {2542 .name = "gcc_video_venus_ctl_clk",2543 .parent_hws = (const struct clk_hw*[]) {2544 &gcc_video_venus_clk_src.clkr.hw,2545 },2546 .num_parents = 1,2547 .flags = CLK_SET_RATE_PARENT,2548 .ops = &clk_branch2_ops,2549 },2550 },2551};2552 2553static struct gdsc gcc_pcie_0_gdsc = {2554 .gdscr = 0x7b004,2555 .en_rest_wait_val = 0x2,2556 .en_few_wait_val = 0x2,2557 .clk_dis_wait_val = 0xf,2558 .pd = {2559 .name = "gcc_pcie_0_gdsc",2560 },2561 .pwrsts = PWRSTS_OFF_ON,2562 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,2563};2564 2565static struct gdsc gcc_ufs_phy_gdsc = {2566 .gdscr = 0x87004,2567 .en_rest_wait_val = 0x2,2568 .en_few_wait_val = 0x2,2569 .clk_dis_wait_val = 0xf,2570 .pd = {2571 .name = "gcc_ufs_phy_gdsc",2572 },2573 .pwrsts = PWRSTS_OFF_ON,2574 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,2575};2576 2577static struct gdsc gcc_usb30_prim_gdsc = {2578 .gdscr = 0x49004,2579 .en_rest_wait_val = 0x2,2580 .en_few_wait_val = 0x2,2581 .clk_dis_wait_val = 0xf,2582 .pd = {2583 .name = "gcc_usb30_prim_gdsc",2584 },2585 .pwrsts = PWRSTS_OFF_ON,2586 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,2587};2588 2589static struct gdsc gcc_vcodec0_gdsc = {2590 .gdscr = 0xb6044,2591 .en_rest_wait_val = 0x2,2592 .en_few_wait_val = 0x2,2593 .clk_dis_wait_val = 0xf,2594 .pd = {2595 .name = "gcc_vcodec0_gdsc",2596 },2597 .pwrsts = PWRSTS_OFF_ON,2598 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,2599};2600 2601static struct gdsc gcc_venus_gdsc = {2602 .gdscr = 0xb6020,2603 .en_rest_wait_val = 0x2,2604 .en_few_wait_val = 0x2,2605 .clk_dis_wait_val = 0xf,2606 .pd = {2607 .name = "gcc_venus_gdsc",2608 },2609 .pwrsts = PWRSTS_OFF_ON,2610 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,2611};2612 2613static struct clk_regmap *gcc_sm4450_clocks[] = {2614 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,2615 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,2616 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,2617 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,2618 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,2619 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,2620 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,2621 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,2622 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,2623 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,2624 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,2625 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,2626 [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,2627 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,2628 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,2629 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,2630 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,2631 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,2632 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,2633 [GCC_GPLL0] = &gcc_gpll0.clkr,2634 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,2635 [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,2636 [GCC_GPLL1] = &gcc_gpll1.clkr,2637 [GCC_GPLL3] = &gcc_gpll3.clkr,2638 [GCC_GPLL4] = &gcc_gpll4.clkr,2639 [GCC_GPLL9] = &gcc_gpll9.clkr,2640 [GCC_GPLL10] = &gcc_gpll10.clkr,2641 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,2642 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,2643 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,2644 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,2645 [GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK] =2646 &gcc_hlos1_vote_aggre_noc_mmu_audio_tbu_clk.clkr,2647 [GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK] =2648 &gcc_hlos1_vote_aggre_noc_mmu_pcie_tbu_clk.clkr,2649 [GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK] = &gcc_hlos1_vote_aggre_noc_mmu_tbu1_clk.clkr,2650 [GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK] = &gcc_hlos1_vote_aggre_noc_mmu_tbu2_clk.clkr,2651 [GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_clk.clkr,2652 [GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_clk.clkr,2653 [GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF0_CLK] = &gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_clk.clkr,2654 [GCC_HLOS1_VOTE_MMU_TCU_CLK] = &gcc_hlos1_vote_mmu_tcu_clk.clkr,2655 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,2656 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,2657 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,2658 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,2659 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,2660 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,2661 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,2662 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,2663 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,2664 [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr,2665 [GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr,2666 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,2667 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,2668 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,2669 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,2670 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,2671 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,2672 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,2673 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,2674 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,2675 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,2676 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,2677 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,2678 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,2679 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,2680 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,2681 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,2682 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,2683 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,2684 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,2685 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,2686 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,2687 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,2688 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,2689 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,2690 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,2691 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,2692 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,2693 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,2694 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,2695 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,2696 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,2697 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,2698 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,2699 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,2700 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,2701 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,2702 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,2703 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,2704 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,2705 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,2706 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,2707 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,2708 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,2709 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,2710 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,2711 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,2712 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,2713 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,2714 [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,2715 [GCC_UFS_PAD_CLKREF_EN] = &gcc_ufs_pad_clkref_en.clkr,2716 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,2717 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,2718 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,2719 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,2720 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,2721 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,2722 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,2723 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,2724 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,2725 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,2726 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,2727 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,2728 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,2729 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,2730 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,2731 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,2732 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,2733 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,2734 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,2735 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,2736 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,2737 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,2738 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,2739 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,2740 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,2741 [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,2742 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,2743 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,2744 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,2745 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,2746 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,2747 [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,2748 [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,2749 [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,2750 [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,2751 [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,2752 [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,2753};2754 2755static struct gdsc *gcc_sm4450_gdscs[] = {2756 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,2757 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,2758 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,2759 [GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,2760 [GCC_VENUS_GDSC] = &gcc_venus_gdsc,2761};2762 2763static const struct qcom_reset_map gcc_sm4450_resets[] = {2764 [GCC_CAMERA_BCR] = { 0x36000 },2765 [GCC_DISPLAY_BCR] = { 0x37000 },2766 [GCC_GPU_BCR] = { 0x81000 },2767 [GCC_PCIE_0_BCR] = { 0x7b000 },2768 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },2769 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },2770 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },2771 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },2772 [GCC_PCIE_PHY_BCR] = { 0x7f000 },2773 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },2774 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },2775 [GCC_PDM_BCR] = { 0x43000 },2776 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },2777 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },2778 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },2779 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },2780 [GCC_SDCC1_BCR] = { 0xb3000 },2781 [GCC_SDCC2_BCR] = { 0x24000 },2782 [GCC_UFS_PHY_BCR] = { 0x87000 },2783 [GCC_USB30_PRIM_BCR] = { 0x49000 },2784 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },2785 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },2786 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },2787 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },2788 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },2789 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },2790 [GCC_VCODEC0_BCR] = { 0xb6040 },2791 [GCC_VENUS_BCR] = { 0xb601c },2792 [GCC_VIDEO_BCR] = { 0x42000 },2793 [GCC_VIDEO_VENUS_BCR] = { 0xb6000 },2794 [GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 },2795 [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 },2796};2797 2798static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {2799 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),2800 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),2801 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),2802 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),2803 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),2804 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),2805 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),2806 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),2807 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),2808 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),2809};2810 2811static const struct regmap_config gcc_sm4450_regmap_config = {2812 .reg_bits = 32,2813 .reg_stride = 4,2814 .val_bits = 32,2815 .max_register = 0x1f41f0,2816 .fast_io = true,2817};2818 2819static const struct qcom_cc_desc gcc_sm4450_desc = {2820 .config = &gcc_sm4450_regmap_config,2821 .clks = gcc_sm4450_clocks,2822 .num_clks = ARRAY_SIZE(gcc_sm4450_clocks),2823 .resets = gcc_sm4450_resets,2824 .num_resets = ARRAY_SIZE(gcc_sm4450_resets),2825 .gdscs = gcc_sm4450_gdscs,2826 .num_gdscs = ARRAY_SIZE(gcc_sm4450_gdscs),2827};2828 2829static const struct of_device_id gcc_sm4450_match_table[] = {2830 { .compatible = "qcom,sm4450-gcc" },2831 { }2832};2833MODULE_DEVICE_TABLE(of, gcc_sm4450_match_table);2834 2835static int gcc_sm4450_probe(struct platform_device *pdev)2836{2837 struct regmap *regmap;2838 int ret;2839 2840 regmap = qcom_cc_map(pdev, &gcc_sm4450_desc);2841 if (IS_ERR(regmap))2842 return PTR_ERR(regmap);2843 2844 clk_lucid_evo_pll_configure(&gcc_gpll3, regmap, &gcc_gpll3_config);2845 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,2846 ARRAY_SIZE(gcc_dfs_clocks));2847 if (ret)2848 return ret;2849 2850 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);2851 2852 /* Keep some clocks always-on */2853 qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */2854 qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */2855 qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */2856 qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */2857 qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */2858 qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */2859 qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */2860 qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */2861 2862 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));2863 2864 return qcom_cc_really_probe(&pdev->dev, &gcc_sm4450_desc, regmap);2865}2866 2867static struct platform_driver gcc_sm4450_driver = {2868 .probe = gcc_sm4450_probe,2869 .driver = {2870 .name = "gcc-sm4450",2871 .of_match_table = gcc_sm4450_match_table,2872 },2873};2874 2875static int __init gcc_sm4450_init(void)2876{2877 return platform_driver_register(&gcc_sm4450_driver);2878}2879subsys_initcall(gcc_sm4450_init);2880 2881static void __exit gcc_sm4450_exit(void)2882{2883 platform_driver_unregister(&gcc_sm4450_driver);2884}2885module_exit(gcc_sm4450_exit);2886 2887MODULE_DESCRIPTION("QTI GCC SM4450 Driver");2888MODULE_LICENSE("GPL");2889