brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.4 */5 6#include <linux/err.h>7#include <linux/kernel.h>8#include <linux/module.h>9#include <linux/of.h>10#include <linux/platform_device.h>11#include <linux/clk-provider.h>12#include <linux/regmap.h>13#include <linux/reset-controller.h>14 15#include <dt-bindings/clock/qcom,gcc-sm6115.h>16 17#include "clk-alpha-pll.h"18#include "clk-branch.h"19#include "clk-pll.h"20#include "clk-rcg.h"21#include "clk-regmap.h"22#include "clk-regmap-divider.h"23#include "common.h"24#include "gdsc.h"25#include "reset.h"26 27enum {28	P_BI_TCXO,29	P_GPLL0_OUT_AUX2,30	P_GPLL0_OUT_EARLY,31	P_GPLL10_OUT_MAIN,32	P_GPLL11_OUT_MAIN,33	P_GPLL3_OUT_EARLY,34	P_GPLL4_OUT_MAIN,35	P_GPLL6_OUT_EARLY,36	P_GPLL6_OUT_MAIN,37	P_GPLL7_OUT_MAIN,38	P_GPLL8_OUT_EARLY,39	P_GPLL8_OUT_MAIN,40	P_GPLL9_OUT_EARLY,41	P_GPLL9_OUT_MAIN,42	P_SLEEP_CLK,43};44 45static const struct pll_vco default_vco[] = {46	{ 500000000, 1000000000, 2 },47};48 49static const struct pll_vco gpll9_vco[] = {50	{ 500000000, 1250000000, 0 },51};52 53static const struct pll_vco gpll10_vco[] = {54	{ 750000000, 1500000000, 1 },55};56 57static struct clk_alpha_pll gpll0 = {58	.offset = 0x0,59	.vco_table = default_vco,60	.num_vco = ARRAY_SIZE(default_vco),61	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],62	.clkr = {63		.enable_reg = 0x79000,64		.enable_mask = BIT(0),65		.hw.init = &(struct clk_init_data){66			.name = "gpll0",67			.parent_data = &(const struct clk_parent_data){68				.fw_name = "bi_tcxo",69			},70			.num_parents = 1,71			.ops = &clk_alpha_pll_ops,72		},73	},74};75 76static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {77	{ 0x1, 2 },78	{ }79};80 81static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {82	.offset = 0x0,83	.post_div_shift = 8,84	.post_div_table = post_div_table_gpll0_out_aux2,85	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),86	.width = 4,87	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],88	.clkr.hw.init = &(struct clk_init_data){89		.name = "gpll0_out_aux2",90		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },91		.num_parents = 1,92		.ops = &clk_alpha_pll_postdiv_ro_ops,93	},94};95 96static const struct clk_div_table post_div_table_gpll0_out_main[] = {97	{ 0x0, 1 },98	{ }99};100 101static struct clk_alpha_pll_postdiv gpll0_out_main = {102	.offset = 0x0,103	.post_div_shift = 8,104	.post_div_table = post_div_table_gpll0_out_main,105	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),106	.width = 4,107	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],108	.clkr.hw.init = &(struct clk_init_data){109		.name = "gpll0_out_main",110		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },111		.num_parents = 1,112		.ops = &clk_alpha_pll_postdiv_ro_ops,113	},114};115 116/* 1152MHz configuration */117static const struct alpha_pll_config gpll10_config = {118	.l = 0x3c,119	.vco_val = 0x1 << 20,120	.vco_mask = GENMASK(21, 20),121	.main_output_mask = BIT(0),122	.config_ctl_val = 0x4001055b,123	.test_ctl_hi1_val = 0x1,124	.test_ctl_hi_mask = 0x1,125};126 127static struct clk_alpha_pll gpll10 = {128	.offset = 0xa000,129	.vco_table = gpll10_vco,130	.num_vco = ARRAY_SIZE(gpll10_vco),131	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],132	.clkr = {133		.enable_reg = 0x79000,134		.enable_mask = BIT(10),135		.hw.init = &(struct clk_init_data){136			.name = "gpll10",137			.parent_data = &(const struct clk_parent_data){138				.fw_name = "bi_tcxo",139			},140			.num_parents = 1,141			.ops = &clk_alpha_pll_ops,142		},143	},144};145 146static const struct clk_div_table post_div_table_gpll10_out_main[] = {147	{ 0x0, 1 },148	{ }149};150 151static struct clk_alpha_pll_postdiv gpll10_out_main = {152	.offset = 0xa000,153	.post_div_shift = 8,154	.post_div_table = post_div_table_gpll10_out_main,155	.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),156	.width = 4,157	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],158	.clkr.hw.init = &(struct clk_init_data){159		.name = "gpll10_out_main",160		.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },161		.num_parents = 1,162		.flags = CLK_SET_RATE_PARENT,163		.ops = &clk_alpha_pll_postdiv_ops,164	},165};166 167/* 600MHz configuration */168static const struct alpha_pll_config gpll11_config = {169	.l = 0x1F,170	.alpha = 0x0,171	.alpha_hi = 0x40,172	.alpha_en_mask = BIT(24),173	.vco_val = 0x2 << 20,174	.vco_mask = GENMASK(21, 20),175	.config_ctl_val = 0x4001055b,176	.test_ctl_hi1_val = 0x1,177	.test_ctl_hi_mask = 0x1,178};179 180static struct clk_alpha_pll gpll11 = {181	.offset = 0xb000,182	.vco_table = default_vco,183	.num_vco = ARRAY_SIZE(default_vco),184	.flags = SUPPORTS_DYNAMIC_UPDATE,185	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],186	.clkr = {187		.enable_reg = 0x79000,188		.enable_mask = BIT(11),189		.hw.init = &(struct clk_init_data){190			.name = "gpll11",191			.parent_data = &(const struct clk_parent_data){192				.fw_name = "bi_tcxo",193			},194			.num_parents = 1,195			.ops = &clk_alpha_pll_ops,196		},197	},198};199 200static const struct clk_div_table post_div_table_gpll11_out_main[] = {201	{ 0x0, 1 },202	{ }203};204 205static struct clk_alpha_pll_postdiv gpll11_out_main = {206	.offset = 0xb000,207	.post_div_shift = 8,208	.post_div_table = post_div_table_gpll11_out_main,209	.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),210	.width = 4,211	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],212	.clkr.hw.init = &(struct clk_init_data){213		.name = "gpll11_out_main",214		.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },215		.num_parents = 1,216		.flags = CLK_SET_RATE_PARENT,217		.ops = &clk_alpha_pll_postdiv_ops,218	},219};220 221static struct clk_alpha_pll gpll3 = {222	.offset = 0x3000,223	.vco_table = default_vco,224	.num_vco = ARRAY_SIZE(default_vco),225	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],226	.clkr = {227		.enable_reg = 0x79000,228		.enable_mask = BIT(3),229		.hw.init = &(struct clk_init_data){230			.name = "gpll3",231			.parent_data = &(const struct clk_parent_data){232				.fw_name = "bi_tcxo",233			},234			.num_parents = 1,235			.ops = &clk_alpha_pll_ops,236		},237	},238};239 240static struct clk_alpha_pll gpll4 = {241	.offset = 0x4000,242	.vco_table = default_vco,243	.num_vco = ARRAY_SIZE(default_vco),244	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],245	.clkr = {246		.enable_reg = 0x79000,247		.enable_mask = BIT(4),248		.hw.init = &(struct clk_init_data){249			.name = "gpll4",250			.parent_data = &(const struct clk_parent_data){251				.fw_name = "bi_tcxo",252			},253			.num_parents = 1,254			.ops = &clk_alpha_pll_ops,255		},256	},257};258 259static const struct clk_div_table post_div_table_gpll4_out_main[] = {260	{ 0x0, 1 },261	{ }262};263 264static struct clk_alpha_pll_postdiv gpll4_out_main = {265	.offset = 0x4000,266	.post_div_shift = 8,267	.post_div_table = post_div_table_gpll4_out_main,268	.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),269	.width = 4,270	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],271	.clkr.hw.init = &(struct clk_init_data){272		.name = "gpll4_out_main",273		.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },274		.num_parents = 1,275		.ops = &clk_alpha_pll_postdiv_ro_ops,276	},277};278 279static struct clk_alpha_pll gpll6 = {280	.offset = 0x6000,281	.vco_table = default_vco,282	.num_vco = ARRAY_SIZE(default_vco),283	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],284	.clkr = {285		.enable_reg = 0x79000,286		.enable_mask = BIT(6),287		.hw.init = &(struct clk_init_data){288			.name = "gpll6",289			.parent_data = &(const struct clk_parent_data){290				.fw_name = "bi_tcxo",291			},292			.num_parents = 1,293			.ops = &clk_alpha_pll_ops,294		},295	},296};297 298static const struct clk_div_table post_div_table_gpll6_out_main[] = {299	{ 0x1, 2 },300	{ }301};302 303static struct clk_alpha_pll_postdiv gpll6_out_main = {304	.offset = 0x6000,305	.post_div_shift = 8,306	.post_div_table = post_div_table_gpll6_out_main,307	.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),308	.width = 4,309	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],310	.clkr.hw.init = &(struct clk_init_data){311		.name = "gpll6_out_main",312		.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },313		.num_parents = 1,314		.ops = &clk_alpha_pll_postdiv_ro_ops,315	},316};317 318static struct clk_alpha_pll gpll7 = {319	.offset = 0x7000,320	.vco_table = default_vco,321	.num_vco = ARRAY_SIZE(default_vco),322	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],323	.clkr = {324		.enable_reg = 0x79000,325		.enable_mask = BIT(7),326		.hw.init = &(struct clk_init_data){327			.name = "gpll7",328			.parent_data = &(const struct clk_parent_data){329				.fw_name = "bi_tcxo",330			},331			.num_parents = 1,332			.ops = &clk_alpha_pll_ops,333		},334	},335};336 337static const struct clk_div_table post_div_table_gpll7_out_main[] = {338	{ 0x0, 1 },339	{ }340};341 342static struct clk_alpha_pll_postdiv gpll7_out_main = {343	.offset = 0x7000,344	.post_div_shift = 8,345	.post_div_table = post_div_table_gpll7_out_main,346	.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),347	.width = 4,348	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],349	.clkr.hw.init = &(struct clk_init_data){350		.name = "gpll7_out_main",351		.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },352		.num_parents = 1,353		.ops = &clk_alpha_pll_postdiv_ro_ops,354	},355};356 357/* 800MHz configuration */358static const struct alpha_pll_config gpll8_config = {359	.l = 0x29,360	.alpha = 0xAAAAAAAA,361	.alpha_hi = 0xAA,362	.alpha_en_mask = BIT(24),363	.vco_val = 0x2 << 20,364	.vco_mask = GENMASK(21, 20),365	.main_output_mask = BIT(0),366	.early_output_mask = BIT(3),367	.post_div_val = 0x1 << 8,368	.post_div_mask = GENMASK(11, 8),369	.config_ctl_val = 0x4001055b,370	.test_ctl_hi1_val = 0x1,371	.test_ctl_hi_mask = 0x1,372};373 374static struct clk_alpha_pll gpll8 = {375	.offset = 0x8000,376	.vco_table = default_vco,377	.num_vco = ARRAY_SIZE(default_vco),378	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],379	.flags = SUPPORTS_DYNAMIC_UPDATE,380	.clkr = {381		.enable_reg = 0x79000,382		.enable_mask = BIT(8),383		.hw.init = &(struct clk_init_data){384			.name = "gpll8",385			.parent_data = &(const struct clk_parent_data){386				.fw_name = "bi_tcxo",387			},388			.num_parents = 1,389			.ops = &clk_alpha_pll_ops,390		},391	},392};393 394static const struct clk_div_table post_div_table_gpll8_out_main[] = {395	{ 0x1, 2 },396	{ }397};398 399static struct clk_alpha_pll_postdiv gpll8_out_main = {400	.offset = 0x8000,401	.post_div_shift = 8,402	.post_div_table = post_div_table_gpll8_out_main,403	.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),404	.width = 4,405	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],406	.clkr.hw.init = &(struct clk_init_data){407		.name = "gpll8_out_main",408		.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },409		.num_parents = 1,410		.flags = CLK_SET_RATE_PARENT,411		.ops = &clk_alpha_pll_postdiv_ro_ops,412	},413};414 415/* 1152MHz configuration */416static const struct alpha_pll_config gpll9_config = {417	.l = 0x3C,418	.alpha = 0x0,419	.post_div_val = 0x1 << 8,420	.post_div_mask = GENMASK(9, 8),421	.main_output_mask = BIT(0),422	.config_ctl_val = 0x00004289,423	.test_ctl_mask = GENMASK(31, 0),424	.test_ctl_val = 0x08000000,425};426 427static struct clk_alpha_pll gpll9 = {428	.offset = 0x9000,429	.vco_table = gpll9_vco,430	.num_vco = ARRAY_SIZE(gpll9_vco),431	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],432	.clkr = {433		.enable_reg = 0x79000,434		.enable_mask = BIT(9),435		.hw.init = &(struct clk_init_data){436			.name = "gpll9",437			.parent_data = &(const struct clk_parent_data){438				.fw_name = "bi_tcxo",439			},440			.num_parents = 1,441			.ops = &clk_alpha_pll_ops,442		},443	},444};445 446static const struct clk_div_table post_div_table_gpll9_out_main[] = {447	{ 0x1, 2 },448	{ }449};450 451static struct clk_alpha_pll_postdiv gpll9_out_main = {452	.offset = 0x9000,453	.post_div_shift = 8,454	.post_div_table = post_div_table_gpll9_out_main,455	.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),456	.width = 2,457	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],458	.clkr.hw.init = &(struct clk_init_data){459		.name = "gpll9_out_main",460		.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },461		.num_parents = 1,462		.flags = CLK_SET_RATE_PARENT,463		.ops = &clk_alpha_pll_postdiv_ops,464	},465};466 467static const struct parent_map gcc_parent_map_0[] = {468	{ P_BI_TCXO, 0 },469	{ P_GPLL0_OUT_EARLY, 1 },470	{ P_GPLL0_OUT_AUX2, 2 },471};472 473static const struct clk_parent_data gcc_parents_0[] = {474	{ .fw_name = "bi_tcxo" },475	{ .hw = &gpll0.clkr.hw },476	{ .hw = &gpll0_out_aux2.clkr.hw },477};478 479static const struct parent_map gcc_parent_map_1[] = {480	{ P_BI_TCXO, 0 },481	{ P_GPLL0_OUT_EARLY, 1 },482	{ P_GPLL0_OUT_AUX2, 2 },483	{ P_GPLL6_OUT_MAIN, 4 },484};485 486static const struct clk_parent_data gcc_parents_1[] = {487	{ .fw_name = "bi_tcxo" },488	{ .hw = &gpll0.clkr.hw },489	{ .hw = &gpll0_out_aux2.clkr.hw },490	{ .hw = &gpll6_out_main.clkr.hw },491};492 493static const struct parent_map gcc_parent_map_2[] = {494	{ P_BI_TCXO, 0 },495	{ P_GPLL0_OUT_EARLY, 1 },496	{ P_GPLL0_OUT_AUX2, 2 },497	{ P_SLEEP_CLK, 5 },498};499 500static const struct clk_parent_data gcc_parents_2[] = {501	{ .fw_name = "bi_tcxo" },502	{ .hw = &gpll0.clkr.hw },503	{ .hw = &gpll0_out_aux2.clkr.hw },504	{ .fw_name = "sleep_clk" },505};506 507static const struct parent_map gcc_parent_map_3[] = {508	{ P_BI_TCXO, 0 },509	{ P_GPLL0_OUT_EARLY, 1 },510	{ P_GPLL9_OUT_EARLY, 2 },511	{ P_GPLL10_OUT_MAIN, 3 },512	{ P_GPLL9_OUT_MAIN, 5 },513};514 515static const struct clk_parent_data gcc_parents_3[] = {516	{ .fw_name = "bi_tcxo" },517	{ .hw = &gpll0.clkr.hw },518	{ .hw = &gpll9.clkr.hw },519	{ .hw = &gpll10_out_main.clkr.hw },520	{ .hw = &gpll9_out_main.clkr.hw },521};522 523static const struct parent_map gcc_parent_map_4[] = {524	{ P_BI_TCXO, 0 },525	{ P_GPLL0_OUT_EARLY, 1 },526	{ P_GPLL0_OUT_AUX2, 2 },527	{ P_GPLL4_OUT_MAIN, 5 },528};529 530static const struct clk_parent_data gcc_parents_4[] = {531	{ .fw_name = "bi_tcxo" },532	{ .hw = &gpll0.clkr.hw },533	{ .hw = &gpll0_out_aux2.clkr.hw },534	{ .hw = &gpll4_out_main.clkr.hw },535};536 537static const struct parent_map gcc_parent_map_5[] = {538	{ P_BI_TCXO, 0 },539	{ P_GPLL0_OUT_EARLY, 1 },540	{ P_GPLL8_OUT_EARLY, 2 },541	{ P_GPLL10_OUT_MAIN, 3 },542	{ P_GPLL8_OUT_MAIN, 4 },543	{ P_GPLL9_OUT_MAIN, 5 },544};545 546static const struct clk_parent_data gcc_parents_5[] = {547	{ .fw_name = "bi_tcxo" },548	{ .hw = &gpll0.clkr.hw },549	{ .hw = &gpll8.clkr.hw },550	{ .hw = &gpll10_out_main.clkr.hw },551	{ .hw = &gpll8_out_main.clkr.hw },552	{ .hw = &gpll9_out_main.clkr.hw },553};554 555static const struct parent_map gcc_parent_map_6[] = {556	{ P_BI_TCXO, 0 },557	{ P_GPLL0_OUT_EARLY, 1 },558	{ P_GPLL8_OUT_EARLY, 2 },559	{ P_GPLL10_OUT_MAIN, 3 },560	{ P_GPLL6_OUT_MAIN, 4 },561	{ P_GPLL9_OUT_MAIN, 5 },562	{ P_GPLL3_OUT_EARLY, 6 },563};564 565static const struct clk_parent_data gcc_parents_6[] = {566	{ .fw_name = "bi_tcxo" },567	{ .hw = &gpll0.clkr.hw },568	{ .hw = &gpll8.clkr.hw },569	{ .hw = &gpll10_out_main.clkr.hw },570	{ .hw = &gpll6_out_main.clkr.hw },571	{ .hw = &gpll9_out_main.clkr.hw },572	{ .hw = &gpll3.clkr.hw },573};574 575static const struct parent_map gcc_parent_map_7[] = {576	{ P_BI_TCXO, 0 },577	{ P_GPLL0_OUT_EARLY, 1 },578	{ P_GPLL0_OUT_AUX2, 2 },579	{ P_GPLL10_OUT_MAIN, 3 },580	{ P_GPLL4_OUT_MAIN, 5 },581	{ P_GPLL3_OUT_EARLY, 6 },582};583 584static const struct clk_parent_data gcc_parents_7[] = {585	{ .fw_name = "bi_tcxo" },586	{ .hw = &gpll0.clkr.hw },587	{ .hw = &gpll0_out_aux2.clkr.hw },588	{ .hw = &gpll10_out_main.clkr.hw },589	{ .hw = &gpll4_out_main.clkr.hw },590	{ .hw = &gpll3.clkr.hw },591};592 593static const struct parent_map gcc_parent_map_8[] = {594	{ P_BI_TCXO, 0 },595	{ P_GPLL0_OUT_EARLY, 1 },596	{ P_GPLL8_OUT_EARLY, 2 },597	{ P_GPLL10_OUT_MAIN, 3 },598	{ P_GPLL8_OUT_MAIN, 4 },599	{ P_GPLL9_OUT_MAIN, 5 },600	{ P_GPLL3_OUT_EARLY, 6 },601};602 603static const struct clk_parent_data gcc_parents_8[] = {604	{ .fw_name = "bi_tcxo" },605	{ .hw = &gpll0.clkr.hw },606	{ .hw = &gpll8.clkr.hw },607	{ .hw = &gpll10_out_main.clkr.hw },608	{ .hw = &gpll8_out_main.clkr.hw },609	{ .hw = &gpll9_out_main.clkr.hw },610	{ .hw = &gpll3.clkr.hw },611};612 613static const struct parent_map gcc_parent_map_9[] = {614	{ P_BI_TCXO, 0 },615	{ P_GPLL0_OUT_EARLY, 1 },616	{ P_GPLL0_OUT_AUX2, 2 },617	{ P_GPLL10_OUT_MAIN, 3 },618	{ P_GPLL8_OUT_MAIN, 4 },619	{ P_GPLL9_OUT_MAIN, 5 },620	{ P_GPLL3_OUT_EARLY, 6 },621};622 623static const struct clk_parent_data gcc_parents_9[] = {624	{ .fw_name = "bi_tcxo" },625	{ .hw = &gpll0.clkr.hw },626	{ .hw = &gpll0_out_aux2.clkr.hw },627	{ .hw = &gpll10_out_main.clkr.hw },628	{ .hw = &gpll8_out_main.clkr.hw },629	{ .hw = &gpll9_out_main.clkr.hw },630	{ .hw = &gpll3.clkr.hw },631};632 633static const struct parent_map gcc_parent_map_10[] = {634	{ P_BI_TCXO, 0 },635	{ P_GPLL0_OUT_EARLY, 1 },636	{ P_GPLL8_OUT_EARLY, 2 },637	{ P_GPLL10_OUT_MAIN, 3 },638	{ P_GPLL6_OUT_EARLY, 4 },639	{ P_GPLL9_OUT_MAIN, 5 },640};641 642static const struct clk_parent_data gcc_parents_10[] = {643	{ .fw_name = "bi_tcxo" },644	{ .hw = &gpll0.clkr.hw },645	{ .hw = &gpll8.clkr.hw },646	{ .hw = &gpll10_out_main.clkr.hw },647	{ .hw = &gpll6.clkr.hw },648	{ .hw = &gpll9_out_main.clkr.hw },649};650 651static const struct parent_map gcc_parent_map_11[] = {652	{ P_BI_TCXO, 0 },653	{ P_GPLL0_OUT_EARLY, 1 },654	{ P_GPLL0_OUT_AUX2, 2 },655	{ P_GPLL7_OUT_MAIN, 3 },656	{ P_GPLL4_OUT_MAIN, 5 },657};658 659static const struct clk_parent_data gcc_parents_11[] = {660	{ .fw_name = "bi_tcxo" },661	{ .hw = &gpll0.clkr.hw },662	{ .hw = &gpll0_out_aux2.clkr.hw },663	{ .hw = &gpll7_out_main.clkr.hw },664	{ .hw = &gpll4_out_main.clkr.hw },665};666 667static const struct parent_map gcc_parent_map_12[] = {668	{ P_BI_TCXO, 0 },669	{ P_SLEEP_CLK, 5 },670};671 672static const struct clk_parent_data gcc_parents_12[] = {673	{ .fw_name = "bi_tcxo" },674	{ .fw_name = "sleep_clk" },675};676 677static const struct parent_map gcc_parent_map_13[] = {678	{ P_BI_TCXO, 0 },679	{ P_GPLL11_OUT_MAIN, 1 },680};681 682static const struct clk_parent_data gcc_parents_13[] = {683	{ .fw_name = "bi_tcxo" },684	{ .hw = &gpll11_out_main.clkr.hw },685};686 687static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {688	F(19200000, P_BI_TCXO, 1, 0, 0),689	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),690	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),691	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),692	{ }693};694 695static struct clk_rcg2 gcc_camss_axi_clk_src = {696	.cmd_rcgr = 0x5802c,697	.mnd_width = 0,698	.hid_width = 5,699	.parent_map = gcc_parent_map_7,700	.freq_tbl = ftbl_gcc_camss_axi_clk_src,701	.clkr.hw.init = &(struct clk_init_data){702		.name = "gcc_camss_axi_clk_src",703		.parent_data = gcc_parents_7,704		.num_parents = ARRAY_SIZE(gcc_parents_7),705		.flags = CLK_SET_RATE_PARENT,706		.ops = &clk_rcg2_shared_ops,707	},708};709 710static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {711	F(19200000, P_BI_TCXO, 1, 0, 0),712	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),713	{ }714};715 716static struct clk_rcg2 gcc_camss_cci_clk_src = {717	.cmd_rcgr = 0x56000,718	.mnd_width = 0,719	.hid_width = 5,720	.parent_map = gcc_parent_map_9,721	.freq_tbl = ftbl_gcc_camss_cci_clk_src,722	.clkr.hw.init = &(struct clk_init_data){723		.name = "gcc_camss_cci_clk_src",724		.parent_data = gcc_parents_9,725		.num_parents = ARRAY_SIZE(gcc_parents_9),726		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,727		.ops = &clk_rcg2_shared_ops,728	},729};730 731static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {732	F(19200000, P_BI_TCXO, 1, 0, 0),733	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),734	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),735	F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),736	{ }737};738 739static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {740	.cmd_rcgr = 0x59000,741	.mnd_width = 0,742	.hid_width = 5,743	.parent_map = gcc_parent_map_4,744	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,745	.clkr.hw.init = &(struct clk_init_data){746		.name = "gcc_camss_csi0phytimer_clk_src",747		.parent_data = gcc_parents_4,748		.num_parents = ARRAY_SIZE(gcc_parents_4),749		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,750		.ops = &clk_rcg2_shared_ops,751	},752};753 754static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {755	.cmd_rcgr = 0x5901c,756	.mnd_width = 0,757	.hid_width = 5,758	.parent_map = gcc_parent_map_4,759	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,760	.clkr.hw.init = &(struct clk_init_data){761		.name = "gcc_camss_csi1phytimer_clk_src",762		.parent_data = gcc_parents_4,763		.num_parents = ARRAY_SIZE(gcc_parents_4),764		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,765		.ops = &clk_rcg2_shared_ops,766	},767};768 769static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {770	.cmd_rcgr = 0x59038,771	.mnd_width = 0,772	.hid_width = 5,773	.parent_map = gcc_parent_map_4,774	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,775	.clkr.hw.init = &(struct clk_init_data){776		.name = "gcc_camss_csi2phytimer_clk_src",777		.parent_data = gcc_parents_4,778		.num_parents = ARRAY_SIZE(gcc_parents_4),779		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,780		.ops = &clk_rcg2_shared_ops,781	},782};783 784static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {785	F(19200000, P_BI_TCXO, 1, 0, 0),786	F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),787	F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),788	{ }789};790 791static struct clk_rcg2 gcc_camss_mclk0_clk_src = {792	.cmd_rcgr = 0x51000,793	.mnd_width = 8,794	.hid_width = 5,795	.parent_map = gcc_parent_map_3,796	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,797	.clkr.hw.init = &(struct clk_init_data){798		.name = "gcc_camss_mclk0_clk_src",799		.parent_data = gcc_parents_3,800		.num_parents = ARRAY_SIZE(gcc_parents_3),801		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,802		.ops = &clk_rcg2_shared_ops,803	},804};805 806static struct clk_rcg2 gcc_camss_mclk1_clk_src = {807	.cmd_rcgr = 0x5101c,808	.mnd_width = 8,809	.hid_width = 5,810	.parent_map = gcc_parent_map_3,811	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,812	.clkr.hw.init = &(struct clk_init_data){813		.name = "gcc_camss_mclk1_clk_src",814		.parent_data = gcc_parents_3,815		.num_parents = ARRAY_SIZE(gcc_parents_3),816		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,817		.ops = &clk_rcg2_shared_ops,818	},819};820 821static struct clk_rcg2 gcc_camss_mclk2_clk_src = {822	.cmd_rcgr = 0x51038,823	.mnd_width = 8,824	.hid_width = 5,825	.parent_map = gcc_parent_map_3,826	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,827	.clkr.hw.init = &(struct clk_init_data){828		.name = "gcc_camss_mclk2_clk_src",829		.parent_data = gcc_parents_3,830		.num_parents = ARRAY_SIZE(gcc_parents_3),831		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,832		.ops = &clk_rcg2_shared_ops,833	},834};835 836static struct clk_rcg2 gcc_camss_mclk3_clk_src = {837	.cmd_rcgr = 0x51054,838	.mnd_width = 8,839	.hid_width = 5,840	.parent_map = gcc_parent_map_3,841	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,842	.clkr.hw.init = &(struct clk_init_data){843		.name = "gcc_camss_mclk3_clk_src",844		.parent_data = gcc_parents_3,845		.num_parents = ARRAY_SIZE(gcc_parents_3),846		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,847		.ops = &clk_rcg2_shared_ops,848	},849};850 851static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {852	F(19200000, P_BI_TCXO, 1, 0, 0),853	F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),854	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),855	{ }856};857 858static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {859	.cmd_rcgr = 0x55024,860	.mnd_width = 0,861	.hid_width = 5,862	.parent_map = gcc_parent_map_8,863	.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,864	.clkr.hw.init = &(struct clk_init_data){865		.name = "gcc_camss_ope_ahb_clk_src",866		.parent_data = gcc_parents_8,867		.num_parents = ARRAY_SIZE(gcc_parents_8),868		.flags = CLK_SET_RATE_PARENT,869		.ops = &clk_rcg2_shared_ops,870	},871};872 873static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {874	F(19200000, P_BI_TCXO, 1, 0, 0),875	F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),876	F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),877	F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),878	F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),879	{ }880};881 882static struct clk_rcg2 gcc_camss_ope_clk_src = {883	.cmd_rcgr = 0x55004,884	.mnd_width = 0,885	.hid_width = 5,886	.parent_map = gcc_parent_map_8,887	.freq_tbl = ftbl_gcc_camss_ope_clk_src,888	.clkr.hw.init = &(struct clk_init_data){889		.name = "gcc_camss_ope_clk_src",890		.parent_data = gcc_parents_8,891		.num_parents = ARRAY_SIZE(gcc_parents_8),892		.flags = CLK_SET_RATE_PARENT,893		.ops = &clk_rcg2_shared_ops,894	},895};896 897static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {898	F(19200000, P_BI_TCXO, 1, 0, 0),899	F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),900	F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),901	F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),902	F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),903	F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),904	F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),905	F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),906	F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),907	F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),908	F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),909	F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),910	F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),911	F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),912	F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),913	F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),914	{ }915};916 917static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {918	.cmd_rcgr = 0x52004,919	.mnd_width = 8,920	.hid_width = 5,921	.parent_map = gcc_parent_map_5,922	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,923	.clkr.hw.init = &(struct clk_init_data){924		.name = "gcc_camss_tfe_0_clk_src",925		.parent_data = gcc_parents_5,926		.num_parents = ARRAY_SIZE(gcc_parents_5),927		.flags = CLK_SET_RATE_PARENT,928		.ops = &clk_rcg2_shared_ops,929	},930};931 932static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {933	F(19200000, P_BI_TCXO, 1, 0, 0),934	F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),935	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),936	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),937	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),938	F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),939	{ }940};941 942static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {943	.cmd_rcgr = 0x52094,944	.mnd_width = 0,945	.hid_width = 5,946	.parent_map = gcc_parent_map_6,947	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,948	.clkr.hw.init = &(struct clk_init_data){949		.name = "gcc_camss_tfe_0_csid_clk_src",950		.parent_data = gcc_parents_6,951		.num_parents = ARRAY_SIZE(gcc_parents_6),952		.flags = CLK_SET_RATE_PARENT,953		.ops = &clk_rcg2_shared_ops,954	},955};956 957static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {958	.cmd_rcgr = 0x52024,959	.mnd_width = 8,960	.hid_width = 5,961	.parent_map = gcc_parent_map_5,962	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,963	.clkr.hw.init = &(struct clk_init_data){964		.name = "gcc_camss_tfe_1_clk_src",965		.parent_data = gcc_parents_5,966		.num_parents = ARRAY_SIZE(gcc_parents_5),967		.flags = CLK_SET_RATE_PARENT,968		.ops = &clk_rcg2_shared_ops,969	},970};971 972static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {973	.cmd_rcgr = 0x520b4,974	.mnd_width = 0,975	.hid_width = 5,976	.parent_map = gcc_parent_map_6,977	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,978	.clkr.hw.init = &(struct clk_init_data){979		.name = "gcc_camss_tfe_1_csid_clk_src",980		.parent_data = gcc_parents_6,981		.num_parents = ARRAY_SIZE(gcc_parents_6),982		.flags = CLK_SET_RATE_PARENT,983		.ops = &clk_rcg2_shared_ops,984	},985};986 987static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {988	.cmd_rcgr = 0x52044,989	.mnd_width = 8,990	.hid_width = 5,991	.parent_map = gcc_parent_map_5,992	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,993	.clkr.hw.init = &(struct clk_init_data){994		.name = "gcc_camss_tfe_2_clk_src",995		.parent_data = gcc_parents_5,996		.num_parents = ARRAY_SIZE(gcc_parents_5),997		.flags = CLK_SET_RATE_PARENT,998		.ops = &clk_rcg2_shared_ops,999	},1000};1001 1002static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {1003	.cmd_rcgr = 0x520d4,1004	.mnd_width = 0,1005	.hid_width = 5,1006	.parent_map = gcc_parent_map_6,1007	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,1008	.clkr.hw.init = &(struct clk_init_data){1009		.name = "gcc_camss_tfe_2_csid_clk_src",1010		.parent_data = gcc_parents_6,1011		.num_parents = ARRAY_SIZE(gcc_parents_6),1012		.flags = CLK_SET_RATE_PARENT,1013		.ops = &clk_rcg2_shared_ops,1014	},1015};1016 1017static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {1018	F(19200000, P_BI_TCXO, 1, 0, 0),1019	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),1020	F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),1021	F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),1022	{ }1023};1024 1025static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {1026	.cmd_rcgr = 0x52064,1027	.mnd_width = 16,1028	.hid_width = 5,1029	.parent_map = gcc_parent_map_10,1030	.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,1031	.clkr.hw.init = &(struct clk_init_data){1032		.name = "gcc_camss_tfe_cphy_rx_clk_src",1033		.parent_data = gcc_parents_10,1034		.num_parents = ARRAY_SIZE(gcc_parents_10),1035		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,1036		.ops = &clk_rcg2_shared_ops,1037	},1038};1039 1040static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {1041	F(19200000, P_BI_TCXO, 1, 0, 0),1042	F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),1043	F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),1044	{ }1045};1046 1047static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {1048	.cmd_rcgr = 0x58010,1049	.mnd_width = 0,1050	.hid_width = 5,1051	.parent_map = gcc_parent_map_7,1052	.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,1053	.clkr.hw.init = &(struct clk_init_data){1054		.name = "gcc_camss_top_ahb_clk_src",1055		.parent_data = gcc_parents_7,1056		.num_parents = ARRAY_SIZE(gcc_parents_7),1057		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,1058		.ops = &clk_rcg2_shared_ops,1059	},1060};1061 1062static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {1063	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),1064	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),1065	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1066	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),1067	{ }1068};1069 1070static struct clk_rcg2 gcc_gp1_clk_src = {1071	.cmd_rcgr = 0x4d004,1072	.mnd_width = 8,1073	.hid_width = 5,1074	.parent_map = gcc_parent_map_2,1075	.freq_tbl = ftbl_gcc_gp1_clk_src,1076	.clkr.hw.init = &(struct clk_init_data){1077		.name = "gcc_gp1_clk_src",1078		.parent_data = gcc_parents_2,1079		.num_parents = ARRAY_SIZE(gcc_parents_2),1080		.ops = &clk_rcg2_ops,1081	},1082};1083 1084static struct clk_rcg2 gcc_gp2_clk_src = {1085	.cmd_rcgr = 0x4e004,1086	.mnd_width = 8,1087	.hid_width = 5,1088	.parent_map = gcc_parent_map_2,1089	.freq_tbl = ftbl_gcc_gp1_clk_src,1090	.clkr.hw.init = &(struct clk_init_data){1091		.name = "gcc_gp2_clk_src",1092		.parent_data = gcc_parents_2,1093		.num_parents = ARRAY_SIZE(gcc_parents_2),1094		.ops = &clk_rcg2_ops,1095	},1096};1097 1098static struct clk_rcg2 gcc_gp3_clk_src = {1099	.cmd_rcgr = 0x4f004,1100	.mnd_width = 8,1101	.hid_width = 5,1102	.parent_map = gcc_parent_map_2,1103	.freq_tbl = ftbl_gcc_gp1_clk_src,1104	.clkr.hw.init = &(struct clk_init_data){1105		.name = "gcc_gp3_clk_src",1106		.parent_data = gcc_parents_2,1107		.num_parents = ARRAY_SIZE(gcc_parents_2),1108		.ops = &clk_rcg2_ops,1109	},1110};1111 1112static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {1113	F(19200000, P_BI_TCXO, 1, 0, 0),1114	F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),1115	{ }1116};1117 1118static struct clk_rcg2 gcc_pdm2_clk_src = {1119	.cmd_rcgr = 0x20010,1120	.mnd_width = 0,1121	.hid_width = 5,1122	.parent_map = gcc_parent_map_0,1123	.freq_tbl = ftbl_gcc_pdm2_clk_src,1124	.clkr.hw.init = &(struct clk_init_data){1125		.name = "gcc_pdm2_clk_src",1126		.parent_data = gcc_parents_0,1127		.num_parents = ARRAY_SIZE(gcc_parents_0),1128		.ops = &clk_rcg2_shared_ops,1129	},1130};1131 1132static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {1133	F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),1134	F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),1135	F(19200000, P_BI_TCXO, 1, 0, 0),1136	F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),1137	F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),1138	F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),1139	F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),1140	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),1141	F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),1142	F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),1143	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1144	F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),1145	F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),1146	F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),1147	F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),1148	F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),1149	{ }1150};1151 1152static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {1153	.name = "gcc_qupv3_wrap0_s0_clk_src",1154	.parent_data = gcc_parents_1,1155	.num_parents = ARRAY_SIZE(gcc_parents_1),1156	.ops = &clk_rcg2_ops,1157};1158 1159static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {1160	.cmd_rcgr = 0x1f148,1161	.mnd_width = 16,1162	.hid_width = 5,1163	.parent_map = gcc_parent_map_1,1164	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1165	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,1166};1167 1168static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {1169	.name = "gcc_qupv3_wrap0_s1_clk_src",1170	.parent_data = gcc_parents_1,1171	.num_parents = ARRAY_SIZE(gcc_parents_1),1172	.ops = &clk_rcg2_ops,1173};1174 1175static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {1176	.cmd_rcgr = 0x1f278,1177	.mnd_width = 16,1178	.hid_width = 5,1179	.parent_map = gcc_parent_map_1,1180	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1181	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,1182};1183 1184static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {1185	.name = "gcc_qupv3_wrap0_s2_clk_src",1186	.parent_data = gcc_parents_1,1187	.num_parents = ARRAY_SIZE(gcc_parents_1),1188	.ops = &clk_rcg2_ops,1189};1190 1191static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {1192	.cmd_rcgr = 0x1f3a8,1193	.mnd_width = 16,1194	.hid_width = 5,1195	.parent_map = gcc_parent_map_1,1196	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1197	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,1198};1199 1200static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {1201	.name = "gcc_qupv3_wrap0_s3_clk_src",1202	.parent_data = gcc_parents_1,1203	.num_parents = ARRAY_SIZE(gcc_parents_1),1204	.ops = &clk_rcg2_ops,1205};1206 1207static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {1208	.cmd_rcgr = 0x1f4d8,1209	.mnd_width = 16,1210	.hid_width = 5,1211	.parent_map = gcc_parent_map_1,1212	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1213	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,1214};1215 1216static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {1217	.name = "gcc_qupv3_wrap0_s4_clk_src",1218	.parent_data = gcc_parents_1,1219	.num_parents = ARRAY_SIZE(gcc_parents_1),1220	.ops = &clk_rcg2_ops,1221};1222 1223static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {1224	.cmd_rcgr = 0x1f608,1225	.mnd_width = 16,1226	.hid_width = 5,1227	.parent_map = gcc_parent_map_1,1228	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1229	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,1230};1231 1232static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {1233	.name = "gcc_qupv3_wrap0_s5_clk_src",1234	.parent_data = gcc_parents_1,1235	.num_parents = ARRAY_SIZE(gcc_parents_1),1236	.ops = &clk_rcg2_ops,1237};1238 1239static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {1240	.cmd_rcgr = 0x1f738,1241	.mnd_width = 16,1242	.hid_width = 5,1243	.parent_map = gcc_parent_map_1,1244	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,1245	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,1246};1247 1248static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {1249	F(144000, P_BI_TCXO, 16, 3, 25),1250	F(400000, P_BI_TCXO, 12, 1, 4),1251	F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),1252	F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),1253	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),1254	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1255	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),1256	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),1257	{ }1258};1259 1260static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {1261	.cmd_rcgr = 0x38028,1262	.mnd_width = 8,1263	.hid_width = 5,1264	.parent_map = gcc_parent_map_1,1265	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,1266	.clkr.hw.init = &(struct clk_init_data){1267		.name = "gcc_sdcc1_apps_clk_src",1268		.parent_data = gcc_parents_1,1269		.num_parents = ARRAY_SIZE(gcc_parents_1),1270		.ops = &clk_rcg2_floor_ops,1271	},1272};1273 1274static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {1275	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),1276	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1277	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),1278	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),1279	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),1280	{ }1281};1282 1283static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {1284	.cmd_rcgr = 0x38010,1285	.mnd_width = 0,1286	.hid_width = 5,1287	.parent_map = gcc_parent_map_0,1288	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,1289	.clkr.hw.init = &(struct clk_init_data){1290		.name = "gcc_sdcc1_ice_core_clk_src",1291		.parent_data = gcc_parents_0,1292		.num_parents = ARRAY_SIZE(gcc_parents_0),1293		.ops = &clk_rcg2_ops,1294	},1295};1296 1297static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {1298	F(400000, P_BI_TCXO, 12, 1, 4),1299	F(19200000, P_BI_TCXO, 1, 0, 0),1300	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),1301	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),1302	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1303	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),1304	{ }1305};1306 1307static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {1308	.cmd_rcgr = 0x1e00c,1309	.mnd_width = 8,1310	.hid_width = 5,1311	.parent_map = gcc_parent_map_11,1312	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,1313	.clkr.hw.init = &(struct clk_init_data){1314		.name = "gcc_sdcc2_apps_clk_src",1315		.parent_data = gcc_parents_11,1316		.num_parents = ARRAY_SIZE(gcc_parents_11),1317		.ops = &clk_rcg2_floor_ops,1318		.flags = CLK_OPS_PARENT_ENABLE,1319	},1320};1321 1322static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {1323	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),1324	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),1325	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),1326	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),1327	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),1328	{ }1329};1330 1331static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {1332	.cmd_rcgr = 0x45020,1333	.mnd_width = 8,1334	.hid_width = 5,1335	.parent_map = gcc_parent_map_0,1336	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,1337	.clkr.hw.init = &(struct clk_init_data){1338		.name = "gcc_ufs_phy_axi_clk_src",1339		.parent_data = gcc_parents_0,1340		.num_parents = ARRAY_SIZE(gcc_parents_0),1341		.ops = &clk_rcg2_shared_ops,1342	},1343};1344 1345static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {1346	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),1347	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),1348	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),1349	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),1350	{ }1351};1352 1353static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {1354	.cmd_rcgr = 0x45048,1355	.mnd_width = 0,1356	.hid_width = 5,1357	.parent_map = gcc_parent_map_0,1358	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,1359	.clkr.hw.init = &(struct clk_init_data){1360		.name = "gcc_ufs_phy_ice_core_clk_src",1361		.parent_data = gcc_parents_0,1362		.num_parents = ARRAY_SIZE(gcc_parents_0),1363		.ops = &clk_rcg2_shared_ops,1364	},1365};1366 1367static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {1368	F(9600000, P_BI_TCXO, 2, 0, 0),1369	F(19200000, P_BI_TCXO, 1, 0, 0),1370	{ }1371};1372 1373static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {1374	.cmd_rcgr = 0x4507c,1375	.mnd_width = 0,1376	.hid_width = 5,1377	.parent_map = gcc_parent_map_0,1378	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,1379	.clkr.hw.init = &(struct clk_init_data){1380		.name = "gcc_ufs_phy_phy_aux_clk_src",1381		.parent_data = gcc_parents_0,1382		.num_parents = ARRAY_SIZE(gcc_parents_0),1383		.ops = &clk_rcg2_ops,1384	},1385};1386 1387static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {1388	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),1389	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),1390	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),1391	{ }1392};1393 1394static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {1395	.cmd_rcgr = 0x45060,1396	.mnd_width = 0,1397	.hid_width = 5,1398	.parent_map = gcc_parent_map_0,1399	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,1400	.clkr.hw.init = &(struct clk_init_data){1401		.name = "gcc_ufs_phy_unipro_core_clk_src",1402		.parent_data = gcc_parents_0,1403		.num_parents = ARRAY_SIZE(gcc_parents_0),1404		.ops = &clk_rcg2_shared_ops,1405	},1406};1407 1408static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {1409	F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),1410	F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),1411	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),1412	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),1413	{ }1414};1415 1416static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {1417	.cmd_rcgr = 0x1a01c,1418	.mnd_width = 8,1419	.hid_width = 5,1420	.parent_map = gcc_parent_map_0,1421	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,1422	.clkr.hw.init = &(struct clk_init_data){1423		.name = "gcc_usb30_prim_master_clk_src",1424		.parent_data = gcc_parents_0,1425		.num_parents = ARRAY_SIZE(gcc_parents_0),1426		.ops = &clk_rcg2_shared_ops,1427	},1428};1429 1430static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {1431	F(19200000, P_BI_TCXO, 1, 0, 0),1432	{ }1433};1434 1435static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {1436	.cmd_rcgr = 0x1a034,1437	.mnd_width = 0,1438	.hid_width = 5,1439	.parent_map = gcc_parent_map_0,1440	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,1441	.clkr.hw.init = &(struct clk_init_data){1442		.name = "gcc_usb30_prim_mock_utmi_clk_src",1443		.parent_data = gcc_parents_0,1444		.num_parents = ARRAY_SIZE(gcc_parents_0),1445		.ops = &clk_rcg2_ops,1446	},1447};1448 1449static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {1450	.reg = 0x1a04c,1451	.shift = 0,1452	.width = 2,1453	.clkr.hw.init = &(struct clk_init_data) {1454		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",1455		.parent_hws = (const struct clk_hw *[]) {1456			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },1457		.num_parents = 1,1458		.ops = &clk_regmap_div_ro_ops,1459	},1460};1461 1462static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {1463	.cmd_rcgr = 0x1a060,1464	.mnd_width = 0,1465	.hid_width = 5,1466	.parent_map = gcc_parent_map_12,1467	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,1468	.clkr.hw.init = &(struct clk_init_data){1469		.name = "gcc_usb3_prim_phy_aux_clk_src",1470		.parent_data = gcc_parents_12,1471		.num_parents = ARRAY_SIZE(gcc_parents_12),1472		.ops = &clk_rcg2_ops,1473	},1474};1475 1476static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {1477	F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),1478	F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),1479	F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),1480	F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),1481	{ }1482};1483 1484static struct clk_rcg2 gcc_video_venus_clk_src = {1485	.cmd_rcgr = 0x58060,1486	.mnd_width = 0,1487	.hid_width = 5,1488	.parent_map = gcc_parent_map_13,1489	.freq_tbl = ftbl_gcc_video_venus_clk_src,1490	.clkr.hw.init = &(struct clk_init_data){1491		.name = "gcc_video_venus_clk_src",1492		.parent_data = gcc_parents_13,1493		.num_parents = ARRAY_SIZE(gcc_parents_13),1494		.flags = CLK_SET_RATE_PARENT,1495		.ops = &clk_rcg2_shared_ops,1496	},1497};1498 1499static struct clk_branch gcc_ahb2phy_csi_clk = {1500	.halt_reg = 0x1d004,1501	.halt_check = BRANCH_HALT,1502	.hwcg_reg = 0x1d004,1503	.hwcg_bit = 1,1504	.clkr = {1505		.enable_reg = 0x1d004,1506		.enable_mask = BIT(0),1507		.hw.init = &(struct clk_init_data){1508			.name = "gcc_ahb2phy_csi_clk",1509			.ops = &clk_branch2_ops,1510		},1511	},1512};1513 1514static struct clk_branch gcc_ahb2phy_usb_clk = {1515	.halt_reg = 0x1d008,1516	.halt_check = BRANCH_HALT,1517	.hwcg_reg = 0x1d008,1518	.hwcg_bit = 1,1519	.clkr = {1520		.enable_reg = 0x1d008,1521		.enable_mask = BIT(0),1522		.hw.init = &(struct clk_init_data){1523			.name = "gcc_ahb2phy_usb_clk",1524			.ops = &clk_branch2_ops,1525		},1526	},1527};1528 1529static struct clk_branch gcc_bimc_gpu_axi_clk = {1530	.halt_reg = 0x71154,1531	.halt_check = BRANCH_HALT_DELAY,1532	.hwcg_reg = 0x71154,1533	.hwcg_bit = 1,1534	.clkr = {1535		.enable_reg = 0x71154,1536		.enable_mask = BIT(0),1537		.hw.init = &(struct clk_init_data){1538			.name = "gcc_bimc_gpu_axi_clk",1539			.ops = &clk_branch2_ops,1540		},1541	},1542};1543 1544static struct clk_branch gcc_boot_rom_ahb_clk = {1545	.halt_reg = 0x23004,1546	.halt_check = BRANCH_HALT_VOTED,1547	.hwcg_reg = 0x23004,1548	.hwcg_bit = 1,1549	.clkr = {1550		.enable_reg = 0x79004,1551		.enable_mask = BIT(10),1552		.hw.init = &(struct clk_init_data){1553			.name = "gcc_boot_rom_ahb_clk",1554			.ops = &clk_branch2_ops,1555		},1556	},1557};1558 1559static struct clk_branch gcc_cam_throttle_nrt_clk = {1560	.halt_reg = 0x17070,1561	.halt_check = BRANCH_HALT_VOTED,1562	.hwcg_reg = 0x17070,1563	.hwcg_bit = 1,1564	.clkr = {1565		.enable_reg = 0x79004,1566		.enable_mask = BIT(27),1567		.hw.init = &(struct clk_init_data){1568			.name = "gcc_cam_throttle_nrt_clk",1569			.ops = &clk_branch2_ops,1570		},1571	},1572};1573 1574static struct clk_branch gcc_cam_throttle_rt_clk = {1575	.halt_reg = 0x1706c,1576	.halt_check = BRANCH_HALT_VOTED,1577	.hwcg_reg = 0x1706c,1578	.hwcg_bit = 1,1579	.clkr = {1580		.enable_reg = 0x79004,1581		.enable_mask = BIT(26),1582		.hw.init = &(struct clk_init_data){1583			.name = "gcc_cam_throttle_rt_clk",1584			.ops = &clk_branch2_ops,1585		},1586	},1587};1588 1589static struct clk_branch gcc_camera_ahb_clk = {1590	.halt_reg = 0x17008,1591	.halt_check = BRANCH_HALT_DELAY,1592	.hwcg_reg = 0x17008,1593	.hwcg_bit = 1,1594	.clkr = {1595		.enable_reg = 0x17008,1596		.enable_mask = BIT(0),1597		.hw.init = &(struct clk_init_data){1598			.name = "gcc_camera_ahb_clk",1599			.flags = CLK_IS_CRITICAL,1600			.ops = &clk_branch2_ops,1601		},1602	},1603};1604 1605static struct clk_branch gcc_camera_xo_clk = {1606	.halt_reg = 0x17028,1607	.halt_check = BRANCH_HALT,1608	.clkr = {1609		.enable_reg = 0x17028,1610		.enable_mask = BIT(0),1611		.hw.init = &(struct clk_init_data){1612			.name = "gcc_camera_xo_clk",1613			.flags = CLK_IS_CRITICAL,1614			.ops = &clk_branch2_ops,1615		},1616	},1617};1618 1619static struct clk_branch gcc_camss_axi_clk = {1620	.halt_reg = 0x58044,1621	.halt_check = BRANCH_HALT,1622	.clkr = {1623		.enable_reg = 0x58044,1624		.enable_mask = BIT(0),1625		.hw.init = &(struct clk_init_data){1626			.name = "gcc_camss_axi_clk",1627			.parent_hws = (const struct clk_hw *[]){1628				&gcc_camss_axi_clk_src.clkr.hw,1629			},1630			.num_parents = 1,1631			.flags = CLK_SET_RATE_PARENT,1632			.ops = &clk_branch2_ops,1633		},1634	},1635};1636 1637static struct clk_branch gcc_camss_camnoc_atb_clk = {1638	.halt_reg = 0x5804c,1639	.halt_check = BRANCH_HALT_DELAY,1640	.hwcg_reg = 0x5804c,1641	.hwcg_bit = 1,1642	.clkr = {1643		.enable_reg = 0x5804c,1644		.enable_mask = BIT(0),1645		.hw.init = &(struct clk_init_data){1646			.name = "gcc_camss_camnoc_atb_clk",1647			.ops = &clk_branch2_ops,1648		},1649	},1650};1651 1652static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {1653	.halt_reg = 0x58050,1654	.halt_check = BRANCH_HALT_DELAY,1655	.hwcg_reg = 0x58050,1656	.hwcg_bit = 1,1657	.clkr = {1658		.enable_reg = 0x58050,1659		.enable_mask = BIT(0),1660		.hw.init = &(struct clk_init_data){1661			.name = "gcc_camss_camnoc_nts_xo_clk",1662			.ops = &clk_branch2_ops,1663		},1664	},1665};1666 1667static struct clk_branch gcc_camss_cci_0_clk = {1668	.halt_reg = 0x56018,1669	.halt_check = BRANCH_HALT,1670	.clkr = {1671		.enable_reg = 0x56018,1672		.enable_mask = BIT(0),1673		.hw.init = &(struct clk_init_data){1674			.name = "gcc_camss_cci_0_clk",1675			.parent_hws = (const struct clk_hw *[]){1676				&gcc_camss_cci_clk_src.clkr.hw,1677			},1678			.num_parents = 1,1679			.flags = CLK_SET_RATE_PARENT,1680			.ops = &clk_branch2_ops,1681		},1682	},1683};1684 1685static struct clk_branch gcc_camss_cphy_0_clk = {1686	.halt_reg = 0x52088,1687	.halt_check = BRANCH_HALT,1688	.clkr = {1689		.enable_reg = 0x52088,1690		.enable_mask = BIT(0),1691		.hw.init = &(struct clk_init_data){1692			.name = "gcc_camss_cphy_0_clk",1693			.parent_hws = (const struct clk_hw *[]){1694				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,1695			},1696			.num_parents = 1,1697			.flags = CLK_SET_RATE_PARENT,1698			.ops = &clk_branch2_ops,1699		},1700	},1701};1702 1703static struct clk_branch gcc_camss_cphy_1_clk = {1704	.halt_reg = 0x5208c,1705	.halt_check = BRANCH_HALT,1706	.clkr = {1707		.enable_reg = 0x5208c,1708		.enable_mask = BIT(0),1709		.hw.init = &(struct clk_init_data){1710			.name = "gcc_camss_cphy_1_clk",1711			.parent_hws = (const struct clk_hw *[]){1712				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,1713			},1714			.num_parents = 1,1715			.flags = CLK_SET_RATE_PARENT,1716			.ops = &clk_branch2_ops,1717		},1718	},1719};1720 1721static struct clk_branch gcc_camss_cphy_2_clk = {1722	.halt_reg = 0x52090,1723	.halt_check = BRANCH_HALT,1724	.clkr = {1725		.enable_reg = 0x52090,1726		.enable_mask = BIT(0),1727		.hw.init = &(struct clk_init_data){1728			.name = "gcc_camss_cphy_2_clk",1729			.parent_hws = (const struct clk_hw *[]){1730				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,1731			},1732			.num_parents = 1,1733			.flags = CLK_SET_RATE_PARENT,1734			.ops = &clk_branch2_ops,1735		},1736	},1737};1738 1739static struct clk_branch gcc_camss_csi0phytimer_clk = {1740	.halt_reg = 0x59018,1741	.halt_check = BRANCH_HALT,1742	.clkr = {1743		.enable_reg = 0x59018,1744		.enable_mask = BIT(0),1745		.hw.init = &(struct clk_init_data){1746			.name = "gcc_camss_csi0phytimer_clk",1747			.parent_hws = (const struct clk_hw *[]){1748				&gcc_camss_csi0phytimer_clk_src.clkr.hw,1749			},1750			.num_parents = 1,1751			.flags = CLK_SET_RATE_PARENT,1752			.ops = &clk_branch2_ops,1753		},1754	},1755};1756 1757static struct clk_branch gcc_camss_csi1phytimer_clk = {1758	.halt_reg = 0x59034,1759	.halt_check = BRANCH_HALT,1760	.clkr = {1761		.enable_reg = 0x59034,1762		.enable_mask = BIT(0),1763		.hw.init = &(struct clk_init_data){1764			.name = "gcc_camss_csi1phytimer_clk",1765			.parent_hws = (const struct clk_hw *[]){1766				&gcc_camss_csi1phytimer_clk_src.clkr.hw,1767			},1768			.num_parents = 1,1769			.flags = CLK_SET_RATE_PARENT,1770			.ops = &clk_branch2_ops,1771		},1772	},1773};1774 1775static struct clk_branch gcc_camss_csi2phytimer_clk = {1776	.halt_reg = 0x59050,1777	.halt_check = BRANCH_HALT,1778	.clkr = {1779		.enable_reg = 0x59050,1780		.enable_mask = BIT(0),1781		.hw.init = &(struct clk_init_data){1782			.name = "gcc_camss_csi2phytimer_clk",1783			.parent_hws = (const struct clk_hw *[]){1784				&gcc_camss_csi2phytimer_clk_src.clkr.hw,1785			},1786			.num_parents = 1,1787			.flags = CLK_SET_RATE_PARENT,1788			.ops = &clk_branch2_ops,1789		},1790	},1791};1792 1793static struct clk_branch gcc_camss_mclk0_clk = {1794	.halt_reg = 0x51018,1795	.halt_check = BRANCH_HALT,1796	.clkr = {1797		.enable_reg = 0x51018,1798		.enable_mask = BIT(0),1799		.hw.init = &(struct clk_init_data){1800			.name = "gcc_camss_mclk0_clk",1801			.parent_hws = (const struct clk_hw *[]){1802				&gcc_camss_mclk0_clk_src.clkr.hw,1803			},1804			.num_parents = 1,1805			.flags = CLK_SET_RATE_PARENT,1806			.ops = &clk_branch2_ops,1807		},1808	},1809};1810 1811static struct clk_branch gcc_camss_mclk1_clk = {1812	.halt_reg = 0x51034,1813	.halt_check = BRANCH_HALT,1814	.clkr = {1815		.enable_reg = 0x51034,1816		.enable_mask = BIT(0),1817		.hw.init = &(struct clk_init_data){1818			.name = "gcc_camss_mclk1_clk",1819			.parent_hws = (const struct clk_hw *[]){1820				&gcc_camss_mclk1_clk_src.clkr.hw,1821			},1822			.num_parents = 1,1823			.flags = CLK_SET_RATE_PARENT,1824			.ops = &clk_branch2_ops,1825		},1826	},1827};1828 1829static struct clk_branch gcc_camss_mclk2_clk = {1830	.halt_reg = 0x51050,1831	.halt_check = BRANCH_HALT,1832	.clkr = {1833		.enable_reg = 0x51050,1834		.enable_mask = BIT(0),1835		.hw.init = &(struct clk_init_data){1836			.name = "gcc_camss_mclk2_clk",1837			.parent_hws = (const struct clk_hw *[]){1838				&gcc_camss_mclk2_clk_src.clkr.hw,1839			},1840			.num_parents = 1,1841			.flags = CLK_SET_RATE_PARENT,1842			.ops = &clk_branch2_ops,1843		},1844	},1845};1846 1847static struct clk_branch gcc_camss_mclk3_clk = {1848	.halt_reg = 0x5106c,1849	.halt_check = BRANCH_HALT,1850	.clkr = {1851		.enable_reg = 0x5106c,1852		.enable_mask = BIT(0),1853		.hw.init = &(struct clk_init_data){1854			.name = "gcc_camss_mclk3_clk",1855			.parent_hws = (const struct clk_hw *[]){1856				&gcc_camss_mclk3_clk_src.clkr.hw,1857			},1858			.num_parents = 1,1859			.flags = CLK_SET_RATE_PARENT,1860			.ops = &clk_branch2_ops,1861		},1862	},1863};1864 1865static struct clk_branch gcc_camss_nrt_axi_clk = {1866	.halt_reg = 0x58054,1867	.halt_check = BRANCH_HALT,1868	.clkr = {1869		.enable_reg = 0x58054,1870		.enable_mask = BIT(0),1871		.hw.init = &(struct clk_init_data){1872			.name = "gcc_camss_nrt_axi_clk",1873			.ops = &clk_branch2_ops,1874		},1875	},1876};1877 1878static struct clk_branch gcc_camss_ope_ahb_clk = {1879	.halt_reg = 0x5503c,1880	.halt_check = BRANCH_HALT,1881	.clkr = {1882		.enable_reg = 0x5503c,1883		.enable_mask = BIT(0),1884		.hw.init = &(struct clk_init_data){1885			.name = "gcc_camss_ope_ahb_clk",1886			.parent_hws = (const struct clk_hw *[]){1887				&gcc_camss_ope_ahb_clk_src.clkr.hw,1888			},1889			.num_parents = 1,1890			.flags = CLK_SET_RATE_PARENT,1891			.ops = &clk_branch2_ops,1892		},1893	},1894};1895 1896static struct clk_branch gcc_camss_ope_clk = {1897	.halt_reg = 0x5501c,1898	.halt_check = BRANCH_HALT,1899	.clkr = {1900		.enable_reg = 0x5501c,1901		.enable_mask = BIT(0),1902		.hw.init = &(struct clk_init_data){1903			.name = "gcc_camss_ope_clk",1904			.parent_hws = (const struct clk_hw *[]){1905				&gcc_camss_ope_clk_src.clkr.hw,1906			},1907			.num_parents = 1,1908			.flags = CLK_SET_RATE_PARENT,1909			.ops = &clk_branch2_ops,1910		},1911	},1912};1913 1914static struct clk_branch gcc_camss_rt_axi_clk = {1915	.halt_reg = 0x5805c,1916	.halt_check = BRANCH_HALT,1917	.clkr = {1918		.enable_reg = 0x5805c,1919		.enable_mask = BIT(0),1920		.hw.init = &(struct clk_init_data){1921			.name = "gcc_camss_rt_axi_clk",1922			.ops = &clk_branch2_ops,1923		},1924	},1925};1926 1927static struct clk_branch gcc_camss_tfe_0_clk = {1928	.halt_reg = 0x5201c,1929	.halt_check = BRANCH_HALT,1930	.clkr = {1931		.enable_reg = 0x5201c,1932		.enable_mask = BIT(0),1933		.hw.init = &(struct clk_init_data){1934			.name = "gcc_camss_tfe_0_clk",1935			.parent_hws = (const struct clk_hw *[]){1936				&gcc_camss_tfe_0_clk_src.clkr.hw,1937			},1938			.num_parents = 1,1939			.flags = CLK_SET_RATE_PARENT,1940			.ops = &clk_branch2_ops,1941		},1942	},1943};1944 1945static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {1946	.halt_reg = 0x5207c,1947	.halt_check = BRANCH_HALT,1948	.clkr = {1949		.enable_reg = 0x5207c,1950		.enable_mask = BIT(0),1951		.hw.init = &(struct clk_init_data){1952			.name = "gcc_camss_tfe_0_cphy_rx_clk",1953			.parent_hws = (const struct clk_hw *[]){1954				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,1955			},1956			.num_parents = 1,1957			.flags = CLK_SET_RATE_PARENT,1958			.ops = &clk_branch2_ops,1959		},1960	},1961};1962 1963static struct clk_branch gcc_camss_tfe_0_csid_clk = {1964	.halt_reg = 0x520ac,1965	.halt_check = BRANCH_HALT,1966	.clkr = {1967		.enable_reg = 0x520ac,1968		.enable_mask = BIT(0),1969		.hw.init = &(struct clk_init_data){1970			.name = "gcc_camss_tfe_0_csid_clk",1971			.parent_hws = (const struct clk_hw *[]){1972				&gcc_camss_tfe_0_csid_clk_src.clkr.hw,1973			},1974			.num_parents = 1,1975			.flags = CLK_SET_RATE_PARENT,1976			.ops = &clk_branch2_ops,1977		},1978	},1979};1980 1981static struct clk_branch gcc_camss_tfe_1_clk = {1982	.halt_reg = 0x5203c,1983	.halt_check = BRANCH_HALT,1984	.clkr = {1985		.enable_reg = 0x5203c,1986		.enable_mask = BIT(0),1987		.hw.init = &(struct clk_init_data){1988			.name = "gcc_camss_tfe_1_clk",1989			.parent_hws = (const struct clk_hw *[]){1990				&gcc_camss_tfe_1_clk_src.clkr.hw,1991			},1992			.num_parents = 1,1993			.flags = CLK_SET_RATE_PARENT,1994			.ops = &clk_branch2_ops,1995		},1996	},1997};1998 1999static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {2000	.halt_reg = 0x52080,2001	.halt_check = BRANCH_HALT,2002	.clkr = {2003		.enable_reg = 0x52080,2004		.enable_mask = BIT(0),2005		.hw.init = &(struct clk_init_data){2006			.name = "gcc_camss_tfe_1_cphy_rx_clk",2007			.parent_hws = (const struct clk_hw *[]){2008				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,2009			},2010			.num_parents = 1,2011			.flags = CLK_SET_RATE_PARENT,2012			.ops = &clk_branch2_ops,2013		},2014	},2015};2016 2017static struct clk_branch gcc_camss_tfe_1_csid_clk = {2018	.halt_reg = 0x520cc,2019	.halt_check = BRANCH_HALT,2020	.clkr = {2021		.enable_reg = 0x520cc,2022		.enable_mask = BIT(0),2023		.hw.init = &(struct clk_init_data){2024			.name = "gcc_camss_tfe_1_csid_clk",2025			.parent_hws = (const struct clk_hw *[]){2026				&gcc_camss_tfe_1_csid_clk_src.clkr.hw,2027			},2028			.num_parents = 1,2029			.flags = CLK_SET_RATE_PARENT,2030			.ops = &clk_branch2_ops,2031		},2032	},2033};2034 2035static struct clk_branch gcc_camss_tfe_2_clk = {2036	.halt_reg = 0x5205c,2037	.halt_check = BRANCH_HALT,2038	.clkr = {2039		.enable_reg = 0x5205c,2040		.enable_mask = BIT(0),2041		.hw.init = &(struct clk_init_data){2042			.name = "gcc_camss_tfe_2_clk",2043			.parent_hws = (const struct clk_hw *[]){2044				&gcc_camss_tfe_2_clk_src.clkr.hw,2045			},2046			.num_parents = 1,2047			.flags = CLK_SET_RATE_PARENT,2048			.ops = &clk_branch2_ops,2049		},2050	},2051};2052 2053static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {2054	.halt_reg = 0x52084,2055	.halt_check = BRANCH_HALT,2056	.clkr = {2057		.enable_reg = 0x52084,2058		.enable_mask = BIT(0),2059		.hw.init = &(struct clk_init_data){2060			.name = "gcc_camss_tfe_2_cphy_rx_clk",2061			.parent_hws = (const struct clk_hw *[]){2062				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,2063			},2064			.num_parents = 1,2065			.flags = CLK_SET_RATE_PARENT,2066			.ops = &clk_branch2_ops,2067		},2068	},2069};2070 2071static struct clk_branch gcc_camss_tfe_2_csid_clk = {2072	.halt_reg = 0x520ec,2073	.halt_check = BRANCH_HALT,2074	.clkr = {2075		.enable_reg = 0x520ec,2076		.enable_mask = BIT(0),2077		.hw.init = &(struct clk_init_data){2078			.name = "gcc_camss_tfe_2_csid_clk",2079			.parent_hws = (const struct clk_hw *[]){2080				&gcc_camss_tfe_2_csid_clk_src.clkr.hw,2081			},2082			.num_parents = 1,2083			.flags = CLK_SET_RATE_PARENT,2084			.ops = &clk_branch2_ops,2085		},2086	},2087};2088 2089static struct clk_branch gcc_camss_top_ahb_clk = {2090	.halt_reg = 0x58028,2091	.halt_check = BRANCH_HALT,2092	.clkr = {2093		.enable_reg = 0x58028,2094		.enable_mask = BIT(0),2095		.hw.init = &(struct clk_init_data){2096			.name = "gcc_camss_top_ahb_clk",2097			.parent_hws = (const struct clk_hw *[]){2098				&gcc_camss_top_ahb_clk_src.clkr.hw,2099			},2100			.num_parents = 1,2101			.flags = CLK_SET_RATE_PARENT,2102			.ops = &clk_branch2_ops,2103		},2104	},2105};2106 2107static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {2108	.halt_reg = 0x1a084,2109	.halt_check = BRANCH_HALT,2110	.hwcg_reg = 0x1a084,2111	.hwcg_bit = 1,2112	.clkr = {2113		.enable_reg = 0x1a084,2114		.enable_mask = BIT(0),2115		.hw.init = &(struct clk_init_data){2116			.name = "gcc_cfg_noc_usb3_prim_axi_clk",2117			.parent_hws = (const struct clk_hw *[]){2118				&gcc_usb30_prim_master_clk_src.clkr.hw,2119			},2120			.num_parents = 1,2121			.flags = CLK_SET_RATE_PARENT,2122			.ops = &clk_branch2_ops,2123		},2124	},2125};2126 2127static struct clk_branch gcc_cpuss_gnoc_clk = {2128	.halt_reg = 0x2b004,2129	.halt_check = BRANCH_HALT_VOTED,2130	.hwcg_reg = 0x2b004,2131	.hwcg_bit = 1,2132	.clkr = {2133		.enable_reg = 0x79004,2134		.enable_mask = BIT(22),2135		.hw.init = &(struct clk_init_data){2136			.name = "gcc_cpuss_gnoc_clk",2137			.flags = CLK_IS_CRITICAL,2138			.ops = &clk_branch2_ops,2139		},2140	},2141};2142 2143static struct clk_branch gcc_disp_ahb_clk = {2144	.halt_reg = 0x1700c,2145	.halt_check = BRANCH_HALT,2146	.hwcg_reg = 0x1700c,2147	.hwcg_bit = 1,2148	.clkr = {2149		.enable_reg = 0x1700c,2150		.enable_mask = BIT(0),2151		.hw.init = &(struct clk_init_data){2152			.name = "gcc_disp_ahb_clk",2153			.flags = CLK_IS_CRITICAL,2154			.ops = &clk_branch2_ops,2155		},2156	},2157};2158 2159static struct clk_regmap_div gcc_disp_gpll0_clk_src = {2160	.reg = 0x17058,2161	.shift = 0,2162	.width = 2,2163	.clkr.hw.init = &(struct clk_init_data) {2164		.name = "gcc_disp_gpll0_clk_src",2165		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },2166		.num_parents = 1,2167		.ops = &clk_regmap_div_ops,2168	},2169};2170 2171static struct clk_branch gcc_disp_gpll0_div_clk_src = {2172	.halt_check = BRANCH_HALT_DELAY,2173	.clkr = {2174		.enable_reg = 0x79004,2175		.enable_mask = BIT(20),2176		.hw.init = &(struct clk_init_data){2177			.name = "gcc_disp_gpll0_div_clk_src",2178			.parent_hws = (const struct clk_hw *[]){2179				&gcc_disp_gpll0_clk_src.clkr.hw,2180			},2181			.num_parents = 1,2182			.flags = CLK_SET_RATE_PARENT,2183			.ops = &clk_branch2_ops,2184		},2185	},2186};2187 2188static struct clk_branch gcc_disp_hf_axi_clk = {2189	.halt_reg = 0x17020,2190	.halt_check = BRANCH_HALT,2191	.hwcg_reg = 0x17020,2192	.hwcg_bit = 1,2193	.clkr = {2194		.enable_reg = 0x17020,2195		.enable_mask = BIT(0),2196		.hw.init = &(struct clk_init_data){2197			.name = "gcc_disp_hf_axi_clk",2198			.ops = &clk_branch2_ops,2199		},2200	},2201};2202 2203static struct clk_branch gcc_disp_throttle_core_clk = {2204	.halt_reg = 0x17064,2205	.halt_check = BRANCH_HALT_VOTED,2206	.hwcg_reg = 0x17064,2207	.hwcg_bit = 1,2208	.clkr = {2209		.enable_reg = 0x7900c,2210		.enable_mask = BIT(5),2211		.hw.init = &(struct clk_init_data){2212			.name = "gcc_disp_throttle_core_clk",2213			.ops = &clk_branch2_ops,2214		},2215	},2216};2217 2218static struct clk_branch gcc_disp_xo_clk = {2219	.halt_reg = 0x1702c,2220	.halt_check = BRANCH_HALT,2221	.clkr = {2222		.enable_reg = 0x1702c,2223		.enable_mask = BIT(0),2224		.hw.init = &(struct clk_init_data){2225			.name = "gcc_disp_xo_clk",2226			.flags = CLK_IS_CRITICAL,2227			.ops = &clk_branch2_ops,2228		},2229	},2230};2231 2232static struct clk_branch gcc_gp1_clk = {2233	.halt_reg = 0x4d000,2234	.halt_check = BRANCH_HALT,2235	.clkr = {2236		.enable_reg = 0x4d000,2237		.enable_mask = BIT(0),2238		.hw.init = &(struct clk_init_data){2239			.name = "gcc_gp1_clk",2240			.parent_hws = (const struct clk_hw *[]){2241				&gcc_gp1_clk_src.clkr.hw,2242			},2243			.num_parents = 1,2244			.flags = CLK_SET_RATE_PARENT,2245			.ops = &clk_branch2_ops,2246		},2247	},2248};2249 2250static struct clk_branch gcc_gp2_clk = {2251	.halt_reg = 0x4e000,2252	.halt_check = BRANCH_HALT,2253	.clkr = {2254		.enable_reg = 0x4e000,2255		.enable_mask = BIT(0),2256		.hw.init = &(struct clk_init_data){2257			.name = "gcc_gp2_clk",2258			.parent_hws = (const struct clk_hw *[]){2259				&gcc_gp2_clk_src.clkr.hw,2260			},2261			.num_parents = 1,2262			.flags = CLK_SET_RATE_PARENT,2263			.ops = &clk_branch2_ops,2264		},2265	},2266};2267 2268static struct clk_branch gcc_gp3_clk = {2269	.halt_reg = 0x4f000,2270	.halt_check = BRANCH_HALT,2271	.clkr = {2272		.enable_reg = 0x4f000,2273		.enable_mask = BIT(0),2274		.hw.init = &(struct clk_init_data){2275			.name = "gcc_gp3_clk",2276			.parent_hws = (const struct clk_hw *[]){2277				&gcc_gp3_clk_src.clkr.hw,2278			},2279			.num_parents = 1,2280			.flags = CLK_SET_RATE_PARENT,2281			.ops = &clk_branch2_ops,2282		},2283	},2284};2285 2286static struct clk_branch gcc_gpu_cfg_ahb_clk = {2287	.halt_reg = 0x36004,2288	.halt_check = BRANCH_HALT,2289	.hwcg_reg = 0x36004,2290	.hwcg_bit = 1,2291	.clkr = {2292		.enable_reg = 0x36004,2293		.enable_mask = BIT(0),2294		.hw.init = &(struct clk_init_data){2295			.name = "gcc_gpu_cfg_ahb_clk",2296			.flags = CLK_IS_CRITICAL,2297			.ops = &clk_branch2_ops,2298		},2299	},2300};2301 2302static struct clk_branch gcc_gpu_gpll0_clk_src = {2303	.halt_check = BRANCH_HALT_DELAY,2304	.clkr = {2305		.enable_reg = 0x79004,2306		.enable_mask = BIT(15),2307		.hw.init = &(struct clk_init_data){2308			.name = "gcc_gpu_gpll0_clk_src",2309			.parent_hws = (const struct clk_hw *[]){2310				&gpll0.clkr.hw,2311			},2312			.num_parents = 1,2313			.flags = CLK_SET_RATE_PARENT,2314			.ops = &clk_branch2_ops,2315		},2316	},2317};2318 2319static struct clk_branch gcc_gpu_gpll0_div_clk_src = {2320	.halt_check = BRANCH_HALT_DELAY,2321	.clkr = {2322		.enable_reg = 0x79004,2323		.enable_mask = BIT(16),2324		.hw.init = &(struct clk_init_data){2325			.name = "gcc_gpu_gpll0_div_clk_src",2326			.parent_hws = (const struct clk_hw *[]){2327				&gpll0_out_aux2.clkr.hw,2328			},2329			.num_parents = 1,2330			.flags = CLK_SET_RATE_PARENT,2331			.ops = &clk_branch2_ops,2332		},2333	},2334};2335 2336static struct clk_branch gcc_gpu_iref_clk = {2337	.halt_reg = 0x36100,2338	.halt_check = BRANCH_HALT_DELAY,2339	.clkr = {2340		.enable_reg = 0x36100,2341		.enable_mask = BIT(0),2342		.hw.init = &(struct clk_init_data){2343			.name = "gcc_gpu_iref_clk",2344			.ops = &clk_branch2_ops,2345		},2346	},2347};2348 2349static struct clk_branch gcc_gpu_memnoc_gfx_clk = {2350	.halt_reg = 0x3600c,2351	.halt_check = BRANCH_VOTED,2352	.hwcg_reg = 0x3600c,2353	.hwcg_bit = 1,2354	.clkr = {2355		.enable_reg = 0x3600c,2356		.enable_mask = BIT(0),2357		.hw.init = &(struct clk_init_data){2358			.name = "gcc_gpu_memnoc_gfx_clk",2359			.ops = &clk_branch2_ops,2360		},2361	},2362};2363 2364static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {2365	.halt_reg = 0x36018,2366	.halt_check = BRANCH_HALT,2367	.clkr = {2368		.enable_reg = 0x36018,2369		.enable_mask = BIT(0),2370		.hw.init = &(struct clk_init_data){2371			.name = "gcc_gpu_snoc_dvm_gfx_clk",2372			.ops = &clk_branch2_ops,2373		},2374	},2375};2376 2377static struct clk_branch gcc_gpu_throttle_core_clk = {2378	.halt_reg = 0x36048,2379	.halt_check = BRANCH_HALT_VOTED,2380	.hwcg_reg = 0x36048,2381	.hwcg_bit = 1,2382	.clkr = {2383		.enable_reg = 0x79004,2384		.enable_mask = BIT(31),2385		.hw.init = &(struct clk_init_data){2386			.name = "gcc_gpu_throttle_core_clk",2387			.ops = &clk_branch2_ops,2388		},2389	},2390};2391 2392static struct clk_branch gcc_pdm2_clk = {2393	.halt_reg = 0x2000c,2394	.halt_check = BRANCH_HALT,2395	.clkr = {2396		.enable_reg = 0x2000c,2397		.enable_mask = BIT(0),2398		.hw.init = &(struct clk_init_data){2399			.name = "gcc_pdm2_clk",2400			.parent_hws = (const struct clk_hw *[]){2401				&gcc_pdm2_clk_src.clkr.hw,2402			},2403			.num_parents = 1,2404			.flags = CLK_SET_RATE_PARENT,2405			.ops = &clk_branch2_ops,2406		},2407	},2408};2409 2410static struct clk_branch gcc_pdm_ahb_clk = {2411	.halt_reg = 0x20004,2412	.halt_check = BRANCH_HALT,2413	.hwcg_reg = 0x20004,2414	.hwcg_bit = 1,2415	.clkr = {2416		.enable_reg = 0x20004,2417		.enable_mask = BIT(0),2418		.hw.init = &(struct clk_init_data){2419			.name = "gcc_pdm_ahb_clk",2420			.ops = &clk_branch2_ops,2421		},2422	},2423};2424 2425static struct clk_branch gcc_pdm_xo4_clk = {2426	.halt_reg = 0x20008,2427	.halt_check = BRANCH_HALT,2428	.clkr = {2429		.enable_reg = 0x20008,2430		.enable_mask = BIT(0),2431		.hw.init = &(struct clk_init_data){2432			.name = "gcc_pdm_xo4_clk",2433			.ops = &clk_branch2_ops,2434		},2435	},2436};2437 2438static struct clk_branch gcc_prng_ahb_clk = {2439	.halt_reg = 0x21004,2440	.halt_check = BRANCH_HALT_VOTED,2441	.hwcg_reg = 0x21004,2442	.hwcg_bit = 1,2443	.clkr = {2444		.enable_reg = 0x79004,2445		.enable_mask = BIT(13),2446		.hw.init = &(struct clk_init_data){2447			.name = "gcc_prng_ahb_clk",2448			.ops = &clk_branch2_ops,2449		},2450	},2451};2452 2453static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {2454	.halt_reg = 0x17014,2455	.halt_check = BRANCH_HALT_VOTED,2456	.hwcg_reg = 0x17014,2457	.hwcg_bit = 1,2458	.clkr = {2459		.enable_reg = 0x7900c,2460		.enable_mask = BIT(0),2461		.hw.init = &(struct clk_init_data){2462			.name = "gcc_qmip_camera_nrt_ahb_clk",2463			.ops = &clk_branch2_ops,2464		},2465	},2466};2467 2468static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {2469	.halt_reg = 0x17060,2470	.halt_check = BRANCH_HALT_VOTED,2471	.hwcg_reg = 0x17060,2472	.hwcg_bit = 1,2473	.clkr = {2474		.enable_reg = 0x7900c,2475		.enable_mask = BIT(2),2476		.hw.init = &(struct clk_init_data){2477			.name = "gcc_qmip_camera_rt_ahb_clk",2478			.ops = &clk_branch2_ops,2479		},2480	},2481};2482 2483static struct clk_branch gcc_qmip_disp_ahb_clk = {2484	.halt_reg = 0x17018,2485	.halt_check = BRANCH_HALT_VOTED,2486	.hwcg_reg = 0x17018,2487	.hwcg_bit = 1,2488	.clkr = {2489		.enable_reg = 0x7900c,2490		.enable_mask = BIT(1),2491		.hw.init = &(struct clk_init_data){2492			.name = "gcc_qmip_disp_ahb_clk",2493			.ops = &clk_branch2_ops,2494		},2495	},2496};2497 2498static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {2499	.halt_reg = 0x36040,2500	.halt_check = BRANCH_HALT_VOTED,2501	.hwcg_reg = 0x36040,2502	.hwcg_bit = 1,2503	.clkr = {2504		.enable_reg = 0x7900c,2505		.enable_mask = BIT(4),2506		.hw.init = &(struct clk_init_data){2507			.name = "gcc_qmip_gpu_cfg_ahb_clk",2508			.ops = &clk_branch2_ops,2509		},2510	},2511};2512 2513static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {2514	.halt_reg = 0x17010,2515	.halt_check = BRANCH_HALT_VOTED,2516	.hwcg_reg = 0x17010,2517	.hwcg_bit = 1,2518	.clkr = {2519		.enable_reg = 0x79004,2520		.enable_mask = BIT(25),2521		.hw.init = &(struct clk_init_data){2522			.name = "gcc_qmip_video_vcodec_ahb_clk",2523			.ops = &clk_branch2_ops,2524		},2525	},2526};2527 2528static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {2529	.halt_reg = 0x1f014,2530	.halt_check = BRANCH_HALT_VOTED,2531	.clkr = {2532		.enable_reg = 0x7900c,2533		.enable_mask = BIT(9),2534		.hw.init = &(struct clk_init_data){2535			.name = "gcc_qupv3_wrap0_core_2x_clk",2536			.ops = &clk_branch2_ops,2537		},2538	},2539};2540 2541static struct clk_branch gcc_qupv3_wrap0_core_clk = {2542	.halt_reg = 0x1f00c,2543	.halt_check = BRANCH_HALT_VOTED,2544	.clkr = {2545		.enable_reg = 0x7900c,2546		.enable_mask = BIT(8),2547		.hw.init = &(struct clk_init_data){2548			.name = "gcc_qupv3_wrap0_core_clk",2549			.ops = &clk_branch2_ops,2550		},2551	},2552};2553 2554static struct clk_branch gcc_qupv3_wrap0_s0_clk = {2555	.halt_reg = 0x1f144,2556	.halt_check = BRANCH_HALT_VOTED,2557	.clkr = {2558		.enable_reg = 0x7900c,2559		.enable_mask = BIT(10),2560		.hw.init = &(struct clk_init_data){2561			.name = "gcc_qupv3_wrap0_s0_clk",2562			.parent_hws = (const struct clk_hw *[]){2563				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,2564			},2565			.num_parents = 1,2566			.flags = CLK_SET_RATE_PARENT,2567			.ops = &clk_branch2_ops,2568		},2569	},2570};2571 2572static struct clk_branch gcc_qupv3_wrap0_s1_clk = {2573	.halt_reg = 0x1f274,2574	.halt_check = BRANCH_HALT_VOTED,2575	.clkr = {2576		.enable_reg = 0x7900c,2577		.enable_mask = BIT(11),2578		.hw.init = &(struct clk_init_data){2579			.name = "gcc_qupv3_wrap0_s1_clk",2580			.parent_hws = (const struct clk_hw *[]){2581				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,2582			},2583			.num_parents = 1,2584			.flags = CLK_SET_RATE_PARENT,2585			.ops = &clk_branch2_ops,2586		},2587	},2588};2589 2590static struct clk_branch gcc_qupv3_wrap0_s2_clk = {2591	.halt_reg = 0x1f3a4,2592	.halt_check = BRANCH_HALT_VOTED,2593	.clkr = {2594		.enable_reg = 0x7900c,2595		.enable_mask = BIT(12),2596		.hw.init = &(struct clk_init_data){2597			.name = "gcc_qupv3_wrap0_s2_clk",2598			.parent_hws = (const struct clk_hw *[]){2599				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,2600			},2601			.num_parents = 1,2602			.flags = CLK_SET_RATE_PARENT,2603			.ops = &clk_branch2_ops,2604		},2605	},2606};2607 2608static struct clk_branch gcc_qupv3_wrap0_s3_clk = {2609	.halt_reg = 0x1f4d4,2610	.halt_check = BRANCH_HALT_VOTED,2611	.clkr = {2612		.enable_reg = 0x7900c,2613		.enable_mask = BIT(13),2614		.hw.init = &(struct clk_init_data){2615			.name = "gcc_qupv3_wrap0_s3_clk",2616			.parent_hws = (const struct clk_hw *[]){2617				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,2618			},2619			.num_parents = 1,2620			.flags = CLK_SET_RATE_PARENT,2621			.ops = &clk_branch2_ops,2622		},2623	},2624};2625 2626static struct clk_branch gcc_qupv3_wrap0_s4_clk = {2627	.halt_reg = 0x1f604,2628	.halt_check = BRANCH_HALT_VOTED,2629	.clkr = {2630		.enable_reg = 0x7900c,2631		.enable_mask = BIT(14),2632		.hw.init = &(struct clk_init_data){2633			.name = "gcc_qupv3_wrap0_s4_clk",2634			.parent_hws = (const struct clk_hw *[]){2635				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,2636			},2637			.num_parents = 1,2638			.flags = CLK_SET_RATE_PARENT,2639			.ops = &clk_branch2_ops,2640		},2641	},2642};2643 2644static struct clk_branch gcc_qupv3_wrap0_s5_clk = {2645	.halt_reg = 0x1f734,2646	.halt_check = BRANCH_HALT_VOTED,2647	.clkr = {2648		.enable_reg = 0x7900c,2649		.enable_mask = BIT(15),2650		.hw.init = &(struct clk_init_data){2651			.name = "gcc_qupv3_wrap0_s5_clk",2652			.parent_hws = (const struct clk_hw *[]){2653				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,2654			},2655			.num_parents = 1,2656			.flags = CLK_SET_RATE_PARENT,2657			.ops = &clk_branch2_ops,2658		},2659	},2660};2661 2662static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {2663	.halt_reg = 0x1f004,2664	.halt_check = BRANCH_HALT_VOTED,2665	.hwcg_reg = 0x1f004,2666	.hwcg_bit = 1,2667	.clkr = {2668		.enable_reg = 0x7900c,2669		.enable_mask = BIT(6),2670		.hw.init = &(struct clk_init_data){2671			.name = "gcc_qupv3_wrap_0_m_ahb_clk",2672			.ops = &clk_branch2_ops,2673		},2674	},2675};2676 2677static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {2678	.halt_reg = 0x1f008,2679	.halt_check = BRANCH_HALT_VOTED,2680	.hwcg_reg = 0x1f008,2681	.hwcg_bit = 1,2682	.clkr = {2683		.enable_reg = 0x7900c,2684		.enable_mask = BIT(7),2685		.hw.init = &(struct clk_init_data){2686			.name = "gcc_qupv3_wrap_0_s_ahb_clk",2687			.ops = &clk_branch2_ops,2688		},2689	},2690};2691 2692static struct clk_branch gcc_sdcc1_ahb_clk = {2693	.halt_reg = 0x38008,2694	.halt_check = BRANCH_HALT,2695	.clkr = {2696		.enable_reg = 0x38008,2697		.enable_mask = BIT(0),2698		.hw.init = &(struct clk_init_data){2699			.name = "gcc_sdcc1_ahb_clk",2700			.ops = &clk_branch2_ops,2701		},2702	},2703};2704 2705static struct clk_branch gcc_sdcc1_apps_clk = {2706	.halt_reg = 0x38004,2707	.halt_check = BRANCH_HALT,2708	.clkr = {2709		.enable_reg = 0x38004,2710		.enable_mask = BIT(0),2711		.hw.init = &(struct clk_init_data){2712			.name = "gcc_sdcc1_apps_clk",2713			.parent_hws = (const struct clk_hw *[]){2714				&gcc_sdcc1_apps_clk_src.clkr.hw,2715			},2716			.num_parents = 1,2717			.flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */,2718			.ops = &clk_branch2_ops,2719		},2720	},2721};2722 2723static struct clk_branch gcc_sdcc1_ice_core_clk = {2724	.halt_reg = 0x3800c,2725	.halt_check = BRANCH_HALT,2726	.hwcg_reg = 0x3800c,2727	.hwcg_bit = 1,2728	.clkr = {2729		.enable_reg = 0x3800c,2730		.enable_mask = BIT(0),2731		.hw.init = &(struct clk_init_data){2732			.name = "gcc_sdcc1_ice_core_clk",2733			.parent_hws = (const struct clk_hw *[]){2734				&gcc_sdcc1_ice_core_clk_src.clkr.hw,2735			},2736			.num_parents = 1,2737			.flags = CLK_SET_RATE_PARENT,2738			.ops = &clk_branch2_ops,2739		},2740	},2741};2742 2743static struct clk_branch gcc_sdcc2_ahb_clk = {2744	.halt_reg = 0x1e008,2745	.halt_check = BRANCH_HALT,2746	.clkr = {2747		.enable_reg = 0x1e008,2748		.enable_mask = BIT(0),2749		.hw.init = &(struct clk_init_data){2750			.name = "gcc_sdcc2_ahb_clk",2751			.ops = &clk_branch2_ops,2752		},2753	},2754};2755 2756static struct clk_branch gcc_sdcc2_apps_clk = {2757	.halt_reg = 0x1e004,2758	.halt_check = BRANCH_HALT,2759	.clkr = {2760		.enable_reg = 0x1e004,2761		.enable_mask = BIT(0),2762		.hw.init = &(struct clk_init_data){2763			.name = "gcc_sdcc2_apps_clk",2764			.parent_hws = (const struct clk_hw *[]){2765				&gcc_sdcc2_apps_clk_src.clkr.hw,2766			},2767			.num_parents = 1,2768			.flags = CLK_SET_RATE_PARENT,2769			.ops = &clk_branch2_ops,2770		},2771	},2772};2773 2774static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {2775	.halt_reg = 0x2b06c,2776	.halt_check = BRANCH_HALT_VOTED,2777	.hwcg_reg = 0x2b06c,2778	.hwcg_bit = 1,2779	.clkr = {2780		.enable_reg = 0x79004,2781		.enable_mask = BIT(0),2782		.hw.init = &(struct clk_init_data){2783			.name = "gcc_sys_noc_cpuss_ahb_clk",2784			.flags = CLK_IS_CRITICAL,2785			.ops = &clk_branch2_ops,2786		},2787	},2788};2789 2790static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {2791	.halt_reg = 0x45098,2792	.halt_check = BRANCH_HALT,2793	.clkr = {2794		.enable_reg = 0x45098,2795		.enable_mask = BIT(0),2796		.hw.init = &(struct clk_init_data){2797			.name = "gcc_sys_noc_ufs_phy_axi_clk",2798			.parent_hws = (const struct clk_hw *[]){2799				&gcc_ufs_phy_axi_clk_src.clkr.hw,2800			},2801			.num_parents = 1,2802			.flags = CLK_SET_RATE_PARENT,2803			.ops = &clk_branch2_ops,2804		},2805	},2806};2807 2808static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {2809	.halt_reg = 0x1a080,2810	.halt_check = BRANCH_HALT,2811	.hwcg_reg = 0x1a080,2812	.hwcg_bit = 1,2813	.clkr = {2814		.enable_reg = 0x1a080,2815		.enable_mask = BIT(0),2816		.hw.init = &(struct clk_init_data){2817			.name = "gcc_sys_noc_usb3_prim_axi_clk",2818			.parent_hws = (const struct clk_hw *[]){2819				&gcc_usb30_prim_master_clk_src.clkr.hw,2820			},2821			.num_parents = 1,2822			.flags = CLK_SET_RATE_PARENT,2823			.ops = &clk_branch2_ops,2824		},2825	},2826};2827 2828static struct clk_branch gcc_ufs_clkref_clk = {2829	.halt_reg = 0x8c000,2830	.halt_check = BRANCH_HALT,2831	.clkr = {2832		.enable_reg = 0x8c000,2833		.enable_mask = BIT(0),2834		.hw.init = &(struct clk_init_data){2835			.name = "gcc_ufs_clkref_clk",2836			.ops = &clk_branch2_ops,2837		},2838	},2839};2840 2841static struct clk_branch gcc_ufs_phy_ahb_clk = {2842	.halt_reg = 0x45014,2843	.halt_check = BRANCH_HALT,2844	.hwcg_reg = 0x45014,2845	.hwcg_bit = 1,2846	.clkr = {2847		.enable_reg = 0x45014,2848		.enable_mask = BIT(0),2849		.hw.init = &(struct clk_init_data){2850			.name = "gcc_ufs_phy_ahb_clk",2851			.ops = &clk_branch2_ops,2852		},2853	},2854};2855 2856static struct clk_branch gcc_ufs_phy_axi_clk = {2857	.halt_reg = 0x45010,2858	.halt_check = BRANCH_HALT,2859	.hwcg_reg = 0x45010,2860	.hwcg_bit = 1,2861	.clkr = {2862		.enable_reg = 0x45010,2863		.enable_mask = BIT(0),2864		.hw.init = &(struct clk_init_data){2865			.name = "gcc_ufs_phy_axi_clk",2866			.parent_hws = (const struct clk_hw *[]){2867				&gcc_ufs_phy_axi_clk_src.clkr.hw,2868			},2869			.num_parents = 1,2870			.flags = CLK_SET_RATE_PARENT,2871			.ops = &clk_branch2_ops,2872		},2873	},2874};2875 2876static struct clk_branch gcc_ufs_phy_ice_core_clk = {2877	.halt_reg = 0x45044,2878	.halt_check = BRANCH_HALT,2879	.hwcg_reg = 0x45044,2880	.hwcg_bit = 1,2881	.clkr = {2882		.enable_reg = 0x45044,2883		.enable_mask = BIT(0),2884		.hw.init = &(struct clk_init_data){2885			.name = "gcc_ufs_phy_ice_core_clk",2886			.parent_hws = (const struct clk_hw *[]){2887				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,2888			},2889			.num_parents = 1,2890			.flags = CLK_SET_RATE_PARENT,2891			.ops = &clk_branch2_ops,2892		},2893	},2894};2895 2896static struct clk_branch gcc_ufs_phy_phy_aux_clk = {2897	.halt_reg = 0x45078,2898	.halt_check = BRANCH_HALT,2899	.hwcg_reg = 0x45078,2900	.hwcg_bit = 1,2901	.clkr = {2902		.enable_reg = 0x45078,2903		.enable_mask = BIT(0),2904		.hw.init = &(struct clk_init_data){2905			.name = "gcc_ufs_phy_phy_aux_clk",2906			.parent_hws = (const struct clk_hw *[]){2907				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,2908			},2909			.num_parents = 1,2910			.flags = CLK_SET_RATE_PARENT,2911			.ops = &clk_branch2_ops,2912		},2913	},2914};2915 2916static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {2917	.halt_reg = 0x4501c,2918	.halt_check = BRANCH_HALT_SKIP,2919	.clkr = {2920		.enable_reg = 0x4501c,2921		.enable_mask = BIT(0),2922		.hw.init = &(struct clk_init_data){2923			.name = "gcc_ufs_phy_rx_symbol_0_clk",2924			.ops = &clk_branch2_ops,2925		},2926	},2927};2928 2929static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {2930	.halt_reg = 0x45018,2931	.halt_check = BRANCH_HALT_SKIP,2932	.clkr = {2933		.enable_reg = 0x45018,2934		.enable_mask = BIT(0),2935		.hw.init = &(struct clk_init_data){2936			.name = "gcc_ufs_phy_tx_symbol_0_clk",2937			.ops = &clk_branch2_ops,2938		},2939	},2940};2941 2942static struct clk_branch gcc_ufs_phy_unipro_core_clk = {2943	.halt_reg = 0x45040,2944	.halt_check = BRANCH_HALT,2945	.hwcg_reg = 0x45040,2946	.hwcg_bit = 1,2947	.clkr = {2948		.enable_reg = 0x45040,2949		.enable_mask = BIT(0),2950		.hw.init = &(struct clk_init_data){2951			.name = "gcc_ufs_phy_unipro_core_clk",2952			.parent_hws = (const struct clk_hw *[]){2953				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,2954			},2955			.num_parents = 1,2956			.flags = CLK_SET_RATE_PARENT,2957			.ops = &clk_branch2_ops,2958		},2959	},2960};2961 2962static struct clk_branch gcc_usb30_prim_master_clk = {2963	.halt_reg = 0x1a010,2964	.halt_check = BRANCH_HALT,2965	.clkr = {2966		.enable_reg = 0x1a010,2967		.enable_mask = BIT(0),2968		.hw.init = &(struct clk_init_data){2969			.name = "gcc_usb30_prim_master_clk",2970			.parent_hws = (const struct clk_hw *[]){2971				&gcc_usb30_prim_master_clk_src.clkr.hw,2972			},2973			.num_parents = 1,2974			.flags = CLK_SET_RATE_PARENT,2975			.ops = &clk_branch2_ops,2976		},2977	},2978};2979 2980static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {2981	.halt_reg = 0x1a018,2982	.halt_check = BRANCH_HALT,2983	.clkr = {2984		.enable_reg = 0x1a018,2985		.enable_mask = BIT(0),2986		.hw.init = &(struct clk_init_data){2987			.name = "gcc_usb30_prim_mock_utmi_clk",2988			.parent_hws = (const struct clk_hw *[]){2989				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,2990			},2991			.num_parents = 1,2992			.flags = CLK_SET_RATE_PARENT,2993			.ops = &clk_branch2_ops,2994		},2995	},2996};2997 2998static struct clk_branch gcc_usb30_prim_sleep_clk = {2999	.halt_reg = 0x1a014,3000	.halt_check = BRANCH_HALT,3001	.clkr = {3002		.enable_reg = 0x1a014,3003		.enable_mask = BIT(0),3004		.hw.init = &(struct clk_init_data){3005			.name = "gcc_usb30_prim_sleep_clk",3006			.ops = &clk_branch2_ops,3007		},3008	},3009};3010 3011static struct clk_branch gcc_usb3_prim_clkref_clk = {3012	.halt_reg = 0x9f000,3013	.halt_check = BRANCH_HALT,3014	.clkr = {3015		.enable_reg = 0x9f000,3016		.enable_mask = BIT(0),3017		.hw.init = &(struct clk_init_data){3018			.name = "gcc_usb3_prim_clkref_clk",3019			.ops = &clk_branch2_ops,3020		},3021	},3022};3023 3024static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {3025	.halt_reg = 0x1a054,3026	.halt_check = BRANCH_HALT,3027	.clkr = {3028		.enable_reg = 0x1a054,3029		.enable_mask = BIT(0),3030		.hw.init = &(struct clk_init_data){3031			.name = "gcc_usb3_prim_phy_com_aux_clk",3032			.parent_hws = (const struct clk_hw *[]){3033				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,3034			},3035			.num_parents = 1,3036			.flags = CLK_SET_RATE_PARENT,3037			.ops = &clk_branch2_ops,3038		},3039	},3040};3041 3042static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {3043	.halt_reg = 0x1a058,3044	.halt_check = BRANCH_HALT_SKIP,3045	.hwcg_reg = 0x1a058,3046	.hwcg_bit = 1,3047	.clkr = {3048		.enable_reg = 0x1a058,3049		.enable_mask = BIT(0),3050		.hw.init = &(struct clk_init_data){3051			.name = "gcc_usb3_prim_phy_pipe_clk",3052			.ops = &clk_branch2_ops,3053		},3054	},3055};3056 3057static struct clk_branch gcc_vcodec0_axi_clk = {3058	.halt_reg = 0x6e008,3059	.halt_check = BRANCH_HALT,3060	.clkr = {3061		.enable_reg = 0x6e008,3062		.enable_mask = BIT(0),3063		.hw.init = &(struct clk_init_data){3064			.name = "gcc_vcodec0_axi_clk",3065			.ops = &clk_branch2_ops,3066		},3067	},3068};3069 3070static struct clk_branch gcc_venus_ahb_clk = {3071	.halt_reg = 0x6e010,3072	.halt_check = BRANCH_HALT,3073	.clkr = {3074		.enable_reg = 0x6e010,3075		.enable_mask = BIT(0),3076		.hw.init = &(struct clk_init_data){3077			.name = "gcc_venus_ahb_clk",3078			.ops = &clk_branch2_ops,3079		},3080	},3081};3082 3083static struct clk_branch gcc_venus_ctl_axi_clk = {3084	.halt_reg = 0x6e004,3085	.halt_check = BRANCH_HALT,3086	.clkr = {3087		.enable_reg = 0x6e004,3088		.enable_mask = BIT(0),3089		.hw.init = &(struct clk_init_data){3090			.name = "gcc_venus_ctl_axi_clk",3091			.ops = &clk_branch2_ops,3092		},3093	},3094};3095 3096static struct clk_branch gcc_video_ahb_clk = {3097	.halt_reg = 0x17004,3098	.halt_check = BRANCH_HALT,3099	.hwcg_reg = 0x17004,3100	.hwcg_bit = 1,3101	.clkr = {3102		.enable_reg = 0x17004,3103		.enable_mask = BIT(0),3104		.hw.init = &(struct clk_init_data){3105			.name = "gcc_video_ahb_clk",3106			.ops = &clk_branch2_ops,3107		},3108	},3109};3110 3111static struct clk_branch gcc_video_axi0_clk = {3112	.halt_reg = 0x1701c,3113	.halt_check = BRANCH_HALT,3114	.hwcg_reg = 0x1701c,3115	.hwcg_bit = 1,3116	.clkr = {3117		.enable_reg = 0x1701c,3118		.enable_mask = BIT(0),3119		.hw.init = &(struct clk_init_data){3120			.name = "gcc_video_axi0_clk",3121			.ops = &clk_branch2_ops,3122		},3123	},3124};3125 3126static struct clk_branch gcc_video_throttle_core_clk = {3127	.halt_reg = 0x17068,3128	.halt_check = BRANCH_HALT_VOTED,3129	.hwcg_reg = 0x17068,3130	.hwcg_bit = 1,3131	.clkr = {3132		.enable_reg = 0x79004,3133		.enable_mask = BIT(28),3134		.hw.init = &(struct clk_init_data){3135			.name = "gcc_video_throttle_core_clk",3136			.ops = &clk_branch2_ops,3137		},3138	},3139};3140 3141static struct clk_branch gcc_video_vcodec0_sys_clk = {3142	.halt_reg = 0x580a4,3143	.halt_check = BRANCH_HALT_DELAY,3144	.hwcg_reg = 0x580a4,3145	.hwcg_bit = 1,3146	.clkr = {3147		.enable_reg = 0x580a4,3148		.enable_mask = BIT(0),3149		.hw.init = &(struct clk_init_data){3150			.name = "gcc_video_vcodec0_sys_clk",3151			.parent_hws = (const struct clk_hw *[]){3152				&gcc_video_venus_clk_src.clkr.hw,3153			},3154			.num_parents = 1,3155			.flags = CLK_SET_RATE_PARENT,3156			.ops = &clk_branch2_ops,3157		},3158	},3159};3160 3161static struct clk_branch gcc_video_venus_ctl_clk = {3162	.halt_reg = 0x5808c,3163	.halt_check = BRANCH_HALT,3164	.clkr = {3165		.enable_reg = 0x5808c,3166		.enable_mask = BIT(0),3167		.hw.init = &(struct clk_init_data){3168			.name = "gcc_video_venus_ctl_clk",3169			.parent_hws = (const struct clk_hw *[]){3170				&gcc_video_venus_clk_src.clkr.hw,3171			},3172			.num_parents = 1,3173			.flags = CLK_SET_RATE_PARENT,3174			.ops = &clk_branch2_ops,3175		},3176	},3177};3178 3179static struct clk_branch gcc_video_xo_clk = {3180	.halt_reg = 0x17024,3181	.halt_check = BRANCH_HALT,3182	.clkr = {3183		.enable_reg = 0x17024,3184		.enable_mask = BIT(0),3185		.hw.init = &(struct clk_init_data){3186			.name = "gcc_video_xo_clk",3187			.ops = &clk_branch2_ops,3188		},3189	},3190};3191 3192static struct gdsc gcc_camss_top_gdsc = {3193	.gdscr = 0x58004,3194	.pd = {3195		.name = "gcc_camss_top",3196	},3197	.pwrsts = PWRSTS_OFF_ON,3198};3199 3200static struct gdsc gcc_ufs_phy_gdsc = {3201	.gdscr = 0x45004,3202	.pd = {3203		.name = "gcc_ufs_phy",3204	},3205	.pwrsts = PWRSTS_OFF_ON,3206};3207 3208static struct gdsc gcc_usb30_prim_gdsc = {3209	.gdscr = 0x1a004,3210	.pd = {3211		.name = "gcc_usb30_prim",3212	},3213	.pwrsts = PWRSTS_OFF_ON,3214};3215 3216static struct gdsc gcc_vcodec0_gdsc = {3217	.gdscr = 0x58098,3218	.pd = {3219		.name = "gcc_vcodec0",3220	},3221	.pwrsts = PWRSTS_OFF_ON,3222};3223 3224static struct gdsc gcc_venus_gdsc = {3225	.gdscr = 0x5807c,3226	.pd = {3227		.name = "gcc_venus",3228	},3229	.pwrsts = PWRSTS_OFF_ON,3230};3231 3232static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {3233	.gdscr = 0x7d060,3234	.pd = {3235		.name = "hlos1_vote_turing_mmu_tbu1",3236	},3237	.pwrsts = PWRSTS_OFF_ON,3238	.flags = VOTABLE,3239};3240 3241static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {3242	.gdscr = 0x7d07c,3243	.pd = {3244		.name = "hlos1_vote_turing_mmu_tbu0",3245	},3246	.pwrsts = PWRSTS_OFF_ON,3247	.flags = VOTABLE,3248};3249 3250static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {3251	.gdscr = 0x7d074,3252	.pd = {3253		.name = "hlos1_vote_mm_snoc_mmu_tbu_rt",3254	},3255	.pwrsts = PWRSTS_OFF_ON,3256	.flags = VOTABLE,3257};3258 3259static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {3260	.gdscr = 0x7d078,3261	.pd = {3262		.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",3263	},3264	.pwrsts = PWRSTS_OFF_ON,3265	.flags = VOTABLE,3266};3267 3268static struct clk_regmap *gcc_sm6115_clocks[] = {3269	[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,3270	[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,3271	[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,3272	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,3273	[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,3274	[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,3275	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,3276	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,3277	[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,3278	[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,3279	[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,3280	[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,3281	[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,3282	[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,3283	[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,3284	[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,3285	[GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,3286	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,3287	[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,3288	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,3289	[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,3290	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,3291	[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,3292	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,3293	[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,3294	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,3295	[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,3296	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,3297	[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,3298	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,3299	[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,3300	[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,3301	[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,3302	[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,3303	[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,3304	[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,3305	[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,3306	[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,3307	[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,3308	[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,3309	[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,3310	[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,3311	[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,3312	[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,3313	[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,3314	[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,3315	[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,3316	[GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,3317	[GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,3318	[GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,3319	[GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,3320	[GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,3321	[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,3322	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,3323	[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,3324	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,3325	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,3326	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,3327	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,3328	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,3329	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,3330	[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,3331	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,3332	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,3333	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,3334	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,3335	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,3336	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,3337	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,3338	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,3339	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,3340	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,3341	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,3342	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,3343	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,3344	[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,3345	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,3346	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,3347	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,3348	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,3349	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,3350	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,3351	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,3352	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,3353	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,3354	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,3355	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,3356	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,3357	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,3358	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,3359	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,3360	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,3361	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,3362	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,3363	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,3364	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,3365	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,3366	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,3367	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,3368	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,3369	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,3370	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,3371	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,3372	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,3373	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,3374	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,3375	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,3376	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,3377	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,3378	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,3379	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,3380	[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,3381	[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,3382	[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,3383	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,3384	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,3385	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,3386	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,3387	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,3388	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,3389	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,3390	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,3391	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,3392	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,3393	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3394		&gcc_ufs_phy_unipro_core_clk_src.clkr,3395	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,3396	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,3397	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,3398	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3399		&gcc_usb30_prim_mock_utmi_clk_src.clkr,3400	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =3401		&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,3402	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,3403	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,3404	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,3405	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,3406	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,3407	[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,3408	[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,3409	[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,3410	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,3411	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,3412	[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,3413	[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,3414	[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,3415	[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,3416	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,3417	[GPLL0] = &gpll0.clkr,3418	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,3419	[GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,3420	[GPLL10] = &gpll10.clkr,3421	[GPLL10_OUT_MAIN] = &gpll10_out_main.clkr,3422	[GPLL11] = &gpll11.clkr,3423	[GPLL11_OUT_MAIN] = &gpll11_out_main.clkr,3424	[GPLL3] = &gpll3.clkr,3425	[GPLL4] = &gpll4.clkr,3426	[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,3427	[GPLL6] = &gpll6.clkr,3428	[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,3429	[GPLL7] = &gpll7.clkr,3430	[GPLL7_OUT_MAIN] = &gpll7_out_main.clkr,3431	[GPLL8] = &gpll8.clkr,3432	[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,3433	[GPLL9] = &gpll9.clkr,3434	[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,3435};3436 3437static const struct qcom_reset_map gcc_sm6115_resets[] = {3438	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },3439	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },3440	[GCC_SDCC1_BCR] = { 0x38000 },3441	[GCC_SDCC2_BCR] = { 0x1e000 },3442	[GCC_UFS_PHY_BCR] = { 0x45000 },3443	[GCC_USB30_PRIM_BCR] = { 0x1a000 },3444	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },3445	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },3446	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },3447	[GCC_VCODEC0_BCR] = { 0x58094 },3448	[GCC_VENUS_BCR] = { 0x58078 },3449	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },3450};3451 3452static struct gdsc *gcc_sm6115_gdscs[] = {3453	[GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,3454	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,3455	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,3456	[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,3457	[GCC_VENUS_GDSC] = &gcc_venus_gdsc,3458	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,3459	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,3460	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,3461	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,3462};3463 3464static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {3465	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),3466	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),3467	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),3468	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),3469	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),3470	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),3471};3472 3473static const struct regmap_config gcc_sm6115_regmap_config = {3474	.reg_bits = 32,3475	.reg_stride = 4,3476	.val_bits = 32,3477	.max_register = 0xc7000,3478	.fast_io = true,3479};3480 3481static const struct qcom_cc_desc gcc_sm6115_desc = {3482	.config = &gcc_sm6115_regmap_config,3483	.clks = gcc_sm6115_clocks,3484	.num_clks = ARRAY_SIZE(gcc_sm6115_clocks),3485	.resets = gcc_sm6115_resets,3486	.num_resets = ARRAY_SIZE(gcc_sm6115_resets),3487	.gdscs = gcc_sm6115_gdscs,3488	.num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs),3489};3490 3491static const struct of_device_id gcc_sm6115_match_table[] = {3492	{ .compatible = "qcom,gcc-sm6115" },3493	{ }3494};3495MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table);3496 3497static int gcc_sm6115_probe(struct platform_device *pdev)3498{3499	struct regmap *regmap;3500	int ret;3501 3502	regmap = qcom_cc_map(pdev, &gcc_sm6115_desc);3503	if (IS_ERR(regmap))3504		return PTR_ERR(regmap);3505 3506	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,3507			ARRAY_SIZE(gcc_dfs_clocks));3508	if (ret)3509		return ret;3510 3511	clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);3512	clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);3513	clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);3514	clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);3515 3516	return qcom_cc_really_probe(&pdev->dev, &gcc_sm6115_desc, regmap);3517}3518 3519static struct platform_driver gcc_sm6115_driver = {3520	.probe = gcc_sm6115_probe,3521	.driver = {3522		.name = "gcc-sm6115",3523		.of_match_table = gcc_sm6115_match_table,3524	},3525};3526 3527static int __init gcc_sm6115_init(void)3528{3529	return platform_driver_register(&gcc_sm6115_driver);3530}3531subsys_initcall(gcc_sm6115_init);3532 3533static void __exit gcc_sm6115_exit(void)3534{3535	platform_driver_unregister(&gcc_sm6115_driver);3536}3537module_exit(gcc_sm6115_exit);3538 3539MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver");3540MODULE_LICENSE("GPL v2");3541MODULE_ALIAS("platform:gcc-sm6115");3542