brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.3 4#include <linux/kernel.h>5#include <linux/bitops.h>6#include <linux/err.h>7#include <linux/platform_device.h>8#include <linux/module.h>9#include <linux/of.h>10#include <linux/clk-provider.h>11#include <linux/regmap.h>12#include <linux/reset-controller.h>13 14#include <dt-bindings/clock/qcom,gcc-sm8150.h>15 16#include "common.h"17#include "clk-alpha-pll.h"18#include "clk-branch.h"19#include "clk-pll.h"20#include "clk-rcg.h"21#include "clk-regmap.h"22#include "reset.h"23#include "gdsc.h"24 25enum {26	P_BI_TCXO,27	P_AUD_REF_CLK,28	P_GPLL0_OUT_EVEN,29	P_GPLL0_OUT_MAIN,30	P_GPLL7_OUT_MAIN,31	P_GPLL9_OUT_MAIN,32	P_SLEEP_CLK,33};34 35static struct clk_alpha_pll gpll0 = {36	.offset = 0x0,37	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],38	.clkr = {39		.enable_reg = 0x52000,40		.enable_mask = BIT(0),41		.hw.init = &(struct clk_init_data){42			.name = "gpll0",43			.parent_data = &(const struct clk_parent_data){44				.fw_name = "bi_tcxo",45				.name = "bi_tcxo",46			},47			.num_parents = 1,48			.ops = &clk_alpha_pll_fixed_trion_ops,49		},50	},51};52 53static const struct clk_div_table post_div_table_trion_even[] = {54	{ 0x0, 1 },55	{ 0x1, 2 },56	{ 0x3, 4 },57	{ 0x7, 8 },58	{ }59};60 61static struct clk_alpha_pll_postdiv gpll0_out_even = {62	.offset = 0x0,63	.post_div_shift = 8,64	.post_div_table = post_div_table_trion_even,65	.num_post_div = ARRAY_SIZE(post_div_table_trion_even),66	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],67	.width = 4,68	.clkr.hw.init = &(struct clk_init_data){69		.name = "gpll0_out_even",70		.parent_hws = (const struct clk_hw*[]){71			&gpll0.clkr.hw,72		},73		.num_parents = 1,74		.ops = &clk_alpha_pll_postdiv_trion_ops,75	},76};77 78static struct clk_alpha_pll gpll7 = {79	.offset = 0x1a000,80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],81	.clkr = {82		.enable_reg = 0x52000,83		.enable_mask = BIT(7),84		.hw.init = &(struct clk_init_data){85			.name = "gpll7",86			.parent_data = &(const struct clk_parent_data){87				.fw_name = "bi_tcxo",88				.name = "bi_tcxo",89			},90			.num_parents = 1,91			.ops = &clk_alpha_pll_fixed_trion_ops,92		},93	},94};95 96static struct clk_alpha_pll gpll9 = {97	.offset = 0x1c000,98	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],99	.clkr = {100		.enable_reg = 0x52000,101		.enable_mask = BIT(9),102		.hw.init = &(struct clk_init_data){103			.name = "gpll9",104			.parent_data = &(const struct clk_parent_data){105				.fw_name = "bi_tcxo",106				.name = "bi_tcxo",107			},108			.num_parents = 1,109			.ops = &clk_alpha_pll_fixed_trion_ops,110		},111	},112};113 114static const struct parent_map gcc_parent_map_0[] = {115	{ P_BI_TCXO, 0 },116	{ P_GPLL0_OUT_MAIN, 1 },117	{ P_GPLL0_OUT_EVEN, 6 },118};119 120static const struct clk_parent_data gcc_parents_0[] = {121	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },122	{ .hw = &gpll0.clkr.hw },123	{ .hw = &gpll0_out_even.clkr.hw },124};125 126static const struct parent_map gcc_parent_map_1[] = {127	{ P_BI_TCXO, 0 },128	{ P_GPLL0_OUT_MAIN, 1 },129	{ P_SLEEP_CLK, 5 },130	{ P_GPLL0_OUT_EVEN, 6 },131};132 133static const struct clk_parent_data gcc_parents_1[] = {134	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },135	{ .hw = &gpll0.clkr.hw },136	{ .fw_name = "sleep_clk", .name = "sleep_clk" },137	{ .hw = &gpll0_out_even.clkr.hw },138};139 140static const struct parent_map gcc_parent_map_2[] = {141	{ P_BI_TCXO, 0 },142	{ P_SLEEP_CLK, 5 },143};144 145static const struct clk_parent_data gcc_parents_2[] = {146	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },147	{ .fw_name = "sleep_clk", .name = "sleep_clk" },148};149 150static const struct parent_map gcc_parent_map_3[] = {151	{ P_BI_TCXO, 0 },152	{ P_GPLL0_OUT_MAIN, 1 },153};154 155static const struct clk_parent_data gcc_parents_3[] = {156	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },157	{ .hw = &gpll0.clkr.hw },158};159 160static const struct parent_map gcc_parent_map_4[] = {161	{ P_BI_TCXO, 0 },162};163 164static const struct clk_parent_data gcc_parents_4[] = {165	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },166};167 168static const struct parent_map gcc_parent_map_5[] = {169	{ P_BI_TCXO, 0 },170	{ P_GPLL0_OUT_MAIN, 1 },171	{ P_GPLL7_OUT_MAIN, 3 },172	{ P_GPLL0_OUT_EVEN, 6 },173};174 175static const struct clk_parent_data gcc_parents_5[] = {176	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },177	{ .hw = &gpll0.clkr.hw },178	{ .hw = &gpll7.clkr.hw },179	{ .hw = &gpll0_out_even.clkr.hw },180};181 182static const struct parent_map gcc_parent_map_6[] = {183	{ P_BI_TCXO, 0 },184	{ P_GPLL0_OUT_MAIN, 1 },185	{ P_GPLL9_OUT_MAIN, 2 },186	{ P_GPLL0_OUT_EVEN, 6 },187};188 189static const struct clk_parent_data gcc_parents_6[] = {190	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },191	{ .hw = &gpll0.clkr.hw },192	{ .hw = &gpll9.clkr.hw },193	{ .hw = &gpll0_out_even.clkr.hw },194};195 196static const struct parent_map gcc_parent_map_7[] = {197	{ P_BI_TCXO, 0 },198	{ P_GPLL0_OUT_MAIN, 1 },199	{ P_AUD_REF_CLK, 2 },200	{ P_GPLL0_OUT_EVEN, 6 },201};202 203static const struct clk_parent_data gcc_parents_7[] = {204	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },205	{ .hw = &gpll0.clkr.hw },206	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },207	{ .hw = &gpll0_out_even.clkr.hw },208};209 210static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {211	F(19200000, P_BI_TCXO, 1, 0, 0),212	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),213	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),214	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),215	{ }216};217 218static struct clk_rcg2 gcc_emac_ptp_clk_src = {219	.cmd_rcgr = 0x6038,220	.mnd_width = 0,221	.hid_width = 5,222	.parent_map = gcc_parent_map_5,223	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,224	.clkr.hw.init = &(struct clk_init_data){225		.name = "gcc_emac_ptp_clk_src",226		.parent_data = gcc_parents_5,227		.num_parents = ARRAY_SIZE(gcc_parents_5),228		.flags = CLK_SET_RATE_PARENT,229		.ops = &clk_rcg2_ops,230	},231};232 233static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {234	F(2500000, P_BI_TCXO, 1, 25, 192),235	F(5000000, P_BI_TCXO, 1, 25, 96),236	F(19200000, P_BI_TCXO, 1, 0, 0),237	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),238	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),239	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),240	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),241	{ }242};243 244static struct clk_rcg2 gcc_emac_rgmii_clk_src = {245	.cmd_rcgr = 0x601c,246	.mnd_width = 8,247	.hid_width = 5,248	.parent_map = gcc_parent_map_5,249	.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,250	.clkr.hw.init = &(struct clk_init_data){251		.name = "gcc_emac_rgmii_clk_src",252		.parent_data = gcc_parents_5,253		.num_parents = ARRAY_SIZE(gcc_parents_5),254		.flags = CLK_SET_RATE_PARENT,255		.ops = &clk_rcg2_ops,256	},257};258 259static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {260	F(19200000, P_BI_TCXO, 1, 0, 0),261	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),262	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),263	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),264	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),265	{ }266};267 268static struct clk_rcg2 gcc_gp1_clk_src = {269	.cmd_rcgr = 0x64004,270	.mnd_width = 8,271	.hid_width = 5,272	.parent_map = gcc_parent_map_1,273	.freq_tbl = ftbl_gcc_gp1_clk_src,274	.clkr.hw.init = &(struct clk_init_data){275		.name = "gcc_gp1_clk_src",276		.parent_data = gcc_parents_1,277		.num_parents = ARRAY_SIZE(gcc_parents_1),278		.flags = CLK_SET_RATE_PARENT,279		.ops = &clk_rcg2_ops,280	},281};282 283static struct clk_rcg2 gcc_gp2_clk_src = {284	.cmd_rcgr = 0x65004,285	.mnd_width = 8,286	.hid_width = 5,287	.parent_map = gcc_parent_map_1,288	.freq_tbl = ftbl_gcc_gp1_clk_src,289	.clkr.hw.init = &(struct clk_init_data){290		.name = "gcc_gp2_clk_src",291		.parent_data = gcc_parents_1,292		.num_parents = ARRAY_SIZE(gcc_parents_1),293		.flags = CLK_SET_RATE_PARENT,294		.ops = &clk_rcg2_ops,295	},296};297 298static struct clk_rcg2 gcc_gp3_clk_src = {299	.cmd_rcgr = 0x66004,300	.mnd_width = 8,301	.hid_width = 5,302	.parent_map = gcc_parent_map_1,303	.freq_tbl = ftbl_gcc_gp1_clk_src,304	.clkr.hw.init = &(struct clk_init_data){305		.name = "gcc_gp3_clk_src",306		.parent_data = gcc_parents_1,307		.num_parents = ARRAY_SIZE(gcc_parents_1),308		.flags = CLK_SET_RATE_PARENT,309		.ops = &clk_rcg2_ops,310	},311};312 313static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {314	F(9600000, P_BI_TCXO, 2, 0, 0),315	F(19200000, P_BI_TCXO, 1, 0, 0),316	{ }317};318 319static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {320	.cmd_rcgr = 0x6b02c,321	.mnd_width = 16,322	.hid_width = 5,323	.parent_map = gcc_parent_map_2,324	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,325	.clkr.hw.init = &(struct clk_init_data){326		.name = "gcc_pcie_0_aux_clk_src",327		.parent_data = gcc_parents_2,328		.num_parents = ARRAY_SIZE(gcc_parents_2),329		.flags = CLK_SET_RATE_PARENT,330		.ops = &clk_rcg2_ops,331	},332};333 334static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {335	.cmd_rcgr = 0x8d02c,336	.mnd_width = 16,337	.hid_width = 5,338	.parent_map = gcc_parent_map_2,339	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,340	.clkr.hw.init = &(struct clk_init_data){341		.name = "gcc_pcie_1_aux_clk_src",342		.parent_data = gcc_parents_2,343		.num_parents = ARRAY_SIZE(gcc_parents_2),344		.flags = CLK_SET_RATE_PARENT,345		.ops = &clk_rcg2_ops,346	},347};348 349static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {350	F(19200000, P_BI_TCXO, 1, 0, 0),351	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),352	{ }353};354 355static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {356	.cmd_rcgr = 0x6f014,357	.mnd_width = 0,358	.hid_width = 5,359	.parent_map = gcc_parent_map_0,360	.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,361	.clkr.hw.init = &(struct clk_init_data){362		.name = "gcc_pcie_phy_refgen_clk_src",363		.parent_data = gcc_parents_0,364		.num_parents = ARRAY_SIZE(gcc_parents_0),365		.flags = CLK_SET_RATE_PARENT,366		.ops = &clk_rcg2_ops,367	},368};369 370static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {371	F(9600000, P_BI_TCXO, 2, 0, 0),372	F(19200000, P_BI_TCXO, 1, 0, 0),373	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),374	{ }375};376 377static struct clk_rcg2 gcc_pdm2_clk_src = {378	.cmd_rcgr = 0x33010,379	.mnd_width = 0,380	.hid_width = 5,381	.parent_map = gcc_parent_map_0,382	.freq_tbl = ftbl_gcc_pdm2_clk_src,383	.clkr.hw.init = &(struct clk_init_data){384		.name = "gcc_pdm2_clk_src",385		.parent_data = gcc_parents_0,386		.num_parents = ARRAY_SIZE(gcc_parents_0),387		.flags = CLK_SET_RATE_PARENT,388		.ops = &clk_rcg2_ops,389	},390};391 392static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {393	F(19200000, P_BI_TCXO, 1, 0, 0),394	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),395	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),396	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),397	{ }398};399 400static struct clk_rcg2 gcc_qspi_core_clk_src = {401	.cmd_rcgr = 0x4b008,402	.mnd_width = 0,403	.hid_width = 5,404	.parent_map = gcc_parent_map_0,405	.freq_tbl = ftbl_gcc_qspi_core_clk_src,406	.clkr.hw.init = &(struct clk_init_data){407		.name = "gcc_qspi_core_clk_src",408		.parent_data = gcc_parents_0,409		.num_parents = ARRAY_SIZE(gcc_parents_0),410		.flags = CLK_SET_RATE_PARENT,411		.ops = &clk_rcg2_ops,412	},413};414 415static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {416	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),417	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),418	F(19200000, P_BI_TCXO, 1, 0, 0),419	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),420	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),421	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),422	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),423	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),424	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),425	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),426	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),427	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),428	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),429	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),430	F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),431	{ }432};433 434static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {435	.name = "gcc_qupv3_wrap0_s0_clk_src",436	.parent_data = gcc_parents_0,437	.num_parents = ARRAY_SIZE(gcc_parents_0),438	.flags = CLK_SET_RATE_PARENT,439	.ops = &clk_rcg2_ops,440};441 442static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {443	.cmd_rcgr = 0x17148,444	.mnd_width = 16,445	.hid_width = 5,446	.parent_map = gcc_parent_map_0,447	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,448	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,449};450 451static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {452	.name = "gcc_qupv3_wrap0_s1_clk_src",453	.parent_data = gcc_parents_0,454	.num_parents = ARRAY_SIZE(gcc_parents_0),455	.flags = CLK_SET_RATE_PARENT,456	.ops = &clk_rcg2_ops,457};458 459static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {460	.cmd_rcgr = 0x17278,461	.mnd_width = 16,462	.hid_width = 5,463	.parent_map = gcc_parent_map_0,464	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,465	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,466};467 468static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {469	.name = "gcc_qupv3_wrap0_s2_clk_src",470	.parent_data = gcc_parents_0,471	.num_parents = ARRAY_SIZE(gcc_parents_0),472	.flags = CLK_SET_RATE_PARENT,473	.ops = &clk_rcg2_ops,474};475 476static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {477	.cmd_rcgr = 0x173a8,478	.mnd_width = 16,479	.hid_width = 5,480	.parent_map = gcc_parent_map_0,481	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,482	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,483};484 485static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {486	.name = "gcc_qupv3_wrap0_s3_clk_src",487	.parent_data = gcc_parents_0,488	.num_parents = ARRAY_SIZE(gcc_parents_0),489	.flags = CLK_SET_RATE_PARENT,490	.ops = &clk_rcg2_ops,491};492 493static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {494	.cmd_rcgr = 0x174d8,495	.mnd_width = 16,496	.hid_width = 5,497	.parent_map = gcc_parent_map_0,498	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,499	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,500};501 502static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {503	.name = "gcc_qupv3_wrap0_s4_clk_src",504	.parent_data = gcc_parents_0,505	.num_parents = ARRAY_SIZE(gcc_parents_0),506	.flags = CLK_SET_RATE_PARENT,507	.ops = &clk_rcg2_ops,508};509 510static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {511	.cmd_rcgr = 0x17608,512	.mnd_width = 16,513	.hid_width = 5,514	.parent_map = gcc_parent_map_0,515	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,516	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,517};518 519static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {520	.name = "gcc_qupv3_wrap0_s5_clk_src",521	.parent_data = gcc_parents_0,522	.num_parents = ARRAY_SIZE(gcc_parents_0),523	.flags = CLK_SET_RATE_PARENT,524	.ops = &clk_rcg2_ops,525};526 527static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {528	.cmd_rcgr = 0x17738,529	.mnd_width = 16,530	.hid_width = 5,531	.parent_map = gcc_parent_map_0,532	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,533	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,534};535 536static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {537	.name = "gcc_qupv3_wrap0_s6_clk_src",538	.parent_data = gcc_parents_0,539	.num_parents = ARRAY_SIZE(gcc_parents_0),540	.flags = CLK_SET_RATE_PARENT,541	.ops = &clk_rcg2_ops,542};543 544static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {545	.cmd_rcgr = 0x17868,546	.mnd_width = 16,547	.hid_width = 5,548	.parent_map = gcc_parent_map_0,549	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,550	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,551};552 553static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {554	.name = "gcc_qupv3_wrap0_s7_clk_src",555	.parent_data = gcc_parents_0,556	.num_parents = ARRAY_SIZE(gcc_parents_0),557	.flags = CLK_SET_RATE_PARENT,558	.ops = &clk_rcg2_ops,559};560 561static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {562	.cmd_rcgr = 0x17998,563	.mnd_width = 16,564	.hid_width = 5,565	.parent_map = gcc_parent_map_0,566	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,567	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,568};569 570static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {571	.name = "gcc_qupv3_wrap1_s0_clk_src",572	.parent_data = gcc_parents_0,573	.num_parents = ARRAY_SIZE(gcc_parents_0),574	.flags = CLK_SET_RATE_PARENT,575	.ops = &clk_rcg2_ops,576};577 578static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {579	.cmd_rcgr = 0x18148,580	.mnd_width = 16,581	.hid_width = 5,582	.parent_map = gcc_parent_map_0,583	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,584	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,585};586 587static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {588	.name = "gcc_qupv3_wrap1_s1_clk_src",589	.parent_data = gcc_parents_0,590	.num_parents = ARRAY_SIZE(gcc_parents_0),591	.flags = CLK_SET_RATE_PARENT,592	.ops = &clk_rcg2_ops,593};594 595static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {596	.cmd_rcgr = 0x18278,597	.mnd_width = 16,598	.hid_width = 5,599	.parent_map = gcc_parent_map_0,600	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,601	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,602};603 604static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {605	.name = "gcc_qupv3_wrap1_s2_clk_src",606	.parent_data = gcc_parents_0,607	.num_parents = ARRAY_SIZE(gcc_parents_0),608	.flags = CLK_SET_RATE_PARENT,609	.ops = &clk_rcg2_ops,610};611 612static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {613	.cmd_rcgr = 0x183a8,614	.mnd_width = 16,615	.hid_width = 5,616	.parent_map = gcc_parent_map_0,617	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,618	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,619};620 621static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {622	.name = "gcc_qupv3_wrap1_s3_clk_src",623	.parent_data = gcc_parents_0,624	.num_parents = ARRAY_SIZE(gcc_parents_0),625	.flags = CLK_SET_RATE_PARENT,626	.ops = &clk_rcg2_ops,627};628 629static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {630	.cmd_rcgr = 0x184d8,631	.mnd_width = 16,632	.hid_width = 5,633	.parent_map = gcc_parent_map_0,634	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,635	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,636};637 638static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {639	.name = "gcc_qupv3_wrap1_s4_clk_src",640	.parent_data = gcc_parents_0,641	.num_parents = ARRAY_SIZE(gcc_parents_0),642	.flags = CLK_SET_RATE_PARENT,643	.ops = &clk_rcg2_ops,644};645 646static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {647	.cmd_rcgr = 0x18608,648	.mnd_width = 16,649	.hid_width = 5,650	.parent_map = gcc_parent_map_0,651	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,652	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,653};654 655static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {656	.name = "gcc_qupv3_wrap1_s5_clk_src",657	.parent_data = gcc_parents_0,658	.num_parents = ARRAY_SIZE(gcc_parents_0),659	.flags = CLK_SET_RATE_PARENT,660	.ops = &clk_rcg2_ops,661};662 663static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {664	.cmd_rcgr = 0x18738,665	.mnd_width = 16,666	.hid_width = 5,667	.parent_map = gcc_parent_map_0,668	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,669	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,670};671 672static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {673	.name = "gcc_qupv3_wrap2_s0_clk_src",674	.parent_data = gcc_parents_0,675	.num_parents = ARRAY_SIZE(gcc_parents_0),676	.flags = CLK_SET_RATE_PARENT,677	.ops = &clk_rcg2_ops,678};679 680static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {681	.cmd_rcgr = 0x1e148,682	.mnd_width = 16,683	.hid_width = 5,684	.parent_map = gcc_parent_map_0,685	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,686	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,687};688 689static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {690	.name = "gcc_qupv3_wrap2_s1_clk_src",691	.parent_data = gcc_parents_0,692	.num_parents = ARRAY_SIZE(gcc_parents_0),693	.flags = CLK_SET_RATE_PARENT,694	.ops = &clk_rcg2_ops,695};696 697static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {698	.cmd_rcgr = 0x1e278,699	.mnd_width = 16,700	.hid_width = 5,701	.parent_map = gcc_parent_map_0,702	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,703	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,704};705 706static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {707	.name = "gcc_qupv3_wrap2_s2_clk_src",708	.parent_data = gcc_parents_0,709	.num_parents = ARRAY_SIZE(gcc_parents_0),710	.flags = CLK_SET_RATE_PARENT,711	.ops = &clk_rcg2_ops,712};713 714static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {715	.cmd_rcgr = 0x1e3a8,716	.mnd_width = 16,717	.hid_width = 5,718	.parent_map = gcc_parent_map_0,719	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,720	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,721};722 723static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {724	.name = "gcc_qupv3_wrap2_s3_clk_src",725	.parent_data = gcc_parents_0,726	.num_parents = ARRAY_SIZE(gcc_parents_0),727	.flags = CLK_SET_RATE_PARENT,728	.ops = &clk_rcg2_ops,729};730 731static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {732	.cmd_rcgr = 0x1e4d8,733	.mnd_width = 16,734	.hid_width = 5,735	.parent_map = gcc_parent_map_0,736	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,737	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,738};739 740static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {741	.name = "gcc_qupv3_wrap2_s4_clk_src",742	.parent_data = gcc_parents_0,743	.num_parents = ARRAY_SIZE(gcc_parents_0),744	.flags = CLK_SET_RATE_PARENT,745	.ops = &clk_rcg2_ops,746};747 748static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {749	.cmd_rcgr = 0x1e608,750	.mnd_width = 16,751	.hid_width = 5,752	.parent_map = gcc_parent_map_0,753	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,754	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,755};756 757static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {758	.name = "gcc_qupv3_wrap2_s5_clk_src",759	.parent_data = gcc_parents_0,760	.num_parents = ARRAY_SIZE(gcc_parents_0),761	.flags = CLK_SET_RATE_PARENT,762	.ops = &clk_rcg2_ops,763};764 765static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {766	.cmd_rcgr = 0x1e738,767	.mnd_width = 16,768	.hid_width = 5,769	.parent_map = gcc_parent_map_0,770	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,771	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,772};773 774static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {775	F(400000, P_BI_TCXO, 12, 1, 4),776	F(9600000, P_BI_TCXO, 2, 0, 0),777	F(19200000, P_BI_TCXO, 1, 0, 0),778	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),779	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),780	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),781	F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),782	{ }783};784 785static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {786	.cmd_rcgr = 0x1400c,787	.mnd_width = 8,788	.hid_width = 5,789	.parent_map = gcc_parent_map_6,790	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,791	.clkr.hw.init = &(struct clk_init_data){792		.name = "gcc_sdcc2_apps_clk_src",793		.parent_data = gcc_parents_6,794		.num_parents = ARRAY_SIZE(gcc_parents_6),795		.flags = CLK_OPS_PARENT_ENABLE,796		.ops = &clk_rcg2_floor_ops,797	},798};799 800static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {801	F(400000, P_BI_TCXO, 12, 1, 4),802	F(9600000, P_BI_TCXO, 2, 0, 0),803	F(19200000, P_BI_TCXO, 1, 0, 0),804	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),805	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),806	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),807	{ }808};809 810static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {811	.cmd_rcgr = 0x1600c,812	.mnd_width = 8,813	.hid_width = 5,814	.parent_map = gcc_parent_map_3,815	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,816	.clkr.hw.init = &(struct clk_init_data){817		.name = "gcc_sdcc4_apps_clk_src",818		.parent_data = gcc_parents_3,819		.num_parents = ARRAY_SIZE(gcc_parents_3),820		.flags = CLK_SET_RATE_PARENT,821		.ops = &clk_rcg2_floor_ops,822	},823};824 825static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {826	F(105495, P_BI_TCXO, 2, 1, 91),827	{ }828};829 830static struct clk_rcg2 gcc_tsif_ref_clk_src = {831	.cmd_rcgr = 0x36010,832	.mnd_width = 8,833	.hid_width = 5,834	.parent_map = gcc_parent_map_7,835	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,836	.clkr.hw.init = &(struct clk_init_data){837		.name = "gcc_tsif_ref_clk_src",838		.parent_data = gcc_parents_7,839		.num_parents = ARRAY_SIZE(gcc_parents_7),840		.flags = CLK_SET_RATE_PARENT,841		.ops = &clk_rcg2_ops,842	},843};844 845static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {846	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),847	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),848	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),849	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),850	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),851	{ }852};853 854static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {855	.cmd_rcgr = 0x75020,856	.mnd_width = 8,857	.hid_width = 5,858	.parent_map = gcc_parent_map_0,859	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,860	.clkr.hw.init = &(struct clk_init_data){861		.name = "gcc_ufs_card_axi_clk_src",862		.parent_data = gcc_parents_0,863		.num_parents = ARRAY_SIZE(gcc_parents_0),864		.flags = CLK_SET_RATE_PARENT,865		.ops = &clk_rcg2_ops,866	},867};868 869static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {870	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),871	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),872	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),873	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),874	{ }875};876 877static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {878	.cmd_rcgr = 0x75060,879	.mnd_width = 0,880	.hid_width = 5,881	.parent_map = gcc_parent_map_0,882	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,883	.clkr.hw.init = &(struct clk_init_data){884		.name = "gcc_ufs_card_ice_core_clk_src",885		.parent_data = gcc_parents_0,886		.num_parents = ARRAY_SIZE(gcc_parents_0),887		.flags = CLK_SET_RATE_PARENT,888		.ops = &clk_rcg2_ops,889	},890};891 892static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {893	F(19200000, P_BI_TCXO, 1, 0, 0),894	{ }895};896 897static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {898	.cmd_rcgr = 0x75094,899	.mnd_width = 0,900	.hid_width = 5,901	.parent_map = gcc_parent_map_4,902	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,903	.clkr.hw.init = &(struct clk_init_data){904		.name = "gcc_ufs_card_phy_aux_clk_src",905		.parent_data = gcc_parents_4,906		.num_parents = ARRAY_SIZE(gcc_parents_4),907		.flags = CLK_SET_RATE_PARENT,908		.ops = &clk_rcg2_ops,909	},910};911 912static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {913	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),914	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),915	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),916	{ }917};918 919static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {920	.cmd_rcgr = 0x75078,921	.mnd_width = 0,922	.hid_width = 5,923	.parent_map = gcc_parent_map_0,924	.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,925	.clkr.hw.init = &(struct clk_init_data){926		.name = "gcc_ufs_card_unipro_core_clk_src",927		.parent_data = gcc_parents_0,928		.num_parents = ARRAY_SIZE(gcc_parents_0),929		.flags = CLK_SET_RATE_PARENT,930		.ops = &clk_rcg2_ops,931	},932};933 934static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {935	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),936	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),937	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),938	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),939	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),940	{ }941};942 943static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {944	.cmd_rcgr = 0x77020,945	.mnd_width = 8,946	.hid_width = 5,947	.parent_map = gcc_parent_map_0,948	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,949	.clkr.hw.init = &(struct clk_init_data){950		.name = "gcc_ufs_phy_axi_clk_src",951		.parent_data = gcc_parents_0,952		.num_parents = ARRAY_SIZE(gcc_parents_0),953		.flags = CLK_SET_RATE_PARENT,954		.ops = &clk_rcg2_ops,955	},956};957 958static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {959	.cmd_rcgr = 0x77060,960	.mnd_width = 0,961	.hid_width = 5,962	.parent_map = gcc_parent_map_0,963	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,964	.clkr.hw.init = &(struct clk_init_data){965		.name = "gcc_ufs_phy_ice_core_clk_src",966		.parent_data = gcc_parents_0,967		.num_parents = ARRAY_SIZE(gcc_parents_0),968		.flags = CLK_SET_RATE_PARENT,969		.ops = &clk_rcg2_ops,970	},971};972 973static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {974	.cmd_rcgr = 0x77094,975	.mnd_width = 0,976	.hid_width = 5,977	.parent_map = gcc_parent_map_4,978	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,979	.clkr.hw.init = &(struct clk_init_data){980		.name = "gcc_ufs_phy_phy_aux_clk_src",981		.parent_data = gcc_parents_4,982		.num_parents = ARRAY_SIZE(gcc_parents_4),983		.flags = CLK_SET_RATE_PARENT,984		.ops = &clk_rcg2_ops,985	},986};987 988static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {989	.cmd_rcgr = 0x77078,990	.mnd_width = 0,991	.hid_width = 5,992	.parent_map = gcc_parent_map_0,993	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,994	.clkr.hw.init = &(struct clk_init_data){995		.name = "gcc_ufs_phy_unipro_core_clk_src",996		.parent_data = gcc_parents_0,997		.num_parents = ARRAY_SIZE(gcc_parents_0),998		.flags = CLK_SET_RATE_PARENT,999		.ops = &clk_rcg2_ops,1000	},1001};1002 1003static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {1004	F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),1005	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),1006	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),1007	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),1008	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),1009	{ }1010};1011 1012static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {1013	.cmd_rcgr = 0xf01c,1014	.mnd_width = 8,1015	.hid_width = 5,1016	.parent_map = gcc_parent_map_0,1017	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,1018	.clkr.hw.init = &(struct clk_init_data){1019		.name = "gcc_usb30_prim_master_clk_src",1020		.parent_data = gcc_parents_0,1021		.num_parents = ARRAY_SIZE(gcc_parents_0),1022		.flags = CLK_SET_RATE_PARENT,1023		.ops = &clk_rcg2_ops,1024	},1025};1026 1027static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {1028	F(19200000, P_BI_TCXO, 1, 0, 0),1029	F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),1030	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),1031	{ }1032};1033 1034static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {1035	.cmd_rcgr = 0xf034,1036	.mnd_width = 0,1037	.hid_width = 5,1038	.parent_map = gcc_parent_map_0,1039	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,1040	.clkr.hw.init = &(struct clk_init_data){1041		.name = "gcc_usb30_prim_mock_utmi_clk_src",1042		.parent_data = gcc_parents_0,1043		.num_parents = ARRAY_SIZE(gcc_parents_0),1044		.flags = CLK_SET_RATE_PARENT,1045		.ops = &clk_rcg2_ops,1046	},1047};1048 1049static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {1050	.cmd_rcgr = 0x1001c,1051	.mnd_width = 8,1052	.hid_width = 5,1053	.parent_map = gcc_parent_map_0,1054	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,1055	.clkr.hw.init = &(struct clk_init_data){1056		.name = "gcc_usb30_sec_master_clk_src",1057		.parent_data = gcc_parents_0,1058		.num_parents = ARRAY_SIZE(gcc_parents_0),1059		.flags = CLK_SET_RATE_PARENT,1060		.ops = &clk_rcg2_ops,1061	},1062};1063 1064static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {1065	.cmd_rcgr = 0x10034,1066	.mnd_width = 0,1067	.hid_width = 5,1068	.parent_map = gcc_parent_map_0,1069	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,1070	.clkr.hw.init = &(struct clk_init_data){1071		.name = "gcc_usb30_sec_mock_utmi_clk_src",1072		.parent_data = gcc_parents_0,1073		.num_parents = ARRAY_SIZE(gcc_parents_0),1074		.flags = CLK_SET_RATE_PARENT,1075		.ops = &clk_rcg2_ops,1076	},1077};1078 1079static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {1080	.cmd_rcgr = 0xf060,1081	.mnd_width = 0,1082	.hid_width = 5,1083	.parent_map = gcc_parent_map_2,1084	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,1085	.clkr.hw.init = &(struct clk_init_data){1086		.name = "gcc_usb3_prim_phy_aux_clk_src",1087		.parent_data = gcc_parents_2,1088		.num_parents = ARRAY_SIZE(gcc_parents_2),1089		.flags = CLK_SET_RATE_PARENT,1090		.ops = &clk_rcg2_ops,1091	},1092};1093 1094static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {1095	.cmd_rcgr = 0x10060,1096	.mnd_width = 0,1097	.hid_width = 5,1098	.parent_map = gcc_parent_map_2,1099	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,1100	.clkr.hw.init = &(struct clk_init_data){1101		.name = "gcc_usb3_sec_phy_aux_clk_src",1102		.parent_data = gcc_parents_2,1103		.num_parents = ARRAY_SIZE(gcc_parents_2),1104		.flags = CLK_SET_RATE_PARENT,1105		.ops = &clk_rcg2_ops,1106	},1107};1108 1109static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {1110	.halt_reg = 0x90018,1111	.halt_check = BRANCH_HALT,1112	.clkr = {1113		.enable_reg = 0x90018,1114		.enable_mask = BIT(0),1115		.hw.init = &(struct clk_init_data){1116			.name = "gcc_aggre_noc_pcie_tbu_clk",1117			.ops = &clk_branch2_ops,1118		},1119	},1120};1121 1122static struct clk_branch gcc_aggre_ufs_card_axi_clk = {1123	.halt_reg = 0x750c0,1124	.halt_check = BRANCH_HALT,1125	.hwcg_reg = 0x750c0,1126	.hwcg_bit = 1,1127	.clkr = {1128		.enable_reg = 0x750c0,1129		.enable_mask = BIT(0),1130		.hw.init = &(struct clk_init_data){1131			.name = "gcc_aggre_ufs_card_axi_clk",1132			.parent_hws = (const struct clk_hw *[]){1133				      &gcc_ufs_card_axi_clk_src.clkr.hw },1134			.num_parents = 1,1135			.flags = CLK_SET_RATE_PARENT,1136			.ops = &clk_branch2_ops,1137		},1138	},1139};1140 1141static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {1142	.halt_reg = 0x750c0,1143	.halt_check = BRANCH_HALT,1144	.hwcg_reg = 0x750c0,1145	.hwcg_bit = 1,1146	.clkr = {1147		.enable_reg = 0x750c0,1148		.enable_mask = BIT(1),1149		.hw.init = &(struct clk_init_data){1150			.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",1151			.parent_hws = (const struct clk_hw *[]){1152				      &gcc_aggre_ufs_card_axi_clk.clkr.hw },1153			.num_parents = 1,1154			.flags = CLK_SET_RATE_PARENT,1155			.ops = &clk_branch_simple_ops,1156		},1157	},1158};1159 1160static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {1161	.halt_reg = 0x770c0,1162	.halt_check = BRANCH_HALT,1163	.hwcg_reg = 0x770c0,1164	.hwcg_bit = 1,1165	.clkr = {1166		.enable_reg = 0x770c0,1167		.enable_mask = BIT(0),1168		.hw.init = &(struct clk_init_data){1169			.name = "gcc_aggre_ufs_phy_axi_clk",1170			.parent_hws = (const struct clk_hw *[]){1171				      &gcc_ufs_phy_axi_clk_src.clkr.hw },1172			.num_parents = 1,1173			.flags = CLK_SET_RATE_PARENT,1174			.ops = &clk_branch2_ops,1175		},1176	},1177};1178 1179static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {1180	.halt_reg = 0x770c0,1181	.halt_check = BRANCH_HALT,1182	.hwcg_reg = 0x770c0,1183	.hwcg_bit = 1,1184	.clkr = {1185		.enable_reg = 0x770c0,1186		.enable_mask = BIT(1),1187		.hw.init = &(struct clk_init_data){1188			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",1189			.parent_hws = (const struct clk_hw *[]){1190				      &gcc_aggre_ufs_phy_axi_clk.clkr.hw },1191			.num_parents = 1,1192			.flags = CLK_SET_RATE_PARENT,1193			.ops = &clk_branch_simple_ops,1194		},1195	},1196};1197 1198static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {1199	.halt_reg = 0xf07c,1200	.halt_check = BRANCH_HALT,1201	.clkr = {1202		.enable_reg = 0xf07c,1203		.enable_mask = BIT(0),1204		.hw.init = &(struct clk_init_data){1205			.name = "gcc_aggre_usb3_prim_axi_clk",1206			.parent_hws = (const struct clk_hw *[]){1207				      &gcc_usb30_prim_master_clk_src.clkr.hw },1208			.num_parents = 1,1209			.flags = CLK_SET_RATE_PARENT,1210			.ops = &clk_branch2_ops,1211		},1212	},1213};1214 1215static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {1216	.halt_reg = 0x1007c,1217	.halt_check = BRANCH_HALT,1218	.clkr = {1219		.enable_reg = 0x1007c,1220		.enable_mask = BIT(0),1221		.hw.init = &(struct clk_init_data){1222			.name = "gcc_aggre_usb3_sec_axi_clk",1223			.parent_hws = (const struct clk_hw *[]){1224				      &gcc_usb30_sec_master_clk_src.clkr.hw },1225			.num_parents = 1,1226			.flags = CLK_SET_RATE_PARENT,1227			.ops = &clk_branch2_ops,1228		},1229	},1230};1231 1232static struct clk_branch gcc_boot_rom_ahb_clk = {1233	.halt_reg = 0x38004,1234	.halt_check = BRANCH_HALT_VOTED,1235	.hwcg_reg = 0x38004,1236	.hwcg_bit = 1,1237	.clkr = {1238		.enable_reg = 0x52004,1239		.enable_mask = BIT(10),1240		.hw.init = &(struct clk_init_data){1241			.name = "gcc_boot_rom_ahb_clk",1242			.ops = &clk_branch2_ops,1243		},1244	},1245};1246 1247/*1248 * Clock ON depends on external parent 'config noc', so cant poll1249 * delay and also mark as crtitical for camss boot1250 */1251static struct clk_branch gcc_camera_ahb_clk = {1252	.halt_reg = 0xb008,1253	.halt_check = BRANCH_HALT_DELAY,1254	.hwcg_reg = 0xb008,1255	.hwcg_bit = 1,1256	.clkr = {1257		.enable_reg = 0xb008,1258		.enable_mask = BIT(0),1259		.hw.init = &(struct clk_init_data){1260			.name = "gcc_camera_ahb_clk",1261			.flags = CLK_IS_CRITICAL,1262			.ops = &clk_branch2_ops,1263		},1264	},1265};1266 1267static struct clk_branch gcc_camera_hf_axi_clk = {1268	.halt_reg = 0xb030,1269	.halt_check = BRANCH_HALT,1270	.clkr = {1271		.enable_reg = 0xb030,1272		.enable_mask = BIT(0),1273		.hw.init = &(struct clk_init_data){1274			.name = "gcc_camera_hf_axi_clk",1275			.ops = &clk_branch2_ops,1276		},1277	},1278};1279 1280static struct clk_branch gcc_camera_sf_axi_clk = {1281	.halt_reg = 0xb034,1282	.halt_check = BRANCH_HALT,1283	.clkr = {1284		.enable_reg = 0xb034,1285		.enable_mask = BIT(0),1286		.hw.init = &(struct clk_init_data){1287			.name = "gcc_camera_sf_axi_clk",1288			.ops = &clk_branch2_ops,1289		},1290	},1291};1292 1293/* XO critical input to camss, so no need to poll */1294static struct clk_branch gcc_camera_xo_clk = {1295	.halt_reg = 0xb044,1296	.halt_check = BRANCH_HALT_DELAY,1297	.clkr = {1298		.enable_reg = 0xb044,1299		.enable_mask = BIT(0),1300		.hw.init = &(struct clk_init_data){1301			.name = "gcc_camera_xo_clk",1302			.flags = CLK_IS_CRITICAL,1303			.ops = &clk_branch2_ops,1304		},1305	},1306};1307 1308static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {1309	.halt_reg = 0xf078,1310	.halt_check = BRANCH_HALT,1311	.clkr = {1312		.enable_reg = 0xf078,1313		.enable_mask = BIT(0),1314		.hw.init = &(struct clk_init_data){1315			.name = "gcc_cfg_noc_usb3_prim_axi_clk",1316			.parent_hws = (const struct clk_hw *[]){1317				      &gcc_usb30_prim_master_clk_src.clkr.hw },1318			.num_parents = 1,1319			.flags = CLK_SET_RATE_PARENT,1320			.ops = &clk_branch2_ops,1321		},1322	},1323};1324 1325static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {1326	.halt_reg = 0x10078,1327	.halt_check = BRANCH_HALT,1328	.clkr = {1329		.enable_reg = 0x10078,1330		.enable_mask = BIT(0),1331		.hw.init = &(struct clk_init_data){1332			.name = "gcc_cfg_noc_usb3_sec_axi_clk",1333			.parent_hws = (const struct clk_hw *[]){1334				      &gcc_usb30_sec_master_clk_src.clkr.hw },1335			.num_parents = 1,1336			.flags = CLK_SET_RATE_PARENT,1337			.ops = &clk_branch2_ops,1338		},1339	},1340};1341 1342static struct clk_branch gcc_cpuss_dvm_bus_clk = {1343	.halt_reg = 0x48190,1344	.halt_check = BRANCH_HALT,1345	.clkr = {1346		.enable_reg = 0x48190,1347		.enable_mask = BIT(0),1348		.hw.init = &(struct clk_init_data){1349			.name = "gcc_cpuss_dvm_bus_clk",1350			 /* required for cpuss */1351			.flags = CLK_IS_CRITICAL,1352			.ops = &clk_branch2_ops,1353		},1354	},1355};1356 1357static struct clk_branch gcc_cpuss_gnoc_clk = {1358	.halt_reg = 0x48004,1359	.halt_check = BRANCH_HALT_VOTED,1360	.hwcg_reg = 0x48004,1361	.hwcg_bit = 1,1362	.clkr = {1363		.enable_reg = 0x52004,1364		.enable_mask = BIT(22),1365		.hw.init = &(struct clk_init_data){1366			.name = "gcc_cpuss_gnoc_clk",1367			 /* required for cpuss */1368			.flags = CLK_IS_CRITICAL,1369			.ops = &clk_branch2_ops,1370		},1371	},1372};1373 1374static struct clk_branch gcc_cpuss_rbcpr_clk = {1375	.halt_reg = 0x48008,1376	.halt_check = BRANCH_HALT,1377	.clkr = {1378		.enable_reg = 0x48008,1379		.enable_mask = BIT(0),1380		.hw.init = &(struct clk_init_data){1381			.name = "gcc_cpuss_rbcpr_clk",1382			.ops = &clk_branch2_ops,1383		},1384	},1385};1386 1387static struct clk_branch gcc_ddrss_gpu_axi_clk = {1388	.halt_reg = 0x71154,1389	.halt_check = BRANCH_VOTED,1390	.clkr = {1391		.enable_reg = 0x71154,1392		.enable_mask = BIT(0),1393		.hw.init = &(struct clk_init_data){1394			.name = "gcc_ddrss_gpu_axi_clk",1395			.ops = &clk_branch2_ops,1396		},1397	},1398};1399 1400/*1401 * Clock ON depends on external parent 'config noc', so cant poll1402 * delay and also mark as crtitical for disp boot1403 */1404static struct clk_branch gcc_disp_ahb_clk = {1405	.halt_reg = 0xb00c,1406	.halt_check = BRANCH_HALT_DELAY,1407	.hwcg_reg = 0xb00c,1408	.hwcg_bit = 1,1409	.clkr = {1410		.enable_reg = 0xb00c,1411		.enable_mask = BIT(0),1412		.hw.init = &(struct clk_init_data){1413			.name = "gcc_disp_ahb_clk",1414			.flags = CLK_IS_CRITICAL,1415			.ops = &clk_branch2_ops,1416		},1417	},1418};1419 1420static struct clk_branch gcc_disp_hf_axi_clk = {1421	.halt_reg = 0xb038,1422	.halt_check = BRANCH_HALT,1423	.clkr = {1424		.enable_reg = 0xb038,1425		.enable_mask = BIT(0),1426		.hw.init = &(struct clk_init_data){1427			.name = "gcc_disp_hf_axi_clk",1428			.ops = &clk_branch2_ops,1429		},1430	},1431};1432 1433static struct clk_branch gcc_disp_sf_axi_clk = {1434	.halt_reg = 0xb03c,1435	.halt_check = BRANCH_HALT,1436	.clkr = {1437		.enable_reg = 0xb03c,1438		.enable_mask = BIT(0),1439		.hw.init = &(struct clk_init_data){1440			.name = "gcc_disp_sf_axi_clk",1441			.ops = &clk_branch2_ops,1442		},1443	},1444};1445 1446/* XO critical input to disp, so no need to poll */1447static struct clk_branch gcc_disp_xo_clk = {1448	.halt_reg = 0xb048,1449	.halt_check = BRANCH_HALT_DELAY,1450	.clkr = {1451		.enable_reg = 0xb048,1452		.enable_mask = BIT(0),1453		.hw.init = &(struct clk_init_data){1454			.name = "gcc_disp_xo_clk",1455			.flags = CLK_IS_CRITICAL,1456			.ops = &clk_branch2_ops,1457		},1458	},1459};1460 1461static struct clk_branch gcc_emac_axi_clk = {1462	.halt_reg = 0x6010,1463	.halt_check = BRANCH_HALT,1464	.clkr = {1465		.enable_reg = 0x6010,1466		.enable_mask = BIT(0),1467		.hw.init = &(struct clk_init_data){1468			.name = "gcc_emac_axi_clk",1469			.ops = &clk_branch2_ops,1470		},1471	},1472};1473 1474static struct clk_branch gcc_emac_ptp_clk = {1475	.halt_reg = 0x6034,1476	.halt_check = BRANCH_HALT,1477	.clkr = {1478		.enable_reg = 0x6034,1479		.enable_mask = BIT(0),1480		.hw.init = &(struct clk_init_data){1481			.name = "gcc_emac_ptp_clk",1482			.parent_hws = (const struct clk_hw *[]){1483				      &gcc_emac_ptp_clk_src.clkr.hw },1484			.num_parents = 1,1485			.flags = CLK_SET_RATE_PARENT,1486			.ops = &clk_branch2_ops,1487		},1488	},1489};1490 1491static struct clk_branch gcc_emac_rgmii_clk = {1492	.halt_reg = 0x6018,1493	.halt_check = BRANCH_HALT,1494	.clkr = {1495		.enable_reg = 0x6018,1496		.enable_mask = BIT(0),1497		.hw.init = &(struct clk_init_data){1498			.name = "gcc_emac_rgmii_clk",1499			.parent_hws = (const struct clk_hw *[]){1500				      &gcc_emac_rgmii_clk_src.clkr.hw },1501			.num_parents = 1,1502			.flags = CLK_SET_RATE_PARENT,1503			.ops = &clk_branch2_ops,1504		},1505	},1506};1507 1508static struct clk_branch gcc_emac_slv_ahb_clk = {1509	.halt_reg = 0x6014,1510	.halt_check = BRANCH_HALT,1511	.hwcg_reg = 0x6014,1512	.hwcg_bit = 1,1513	.clkr = {1514		.enable_reg = 0x6014,1515		.enable_mask = BIT(0),1516		.hw.init = &(struct clk_init_data){1517			.name = "gcc_emac_slv_ahb_clk",1518			.ops = &clk_branch2_ops,1519		},1520	},1521};1522 1523static struct clk_branch gcc_gp1_clk = {1524	.halt_reg = 0x64000,1525	.halt_check = BRANCH_HALT,1526	.clkr = {1527		.enable_reg = 0x64000,1528		.enable_mask = BIT(0),1529		.hw.init = &(struct clk_init_data){1530			.name = "gcc_gp1_clk",1531			.parent_hws = (const struct clk_hw *[]){1532				      &gcc_gp1_clk_src.clkr.hw },1533			.num_parents = 1,1534			.flags = CLK_SET_RATE_PARENT,1535			.ops = &clk_branch2_ops,1536		},1537	},1538};1539 1540static struct clk_branch gcc_gp2_clk = {1541	.halt_reg = 0x65000,1542	.halt_check = BRANCH_HALT,1543	.clkr = {1544		.enable_reg = 0x65000,1545		.enable_mask = BIT(0),1546		.hw.init = &(struct clk_init_data){1547			.name = "gcc_gp2_clk",1548			.parent_hws = (const struct clk_hw *[]){1549				      &gcc_gp2_clk_src.clkr.hw },1550			.num_parents = 1,1551			.flags = CLK_SET_RATE_PARENT,1552			.ops = &clk_branch2_ops,1553		},1554	},1555};1556 1557static struct clk_branch gcc_gp3_clk = {1558	.halt_reg = 0x66000,1559	.halt_check = BRANCH_HALT,1560	.clkr = {1561		.enable_reg = 0x66000,1562		.enable_mask = BIT(0),1563		.hw.init = &(struct clk_init_data){1564			.name = "gcc_gp3_clk",1565			.parent_hws = (const struct clk_hw *[]){1566				      &gcc_gp3_clk_src.clkr.hw },1567			.num_parents = 1,1568			.flags = CLK_SET_RATE_PARENT,1569			.ops = &clk_branch2_ops,1570		},1571	},1572};1573 1574static struct clk_branch gcc_gpu_cfg_ahb_clk = {1575	.halt_reg = 0x71004,1576	.halt_check = BRANCH_HALT,1577	.hwcg_reg = 0x71004,1578	.hwcg_bit = 1,1579	.clkr = {1580		.enable_reg = 0x71004,1581		.enable_mask = BIT(0),1582		.hw.init = &(struct clk_init_data){1583			.name = "gcc_gpu_cfg_ahb_clk",1584			 /* required for gpu */1585			.flags = CLK_IS_CRITICAL,1586			.ops = &clk_branch2_ops,1587		},1588	},1589};1590 1591static struct clk_branch gcc_gpu_gpll0_clk_src = {1592	.halt_check = BRANCH_HALT_SKIP,1593	.clkr = {1594		.enable_reg = 0x52004,1595		.enable_mask = BIT(15),1596		.hw.init = &(struct clk_init_data){1597			.name = "gcc_gpu_gpll0_clk_src",1598			.parent_hws = (const struct clk_hw *[]){1599				&gpll0.clkr.hw },1600			.num_parents = 1,1601			.flags = CLK_SET_RATE_PARENT,1602			.ops = &clk_branch2_ops,1603		},1604	},1605};1606 1607static struct clk_branch gcc_gpu_gpll0_div_clk_src = {1608	.halt_check = BRANCH_HALT_SKIP,1609	.clkr = {1610		.enable_reg = 0x52004,1611		.enable_mask = BIT(16),1612		.hw.init = &(struct clk_init_data){1613			.name = "gcc_gpu_gpll0_div_clk_src",1614			.parent_hws = (const struct clk_hw *[]){1615				&gpll0_out_even.clkr.hw },1616			.num_parents = 1,1617			.flags = CLK_SET_RATE_PARENT,1618			.ops = &clk_branch2_ops,1619		},1620	},1621};1622 1623static struct clk_branch gcc_gpu_iref_clk = {1624	.halt_reg = 0x8c010,1625	.halt_check = BRANCH_HALT,1626	.clkr = {1627		.enable_reg = 0x8c010,1628		.enable_mask = BIT(0),1629		.hw.init = &(struct clk_init_data){1630			.name = "gcc_gpu_iref_clk",1631			.ops = &clk_branch2_ops,1632		},1633	},1634};1635 1636static struct clk_branch gcc_gpu_memnoc_gfx_clk = {1637	.halt_reg = 0x7100c,1638	.halt_check = BRANCH_VOTED,1639	.clkr = {1640		.enable_reg = 0x7100c,1641		.enable_mask = BIT(0),1642		.hw.init = &(struct clk_init_data){1643			.name = "gcc_gpu_memnoc_gfx_clk",1644			.ops = &clk_branch2_ops,1645		},1646	},1647};1648 1649static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {1650	.halt_reg = 0x71018,1651	.halt_check = BRANCH_HALT,1652	.clkr = {1653		.enable_reg = 0x71018,1654		.enable_mask = BIT(0),1655		.hw.init = &(struct clk_init_data){1656			.name = "gcc_gpu_snoc_dvm_gfx_clk",1657			.ops = &clk_branch2_ops,1658		},1659	},1660};1661 1662static struct clk_branch gcc_npu_at_clk = {1663	.halt_reg = 0x4d010,1664	.halt_check = BRANCH_VOTED,1665	.clkr = {1666		.enable_reg = 0x4d010,1667		.enable_mask = BIT(0),1668		.hw.init = &(struct clk_init_data){1669			.name = "gcc_npu_at_clk",1670			.ops = &clk_branch2_ops,1671		},1672	},1673};1674 1675static struct clk_branch gcc_npu_axi_clk = {1676	.halt_reg = 0x4d008,1677	.halt_check = BRANCH_VOTED,1678	.clkr = {1679		.enable_reg = 0x4d008,1680		.enable_mask = BIT(0),1681		.hw.init = &(struct clk_init_data){1682			.name = "gcc_npu_axi_clk",1683			.ops = &clk_branch2_ops,1684		},1685	},1686};1687 1688static struct clk_branch gcc_npu_cfg_ahb_clk = {1689	.halt_reg = 0x4d004,1690	.halt_check = BRANCH_HALT,1691	.hwcg_reg = 0x4d004,1692	.hwcg_bit = 1,1693	.clkr = {1694		.enable_reg = 0x4d004,1695		.enable_mask = BIT(0),1696		.hw.init = &(struct clk_init_data){1697			.name = "gcc_npu_cfg_ahb_clk",1698			 /* required for npu */1699			.flags = CLK_IS_CRITICAL,1700			.ops = &clk_branch2_ops,1701		},1702	},1703};1704 1705static struct clk_branch gcc_npu_gpll0_clk_src = {1706	.halt_check = BRANCH_HALT_SKIP,1707	.clkr = {1708		.enable_reg = 0x52004,1709		.enable_mask = BIT(18),1710		.hw.init = &(struct clk_init_data){1711			.name = "gcc_npu_gpll0_clk_src",1712			.parent_hws = (const struct clk_hw *[]){1713				&gpll0.clkr.hw },1714			.num_parents = 1,1715			.flags = CLK_SET_RATE_PARENT,1716			.ops = &clk_branch2_ops,1717		},1718	},1719};1720 1721static struct clk_branch gcc_npu_gpll0_div_clk_src = {1722	.halt_check = BRANCH_HALT_SKIP,1723	.clkr = {1724		.enable_reg = 0x52004,1725		.enable_mask = BIT(19),1726		.hw.init = &(struct clk_init_data){1727			.name = "gcc_npu_gpll0_div_clk_src",1728			.parent_hws = (const struct clk_hw *[]){1729				&gpll0_out_even.clkr.hw },1730			.num_parents = 1,1731			.flags = CLK_SET_RATE_PARENT,1732			.ops = &clk_branch2_ops,1733		},1734	},1735};1736 1737static struct clk_branch gcc_npu_trig_clk = {1738	.halt_reg = 0x4d00c,1739	.halt_check = BRANCH_VOTED,1740	.clkr = {1741		.enable_reg = 0x4d00c,1742		.enable_mask = BIT(0),1743		.hw.init = &(struct clk_init_data){1744			.name = "gcc_npu_trig_clk",1745			.ops = &clk_branch2_ops,1746		},1747	},1748};1749 1750static struct clk_branch gcc_pcie0_phy_refgen_clk = {1751	.halt_reg = 0x6f02c,1752	.halt_check = BRANCH_HALT,1753	.clkr = {1754		.enable_reg = 0x6f02c,1755		.enable_mask = BIT(0),1756		.hw.init = &(struct clk_init_data){1757			.name = "gcc_pcie0_phy_refgen_clk",1758			.parent_hws = (const struct clk_hw *[]){1759				      &gcc_pcie_phy_refgen_clk_src.clkr.hw },1760			.num_parents = 1,1761			.flags = CLK_SET_RATE_PARENT,1762			.ops = &clk_branch2_ops,1763		},1764	},1765};1766 1767static struct clk_branch gcc_pcie1_phy_refgen_clk = {1768	.halt_reg = 0x6f030,1769	.halt_check = BRANCH_HALT,1770	.clkr = {1771		.enable_reg = 0x6f030,1772		.enable_mask = BIT(0),1773		.hw.init = &(struct clk_init_data){1774			.name = "gcc_pcie1_phy_refgen_clk",1775			.parent_hws = (const struct clk_hw *[]){1776				      &gcc_pcie_phy_refgen_clk_src.clkr.hw },1777			.num_parents = 1,1778			.flags = CLK_SET_RATE_PARENT,1779			.ops = &clk_branch2_ops,1780		},1781	},1782};1783 1784static struct clk_branch gcc_pcie_0_aux_clk = {1785	.halt_reg = 0x6b020,1786	.halt_check = BRANCH_HALT_VOTED,1787	.clkr = {1788		.enable_reg = 0x5200c,1789		.enable_mask = BIT(3),1790		.hw.init = &(struct clk_init_data){1791			.name = "gcc_pcie_0_aux_clk",1792			.parent_hws = (const struct clk_hw *[]){1793				      &gcc_pcie_0_aux_clk_src.clkr.hw },1794			.num_parents = 1,1795			.flags = CLK_SET_RATE_PARENT,1796			.ops = &clk_branch2_ops,1797		},1798	},1799};1800 1801static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {1802	.halt_reg = 0x6b01c,1803	.halt_check = BRANCH_HALT_VOTED,1804	.hwcg_reg = 0x6b01c,1805	.hwcg_bit = 1,1806	.clkr = {1807		.enable_reg = 0x5200c,1808		.enable_mask = BIT(2),1809		.hw.init = &(struct clk_init_data){1810			.name = "gcc_pcie_0_cfg_ahb_clk",1811			.ops = &clk_branch2_ops,1812		},1813	},1814};1815 1816static struct clk_branch gcc_pcie_0_clkref_clk = {1817	.halt_reg = 0x8c00c,1818	.halt_check = BRANCH_HALT,1819	.clkr = {1820		.enable_reg = 0x8c00c,1821		.enable_mask = BIT(0),1822		.hw.init = &(struct clk_init_data){1823			.name = "gcc_pcie_0_clkref_clk",1824			.ops = &clk_branch2_ops,1825		},1826	},1827};1828 1829static struct clk_branch gcc_pcie_0_mstr_axi_clk = {1830	.halt_reg = 0x6b018,1831	.halt_check = BRANCH_HALT_VOTED,1832	.clkr = {1833		.enable_reg = 0x5200c,1834		.enable_mask = BIT(1),1835		.hw.init = &(struct clk_init_data){1836			.name = "gcc_pcie_0_mstr_axi_clk",1837			.ops = &clk_branch2_ops,1838		},1839	},1840};1841 1842/* Clock ON depends on external parent 'PIPE' clock, so dont poll */1843static struct clk_branch gcc_pcie_0_pipe_clk = {1844	.halt_reg = 0x6b024,1845	.halt_check = BRANCH_HALT_DELAY,1846	.clkr = {1847		.enable_reg = 0x5200c,1848		.enable_mask = BIT(4),1849		.hw.init = &(struct clk_init_data){1850			.name = "gcc_pcie_0_pipe_clk",1851			.ops = &clk_branch2_ops,1852		},1853	},1854};1855 1856static struct clk_branch gcc_pcie_0_slv_axi_clk = {1857	.halt_reg = 0x6b014,1858	.halt_check = BRANCH_HALT_VOTED,1859	.hwcg_reg = 0x6b014,1860	.hwcg_bit = 1,1861	.clkr = {1862		.enable_reg = 0x5200c,1863		.enable_mask = BIT(0),1864		.hw.init = &(struct clk_init_data){1865			.name = "gcc_pcie_0_slv_axi_clk",1866			.ops = &clk_branch2_ops,1867		},1868	},1869};1870 1871static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {1872	.halt_reg = 0x6b010,1873	.halt_check = BRANCH_HALT_VOTED,1874	.clkr = {1875		.enable_reg = 0x5200c,1876		.enable_mask = BIT(5),1877		.hw.init = &(struct clk_init_data){1878			.name = "gcc_pcie_0_slv_q2a_axi_clk",1879			.ops = &clk_branch2_ops,1880		},1881	},1882};1883 1884static struct clk_branch gcc_pcie_1_aux_clk = {1885	.halt_reg = 0x8d020,1886	.halt_check = BRANCH_HALT_VOTED,1887	.clkr = {1888		.enable_reg = 0x52004,1889		.enable_mask = BIT(29),1890		.hw.init = &(struct clk_init_data){1891			.name = "gcc_pcie_1_aux_clk",1892			.parent_hws = (const struct clk_hw *[]){1893				      &gcc_pcie_1_aux_clk_src.clkr.hw },1894			.num_parents = 1,1895			.flags = CLK_SET_RATE_PARENT,1896			.ops = &clk_branch2_ops,1897		},1898	},1899};1900 1901static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {1902	.halt_reg = 0x8d01c,1903	.halt_check = BRANCH_HALT_VOTED,1904	.hwcg_reg = 0x8d01c,1905	.hwcg_bit = 1,1906	.clkr = {1907		.enable_reg = 0x52004,1908		.enable_mask = BIT(28),1909		.hw.init = &(struct clk_init_data){1910			.name = "gcc_pcie_1_cfg_ahb_clk",1911			.ops = &clk_branch2_ops,1912		},1913	},1914};1915 1916static struct clk_branch gcc_pcie_1_clkref_clk = {1917	.halt_reg = 0x8c02c,1918	.halt_check = BRANCH_HALT,1919	.clkr = {1920		.enable_reg = 0x8c02c,1921		.enable_mask = BIT(0),1922		.hw.init = &(struct clk_init_data){1923			.name = "gcc_pcie_1_clkref_clk",1924			.ops = &clk_branch2_ops,1925		},1926	},1927};1928 1929static struct clk_branch gcc_pcie_1_mstr_axi_clk = {1930	.halt_reg = 0x8d018,1931	.halt_check = BRANCH_HALT_VOTED,1932	.clkr = {1933		.enable_reg = 0x52004,1934		.enable_mask = BIT(27),1935		.hw.init = &(struct clk_init_data){1936			.name = "gcc_pcie_1_mstr_axi_clk",1937			.ops = &clk_branch2_ops,1938		},1939	},1940};1941 1942/* Clock ON depends on external parent 'PIPE' clock, so dont poll */1943static struct clk_branch gcc_pcie_1_pipe_clk = {1944	.halt_reg = 0x8d024,1945	.halt_check = BRANCH_HALT_DELAY,1946	.clkr = {1947		.enable_reg = 0x52004,1948		.enable_mask = BIT(30),1949		.hw.init = &(struct clk_init_data){1950			.name = "gcc_pcie_1_pipe_clk",1951			.ops = &clk_branch2_ops,1952		},1953	},1954};1955 1956static struct clk_branch gcc_pcie_1_slv_axi_clk = {1957	.halt_reg = 0x8d014,1958	.halt_check = BRANCH_HALT_VOTED,1959	.hwcg_reg = 0x8d014,1960	.hwcg_bit = 1,1961	.clkr = {1962		.enable_reg = 0x52004,1963		.enable_mask = BIT(26),1964		.hw.init = &(struct clk_init_data){1965			.name = "gcc_pcie_1_slv_axi_clk",1966			.ops = &clk_branch2_ops,1967		},1968	},1969};1970 1971static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {1972	.halt_reg = 0x8d010,1973	.halt_check = BRANCH_HALT_VOTED,1974	.clkr = {1975		.enable_reg = 0x52004,1976		.enable_mask = BIT(25),1977		.hw.init = &(struct clk_init_data){1978			.name = "gcc_pcie_1_slv_q2a_axi_clk",1979			.ops = &clk_branch2_ops,1980		},1981	},1982};1983 1984static struct clk_branch gcc_pcie_phy_aux_clk = {1985	.halt_reg = 0x6f004,1986	.halt_check = BRANCH_HALT,1987	.clkr = {1988		.enable_reg = 0x6f004,1989		.enable_mask = BIT(0),1990		.hw.init = &(struct clk_init_data){1991			.name = "gcc_pcie_phy_aux_clk",1992			.parent_hws = (const struct clk_hw *[]){1993				      &gcc_pcie_0_aux_clk_src.clkr.hw },1994			.num_parents = 1,1995			.flags = CLK_SET_RATE_PARENT,1996			.ops = &clk_branch2_ops,1997		},1998	},1999};2000 2001static struct clk_branch gcc_pdm2_clk = {2002	.halt_reg = 0x3300c,2003	.halt_check = BRANCH_HALT,2004	.clkr = {2005		.enable_reg = 0x3300c,2006		.enable_mask = BIT(0),2007		.hw.init = &(struct clk_init_data){2008			.name = "gcc_pdm2_clk",2009			.parent_hws = (const struct clk_hw *[]){2010				      &gcc_pdm2_clk_src.clkr.hw },2011			.num_parents = 1,2012			.flags = CLK_SET_RATE_PARENT,2013			.ops = &clk_branch2_ops,2014		},2015	},2016};2017 2018static struct clk_branch gcc_pdm_ahb_clk = {2019	.halt_reg = 0x33004,2020	.halt_check = BRANCH_HALT,2021	.hwcg_reg = 0x33004,2022	.hwcg_bit = 1,2023	.clkr = {2024		.enable_reg = 0x33004,2025		.enable_mask = BIT(0),2026		.hw.init = &(struct clk_init_data){2027			.name = "gcc_pdm_ahb_clk",2028			.ops = &clk_branch2_ops,2029		},2030	},2031};2032 2033static struct clk_branch gcc_pdm_xo4_clk = {2034	.halt_reg = 0x33008,2035	.halt_check = BRANCH_HALT,2036	.clkr = {2037		.enable_reg = 0x33008,2038		.enable_mask = BIT(0),2039		.hw.init = &(struct clk_init_data){2040			.name = "gcc_pdm_xo4_clk",2041			.ops = &clk_branch2_ops,2042		},2043	},2044};2045 2046static struct clk_branch gcc_prng_ahb_clk = {2047	.halt_reg = 0x34004,2048	.halt_check = BRANCH_HALT_VOTED,2049	.clkr = {2050		.enable_reg = 0x52004,2051		.enable_mask = BIT(13),2052		.hw.init = &(struct clk_init_data){2053			.name = "gcc_prng_ahb_clk",2054			.ops = &clk_branch2_ops,2055		},2056	},2057};2058 2059static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {2060	.halt_reg = 0xb018,2061	.halt_check = BRANCH_HALT,2062	.hwcg_reg = 0xb018,2063	.hwcg_bit = 1,2064	.clkr = {2065		.enable_reg = 0xb018,2066		.enable_mask = BIT(0),2067		.hw.init = &(struct clk_init_data){2068			.name = "gcc_qmip_camera_nrt_ahb_clk",2069			.ops = &clk_branch2_ops,2070		},2071	},2072};2073 2074static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {2075	.halt_reg = 0xb01c,2076	.halt_check = BRANCH_HALT,2077	.hwcg_reg = 0xb01c,2078	.hwcg_bit = 1,2079	.clkr = {2080		.enable_reg = 0xb01c,2081		.enable_mask = BIT(0),2082		.hw.init = &(struct clk_init_data){2083			.name = "gcc_qmip_camera_rt_ahb_clk",2084			.ops = &clk_branch2_ops,2085		},2086	},2087};2088 2089static struct clk_branch gcc_qmip_disp_ahb_clk = {2090	.halt_reg = 0xb020,2091	.halt_check = BRANCH_HALT,2092	.hwcg_reg = 0xb020,2093	.hwcg_bit = 1,2094	.clkr = {2095		.enable_reg = 0xb020,2096		.enable_mask = BIT(0),2097		.hw.init = &(struct clk_init_data){2098			.name = "gcc_qmip_disp_ahb_clk",2099			.ops = &clk_branch2_ops,2100		},2101	},2102};2103 2104static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {2105	.halt_reg = 0xb010,2106	.halt_check = BRANCH_HALT,2107	.hwcg_reg = 0xb010,2108	.hwcg_bit = 1,2109	.clkr = {2110		.enable_reg = 0xb010,2111		.enable_mask = BIT(0),2112		.hw.init = &(struct clk_init_data){2113			.name = "gcc_qmip_video_cvp_ahb_clk",2114			.ops = &clk_branch2_ops,2115		},2116	},2117};2118 2119static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {2120	.halt_reg = 0xb014,2121	.halt_check = BRANCH_HALT,2122	.hwcg_reg = 0xb014,2123	.hwcg_bit = 1,2124	.clkr = {2125		.enable_reg = 0xb014,2126		.enable_mask = BIT(0),2127		.hw.init = &(struct clk_init_data){2128			.name = "gcc_qmip_video_vcodec_ahb_clk",2129			.ops = &clk_branch2_ops,2130		},2131	},2132};2133 2134static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {2135	.halt_reg = 0x4b000,2136	.halt_check = BRANCH_HALT,2137	.clkr = {2138		.enable_reg = 0x4b000,2139		.enable_mask = BIT(0),2140		.hw.init = &(struct clk_init_data){2141			.name = "gcc_qspi_cnoc_periph_ahb_clk",2142			.ops = &clk_branch2_ops,2143		},2144	},2145};2146 2147static struct clk_branch gcc_qspi_core_clk = {2148	.halt_reg = 0x4b004,2149	.halt_check = BRANCH_HALT,2150	.clkr = {2151		.enable_reg = 0x4b004,2152		.enable_mask = BIT(0),2153		.hw.init = &(struct clk_init_data){2154			.name = "gcc_qspi_core_clk",2155			.parent_hws = (const struct clk_hw *[]){2156				      &gcc_qspi_core_clk_src.clkr.hw },2157			.num_parents = 1,2158			.flags = CLK_SET_RATE_PARENT,2159			.ops = &clk_branch2_ops,2160		},2161	},2162};2163 2164static struct clk_branch gcc_qupv3_wrap0_s0_clk = {2165	.halt_reg = 0x17144,2166	.halt_check = BRANCH_HALT_VOTED,2167	.clkr = {2168		.enable_reg = 0x5200c,2169		.enable_mask = BIT(10),2170		.hw.init = &(struct clk_init_data){2171			.name = "gcc_qupv3_wrap0_s0_clk",2172			.parent_hws = (const struct clk_hw *[]){2173				      &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },2174			.num_parents = 1,2175			.flags = CLK_SET_RATE_PARENT,2176			.ops = &clk_branch2_ops,2177		},2178	},2179};2180 2181static struct clk_branch gcc_qupv3_wrap0_s1_clk = {2182	.halt_reg = 0x17274,2183	.halt_check = BRANCH_HALT_VOTED,2184	.clkr = {2185		.enable_reg = 0x5200c,2186		.enable_mask = BIT(11),2187		.hw.init = &(struct clk_init_data){2188			.name = "gcc_qupv3_wrap0_s1_clk",2189			.parent_hws = (const struct clk_hw *[]){2190				      &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },2191			.num_parents = 1,2192			.flags = CLK_SET_RATE_PARENT,2193			.ops = &clk_branch2_ops,2194		},2195	},2196};2197 2198static struct clk_branch gcc_qupv3_wrap0_s2_clk = {2199	.halt_reg = 0x173a4,2200	.halt_check = BRANCH_HALT_VOTED,2201	.clkr = {2202		.enable_reg = 0x5200c,2203		.enable_mask = BIT(12),2204		.hw.init = &(struct clk_init_data){2205			.name = "gcc_qupv3_wrap0_s2_clk",2206			.parent_hws = (const struct clk_hw *[]){2207				      &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },2208			.num_parents = 1,2209			.flags = CLK_SET_RATE_PARENT,2210			.ops = &clk_branch2_ops,2211		},2212	},2213};2214 2215static struct clk_branch gcc_qupv3_wrap0_s3_clk = {2216	.halt_reg = 0x174d4,2217	.halt_check = BRANCH_HALT_VOTED,2218	.clkr = {2219		.enable_reg = 0x5200c,2220		.enable_mask = BIT(13),2221		.hw.init = &(struct clk_init_data){2222			.name = "gcc_qupv3_wrap0_s3_clk",2223			.parent_hws = (const struct clk_hw *[]){2224				      &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },2225			.num_parents = 1,2226			.flags = CLK_SET_RATE_PARENT,2227			.ops = &clk_branch2_ops,2228		},2229	},2230};2231 2232static struct clk_branch gcc_qupv3_wrap0_s4_clk = {2233	.halt_reg = 0x17604,2234	.halt_check = BRANCH_HALT_VOTED,2235	.clkr = {2236		.enable_reg = 0x5200c,2237		.enable_mask = BIT(14),2238		.hw.init = &(struct clk_init_data){2239			.name = "gcc_qupv3_wrap0_s4_clk",2240			.parent_hws = (const struct clk_hw *[]){2241				      &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },2242			.num_parents = 1,2243			.flags = CLK_SET_RATE_PARENT,2244			.ops = &clk_branch2_ops,2245		},2246	},2247};2248 2249static struct clk_branch gcc_qupv3_wrap0_s5_clk = {2250	.halt_reg = 0x17734,2251	.halt_check = BRANCH_HALT_VOTED,2252	.clkr = {2253		.enable_reg = 0x5200c,2254		.enable_mask = BIT(15),2255		.hw.init = &(struct clk_init_data){2256			.name = "gcc_qupv3_wrap0_s5_clk",2257			.parent_hws = (const struct clk_hw *[]){2258				      &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },2259			.num_parents = 1,2260			.flags = CLK_SET_RATE_PARENT,2261			.ops = &clk_branch2_ops,2262		},2263	},2264};2265 2266static struct clk_branch gcc_qupv3_wrap0_s6_clk = {2267	.halt_reg = 0x17864,2268	.halt_check = BRANCH_HALT_VOTED,2269	.clkr = {2270		.enable_reg = 0x5200c,2271		.enable_mask = BIT(16),2272		.hw.init = &(struct clk_init_data){2273			.name = "gcc_qupv3_wrap0_s6_clk",2274			.parent_hws = (const struct clk_hw *[]){2275				      &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },2276			.num_parents = 1,2277			.flags = CLK_SET_RATE_PARENT,2278			.ops = &clk_branch2_ops,2279		},2280	},2281};2282 2283static struct clk_branch gcc_qupv3_wrap0_s7_clk = {2284	.halt_reg = 0x17994,2285	.halt_check = BRANCH_HALT_VOTED,2286	.clkr = {2287		.enable_reg = 0x5200c,2288		.enable_mask = BIT(17),2289		.hw.init = &(struct clk_init_data){2290			.name = "gcc_qupv3_wrap0_s7_clk",2291			.parent_hws = (const struct clk_hw *[]){2292				      &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },2293			.num_parents = 1,2294			.flags = CLK_SET_RATE_PARENT,2295			.ops = &clk_branch2_ops,2296		},2297	},2298};2299 2300static struct clk_branch gcc_qupv3_wrap1_s0_clk = {2301	.halt_reg = 0x18144,2302	.halt_check = BRANCH_HALT_VOTED,2303	.clkr = {2304		.enable_reg = 0x5200c,2305		.enable_mask = BIT(22),2306		.hw.init = &(struct clk_init_data){2307			.name = "gcc_qupv3_wrap1_s0_clk",2308			.parent_hws = (const struct clk_hw *[]){2309				      &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },2310			.num_parents = 1,2311			.flags = CLK_SET_RATE_PARENT,2312			.ops = &clk_branch2_ops,2313		},2314	},2315};2316 2317static struct clk_branch gcc_qupv3_wrap1_s1_clk = {2318	.halt_reg = 0x18274,2319	.halt_check = BRANCH_HALT_VOTED,2320	.clkr = {2321		.enable_reg = 0x5200c,2322		.enable_mask = BIT(23),2323		.hw.init = &(struct clk_init_data){2324			.name = "gcc_qupv3_wrap1_s1_clk",2325			.parent_hws = (const struct clk_hw *[]){2326				      &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },2327			.num_parents = 1,2328			.flags = CLK_SET_RATE_PARENT,2329			.ops = &clk_branch2_ops,2330		},2331	},2332};2333 2334static struct clk_branch gcc_qupv3_wrap1_s2_clk = {2335	.halt_reg = 0x183a4,2336	.halt_check = BRANCH_HALT_VOTED,2337	.clkr = {2338		.enable_reg = 0x5200c,2339		.enable_mask = BIT(24),2340		.hw.init = &(struct clk_init_data){2341			.name = "gcc_qupv3_wrap1_s2_clk",2342			.parent_hws = (const struct clk_hw *[]){2343				      &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },2344			.num_parents = 1,2345			.flags = CLK_SET_RATE_PARENT,2346			.ops = &clk_branch2_ops,2347		},2348	},2349};2350 2351static struct clk_branch gcc_qupv3_wrap1_s3_clk = {2352	.halt_reg = 0x184d4,2353	.halt_check = BRANCH_HALT_VOTED,2354	.clkr = {2355		.enable_reg = 0x5200c,2356		.enable_mask = BIT(25),2357		.hw.init = &(struct clk_init_data){2358			.name = "gcc_qupv3_wrap1_s3_clk",2359			.parent_hws = (const struct clk_hw *[]){2360				      &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },2361			.num_parents = 1,2362			.flags = CLK_SET_RATE_PARENT,2363			.ops = &clk_branch2_ops,2364		},2365	},2366};2367 2368static struct clk_branch gcc_qupv3_wrap1_s4_clk = {2369	.halt_reg = 0x18604,2370	.halt_check = BRANCH_HALT_VOTED,2371	.clkr = {2372		.enable_reg = 0x5200c,2373		.enable_mask = BIT(26),2374		.hw.init = &(struct clk_init_data){2375			.name = "gcc_qupv3_wrap1_s4_clk",2376			.parent_hws = (const struct clk_hw *[]){2377				      &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },2378			.num_parents = 1,2379			.flags = CLK_SET_RATE_PARENT,2380			.ops = &clk_branch2_ops,2381		},2382	},2383};2384 2385static struct clk_branch gcc_qupv3_wrap1_s5_clk = {2386	.halt_reg = 0x18734,2387	.halt_check = BRANCH_HALT_VOTED,2388	.clkr = {2389		.enable_reg = 0x5200c,2390		.enable_mask = BIT(27),2391		.hw.init = &(struct clk_init_data){2392			.name = "gcc_qupv3_wrap1_s5_clk",2393			.parent_hws = (const struct clk_hw *[]){2394				      &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },2395			.num_parents = 1,2396			.flags = CLK_SET_RATE_PARENT,2397			.ops = &clk_branch2_ops,2398		},2399	},2400};2401 2402static struct clk_branch gcc_qupv3_wrap2_s0_clk = {2403	.halt_reg = 0x1e144,2404	.halt_check = BRANCH_HALT_VOTED,2405	.clkr = {2406		.enable_reg = 0x52014,2407		.enable_mask = BIT(4),2408		.hw.init = &(struct clk_init_data){2409			.name = "gcc_qupv3_wrap2_s0_clk",2410			.parent_hws = (const struct clk_hw *[]){2411				      &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },2412			.num_parents = 1,2413			.flags = CLK_SET_RATE_PARENT,2414			.ops = &clk_branch2_ops,2415		},2416	},2417};2418 2419static struct clk_branch gcc_qupv3_wrap2_s1_clk = {2420	.halt_reg = 0x1e274,2421	.halt_check = BRANCH_HALT_VOTED,2422	.clkr = {2423		.enable_reg = 0x52014,2424		.enable_mask = BIT(5),2425		.hw.init = &(struct clk_init_data){2426			.name = "gcc_qupv3_wrap2_s1_clk",2427			.parent_hws = (const struct clk_hw *[]){2428				      &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },2429			.num_parents = 1,2430			.flags = CLK_SET_RATE_PARENT,2431			.ops = &clk_branch2_ops,2432		},2433	},2434};2435 2436static struct clk_branch gcc_qupv3_wrap2_s2_clk = {2437	.halt_reg = 0x1e3a4,2438	.halt_check = BRANCH_HALT_VOTED,2439	.clkr = {2440		.enable_reg = 0x52014,2441		.enable_mask = BIT(6),2442		.hw.init = &(struct clk_init_data){2443			.name = "gcc_qupv3_wrap2_s2_clk",2444			.parent_hws = (const struct clk_hw *[]){2445				      &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },2446			.num_parents = 1,2447			.flags = CLK_SET_RATE_PARENT,2448			.ops = &clk_branch2_ops,2449		},2450	},2451};2452 2453static struct clk_branch gcc_qupv3_wrap2_s3_clk = {2454	.halt_reg = 0x1e4d4,2455	.halt_check = BRANCH_HALT_VOTED,2456	.clkr = {2457		.enable_reg = 0x52014,2458		.enable_mask = BIT(7),2459		.hw.init = &(struct clk_init_data){2460			.name = "gcc_qupv3_wrap2_s3_clk",2461			.parent_hws = (const struct clk_hw *[]){2462				      &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },2463			.num_parents = 1,2464			.flags = CLK_SET_RATE_PARENT,2465			.ops = &clk_branch2_ops,2466		},2467	},2468};2469 2470static struct clk_branch gcc_qupv3_wrap2_s4_clk = {2471	.halt_reg = 0x1e604,2472	.halt_check = BRANCH_HALT_VOTED,2473	.clkr = {2474		.enable_reg = 0x52014,2475		.enable_mask = BIT(8),2476		.hw.init = &(struct clk_init_data){2477			.name = "gcc_qupv3_wrap2_s4_clk",2478			.parent_hws = (const struct clk_hw *[]){2479				      &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },2480			.num_parents = 1,2481			.flags = CLK_SET_RATE_PARENT,2482			.ops = &clk_branch2_ops,2483		},2484	},2485};2486 2487static struct clk_branch gcc_qupv3_wrap2_s5_clk = {2488	.halt_reg = 0x1e734,2489	.halt_check = BRANCH_HALT_VOTED,2490	.clkr = {2491		.enable_reg = 0x52014,2492		.enable_mask = BIT(9),2493		.hw.init = &(struct clk_init_data){2494			.name = "gcc_qupv3_wrap2_s5_clk",2495			.parent_hws = (const struct clk_hw *[]){2496				      &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },2497			.num_parents = 1,2498			.flags = CLK_SET_RATE_PARENT,2499			.ops = &clk_branch2_ops,2500		},2501	},2502};2503 2504static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {2505	.halt_reg = 0x17004,2506	.halt_check = BRANCH_HALT_VOTED,2507	.clkr = {2508		.enable_reg = 0x5200c,2509		.enable_mask = BIT(6),2510		.hw.init = &(struct clk_init_data){2511			.name = "gcc_qupv3_wrap_0_m_ahb_clk",2512			.ops = &clk_branch2_ops,2513		},2514	},2515};2516 2517static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {2518	.halt_reg = 0x17008,2519	.halt_check = BRANCH_HALT_VOTED,2520	.hwcg_reg = 0x17008,2521	.hwcg_bit = 1,2522	.clkr = {2523		.enable_reg = 0x5200c,2524		.enable_mask = BIT(7),2525		.hw.init = &(struct clk_init_data){2526			.name = "gcc_qupv3_wrap_0_s_ahb_clk",2527			.ops = &clk_branch2_ops,2528		},2529	},2530};2531 2532static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {2533	.halt_reg = 0x18004,2534	.halt_check = BRANCH_HALT_VOTED,2535	.clkr = {2536		.enable_reg = 0x5200c,2537		.enable_mask = BIT(20),2538		.hw.init = &(struct clk_init_data){2539			.name = "gcc_qupv3_wrap_1_m_ahb_clk",2540			.ops = &clk_branch2_ops,2541		},2542	},2543};2544 2545static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {2546	.halt_reg = 0x18008,2547	.halt_check = BRANCH_HALT_VOTED,2548	.hwcg_reg = 0x18008,2549	.hwcg_bit = 1,2550	.clkr = {2551		.enable_reg = 0x5200c,2552		.enable_mask = BIT(21),2553		.hw.init = &(struct clk_init_data){2554			.name = "gcc_qupv3_wrap_1_s_ahb_clk",2555			.ops = &clk_branch2_ops,2556		},2557	},2558};2559 2560static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {2561	.halt_reg = 0x1e004,2562	.halt_check = BRANCH_HALT_VOTED,2563	.clkr = {2564		.enable_reg = 0x52014,2565		.enable_mask = BIT(2),2566		.hw.init = &(struct clk_init_data){2567			.name = "gcc_qupv3_wrap_2_m_ahb_clk",2568			.ops = &clk_branch2_ops,2569		},2570	},2571};2572 2573static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {2574	.halt_reg = 0x1e008,2575	.halt_check = BRANCH_HALT_VOTED,2576	.hwcg_reg = 0x1e008,2577	.hwcg_bit = 1,2578	.clkr = {2579		.enable_reg = 0x52014,2580		.enable_mask = BIT(1),2581		.hw.init = &(struct clk_init_data){2582			.name = "gcc_qupv3_wrap_2_s_ahb_clk",2583			.ops = &clk_branch2_ops,2584		},2585	},2586};2587 2588static struct clk_branch gcc_sdcc2_ahb_clk = {2589	.halt_reg = 0x14008,2590	.halt_check = BRANCH_HALT,2591	.clkr = {2592		.enable_reg = 0x14008,2593		.enable_mask = BIT(0),2594		.hw.init = &(struct clk_init_data){2595			.name = "gcc_sdcc2_ahb_clk",2596			.ops = &clk_branch2_ops,2597		},2598	},2599};2600 2601static struct clk_branch gcc_sdcc2_apps_clk = {2602	.halt_reg = 0x14004,2603	.halt_check = BRANCH_HALT,2604	.clkr = {2605		.enable_reg = 0x14004,2606		.enable_mask = BIT(0),2607		.hw.init = &(struct clk_init_data){2608			.name = "gcc_sdcc2_apps_clk",2609			.parent_hws = (const struct clk_hw *[]){2610				      &gcc_sdcc2_apps_clk_src.clkr.hw },2611			.num_parents = 1,2612			.flags = CLK_SET_RATE_PARENT,2613			.ops = &clk_branch2_ops,2614		},2615	},2616};2617 2618static struct clk_branch gcc_sdcc4_ahb_clk = {2619	.halt_reg = 0x16008,2620	.halt_check = BRANCH_HALT,2621	.clkr = {2622		.enable_reg = 0x16008,2623		.enable_mask = BIT(0),2624		.hw.init = &(struct clk_init_data){2625			.name = "gcc_sdcc4_ahb_clk",2626			.ops = &clk_branch2_ops,2627		},2628	},2629};2630 2631static struct clk_branch gcc_sdcc4_apps_clk = {2632	.halt_reg = 0x16004,2633	.halt_check = BRANCH_HALT,2634	.clkr = {2635		.enable_reg = 0x16004,2636		.enable_mask = BIT(0),2637		.hw.init = &(struct clk_init_data){2638			.name = "gcc_sdcc4_apps_clk",2639			.parent_hws = (const struct clk_hw *[]){2640				      &gcc_sdcc4_apps_clk_src.clkr.hw },2641			.num_parents = 1,2642			.flags = CLK_SET_RATE_PARENT,2643			.ops = &clk_branch2_ops,2644		},2645	},2646};2647 2648static struct clk_branch gcc_tsif_ahb_clk = {2649	.halt_reg = 0x36004,2650	.halt_check = BRANCH_HALT,2651	.clkr = {2652		.enable_reg = 0x36004,2653		.enable_mask = BIT(0),2654		.hw.init = &(struct clk_init_data){2655			.name = "gcc_tsif_ahb_clk",2656			.ops = &clk_branch2_ops,2657		},2658	},2659};2660 2661static struct clk_branch gcc_tsif_inactivity_timers_clk = {2662	.halt_reg = 0x3600c,2663	.halt_check = BRANCH_HALT,2664	.clkr = {2665		.enable_reg = 0x3600c,2666		.enable_mask = BIT(0),2667		.hw.init = &(struct clk_init_data){2668			.name = "gcc_tsif_inactivity_timers_clk",2669			.ops = &clk_branch2_ops,2670		},2671	},2672};2673 2674static struct clk_branch gcc_tsif_ref_clk = {2675	.halt_reg = 0x36008,2676	.halt_check = BRANCH_HALT,2677	.clkr = {2678		.enable_reg = 0x36008,2679		.enable_mask = BIT(0),2680		.hw.init = &(struct clk_init_data){2681			.name = "gcc_tsif_ref_clk",2682			.parent_hws = (const struct clk_hw *[]){2683				      &gcc_tsif_ref_clk_src.clkr.hw },2684			.num_parents = 1,2685			.flags = CLK_SET_RATE_PARENT,2686			.ops = &clk_branch2_ops,2687		},2688	},2689};2690 2691static struct clk_branch gcc_ufs_card_ahb_clk = {2692	.halt_reg = 0x75014,2693	.halt_check = BRANCH_HALT,2694	.hwcg_reg = 0x75014,2695	.hwcg_bit = 1,2696	.clkr = {2697		.enable_reg = 0x75014,2698		.enable_mask = BIT(0),2699		.hw.init = &(struct clk_init_data){2700			.name = "gcc_ufs_card_ahb_clk",2701			.ops = &clk_branch2_ops,2702		},2703	},2704};2705 2706static struct clk_branch gcc_ufs_card_axi_clk = {2707	.halt_reg = 0x75010,2708	.halt_check = BRANCH_HALT,2709	.hwcg_reg = 0x75010,2710	.hwcg_bit = 1,2711	.clkr = {2712		.enable_reg = 0x75010,2713		.enable_mask = BIT(0),2714		.hw.init = &(struct clk_init_data){2715			.name = "gcc_ufs_card_axi_clk",2716			.parent_hws = (const struct clk_hw *[]){2717				      &gcc_ufs_card_axi_clk_src.clkr.hw },2718			.num_parents = 1,2719			.flags = CLK_SET_RATE_PARENT,2720			.ops = &clk_branch2_ops,2721		},2722	},2723};2724 2725static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {2726	.halt_reg = 0x75010,2727	.halt_check = BRANCH_HALT,2728	.hwcg_reg = 0x75010,2729	.hwcg_bit = 1,2730	.clkr = {2731		.enable_reg = 0x75010,2732		.enable_mask = BIT(1),2733		.hw.init = &(struct clk_init_data){2734			.name = "gcc_ufs_card_axi_hw_ctl_clk",2735			.parent_hws = (const struct clk_hw *[]){2736				      &gcc_ufs_card_axi_clk.clkr.hw },2737			.num_parents = 1,2738			.flags = CLK_SET_RATE_PARENT,2739			.ops = &clk_branch_simple_ops,2740		},2741	},2742};2743 2744static struct clk_branch gcc_ufs_card_clkref_clk = {2745	.halt_reg = 0x8c004,2746	.halt_check = BRANCH_HALT,2747	.clkr = {2748		.enable_reg = 0x8c004,2749		.enable_mask = BIT(0),2750		.hw.init = &(struct clk_init_data){2751			.name = "gcc_ufs_card_clkref_clk",2752			.ops = &clk_branch2_ops,2753		},2754	},2755};2756 2757static struct clk_branch gcc_ufs_card_ice_core_clk = {2758	.halt_reg = 0x7505c,2759	.halt_check = BRANCH_HALT,2760	.hwcg_reg = 0x7505c,2761	.hwcg_bit = 1,2762	.clkr = {2763		.enable_reg = 0x7505c,2764		.enable_mask = BIT(0),2765		.hw.init = &(struct clk_init_data){2766			.name = "gcc_ufs_card_ice_core_clk",2767			.parent_hws = (const struct clk_hw *[]){2768				      &gcc_ufs_card_ice_core_clk_src.clkr.hw },2769			.num_parents = 1,2770			.flags = CLK_SET_RATE_PARENT,2771			.ops = &clk_branch2_ops,2772		},2773	},2774};2775 2776static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {2777	.halt_reg = 0x7505c,2778	.halt_check = BRANCH_HALT,2779	.hwcg_reg = 0x7505c,2780	.hwcg_bit = 1,2781	.clkr = {2782		.enable_reg = 0x7505c,2783		.enable_mask = BIT(1),2784		.hw.init = &(struct clk_init_data){2785			.name = "gcc_ufs_card_ice_core_hw_ctl_clk",2786			.parent_hws = (const struct clk_hw *[]){2787				      &gcc_ufs_card_ice_core_clk.clkr.hw },2788			.num_parents = 1,2789			.flags = CLK_SET_RATE_PARENT,2790			.ops = &clk_branch_simple_ops,2791		},2792	},2793};2794 2795static struct clk_branch gcc_ufs_card_phy_aux_clk = {2796	.halt_reg = 0x75090,2797	.halt_check = BRANCH_HALT,2798	.hwcg_reg = 0x75090,2799	.hwcg_bit = 1,2800	.clkr = {2801		.enable_reg = 0x75090,2802		.enable_mask = BIT(0),2803		.hw.init = &(struct clk_init_data){2804			.name = "gcc_ufs_card_phy_aux_clk",2805			.parent_hws = (const struct clk_hw *[]){2806				      &gcc_ufs_card_phy_aux_clk_src.clkr.hw },2807			.num_parents = 1,2808			.flags = CLK_SET_RATE_PARENT,2809			.ops = &clk_branch2_ops,2810		},2811	},2812};2813 2814static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {2815	.halt_reg = 0x75090,2816	.halt_check = BRANCH_HALT,2817	.hwcg_reg = 0x75090,2818	.hwcg_bit = 1,2819	.clkr = {2820		.enable_reg = 0x75090,2821		.enable_mask = BIT(1),2822		.hw.init = &(struct clk_init_data){2823			.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",2824			.parent_hws = (const struct clk_hw *[]){2825				      &gcc_ufs_card_phy_aux_clk.clkr.hw },2826			.num_parents = 1,2827			.flags = CLK_SET_RATE_PARENT,2828			.ops = &clk_branch_simple_ops,2829		},2830	},2831};2832 2833/* external clocks so add BRANCH_HALT_SKIP */2834static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {2835	.halt_check = BRANCH_HALT_SKIP,2836	.clkr = {2837		.enable_reg = 0x7501c,2838		.enable_mask = BIT(0),2839		.hw.init = &(struct clk_init_data){2840			.name = "gcc_ufs_card_rx_symbol_0_clk",2841			.ops = &clk_branch2_ops,2842		},2843	},2844};2845 2846/* external clocks so add BRANCH_HALT_SKIP */2847static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {2848	.halt_check = BRANCH_HALT_SKIP,2849	.clkr = {2850		.enable_reg = 0x750ac,2851		.enable_mask = BIT(0),2852		.hw.init = &(struct clk_init_data){2853			.name = "gcc_ufs_card_rx_symbol_1_clk",2854			.ops = &clk_branch2_ops,2855		},2856	},2857};2858 2859/* external clocks so add BRANCH_HALT_SKIP */2860static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {2861	.halt_check = BRANCH_HALT_SKIP,2862	.clkr = {2863		.enable_reg = 0x75018,2864		.enable_mask = BIT(0),2865		.hw.init = &(struct clk_init_data){2866			.name = "gcc_ufs_card_tx_symbol_0_clk",2867			.ops = &clk_branch2_ops,2868		},2869	},2870};2871 2872static struct clk_branch gcc_ufs_card_unipro_core_clk = {2873	.halt_reg = 0x75058,2874	.halt_check = BRANCH_HALT,2875	.hwcg_reg = 0x75058,2876	.hwcg_bit = 1,2877	.clkr = {2878		.enable_reg = 0x75058,2879		.enable_mask = BIT(0),2880		.hw.init = &(struct clk_init_data){2881			.name = "gcc_ufs_card_unipro_core_clk",2882			.parent_hws = (const struct clk_hw *[]){2883				&gcc_ufs_card_unipro_core_clk_src.clkr.hw },2884			.num_parents = 1,2885			.flags = CLK_SET_RATE_PARENT,2886			.ops = &clk_branch2_ops,2887		},2888	},2889};2890 2891static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {2892	.halt_reg = 0x75058,2893	.halt_check = BRANCH_HALT,2894	.hwcg_reg = 0x75058,2895	.hwcg_bit = 1,2896	.clkr = {2897		.enable_reg = 0x75058,2898		.enable_mask = BIT(1),2899		.hw.init = &(struct clk_init_data){2900			.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",2901			.parent_hws = (const struct clk_hw *[]){2902				      &gcc_ufs_card_unipro_core_clk.clkr.hw },2903			.num_parents = 1,2904			.flags = CLK_SET_RATE_PARENT,2905			.ops = &clk_branch_simple_ops,2906		},2907	},2908};2909 2910static struct clk_branch gcc_ufs_mem_clkref_clk = {2911	.halt_reg = 0x8c000,2912	.halt_check = BRANCH_HALT,2913	.clkr = {2914		.enable_reg = 0x8c000,2915		.enable_mask = BIT(0),2916		.hw.init = &(struct clk_init_data){2917			.name = "gcc_ufs_mem_clkref_clk",2918			.ops = &clk_branch2_ops,2919		},2920	},2921};2922 2923static struct clk_branch gcc_ufs_phy_ahb_clk = {2924	.halt_reg = 0x77014,2925	.halt_check = BRANCH_HALT,2926	.hwcg_reg = 0x77014,2927	.hwcg_bit = 1,2928	.clkr = {2929		.enable_reg = 0x77014,2930		.enable_mask = BIT(0),2931		.hw.init = &(struct clk_init_data){2932			.name = "gcc_ufs_phy_ahb_clk",2933			.ops = &clk_branch2_ops,2934		},2935	},2936};2937 2938static struct clk_branch gcc_ufs_phy_axi_clk = {2939	.halt_reg = 0x77010,2940	.halt_check = BRANCH_HALT,2941	.hwcg_reg = 0x77010,2942	.hwcg_bit = 1,2943	.clkr = {2944		.enable_reg = 0x77010,2945		.enable_mask = BIT(0),2946		.hw.init = &(struct clk_init_data){2947			.name = "gcc_ufs_phy_axi_clk",2948			.parent_hws = (const struct clk_hw *[]){2949				&gcc_ufs_phy_axi_clk_src.clkr.hw },2950			.num_parents = 1,2951			.flags = CLK_SET_RATE_PARENT,2952			.ops = &clk_branch2_ops,2953		},2954	},2955};2956 2957static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {2958	.halt_reg = 0x77010,2959	.halt_check = BRANCH_HALT,2960	.hwcg_reg = 0x77010,2961	.hwcg_bit = 1,2962	.clkr = {2963		.enable_reg = 0x77010,2964		.enable_mask = BIT(1),2965		.hw.init = &(struct clk_init_data){2966			.name = "gcc_ufs_phy_axi_hw_ctl_clk",2967			.parent_hws = (const struct clk_hw *[]){2968				      &gcc_ufs_phy_axi_clk.clkr.hw },2969			.num_parents = 1,2970			.flags = CLK_SET_RATE_PARENT,2971			.ops = &clk_branch_simple_ops,2972		},2973	},2974};2975 2976static struct clk_branch gcc_ufs_phy_ice_core_clk = {2977	.halt_reg = 0x7705c,2978	.halt_check = BRANCH_HALT,2979	.hwcg_reg = 0x7705c,2980	.hwcg_bit = 1,2981	.clkr = {2982		.enable_reg = 0x7705c,2983		.enable_mask = BIT(0),2984		.hw.init = &(struct clk_init_data){2985			.name = "gcc_ufs_phy_ice_core_clk",2986			.parent_hws = (const struct clk_hw *[]){2987				      &gcc_ufs_phy_ice_core_clk_src.clkr.hw },2988			.num_parents = 1,2989			.flags = CLK_SET_RATE_PARENT,2990			.ops = &clk_branch2_ops,2991		},2992	},2993};2994 2995static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {2996	.halt_reg = 0x7705c,2997	.halt_check = BRANCH_HALT,2998	.hwcg_reg = 0x7705c,2999	.hwcg_bit = 1,3000	.clkr = {3001		.enable_reg = 0x7705c,3002		.enable_mask = BIT(1),3003		.hw.init = &(struct clk_init_data){3004			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",3005			.parent_hws = (const struct clk_hw *[]){3006				      &gcc_ufs_phy_ice_core_clk.clkr.hw },3007			.num_parents = 1,3008			.flags = CLK_SET_RATE_PARENT,3009			.ops = &clk_branch_simple_ops,3010		},3011	},3012};3013 3014static struct clk_branch gcc_ufs_phy_phy_aux_clk = {3015	.halt_reg = 0x77090,3016	.halt_check = BRANCH_HALT,3017	.hwcg_reg = 0x77090,3018	.hwcg_bit = 1,3019	.clkr = {3020		.enable_reg = 0x77090,3021		.enable_mask = BIT(0),3022		.hw.init = &(struct clk_init_data){3023			.name = "gcc_ufs_phy_phy_aux_clk",3024			.parent_hws = (const struct clk_hw *[]){3025				      &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },3026			.num_parents = 1,3027			.flags = CLK_SET_RATE_PARENT,3028			.ops = &clk_branch2_ops,3029		},3030	},3031};3032 3033static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {3034	.halt_reg = 0x77090,3035	.halt_check = BRANCH_HALT,3036	.hwcg_reg = 0x77090,3037	.hwcg_bit = 1,3038	.clkr = {3039		.enable_reg = 0x77090,3040		.enable_mask = BIT(1),3041		.hw.init = &(struct clk_init_data){3042			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",3043			.parent_hws = (const struct clk_hw *[]){3044				      &gcc_ufs_phy_phy_aux_clk.clkr.hw },3045			.num_parents = 1,3046			.flags = CLK_SET_RATE_PARENT,3047			.ops = &clk_branch_simple_ops,3048		},3049	},3050};3051 3052/* external clocks so add BRANCH_HALT_SKIP */3053static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {3054	.halt_check = BRANCH_HALT_SKIP,3055	.clkr = {3056		.enable_reg = 0x7701c,3057		.enable_mask = BIT(0),3058		.hw.init = &(struct clk_init_data){3059			.name = "gcc_ufs_phy_rx_symbol_0_clk",3060			.ops = &clk_branch2_ops,3061		},3062	},3063};3064 3065/* external clocks so add BRANCH_HALT_SKIP */3066static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {3067	.halt_check = BRANCH_HALT_SKIP,3068	.clkr = {3069		.enable_reg = 0x770ac,3070		.enable_mask = BIT(0),3071		.hw.init = &(struct clk_init_data){3072			.name = "gcc_ufs_phy_rx_symbol_1_clk",3073			.ops = &clk_branch2_ops,3074		},3075	},3076};3077 3078/* external clocks so add BRANCH_HALT_SKIP */3079static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {3080	.halt_check = BRANCH_HALT_SKIP,3081	.clkr = {3082		.enable_reg = 0x77018,3083		.enable_mask = BIT(0),3084		.hw.init = &(struct clk_init_data){3085			.name = "gcc_ufs_phy_tx_symbol_0_clk",3086			.ops = &clk_branch2_ops,3087		},3088	},3089};3090 3091static struct clk_branch gcc_ufs_phy_unipro_core_clk = {3092	.halt_reg = 0x77058,3093	.halt_check = BRANCH_HALT,3094	.hwcg_reg = 0x77058,3095	.hwcg_bit = 1,3096	.clkr = {3097		.enable_reg = 0x77058,3098		.enable_mask = BIT(0),3099		.hw.init = &(struct clk_init_data){3100			.name = "gcc_ufs_phy_unipro_core_clk",3101			.parent_hws = (const struct clk_hw *[]){3102				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw },3103			.num_parents = 1,3104			.flags = CLK_SET_RATE_PARENT,3105			.ops = &clk_branch2_ops,3106		},3107	},3108};3109 3110static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {3111	.halt_reg = 0x77058,3112	.halt_check = BRANCH_HALT,3113	.hwcg_reg = 0x77058,3114	.hwcg_bit = 1,3115	.clkr = {3116		.enable_reg = 0x77058,3117		.enable_mask = BIT(1),3118		.hw.init = &(struct clk_init_data){3119			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",3120			.parent_hws = (const struct clk_hw *[]){3121				      &gcc_ufs_phy_unipro_core_clk.clkr.hw },3122			.num_parents = 1,3123			.flags = CLK_SET_RATE_PARENT,3124			.ops = &clk_branch_simple_ops,3125		},3126	},3127};3128 3129static struct clk_branch gcc_usb30_prim_master_clk = {3130	.halt_reg = 0xf010,3131	.halt_check = BRANCH_HALT,3132	.clkr = {3133		.enable_reg = 0xf010,3134		.enable_mask = BIT(0),3135		.hw.init = &(struct clk_init_data){3136			.name = "gcc_usb30_prim_master_clk",3137			.parent_hws = (const struct clk_hw *[]){3138				      &gcc_usb30_prim_master_clk_src.clkr.hw },3139			.num_parents = 1,3140			.flags = CLK_SET_RATE_PARENT,3141			.ops = &clk_branch2_ops,3142		},3143	},3144};3145 3146static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {3147	.halt_reg = 0xf018,3148	.halt_check = BRANCH_HALT,3149	.clkr = {3150		.enable_reg = 0xf018,3151		.enable_mask = BIT(0),3152		.hw.init = &(struct clk_init_data){3153			.name = "gcc_usb30_prim_mock_utmi_clk",3154			.parent_hws = (const struct clk_hw *[]){3155				&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },3156			.num_parents = 1,3157			.flags = CLK_SET_RATE_PARENT,3158			.ops = &clk_branch2_ops,3159		},3160	},3161};3162 3163static struct clk_branch gcc_usb30_prim_sleep_clk = {3164	.halt_reg = 0xf014,3165	.halt_check = BRANCH_HALT,3166	.clkr = {3167		.enable_reg = 0xf014,3168		.enable_mask = BIT(0),3169		.hw.init = &(struct clk_init_data){3170			.name = "gcc_usb30_prim_sleep_clk",3171			.ops = &clk_branch2_ops,3172		},3173	},3174};3175 3176static struct clk_branch gcc_usb30_sec_master_clk = {3177	.halt_reg = 0x10010,3178	.halt_check = BRANCH_HALT,3179	.clkr = {3180		.enable_reg = 0x10010,3181		.enable_mask = BIT(0),3182		.hw.init = &(struct clk_init_data){3183			.name = "gcc_usb30_sec_master_clk",3184			.parent_hws = (const struct clk_hw *[]){3185				      &gcc_usb30_sec_master_clk_src.clkr.hw },3186			.num_parents = 1,3187			.flags = CLK_SET_RATE_PARENT,3188			.ops = &clk_branch2_ops,3189		},3190	},3191};3192 3193static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {3194	.halt_reg = 0x10018,3195	.halt_check = BRANCH_HALT,3196	.clkr = {3197		.enable_reg = 0x10018,3198		.enable_mask = BIT(0),3199		.hw.init = &(struct clk_init_data){3200			.name = "gcc_usb30_sec_mock_utmi_clk",3201			.parent_hws = (const struct clk_hw *[]){3202				&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },3203			.num_parents = 1,3204			.flags = CLK_SET_RATE_PARENT,3205			.ops = &clk_branch2_ops,3206		},3207	},3208};3209 3210static struct clk_branch gcc_usb30_sec_sleep_clk = {3211	.halt_reg = 0x10014,3212	.halt_check = BRANCH_HALT,3213	.clkr = {3214		.enable_reg = 0x10014,3215		.enable_mask = BIT(0),3216		.hw.init = &(struct clk_init_data){3217			.name = "gcc_usb30_sec_sleep_clk",3218			.ops = &clk_branch2_ops,3219		},3220	},3221};3222 3223static struct clk_branch gcc_usb3_prim_clkref_clk = {3224	.halt_reg = 0x8c008,3225	.halt_check = BRANCH_HALT,3226	.clkr = {3227		.enable_reg = 0x8c008,3228		.enable_mask = BIT(0),3229		.hw.init = &(struct clk_init_data){3230			.name = "gcc_usb3_prim_clkref_clk",3231			.ops = &clk_branch2_ops,3232		},3233	},3234};3235 3236static struct clk_branch gcc_usb3_prim_phy_aux_clk = {3237	.halt_reg = 0xf050,3238	.halt_check = BRANCH_HALT,3239	.clkr = {3240		.enable_reg = 0xf050,3241		.enable_mask = BIT(0),3242		.hw.init = &(struct clk_init_data){3243			.name = "gcc_usb3_prim_phy_aux_clk",3244			.parent_hws = (const struct clk_hw *[]){3245				      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },3246			.num_parents = 1,3247			.flags = CLK_SET_RATE_PARENT,3248			.ops = &clk_branch2_ops,3249		},3250	},3251};3252 3253static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {3254	.halt_reg = 0xf054,3255	.halt_check = BRANCH_HALT,3256	.clkr = {3257		.enable_reg = 0xf054,3258		.enable_mask = BIT(0),3259		.hw.init = &(struct clk_init_data){3260			.name = "gcc_usb3_prim_phy_com_aux_clk",3261			.parent_hws = (const struct clk_hw *[]){3262				      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },3263			.num_parents = 1,3264			.flags = CLK_SET_RATE_PARENT,3265			.ops = &clk_branch2_ops,3266		},3267	},3268};3269 3270static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {3271	.halt_check = BRANCH_HALT_SKIP,3272	.clkr = {3273		.enable_reg = 0xf058,3274		.enable_mask = BIT(0),3275		.hw.init = &(struct clk_init_data){3276			.name = "gcc_usb3_prim_phy_pipe_clk",3277			.ops = &clk_branch2_ops,3278		},3279	},3280};3281 3282static struct clk_branch gcc_usb3_sec_clkref_clk = {3283	.halt_reg = 0x8c028,3284	.halt_check = BRANCH_HALT,3285	.clkr = {3286		.enable_reg = 0x8c028,3287		.enable_mask = BIT(0),3288		.hw.init = &(struct clk_init_data){3289			.name = "gcc_usb3_sec_clkref_clk",3290			.ops = &clk_branch2_ops,3291		},3292	},3293};3294 3295static struct clk_branch gcc_usb3_sec_phy_aux_clk = {3296	.halt_reg = 0x10050,3297	.halt_check = BRANCH_HALT,3298	.clkr = {3299		.enable_reg = 0x10050,3300		.enable_mask = BIT(0),3301		.hw.init = &(struct clk_init_data){3302			.name = "gcc_usb3_sec_phy_aux_clk",3303			.parent_hws = (const struct clk_hw *[]){3304				      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },3305			.num_parents = 1,3306			.flags = CLK_SET_RATE_PARENT,3307			.ops = &clk_branch2_ops,3308		},3309	},3310};3311 3312static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {3313	.halt_reg = 0x10054,3314	.halt_check = BRANCH_HALT,3315	.clkr = {3316		.enable_reg = 0x10054,3317		.enable_mask = BIT(0),3318		.hw.init = &(struct clk_init_data){3319			.name = "gcc_usb3_sec_phy_com_aux_clk",3320			.parent_hws = (const struct clk_hw *[]){3321				      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },3322			.num_parents = 1,3323			.flags = CLK_SET_RATE_PARENT,3324			.ops = &clk_branch2_ops,3325		},3326	},3327};3328 3329static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {3330	.halt_check = BRANCH_HALT_SKIP,3331	.clkr = {3332		.enable_reg = 0x10058,3333		.enable_mask = BIT(0),3334		.hw.init = &(struct clk_init_data){3335			.name = "gcc_usb3_sec_phy_pipe_clk",3336			.ops = &clk_branch2_ops,3337		},3338	},3339};3340 3341/*3342 * Clock ON depends on external parent 'config noc', so cant poll3343 * delay and also mark as crtitical for video boot3344 */3345static struct clk_branch gcc_video_ahb_clk = {3346	.halt_reg = 0xb004,3347	.halt_check = BRANCH_HALT_DELAY,3348	.hwcg_reg = 0xb004,3349	.hwcg_bit = 1,3350	.clkr = {3351		.enable_reg = 0xb004,3352		.enable_mask = BIT(0),3353		.hw.init = &(struct clk_init_data){3354			.name = "gcc_video_ahb_clk",3355			.flags = CLK_IS_CRITICAL,3356			.ops = &clk_branch2_ops,3357		},3358	},3359};3360 3361static struct clk_branch gcc_video_axi0_clk = {3362	.halt_reg = 0xb024,3363	.halt_check = BRANCH_HALT,3364	.clkr = {3365		.enable_reg = 0xb024,3366		.enable_mask = BIT(0),3367		.hw.init = &(struct clk_init_data){3368			.name = "gcc_video_axi0_clk",3369			.ops = &clk_branch2_ops,3370		},3371	},3372};3373 3374static struct clk_branch gcc_video_axi1_clk = {3375	.halt_reg = 0xb028,3376	.halt_check = BRANCH_HALT,3377	.clkr = {3378		.enable_reg = 0xb028,3379		.enable_mask = BIT(0),3380		.hw.init = &(struct clk_init_data){3381			.name = "gcc_video_axi1_clk",3382			.ops = &clk_branch2_ops,3383		},3384	},3385};3386 3387static struct clk_branch gcc_video_axic_clk = {3388	.halt_reg = 0xb02c,3389	.halt_check = BRANCH_HALT,3390	.clkr = {3391		.enable_reg = 0xb02c,3392		.enable_mask = BIT(0),3393		.hw.init = &(struct clk_init_data){3394			.name = "gcc_video_axic_clk",3395			.ops = &clk_branch2_ops,3396		},3397	},3398};3399 3400/* XO critical input to video, so no need to poll */3401static struct clk_branch gcc_video_xo_clk = {3402	.halt_reg = 0xb040,3403	.halt_check = BRANCH_HALT_DELAY,3404	.clkr = {3405		.enable_reg = 0xb040,3406		.enable_mask = BIT(0),3407		.hw.init = &(struct clk_init_data){3408			.name = "gcc_video_xo_clk",3409			.flags = CLK_IS_CRITICAL,3410			.ops = &clk_branch2_ops,3411		},3412	},3413};3414 3415static struct gdsc pcie_0_gdsc = {3416	.gdscr = 0x6b004,3417	.pd = {3418		.name = "pcie_0_gdsc",3419	},3420	.pwrsts = PWRSTS_OFF_ON,3421	.flags = POLL_CFG_GDSCR,3422};3423 3424static struct gdsc pcie_1_gdsc = {3425	.gdscr = 0x8d004,3426	.pd = {3427		.name = "pcie_1_gdsc",3428	},3429	.pwrsts = PWRSTS_OFF_ON,3430	.flags = POLL_CFG_GDSCR,3431};3432 3433static struct gdsc ufs_card_gdsc = {3434	.gdscr = 0x75004,3435	.pd = {3436		.name = "ufs_card_gdsc",3437	},3438	.pwrsts = PWRSTS_OFF_ON,3439	.flags = POLL_CFG_GDSCR,3440};3441 3442static struct gdsc ufs_phy_gdsc = {3443	.gdscr = 0x77004,3444	.pd = {3445		.name = "ufs_phy_gdsc",3446	},3447	.pwrsts = PWRSTS_OFF_ON,3448	.flags = POLL_CFG_GDSCR,3449};3450 3451static struct gdsc emac_gdsc = {3452	.gdscr = 0x6004,3453	.pd = {3454		.name = "emac_gdsc",3455	},3456	.pwrsts = PWRSTS_OFF_ON,3457	.flags = POLL_CFG_GDSCR,3458};3459 3460static struct gdsc usb30_prim_gdsc = {3461	.gdscr = 0xf004,3462	.pd = {3463		.name = "usb30_prim_gdsc",3464	},3465	.pwrsts = PWRSTS_OFF_ON,3466	.flags = POLL_CFG_GDSCR,3467};3468 3469static struct gdsc usb30_sec_gdsc = {3470	.gdscr = 0x10004,3471	.pd = {3472		.name = "usb30_sec_gdsc",3473	},3474	.pwrsts = PWRSTS_OFF_ON,3475	.flags = POLL_CFG_GDSCR,3476};3477 3478static struct clk_regmap *gcc_sm8150_clocks[] = {3479	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,3480	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,3481	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =3482		&gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,3483	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,3484	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =3485		&gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,3486	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,3487	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,3488	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,3489	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,3490	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,3491	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,3492	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,3493	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,3494	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,3495	[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,3496	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,3497	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,3498	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,3499	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,3500	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,3501	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,3502	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,3503	[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,3504	[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,3505	[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,3506	[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,3507	[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,3508	[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,3509	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,3510	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,3511	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,3512	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,3513	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,3514	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,3515	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,3516	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,3517	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,3518	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,3519	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,3520	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,3521	[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,3522	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,3523	[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,3524	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,3525	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,3526	[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,3527	[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,3528	[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,3529	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,3530	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,3531	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,3532	[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,3533	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,3534	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,3535	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,3536	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,3537	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,3538	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,3539	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,3540	[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,3541	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,3542	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,3543	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,3544	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,3545	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,3546	[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,3547	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,3548	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,3549	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,3550	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,3551	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,3552	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,3553	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,3554	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,3555	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,3556	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,3557	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,3558	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,3559	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,3560	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,3561	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,3562	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,3563	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,3564	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,3565	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,3566	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,3567	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,3568	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,3569	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,3570	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,3571	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,3572	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,3573	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,3574	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,3575	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,3576	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,3577	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,3578	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,3579	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,3580	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,3581	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,3582	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,3583	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,3584	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,3585	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,3586	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,3587	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,3588	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,3589	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,3590	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,3591	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,3592	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,3593	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,3594	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,3595	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,3596	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,3597	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,3598	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,3599	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,3600	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,3601	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,3602	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,3603	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,3604	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,3605	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,3606	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,3607	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,3608	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,3609	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,3610	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,3611	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,3612	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,3613	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,3614	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,3615	[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,3616	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,3617	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,3618	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,3619	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,3620	[GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,3621	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,3622	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,3623	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =3624		&gcc_ufs_card_ice_core_hw_ctl_clk.clkr,3625	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,3626	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,3627	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =3628		&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,3629	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,3630	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,3631	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,3632	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,3633	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =3634		&gcc_ufs_card_unipro_core_clk_src.clkr,3635	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =3636		&gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,3637	[GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,3638	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,3639	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,3640	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,3641	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,3642	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,3643	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,3644	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =3645		&gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,3646	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,3647	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,3648	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,3649	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,3650	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,3651	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,3652	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,3653	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =3654		&gcc_ufs_phy_unipro_core_clk_src.clkr,3655	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =3656		&gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,3657	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,3658	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,3659	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,3660	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =3661		&gcc_usb30_prim_mock_utmi_clk_src.clkr,3662	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,3663	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,3664	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,3665	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,3666	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =3667		&gcc_usb30_sec_mock_utmi_clk_src.clkr,3668	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,3669	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,3670	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,3671	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,3672	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,3673	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,3674	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,3675	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,3676	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,3677	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,3678	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,3679	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,3680	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,3681	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,3682	[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,3683	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,3684	[GPLL0] = &gpll0.clkr,3685	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,3686	[GPLL7] = &gpll7.clkr,3687	[GPLL9] = &gpll9.clkr,3688};3689 3690static const struct qcom_reset_map gcc_sm8150_resets[] = {3691	[GCC_EMAC_BCR] = { 0x6000 },3692	[GCC_GPU_BCR] = { 0x71000 },3693	[GCC_MMSS_BCR] = { 0xb000 },3694	[GCC_NPU_BCR] = { 0x4d000 },3695	[GCC_PCIE_0_BCR] = { 0x6b000 },3696	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },3697	[GCC_PCIE_1_BCR] = { 0x8d000 },3698	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },3699	[GCC_PCIE_PHY_BCR] = { 0x6f000 },3700	[GCC_PDM_BCR] = { 0x33000 },3701	[GCC_PRNG_BCR] = { 0x34000 },3702	[GCC_QSPI_BCR] = { 0x24008 },3703	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },3704	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },3705	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },3706	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },3707	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },3708	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },3709	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },3710	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },3711	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },3712	[GCC_SDCC2_BCR] = { 0x14000 },3713	[GCC_SDCC4_BCR] = { 0x16000 },3714	[GCC_TSIF_BCR] = { 0x36000 },3715	[GCC_UFS_CARD_BCR] = { 0x75000 },3716	[GCC_UFS_PHY_BCR] = { 0x77000 },3717	[GCC_USB30_PRIM_BCR] = { 0xf000 },3718	[GCC_USB30_SEC_BCR] = { 0x10000 },3719	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },3720	[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },3721	[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },3722	[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },3723};3724 3725static struct gdsc *gcc_sm8150_gdscs[] = {3726	[EMAC_GDSC] = &emac_gdsc,3727	[PCIE_0_GDSC] = &pcie_0_gdsc,3728	[PCIE_1_GDSC] = &pcie_1_gdsc,3729	[UFS_CARD_GDSC] = &ufs_card_gdsc,3730	[UFS_PHY_GDSC] = &ufs_phy_gdsc,3731	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,3732	[USB30_SEC_GDSC] = &usb30_sec_gdsc,3733};3734 3735static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {3736	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),3737	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),3738	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),3739	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),3740	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),3741	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),3742	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),3743	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),3744	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),3745	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),3746	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),3747	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),3748	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),3749	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),3750	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),3751	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),3752	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),3753	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),3754	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),3755	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),3756};3757 3758static const struct regmap_config gcc_sm8150_regmap_config = {3759	.reg_bits	= 32,3760	.reg_stride	= 4,3761	.val_bits	= 32,3762	.max_register	= 0x9c040,3763	.fast_io	= true,3764};3765 3766static const struct qcom_cc_desc gcc_sm8150_desc = {3767	.config = &gcc_sm8150_regmap_config,3768	.clks = gcc_sm8150_clocks,3769	.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),3770	.resets = gcc_sm8150_resets,3771	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),3772	.gdscs = gcc_sm8150_gdscs,3773	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),3774};3775 3776static const struct of_device_id gcc_sm8150_match_table[] = {3777	{ .compatible = "qcom,gcc-sm8150" },3778	{ }3779};3780MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);3781 3782static int gcc_sm8150_probe(struct platform_device *pdev)3783{3784	struct regmap *regmap;3785	int ret;3786 3787	regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);3788	if (IS_ERR(regmap))3789		return PTR_ERR(regmap);3790 3791	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */3792	regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);3793	regmap_update_bits(regmap, 0x71028, 0x3, 0x3);3794 3795	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,3796				       ARRAY_SIZE(gcc_dfs_clocks));3797	if (ret)3798		dev_err_probe(&pdev->dev, ret, "Failed to register with DFS!\n");3799 3800	return qcom_cc_really_probe(&pdev->dev, &gcc_sm8150_desc, regmap);3801}3802 3803static struct platform_driver gcc_sm8150_driver = {3804	.probe		= gcc_sm8150_probe,3805	.driver		= {3806		.name	= "gcc-sm8150",3807		.of_match_table = gcc_sm8150_match_table,3808	},3809};3810 3811static int __init gcc_sm8150_init(void)3812{3813	return platform_driver_register(&gcc_sm8150_driver);3814}3815subsys_initcall(gcc_sm8150_init);3816 3817static void __exit gcc_sm8150_exit(void)3818{3819	platform_driver_unregister(&gcc_sm8150_driver);3820}3821module_exit(gcc_sm8150_exit);3822 3823MODULE_DESCRIPTION("QTI GCC SM8150 Driver");3824MODULE_LICENSE("GPL v2");3825