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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/regmap.h>11 12#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>13#include <dt-bindings/reset/qcom,x1e80100-gpucc.h>14 15#include "clk-alpha-pll.h"16#include "clk-branch.h"17#include "clk-rcg.h"18#include "clk-regmap.h"19#include "clk-regmap-divider.h"20#include "clk-regmap-mux.h"21#include "gdsc.h"22#include "reset.h"23 24enum {25 DT_BI_TCXO,26 DT_GPLL0_OUT_MAIN,27 DT_GPLL0_OUT_MAIN_DIV,28};29 30enum {31 P_BI_TCXO,32 P_GPLL0_OUT_MAIN,33 P_GPLL0_OUT_MAIN_DIV,34 P_GPU_CC_PLL0_OUT_MAIN,35 P_GPU_CC_PLL1_OUT_MAIN,36};37 38static const struct pll_vco lucid_ole_vco[] = {39 { 249600000, 2300000000, 0 },40};41 42static const struct pll_vco zonda_ole_vco[] = {43 { 700000000, 3600000000, 0 },44};45 46static const struct alpha_pll_config gpu_cc_pll0_config = {47 .l = 0x29,48 .alpha = 0xa000,49 .config_ctl_val = 0x08240800,50 .config_ctl_hi_val = 0x05008001,51 .config_ctl_hi1_val = 0x00000000,52 .config_ctl_hi2_val = 0x00000000,53 .user_ctl_val = 0x00000000,54 .user_ctl_hi_val = 0x02000000,55};56 57static struct clk_alpha_pll gpu_cc_pll0 = {58 .offset = 0x0,59 .vco_table = zonda_ole_vco,60 .num_vco = ARRAY_SIZE(zonda_ole_vco),61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE],62 .clkr = {63 .hw.init = &(const struct clk_init_data) {64 .name = "gpu_cc_pll0",65 .parent_data = &(const struct clk_parent_data) {66 .index = DT_BI_TCXO,67 },68 .num_parents = 1,69 .ops = &clk_alpha_pll_zonda_ole_ops,70 },71 },72};73 74static const struct alpha_pll_config gpu_cc_pll1_config = {75 .l = 0x16,76 .alpha = 0xeaaa,77 .config_ctl_val = 0x20485699,78 .config_ctl_hi_val = 0x00182261,79 .config_ctl_hi1_val = 0x82aa299c,80 .test_ctl_val = 0x00000000,81 .test_ctl_hi_val = 0x00000003,82 .test_ctl_hi1_val = 0x00009000,83 .test_ctl_hi2_val = 0x00000034,84 .user_ctl_val = 0x00000000,85 .user_ctl_hi_val = 0x00000005,86};87 88static struct clk_alpha_pll gpu_cc_pll1 = {89 .offset = 0x1000,90 .vco_table = lucid_ole_vco,91 .num_vco = ARRAY_SIZE(lucid_ole_vco),92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],93 .clkr = {94 .hw.init = &(const struct clk_init_data) {95 .name = "gpu_cc_pll1",96 .parent_data = &(const struct clk_parent_data) {97 .index = DT_BI_TCXO,98 },99 .num_parents = 1,100 .ops = &clk_alpha_pll_lucid_evo_ops,101 },102 },103};104 105static const struct parent_map gpu_cc_parent_map_0[] = {106 { P_BI_TCXO, 0 },107 { P_GPLL0_OUT_MAIN, 5 },108 { P_GPLL0_OUT_MAIN_DIV, 6 },109};110 111static const struct clk_parent_data gpu_cc_parent_data_0[] = {112 { .index = DT_BI_TCXO },113 { .index = DT_GPLL0_OUT_MAIN },114 { .index = DT_GPLL0_OUT_MAIN_DIV },115};116 117static const struct parent_map gpu_cc_parent_map_1[] = {118 { P_BI_TCXO, 0 },119 { P_GPU_CC_PLL0_OUT_MAIN, 1 },120 { P_GPU_CC_PLL1_OUT_MAIN, 3 },121 { P_GPLL0_OUT_MAIN, 5 },122 { P_GPLL0_OUT_MAIN_DIV, 6 },123};124 125static const struct clk_parent_data gpu_cc_parent_data_1[] = {126 { .index = DT_BI_TCXO },127 { .hw = &gpu_cc_pll0.clkr.hw },128 { .hw = &gpu_cc_pll1.clkr.hw },129 { .index = DT_GPLL0_OUT_MAIN },130 { .index = DT_GPLL0_OUT_MAIN_DIV },131};132 133static const struct parent_map gpu_cc_parent_map_2[] = {134 { P_BI_TCXO, 0 },135 { P_GPU_CC_PLL1_OUT_MAIN, 3 },136 { P_GPLL0_OUT_MAIN, 5 },137 { P_GPLL0_OUT_MAIN_DIV, 6 },138};139 140static const struct clk_parent_data gpu_cc_parent_data_2[] = {141 { .index = DT_BI_TCXO },142 { .hw = &gpu_cc_pll1.clkr.hw },143 { .index = DT_GPLL0_OUT_MAIN },144 { .index = DT_GPLL0_OUT_MAIN_DIV },145};146 147static const struct parent_map gpu_cc_parent_map_3[] = {148 { P_BI_TCXO, 0 },149};150 151static const struct clk_parent_data gpu_cc_parent_data_3[] = {152 { .index = DT_BI_TCXO },153};154 155static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {156 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),157 { }158};159 160static struct clk_rcg2 gpu_cc_ff_clk_src = {161 .cmd_rcgr = 0x9474,162 .mnd_width = 0,163 .hid_width = 5,164 .parent_map = gpu_cc_parent_map_0,165 .freq_tbl = ftbl_gpu_cc_ff_clk_src,166 .clkr.hw.init = &(const struct clk_init_data) {167 .name = "gpu_cc_ff_clk_src",168 .parent_data = gpu_cc_parent_data_0,169 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),170 .flags = CLK_SET_RATE_PARENT,171 .ops = &clk_rcg2_ops,172 },173};174 175static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {176 F(19200000, P_BI_TCXO, 1, 0, 0),177 F(220000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),178 F(550000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),179 { }180};181 182static struct clk_rcg2 gpu_cc_gmu_clk_src = {183 .cmd_rcgr = 0x9318,184 .mnd_width = 0,185 .hid_width = 5,186 .parent_map = gpu_cc_parent_map_1,187 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,188 .clkr.hw.init = &(const struct clk_init_data) {189 .name = "gpu_cc_gmu_clk_src",190 .parent_data = gpu_cc_parent_data_1,191 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),192 .flags = CLK_SET_RATE_PARENT,193 .ops = &clk_rcg2_shared_ops,194 },195};196 197static struct clk_rcg2 gpu_cc_hub_clk_src = {198 .cmd_rcgr = 0x93ec,199 .mnd_width = 0,200 .hid_width = 5,201 .parent_map = gpu_cc_parent_map_2,202 .freq_tbl = ftbl_gpu_cc_ff_clk_src,203 .clkr.hw.init = &(const struct clk_init_data) {204 .name = "gpu_cc_hub_clk_src",205 .parent_data = gpu_cc_parent_data_2,206 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),207 .flags = CLK_SET_RATE_PARENT,208 .ops = &clk_rcg2_ops,209 },210};211 212static struct clk_rcg2 gpu_cc_xo_clk_src = {213 .cmd_rcgr = 0x9010,214 .mnd_width = 0,215 .hid_width = 5,216 .parent_map = gpu_cc_parent_map_3,217 .freq_tbl = NULL,218 .clkr.hw.init = &(const struct clk_init_data) {219 .name = "gpu_cc_xo_clk_src",220 .parent_data = gpu_cc_parent_data_3,221 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),222 .flags = CLK_SET_RATE_PARENT,223 .ops = &clk_rcg2_ops,224 },225};226 227static struct clk_regmap_div gpu_cc_demet_div_clk_src = {228 .reg = 0x9054,229 .shift = 0,230 .width = 4,231 .clkr.hw.init = &(const struct clk_init_data) {232 .name = "gpu_cc_demet_div_clk_src",233 .parent_hws = (const struct clk_hw*[]) {234 &gpu_cc_xo_clk_src.clkr.hw,235 },236 .num_parents = 1,237 .flags = CLK_SET_RATE_PARENT,238 .ops = &clk_regmap_div_ro_ops,239 },240};241 242static struct clk_regmap_div gpu_cc_xo_div_clk_src = {243 .reg = 0x9050,244 .shift = 0,245 .width = 4,246 .clkr.hw.init = &(const struct clk_init_data) {247 .name = "gpu_cc_xo_div_clk_src",248 .parent_hws = (const struct clk_hw*[]) {249 &gpu_cc_xo_clk_src.clkr.hw,250 },251 .num_parents = 1,252 .flags = CLK_SET_RATE_PARENT,253 .ops = &clk_regmap_div_ro_ops,254 },255};256 257static struct clk_branch gpu_cc_ahb_clk = {258 .halt_reg = 0x911c,259 .halt_check = BRANCH_HALT_VOTED,260 .clkr = {261 .enable_reg = 0x911c,262 .enable_mask = BIT(0),263 .hw.init = &(const struct clk_init_data) {264 .name = "gpu_cc_ahb_clk",265 .parent_hws = (const struct clk_hw*[]) {266 &gpu_cc_hub_clk_src.clkr.hw,267 },268 .num_parents = 1,269 .flags = CLK_SET_RATE_PARENT,270 .ops = &clk_branch2_ops,271 },272 },273};274 275static struct clk_branch gpu_cc_crc_ahb_clk = {276 .halt_reg = 0x9120,277 .halt_check = BRANCH_HALT_VOTED,278 .clkr = {279 .enable_reg = 0x9120,280 .enable_mask = BIT(0),281 .hw.init = &(const struct clk_init_data) {282 .name = "gpu_cc_crc_ahb_clk",283 .parent_hws = (const struct clk_hw*[]) {284 &gpu_cc_hub_clk_src.clkr.hw,285 },286 .num_parents = 1,287 .flags = CLK_SET_RATE_PARENT,288 .ops = &clk_branch2_ops,289 },290 },291};292 293static struct clk_branch gpu_cc_cx_ff_clk = {294 .halt_reg = 0x914c,295 .halt_check = BRANCH_HALT,296 .clkr = {297 .enable_reg = 0x914c,298 .enable_mask = BIT(0),299 .hw.init = &(const struct clk_init_data) {300 .name = "gpu_cc_cx_ff_clk",301 .parent_hws = (const struct clk_hw*[]) {302 &gpu_cc_ff_clk_src.clkr.hw,303 },304 .num_parents = 1,305 .flags = CLK_SET_RATE_PARENT,306 .ops = &clk_branch2_ops,307 },308 },309};310 311static struct clk_branch gpu_cc_cx_gmu_clk = {312 .halt_reg = 0x913c,313 .halt_check = BRANCH_HALT_VOTED,314 .clkr = {315 .enable_reg = 0x913c,316 .enable_mask = BIT(0),317 .hw.init = &(const struct clk_init_data) {318 .name = "gpu_cc_cx_gmu_clk",319 .parent_hws = (const struct clk_hw*[]) {320 &gpu_cc_gmu_clk_src.clkr.hw,321 },322 .num_parents = 1,323 .flags = CLK_SET_RATE_PARENT,324 .ops = &clk_branch2_aon_ops,325 },326 },327};328 329static struct clk_branch gpu_cc_cxo_aon_clk = {330 .halt_reg = 0x9004,331 .halt_check = BRANCH_HALT_VOTED,332 .clkr = {333 .enable_reg = 0x9004,334 .enable_mask = BIT(0),335 .hw.init = &(const struct clk_init_data) {336 .name = "gpu_cc_cxo_aon_clk",337 .parent_hws = (const struct clk_hw*[]) {338 &gpu_cc_xo_clk_src.clkr.hw,339 },340 .num_parents = 1,341 .flags = CLK_SET_RATE_PARENT,342 .ops = &clk_branch2_ops,343 },344 },345};346 347static struct clk_branch gpu_cc_cxo_clk = {348 .halt_reg = 0x9144,349 .halt_check = BRANCH_HALT,350 .clkr = {351 .enable_reg = 0x9144,352 .enable_mask = BIT(0),353 .hw.init = &(const struct clk_init_data) {354 .name = "gpu_cc_cxo_clk",355 .parent_hws = (const struct clk_hw*[]) {356 &gpu_cc_xo_clk_src.clkr.hw,357 },358 .num_parents = 1,359 .flags = CLK_SET_RATE_PARENT,360 .ops = &clk_branch2_ops,361 },362 },363};364 365static struct clk_branch gpu_cc_demet_clk = {366 .halt_reg = 0x900c,367 .halt_check = BRANCH_HALT,368 .clkr = {369 .enable_reg = 0x900c,370 .enable_mask = BIT(0),371 .hw.init = &(const struct clk_init_data) {372 .name = "gpu_cc_demet_clk",373 .parent_hws = (const struct clk_hw*[]) {374 &gpu_cc_demet_div_clk_src.clkr.hw,375 },376 .num_parents = 1,377 .flags = CLK_SET_RATE_PARENT,378 .ops = &clk_branch2_aon_ops,379 },380 },381};382 383static struct clk_branch gpu_cc_freq_measure_clk = {384 .halt_reg = 0x9008,385 .halt_check = BRANCH_HALT,386 .clkr = {387 .enable_reg = 0x9008,388 .enable_mask = BIT(0),389 .hw.init = &(const struct clk_init_data) {390 .name = "gpu_cc_freq_measure_clk",391 .parent_hws = (const struct clk_hw*[]) {392 &gpu_cc_xo_div_clk_src.clkr.hw,393 },394 .num_parents = 1,395 .flags = CLK_SET_RATE_PARENT,396 .ops = &clk_branch2_ops,397 },398 },399};400 401static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {402 .halt_reg = 0x7000,403 .halt_check = BRANCH_HALT_VOTED,404 .clkr = {405 .enable_reg = 0x7000,406 .enable_mask = BIT(0),407 .hw.init = &(const struct clk_init_data) {408 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",409 .ops = &clk_branch2_ops,410 },411 },412};413 414static struct clk_branch gpu_cc_gx_gmu_clk = {415 .halt_reg = 0x90bc,416 .halt_check = BRANCH_HALT,417 .clkr = {418 .enable_reg = 0x90bc,419 .enable_mask = BIT(0),420 .hw.init = &(const struct clk_init_data) {421 .name = "gpu_cc_gx_gmu_clk",422 .parent_hws = (const struct clk_hw*[]) {423 &gpu_cc_gmu_clk_src.clkr.hw,424 },425 .num_parents = 1,426 .flags = CLK_SET_RATE_PARENT,427 .ops = &clk_branch2_ops,428 },429 },430};431 432static struct clk_branch gpu_cc_gx_vsense_clk = {433 .halt_reg = 0x90b0,434 .halt_check = BRANCH_HALT_VOTED,435 .clkr = {436 .enable_reg = 0x90b0,437 .enable_mask = BIT(0),438 .hw.init = &(const struct clk_init_data) {439 .name = "gpu_cc_gx_vsense_clk",440 .ops = &clk_branch2_ops,441 },442 },443};444 445static struct clk_branch gpu_cc_hub_aon_clk = {446 .halt_reg = 0x93e8,447 .halt_check = BRANCH_HALT,448 .clkr = {449 .enable_reg = 0x93e8,450 .enable_mask = BIT(0),451 .hw.init = &(const struct clk_init_data) {452 .name = "gpu_cc_hub_aon_clk",453 .parent_hws = (const struct clk_hw*[]) {454 &gpu_cc_hub_clk_src.clkr.hw,455 },456 .num_parents = 1,457 .flags = CLK_SET_RATE_PARENT,458 .ops = &clk_branch2_aon_ops,459 },460 },461};462 463static struct clk_branch gpu_cc_hub_cx_int_clk = {464 .halt_reg = 0x9148,465 .halt_check = BRANCH_HALT_VOTED,466 .clkr = {467 .enable_reg = 0x9148,468 .enable_mask = BIT(0),469 .hw.init = &(const struct clk_init_data) {470 .name = "gpu_cc_hub_cx_int_clk",471 .parent_hws = (const struct clk_hw*[]) {472 &gpu_cc_hub_clk_src.clkr.hw,473 },474 .num_parents = 1,475 .flags = CLK_SET_RATE_PARENT,476 .ops = &clk_branch2_aon_ops,477 },478 },479};480 481static struct clk_branch gpu_cc_memnoc_gfx_clk = {482 .halt_reg = 0x9150,483 .halt_check = BRANCH_HALT_VOTED,484 .clkr = {485 .enable_reg = 0x9150,486 .enable_mask = BIT(0),487 .hw.init = &(const struct clk_init_data) {488 .name = "gpu_cc_memnoc_gfx_clk",489 .ops = &clk_branch2_ops,490 },491 },492};493 494static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {495 .halt_reg = 0x9288,496 .halt_check = BRANCH_HALT,497 .clkr = {498 .enable_reg = 0x9288,499 .enable_mask = BIT(0),500 .hw.init = &(const struct clk_init_data) {501 .name = "gpu_cc_mnd1x_0_gfx3d_clk",502 .ops = &clk_branch2_ops,503 },504 },505};506 507static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {508 .halt_reg = 0x928c,509 .halt_check = BRANCH_HALT,510 .clkr = {511 .enable_reg = 0x928c,512 .enable_mask = BIT(0),513 .hw.init = &(const struct clk_init_data) {514 .name = "gpu_cc_mnd1x_1_gfx3d_clk",515 .ops = &clk_branch2_ops,516 },517 },518};519 520static struct clk_branch gpu_cc_sleep_clk = {521 .halt_reg = 0x9134,522 .halt_check = BRANCH_HALT_VOTED,523 .clkr = {524 .enable_reg = 0x9134,525 .enable_mask = BIT(0),526 .hw.init = &(const struct clk_init_data) {527 .name = "gpu_cc_sleep_clk",528 .ops = &clk_branch2_ops,529 },530 },531};532 533static struct gdsc gpu_cx_gdsc = {534 .gdscr = 0x9108,535 .gds_hw_ctrl = 0x953c,536 .en_rest_wait_val = 0x2,537 .en_few_wait_val = 0x2,538 .clk_dis_wait_val = 0xf,539 .pd = {540 .name = "gpu_cx_gdsc",541 },542 .pwrsts = PWRSTS_OFF_ON,543 .flags = VOTABLE | RETAIN_FF_ENABLE,544};545 546static struct gdsc gpu_gx_gdsc = {547 .gdscr = 0x905c,548 .clamp_io_ctrl = 0x9504,549 .en_rest_wait_val = 0x2,550 .en_few_wait_val = 0x2,551 .clk_dis_wait_val = 0xf,552 .pd = {553 .name = "gpu_gx_gdsc",554 .power_on = gdsc_gx_do_nothing_enable,555 },556 .pwrsts = PWRSTS_OFF_ON,557 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,558};559 560static struct clk_regmap *gpu_cc_x1e80100_clocks[] = {561 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,562 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,563 [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,564 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,565 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,566 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,567 [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,568 [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,569 [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,570 [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,571 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,572 [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,573 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,574 [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,575 [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,576 [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,577 [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,578 [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,579 [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,580 [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,581 [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,582 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,583 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,584 [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,585 [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr,586};587 588static const struct qcom_reset_map gpu_cc_x1e80100_resets[] = {589 [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },590 [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },591 [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },592 [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },593 [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },594 [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },595 [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },596 [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },597 [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },598};599 600static struct gdsc *gpu_cc_x1e80100_gdscs[] = {601 [GPU_CX_GDSC] = &gpu_cx_gdsc,602 [GPU_GX_GDSC] = &gpu_gx_gdsc,603};604 605static const struct regmap_config gpu_cc_x1e80100_regmap_config = {606 .reg_bits = 32,607 .reg_stride = 4,608 .val_bits = 32,609 .max_register = 0x9988,610 .fast_io = true,611};612 613static const struct qcom_cc_desc gpu_cc_x1e80100_desc = {614 .config = &gpu_cc_x1e80100_regmap_config,615 .clks = gpu_cc_x1e80100_clocks,616 .num_clks = ARRAY_SIZE(gpu_cc_x1e80100_clocks),617 .resets = gpu_cc_x1e80100_resets,618 .num_resets = ARRAY_SIZE(gpu_cc_x1e80100_resets),619 .gdscs = gpu_cc_x1e80100_gdscs,620 .num_gdscs = ARRAY_SIZE(gpu_cc_x1e80100_gdscs),621};622 623static const struct of_device_id gpu_cc_x1e80100_match_table[] = {624 { .compatible = "qcom,x1e80100-gpucc" },625 { }626};627MODULE_DEVICE_TABLE(of, gpu_cc_x1e80100_match_table);628 629static int gpu_cc_x1e80100_probe(struct platform_device *pdev)630{631 struct regmap *regmap;632 633 regmap = qcom_cc_map(pdev, &gpu_cc_x1e80100_desc);634 if (IS_ERR(regmap))635 return PTR_ERR(regmap);636 637 clk_zonda_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);638 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);639 640 /* Keep clocks always enabled */641 qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */642 643 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_x1e80100_desc, regmap);644}645 646static struct platform_driver gpu_cc_x1e80100_driver = {647 .probe = gpu_cc_x1e80100_probe,648 .driver = {649 .name = "gpucc-x1e80100",650 .of_match_table = gpu_cc_x1e80100_match_table,651 },652};653module_platform_driver(gpu_cc_x1e80100_driver);654 655MODULE_DESCRIPTION("QTI GPU Clock Controller X1E80100 Driver");656MODULE_LICENSE("GPL");657