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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/mod_devicetable.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/pm_runtime.h>11#include <linux/regmap.h>12 13#include <dt-bindings/clock/qcom,sm8650-videocc.h>14 15#include "clk-alpha-pll.h"16#include "clk-branch.h"17#include "clk-rcg.h"18#include "clk-regmap.h"19#include "clk-regmap-divider.h"20#include "common.h"21#include "gdsc.h"22#include "reset.h"23 24enum {25 DT_BI_TCXO,26};27 28enum {29 P_BI_TCXO,30 P_VIDEO_CC_PLL0_OUT_MAIN,31 P_VIDEO_CC_PLL1_OUT_MAIN,32};33 34static const struct pll_vco lucid_ole_vco[] = {35 { 249600000, 2300000000, 0 },36};37 38static struct alpha_pll_config video_cc_pll0_config = {39 .l = 0x25,40 .alpha = 0x8000,41 .config_ctl_val = 0x20485699,42 .config_ctl_hi_val = 0x00182261,43 .config_ctl_hi1_val = 0x82aa299c,44 .test_ctl_val = 0x00000000,45 .test_ctl_hi_val = 0x00000003,46 .test_ctl_hi1_val = 0x00009000,47 .test_ctl_hi2_val = 0x00000034,48 .user_ctl_val = 0x00000000,49 .user_ctl_hi_val = 0x00000005,50};51 52static struct clk_alpha_pll video_cc_pll0 = {53 .offset = 0x0,54 .vco_table = lucid_ole_vco,55 .num_vco = ARRAY_SIZE(lucid_ole_vco),56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],57 .clkr = {58 .hw.init = &(const struct clk_init_data) {59 .name = "video_cc_pll0",60 .parent_data = &(const struct clk_parent_data) {61 .index = DT_BI_TCXO,62 },63 .num_parents = 1,64 .ops = &clk_alpha_pll_lucid_evo_ops,65 },66 },67};68 69static struct alpha_pll_config video_cc_pll1_config = {70 .l = 0x36,71 .alpha = 0xb000,72 .config_ctl_val = 0x20485699,73 .config_ctl_hi_val = 0x00182261,74 .config_ctl_hi1_val = 0x82aa299c,75 .test_ctl_val = 0x00000000,76 .test_ctl_hi_val = 0x00000003,77 .test_ctl_hi1_val = 0x00009000,78 .test_ctl_hi2_val = 0x00000034,79 .user_ctl_val = 0x00000000,80 .user_ctl_hi_val = 0x00000005,81};82 83static struct clk_alpha_pll video_cc_pll1 = {84 .offset = 0x1000,85 .vco_table = lucid_ole_vco,86 .num_vco = ARRAY_SIZE(lucid_ole_vco),87 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],88 .clkr = {89 .hw.init = &(const struct clk_init_data) {90 .name = "video_cc_pll1",91 .parent_data = &(const struct clk_parent_data) {92 .index = DT_BI_TCXO,93 },94 .num_parents = 1,95 .ops = &clk_alpha_pll_lucid_evo_ops,96 },97 },98};99 100static const struct parent_map video_cc_parent_map_0[] = {101 { P_BI_TCXO, 0 },102 { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },103};104 105static const struct clk_parent_data video_cc_parent_data_0[] = {106 { .index = DT_BI_TCXO },107 { .hw = &video_cc_pll0.clkr.hw },108};109 110static const struct parent_map video_cc_parent_map_1[] = {111 { P_BI_TCXO, 0 },112 { P_VIDEO_CC_PLL1_OUT_MAIN, 1 },113};114 115static const struct clk_parent_data video_cc_parent_data_1[] = {116 { .index = DT_BI_TCXO },117 { .hw = &video_cc_pll1.clkr.hw },118};119 120static const struct parent_map video_cc_parent_map_2[] = {121 { P_BI_TCXO, 0 },122};123 124static const struct clk_parent_data video_cc_parent_data_2[] = {125 { .index = DT_BI_TCXO },126};127 128static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {129 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),130 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),131 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),132 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),133 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),134 { }135};136 137static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {138 F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),139 F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),140 F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),141 F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),142 F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),143 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),144 { }145};146 147static struct clk_rcg2 video_cc_mvs0_clk_src = {148 .cmd_rcgr = 0x8000,149 .mnd_width = 0,150 .hid_width = 5,151 .parent_map = video_cc_parent_map_0,152 .freq_tbl = ftbl_video_cc_mvs0_clk_src,153 .clkr.hw.init = &(const struct clk_init_data) {154 .name = "video_cc_mvs0_clk_src",155 .parent_data = video_cc_parent_data_0,156 .num_parents = ARRAY_SIZE(video_cc_parent_data_0),157 .flags = CLK_SET_RATE_PARENT,158 .ops = &clk_rcg2_shared_ops,159 },160};161 162static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {163 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),164 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),165 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),166 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),167 { }168};169 170static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {171 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),172 F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),173 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),174 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),175 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),176 { }177};178 179static struct clk_rcg2 video_cc_mvs1_clk_src = {180 .cmd_rcgr = 0x8018,181 .mnd_width = 0,182 .hid_width = 5,183 .parent_map = video_cc_parent_map_1,184 .freq_tbl = ftbl_video_cc_mvs1_clk_src,185 .clkr.hw.init = &(const struct clk_init_data) {186 .name = "video_cc_mvs1_clk_src",187 .parent_data = video_cc_parent_data_1,188 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),189 .flags = CLK_SET_RATE_PARENT,190 .ops = &clk_rcg2_shared_ops,191 },192};193 194static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {195 F(19200000, P_BI_TCXO, 1, 0, 0),196 { }197};198 199static struct clk_rcg2 video_cc_xo_clk_src = {200 .cmd_rcgr = 0x810c,201 .mnd_width = 0,202 .hid_width = 5,203 .parent_map = video_cc_parent_map_2,204 .freq_tbl = ftbl_video_cc_xo_clk_src,205 .clkr.hw.init = &(const struct clk_init_data) {206 .name = "video_cc_xo_clk_src",207 .parent_data = video_cc_parent_data_2,208 .num_parents = ARRAY_SIZE(video_cc_parent_data_2),209 .flags = CLK_SET_RATE_PARENT,210 .ops = &clk_rcg2_shared_ops,211 },212};213 214static struct clk_regmap_div video_cc_mvs0_div_clk_src = {215 .reg = 0x80c4,216 .shift = 0,217 .width = 4,218 .clkr.hw.init = &(const struct clk_init_data) {219 .name = "video_cc_mvs0_div_clk_src",220 .parent_hws = (const struct clk_hw*[]) {221 &video_cc_mvs0_clk_src.clkr.hw,222 },223 .num_parents = 1,224 .flags = CLK_SET_RATE_PARENT,225 .ops = &clk_regmap_div_ro_ops,226 },227};228 229static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {230 .reg = 0x8070,231 .shift = 0,232 .width = 4,233 .clkr.hw.init = &(const struct clk_init_data) {234 .name = "video_cc_mvs0c_div2_div_clk_src",235 .parent_hws = (const struct clk_hw*[]) {236 &video_cc_mvs0_clk_src.clkr.hw,237 },238 .num_parents = 1,239 .flags = CLK_SET_RATE_PARENT,240 .ops = &clk_regmap_div_ro_ops,241 },242};243 244static struct clk_regmap_div video_cc_mvs1_div_clk_src = {245 .reg = 0x80ec,246 .shift = 0,247 .width = 4,248 .clkr.hw.init = &(const struct clk_init_data) {249 .name = "video_cc_mvs1_div_clk_src",250 .parent_hws = (const struct clk_hw*[]) {251 &video_cc_mvs1_clk_src.clkr.hw,252 },253 .num_parents = 1,254 .flags = CLK_SET_RATE_PARENT,255 .ops = &clk_regmap_div_ro_ops,256 },257};258 259static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {260 .reg = 0x809c,261 .shift = 0,262 .width = 4,263 .clkr.hw.init = &(const struct clk_init_data) {264 .name = "video_cc_mvs1c_div2_div_clk_src",265 .parent_hws = (const struct clk_hw*[]) {266 &video_cc_mvs1_clk_src.clkr.hw,267 },268 .num_parents = 1,269 .flags = CLK_SET_RATE_PARENT,270 .ops = &clk_regmap_div_ro_ops,271 },272};273 274static struct clk_branch video_cc_mvs0_clk = {275 .halt_reg = 0x80b8,276 .halt_check = BRANCH_HALT_SKIP,277 .hwcg_reg = 0x80b8,278 .hwcg_bit = 1,279 .clkr = {280 .enable_reg = 0x80b8,281 .enable_mask = BIT(0),282 .hw.init = &(const struct clk_init_data) {283 .name = "video_cc_mvs0_clk",284 .parent_hws = (const struct clk_hw*[]) {285 &video_cc_mvs0_div_clk_src.clkr.hw,286 },287 .num_parents = 1,288 .flags = CLK_SET_RATE_PARENT,289 .ops = &clk_branch2_ops,290 },291 },292};293 294static struct clk_branch video_cc_mvs0_shift_clk = {295 .halt_reg = 0x8128,296 .halt_check = BRANCH_HALT_VOTED,297 .hwcg_reg = 0x8128,298 .hwcg_bit = 1,299 .clkr = {300 .enable_reg = 0x8128,301 .enable_mask = BIT(0),302 .hw.init = &(const struct clk_init_data) {303 .name = "video_cc_mvs0_shift_clk",304 .parent_hws = (const struct clk_hw*[]) {305 &video_cc_xo_clk_src.clkr.hw,306 },307 .num_parents = 1,308 .flags = CLK_SET_RATE_PARENT,309 .ops = &clk_branch2_ops,310 },311 },312};313 314static struct clk_branch video_cc_mvs0c_clk = {315 .halt_reg = 0x8064,316 .halt_check = BRANCH_HALT,317 .clkr = {318 .enable_reg = 0x8064,319 .enable_mask = BIT(0),320 .hw.init = &(const struct clk_init_data) {321 .name = "video_cc_mvs0c_clk",322 .parent_hws = (const struct clk_hw*[]) {323 &video_cc_mvs0c_div2_div_clk_src.clkr.hw,324 },325 .num_parents = 1,326 .flags = CLK_SET_RATE_PARENT,327 .ops = &clk_branch2_ops,328 },329 },330};331 332static struct clk_branch video_cc_mvs0c_shift_clk = {333 .halt_reg = 0x812c,334 .halt_check = BRANCH_HALT_VOTED,335 .hwcg_reg = 0x812c,336 .hwcg_bit = 1,337 .clkr = {338 .enable_reg = 0x812c,339 .enable_mask = BIT(0),340 .hw.init = &(const struct clk_init_data) {341 .name = "video_cc_mvs0c_shift_clk",342 .parent_hws = (const struct clk_hw*[]) {343 &video_cc_xo_clk_src.clkr.hw,344 },345 .num_parents = 1,346 .flags = CLK_SET_RATE_PARENT,347 .ops = &clk_branch2_ops,348 },349 },350};351 352static struct clk_branch video_cc_mvs1_clk = {353 .halt_reg = 0x80e0,354 .halt_check = BRANCH_HALT_SKIP,355 .hwcg_reg = 0x80e0,356 .hwcg_bit = 1,357 .clkr = {358 .enable_reg = 0x80e0,359 .enable_mask = BIT(0),360 .hw.init = &(const struct clk_init_data) {361 .name = "video_cc_mvs1_clk",362 .parent_hws = (const struct clk_hw*[]) {363 &video_cc_mvs1_div_clk_src.clkr.hw,364 },365 .num_parents = 1,366 .flags = CLK_SET_RATE_PARENT,367 .ops = &clk_branch2_ops,368 },369 },370};371 372static struct clk_branch video_cc_mvs1_shift_clk = {373 .halt_reg = 0x8130,374 .halt_check = BRANCH_HALT_VOTED,375 .hwcg_reg = 0x8130,376 .hwcg_bit = 1,377 .clkr = {378 .enable_reg = 0x8130,379 .enable_mask = BIT(0),380 .hw.init = &(const struct clk_init_data) {381 .name = "video_cc_mvs1_shift_clk",382 .parent_hws = (const struct clk_hw*[]) {383 &video_cc_xo_clk_src.clkr.hw,384 },385 .num_parents = 1,386 .flags = CLK_SET_RATE_PARENT,387 .ops = &clk_branch2_ops,388 },389 },390};391 392static struct clk_branch video_cc_mvs1c_clk = {393 .halt_reg = 0x8090,394 .halt_check = BRANCH_HALT,395 .clkr = {396 .enable_reg = 0x8090,397 .enable_mask = BIT(0),398 .hw.init = &(const struct clk_init_data) {399 .name = "video_cc_mvs1c_clk",400 .parent_hws = (const struct clk_hw*[]) {401 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,402 },403 .num_parents = 1,404 .flags = CLK_SET_RATE_PARENT,405 .ops = &clk_branch2_ops,406 },407 },408};409 410static struct clk_branch video_cc_mvs1c_shift_clk = {411 .halt_reg = 0x8134,412 .halt_check = BRANCH_HALT_VOTED,413 .hwcg_reg = 0x8134,414 .hwcg_bit = 1,415 .clkr = {416 .enable_reg = 0x8134,417 .enable_mask = BIT(0),418 .hw.init = &(const struct clk_init_data) {419 .name = "video_cc_mvs1c_shift_clk",420 .parent_hws = (const struct clk_hw*[]) {421 &video_cc_xo_clk_src.clkr.hw,422 },423 .num_parents = 1,424 .flags = CLK_SET_RATE_PARENT,425 .ops = &clk_branch2_ops,426 },427 },428};429 430static struct gdsc video_cc_mvs0c_gdsc = {431 .gdscr = 0x804c,432 .en_rest_wait_val = 0x2,433 .en_few_wait_val = 0x2,434 .clk_dis_wait_val = 0x6,435 .pd = {436 .name = "video_cc_mvs0c_gdsc",437 },438 .pwrsts = PWRSTS_OFF_ON,439 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,440};441 442static struct gdsc video_cc_mvs0_gdsc = {443 .gdscr = 0x80a4,444 .en_rest_wait_val = 0x2,445 .en_few_wait_val = 0x2,446 .clk_dis_wait_val = 0x6,447 .pd = {448 .name = "video_cc_mvs0_gdsc",449 },450 .pwrsts = PWRSTS_OFF_ON,451 .parent = &video_cc_mvs0c_gdsc.pd,452 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,453};454 455static struct gdsc video_cc_mvs1c_gdsc = {456 .gdscr = 0x8078,457 .en_rest_wait_val = 0x2,458 .en_few_wait_val = 0x2,459 .clk_dis_wait_val = 0x6,460 .pd = {461 .name = "video_cc_mvs1c_gdsc",462 },463 .pwrsts = PWRSTS_OFF_ON,464 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,465};466 467static struct gdsc video_cc_mvs1_gdsc = {468 .gdscr = 0x80cc,469 .en_rest_wait_val = 0x2,470 .en_few_wait_val = 0x2,471 .clk_dis_wait_val = 0x6,472 .pd = {473 .name = "video_cc_mvs1_gdsc",474 },475 .pwrsts = PWRSTS_OFF_ON,476 .parent = &video_cc_mvs1c_gdsc.pd,477 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,478};479 480static struct clk_regmap *video_cc_sm8550_clocks[] = {481 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,482 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,483 [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,484 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,485 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,486 [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,487 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,488 [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,489 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,490 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,491 [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,492 [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,493 [VIDEO_CC_XO_CLK_SRC] = NULL,494};495 496static struct gdsc *video_cc_sm8550_gdscs[] = {497 [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,498 [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,499 [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,500 [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,501};502 503static const struct qcom_reset_map video_cc_sm8550_resets[] = {504 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },505 [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },506 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },507 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },508 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },509 [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },510 [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },511 [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },512};513 514static const struct regmap_config video_cc_sm8550_regmap_config = {515 .reg_bits = 32,516 .reg_stride = 4,517 .val_bits = 32,518 .max_register = 0x9f4c,519 .fast_io = true,520};521 522static struct qcom_cc_desc video_cc_sm8550_desc = {523 .config = &video_cc_sm8550_regmap_config,524 .clks = video_cc_sm8550_clocks,525 .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),526 .resets = video_cc_sm8550_resets,527 .num_resets = ARRAY_SIZE(video_cc_sm8550_resets),528 .gdscs = video_cc_sm8550_gdscs,529 .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),530};531 532static const struct of_device_id video_cc_sm8550_match_table[] = {533 { .compatible = "qcom,sm8550-videocc" },534 { .compatible = "qcom,sm8650-videocc" },535 { }536};537MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);538 539static int video_cc_sm8550_probe(struct platform_device *pdev)540{541 struct regmap *regmap;542 int ret;543 u32 sleep_clk_offset = 0x8140;544 545 ret = devm_pm_runtime_enable(&pdev->dev);546 if (ret)547 return ret;548 549 ret = pm_runtime_resume_and_get(&pdev->dev);550 if (ret)551 return ret;552 553 regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);554 if (IS_ERR(regmap)) {555 pm_runtime_put(&pdev->dev);556 return PTR_ERR(regmap);557 }558 559 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {560 sleep_clk_offset = 0x8150;561 video_cc_pll0_config.l = 0x1e;562 video_cc_pll0_config.alpha = 0xa000;563 video_cc_pll1_config.l = 0x2b;564 video_cc_pll1_config.alpha = 0xc000;565 video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;566 video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;567 video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;568 video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;569 video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;570 video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;571 video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;572 }573 574 clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);575 clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);576 577 /* Keep some clocks always-on */578 qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */579 qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */580 qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */581 582 ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap);583 584 pm_runtime_put(&pdev->dev);585 586 return ret;587}588 589static struct platform_driver video_cc_sm8550_driver = {590 .probe = video_cc_sm8550_probe,591 .driver = {592 .name = "video_cc-sm8550",593 .of_match_table = video_cc_sm8550_match_table,594 },595};596 597module_platform_driver(video_cc_sm8550_driver);598 599MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");600MODULE_LICENSE("GPL");601