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1// SPDX-License-Identifier: GPL-2.02/*3 * R-Car MSTP clocks4 *5 * Copyright (C) 2013 Ideas On Board SPRL6 * Copyright (C) 2015 Glider bvba7 *8 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>9 */10 11#include <linux/clk.h>12#include <linux/clk-provider.h>13#include <linux/clk/renesas.h>14#include <linux/device.h>15#include <linux/io.h>16#include <linux/iopoll.h>17#include <linux/of.h>18#include <linux/of_address.h>19#include <linux/pm_clock.h>20#include <linux/pm_domain.h>21#include <linux/slab.h>22#include <linux/spinlock.h>23 24/*25 * MSTP clocks. We can't use standard gate clocks as we need to poll on the26 * status register when enabling the clock.27 */28 29#define MSTP_MAX_CLOCKS 3230 31/**32 * struct mstp_clock_group - MSTP gating clocks group33 *34 * @data: clock specifier translation for clocks in this group35 * @smstpcr: module stop control register36 * @mstpsr: module stop status register (optional)37 * @lock: protects writes to SMSTPCR38 * @width_8bit: registers are 8-bit, not 32-bit39 * @clks: clocks in this group40 */41struct mstp_clock_group {42 struct clk_onecell_data data;43 void __iomem *smstpcr;44 void __iomem *mstpsr;45 spinlock_t lock;46 bool width_8bit;47 struct clk *clks[];48};49 50/**51 * struct mstp_clock - MSTP gating clock52 * @hw: handle between common and hardware-specific interfaces53 * @bit_index: control bit index54 * @group: MSTP clocks group55 */56struct mstp_clock {57 struct clk_hw hw;58 u32 bit_index;59 struct mstp_clock_group *group;60};61 62#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)63 64static inline u32 cpg_mstp_read(struct mstp_clock_group *group,65 u32 __iomem *reg)66{67 return group->width_8bit ? readb(reg) : readl(reg);68}69 70static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,71 u32 __iomem *reg)72{73 group->width_8bit ? writeb(val, reg) : writel(val, reg);74}75 76static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)77{78 struct mstp_clock *clock = to_mstp_clock(hw);79 struct mstp_clock_group *group = clock->group;80 u32 bitmask = BIT(clock->bit_index);81 unsigned long flags;82 u32 value;83 int ret;84 85 spin_lock_irqsave(&group->lock, flags);86 87 value = cpg_mstp_read(group, group->smstpcr);88 if (enable)89 value &= ~bitmask;90 else91 value |= bitmask;92 cpg_mstp_write(group, value, group->smstpcr);93 94 if (!group->mstpsr) {95 /* dummy read to ensure write has completed */96 cpg_mstp_read(group, group->smstpcr);97 barrier_data(group->smstpcr);98 }99 100 spin_unlock_irqrestore(&group->lock, flags);101 102 if (!enable || !group->mstpsr)103 return 0;104 105 /* group->width_8bit is always false if group->mstpsr is present */106 ret = readl_poll_timeout_atomic(group->mstpsr, value,107 !(value & bitmask), 0, 10);108 if (ret)109 pr_err("%s: failed to enable %p[%d]\n", __func__,110 group->smstpcr, clock->bit_index);111 112 return ret;113}114 115static int cpg_mstp_clock_enable(struct clk_hw *hw)116{117 return cpg_mstp_clock_endisable(hw, true);118}119 120static void cpg_mstp_clock_disable(struct clk_hw *hw)121{122 cpg_mstp_clock_endisable(hw, false);123}124 125static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)126{127 struct mstp_clock *clock = to_mstp_clock(hw);128 struct mstp_clock_group *group = clock->group;129 u32 value;130 131 if (group->mstpsr)132 value = cpg_mstp_read(group, group->mstpsr);133 else134 value = cpg_mstp_read(group, group->smstpcr);135 136 return !(value & BIT(clock->bit_index));137}138 139static const struct clk_ops cpg_mstp_clock_ops = {140 .enable = cpg_mstp_clock_enable,141 .disable = cpg_mstp_clock_disable,142 .is_enabled = cpg_mstp_clock_is_enabled,143};144 145static struct clk * __init cpg_mstp_clock_register(const char *name,146 const char *parent_name, unsigned int index,147 struct mstp_clock_group *group)148{149 struct clk_init_data init = {};150 struct mstp_clock *clock;151 struct clk *clk;152 153 clock = kzalloc(sizeof(*clock), GFP_KERNEL);154 if (!clock)155 return ERR_PTR(-ENOMEM);156 157 init.name = name;158 init.ops = &cpg_mstp_clock_ops;159 init.flags = CLK_SET_RATE_PARENT;160 /* INTC-SYS is the module clock of the GIC, and must not be disabled */161 if (!strcmp(name, "intc-sys")) {162 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);163 init.flags |= CLK_IS_CRITICAL;164 }165 init.parent_names = &parent_name;166 init.num_parents = 1;167 168 clock->bit_index = index;169 clock->group = group;170 clock->hw.init = &init;171 172 clk = clk_register(NULL, &clock->hw);173 174 if (IS_ERR(clk))175 kfree(clock);176 177 return clk;178}179 180static void __init cpg_mstp_clocks_init(struct device_node *np)181{182 struct mstp_clock_group *group;183 const char *idxname;184 struct clk **clks;185 unsigned int i;186 187 group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);188 if (!group)189 return;190 191 clks = group->clks;192 spin_lock_init(&group->lock);193 group->data.clks = clks;194 195 group->smstpcr = of_iomap(np, 0);196 group->mstpsr = of_iomap(np, 1);197 198 if (group->smstpcr == NULL) {199 pr_err("%s: failed to remap SMSTPCR\n", __func__);200 kfree(group);201 return;202 }203 204 if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))205 group->width_8bit = true;206 207 for (i = 0; i < MSTP_MAX_CLOCKS; ++i)208 clks[i] = ERR_PTR(-ENOENT);209 210 if (of_property_present(np, "clock-indices"))211 idxname = "clock-indices";212 else213 idxname = "renesas,clock-indices";214 215 for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {216 const char *parent_name;217 const char *name;218 u32 clkidx;219 int ret;220 221 /* Skip clocks with no name. */222 ret = of_property_read_string_index(np, "clock-output-names",223 i, &name);224 if (ret < 0 || strlen(name) == 0)225 continue;226 227 parent_name = of_clk_get_parent_name(np, i);228 ret = of_property_read_u32_index(np, idxname, i, &clkidx);229 if (parent_name == NULL || ret < 0)230 break;231 232 if (clkidx >= MSTP_MAX_CLOCKS) {233 pr_err("%s: invalid clock %pOFn %s index %u\n",234 __func__, np, name, clkidx);235 continue;236 }237 238 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,239 clkidx, group);240 if (!IS_ERR(clks[clkidx]))241 group->data.clk_num = max(group->data.clk_num,242 clkidx + 1);243 else244 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",245 __func__, np, name, PTR_ERR(clks[clkidx]));246 }247 248 of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);249}250CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);251 252int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)253{254 struct device_node *np = dev->of_node;255 struct of_phandle_args clkspec;256 struct clk *clk;257 int i = 0;258 int error;259 260 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,261 &clkspec)) {262 if (of_device_is_compatible(clkspec.np,263 "renesas,cpg-mstp-clocks"))264 goto found;265 266 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */267 if (of_node_name_eq(clkspec.np, "zb_clk"))268 goto found;269 270 of_node_put(clkspec.np);271 i++;272 }273 274 return 0;275 276found:277 clk = of_clk_get_from_provider(&clkspec);278 of_node_put(clkspec.np);279 280 if (IS_ERR(clk))281 return PTR_ERR(clk);282 283 error = pm_clk_create(dev);284 if (error)285 goto fail_put;286 287 error = pm_clk_add_clk(dev, clk);288 if (error)289 goto fail_destroy;290 291 return 0;292 293fail_destroy:294 pm_clk_destroy(dev);295fail_put:296 clk_put(clk);297 return error;298}299 300void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)301{302 if (!pm_clk_no_clocks(dev))303 pm_clk_destroy(dev);304}305 306void __init cpg_mstp_add_clk_domain(struct device_node *np)307{308 struct generic_pm_domain *pd;309 u32 ncells;310 311 if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {312 pr_warn("%pOF lacks #power-domain-cells\n", np);313 return;314 }315 316 pd = kzalloc(sizeof(*pd), GFP_KERNEL);317 if (!pd)318 return;319 320 pd->name = np->name;321 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |322 GENPD_FLAG_ACTIVE_WAKEUP;323 pd->attach_dev = cpg_mstp_attach_dev;324 pd->detach_dev = cpg_mstp_detach_dev;325 pm_genpd_init(pd, &pm_domain_always_on_gov, false);326 327 of_genpd_add_provider_simple(np, pd);328}329