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1// SPDX-License-Identifier: GPL-2.02/*3 * r8a7779 Core CPG Clocks4 *5 * Copyright (C) 2013, 2014 Horms Solutions Ltd.6 *7 * Contact: Simon Horman <horms@verge.net.au>8 */9 10#include <linux/clk-provider.h>11#include <linux/clk/renesas.h>12#include <linux/init.h>13#include <linux/kernel.h>14#include <linux/of.h>15#include <linux/of_address.h>16#include <linux/slab.h>17#include <linux/spinlock.h>18#include <linux/soc/renesas/rcar-rst.h>19 20#include <dt-bindings/clock/r8a7779-clock.h>21 22#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)23 24/* -----------------------------------------------------------------------------25 * CPG Clock Data26 */27 28/*29 * MD1 = 1 MD1 = 030 * (PLLA = 1500) (PLLA = 1600)31 * (MHz) (MHz)32 *------------------------------------------------+--------------------33 * clkz 1000 (2/3) 800 (1/2)34 * clkzs 250 (1/6) 200 (1/8)35 * clki 750 (1/2) 800 (1/2)36 * clks 250 (1/6) 200 (1/8)37 * clks1 125 (1/12) 100 (1/16)38 * clks3 187.5 (1/8) 200 (1/8)39 * clks4 93.7 (1/16) 100 (1/16)40 * clkp 62.5 (1/24) 50 (1/32)41 * clkg 62.5 (1/24) 66.6 (1/24)42 * clkb, CLKOUT43 * (MD2 = 0) 62.5 (1/24) 66.6 (1/24)44 * (MD2 = 1) 41.6 (1/36) 50 (1/32)45 */46 47#define CPG_CLK_CONFIG_INDEX(md) (((md) & (BIT(2)|BIT(1))) >> 1)48 49struct cpg_clk_config {50 unsigned int z_mult;51 unsigned int z_div;52 unsigned int zs_and_s_div;53 unsigned int s1_div;54 unsigned int p_div;55 unsigned int b_and_out_div;56};57 58static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {59 { 1, 2, 8, 16, 32, 24 },60 { 2, 3, 6, 12, 24, 24 },61 { 1, 2, 8, 16, 32, 32 },62 { 2, 3, 6, 12, 24, 36 },63};64 65/*66 * MD PLLA Ratio67 * 12 1168 *------------------------69 * 0 0 x4270 * 0 1 x4871 * 1 0 x5672 * 1 1 x6473 */74 75#define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)76 77static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };78 79/* -----------------------------------------------------------------------------80 * Initialization81 */82 83static struct clk * __init84r8a7779_cpg_register_clock(struct device_node *np,85 const struct cpg_clk_config *config,86 unsigned int plla_mult, const char *name)87{88 const char *parent_name = "plla";89 unsigned int mult = 1;90 unsigned int div = 1;91 92 if (!strcmp(name, "plla")) {93 parent_name = of_clk_get_parent_name(np, 0);94 mult = plla_mult;95 } else if (!strcmp(name, "z")) {96 div = config->z_div;97 mult = config->z_mult;98 } else if (!strcmp(name, "zs") || !strcmp(name, "s")) {99 div = config->zs_and_s_div;100 } else if (!strcmp(name, "s1")) {101 div = config->s1_div;102 } else if (!strcmp(name, "p")) {103 div = config->p_div;104 } else if (!strcmp(name, "b") || !strcmp(name, "out")) {105 div = config->b_and_out_div;106 } else {107 return ERR_PTR(-EINVAL);108 }109 110 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);111}112 113static void __init r8a7779_cpg_clocks_init(struct device_node *np)114{115 const struct cpg_clk_config *config;116 struct clk_onecell_data *data;117 struct clk **clks;118 unsigned int i, plla_mult;119 int num_clks;120 u32 mode;121 122 if (rcar_rst_read_mode_pins(&mode))123 return;124 125 num_clks = of_property_count_strings(np, "clock-output-names");126 if (num_clks < 0) {127 pr_err("%s: failed to count clocks\n", __func__);128 return;129 }130 131 data = kzalloc(sizeof(*data), GFP_KERNEL);132 clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);133 if (data == NULL || clks == NULL) {134 /* We're leaking memory on purpose, there's no point in cleaning135 * up as the system won't boot anyway.136 */137 return;138 }139 140 data->clks = clks;141 data->clk_num = num_clks;142 143 config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];144 plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];145 146 for (i = 0; i < num_clks; ++i) {147 const char *name;148 struct clk *clk;149 150 of_property_read_string_index(np, "clock-output-names", i,151 &name);152 153 clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);154 if (IS_ERR(clk))155 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",156 __func__, np, name, PTR_ERR(clk));157 else158 data->clks[i] = clk;159 }160 161 of_clk_add_provider(np, of_clk_src_onecell_get, data);162 163 cpg_mstp_add_clk_domain(np);164}165CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",166 r8a7779_cpg_clocks_init);167