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1// SPDX-License-Identifier: GPL-2.02/*3 * sh73a0 Core CPG Clocks4 *5 * Copyright (C) 2014 Ulrich Hecht6 */7 8#include <linux/clk-provider.h>9#include <linux/clk/renesas.h>10#include <linux/init.h>11#include <linux/io.h>12#include <linux/kernel.h>13#include <linux/of.h>14#include <linux/of_address.h>15#include <linux/slab.h>16#include <linux/spinlock.h>17 18struct sh73a0_cpg {19 struct clk_onecell_data data;20 spinlock_t lock;21};22 23#define CPG_FRQCRA 0x0024#define CPG_FRQCRB 0x0425#define CPG_SD0CKCR 0x7426#define CPG_SD1CKCR 0x7827#define CPG_SD2CKCR 0x7c28#define CPG_PLLECR 0xd029#define CPG_PLL0CR 0xd830#define CPG_PLL1CR 0x2831#define CPG_PLL2CR 0x2c32#define CPG_PLL3CR 0xdc33#define CPG_CKSCR 0xc034#define CPG_DSI0PHYCR 0x6c35#define CPG_DSI1PHYCR 0x7036 37struct div4_clk {38 const char *name;39 const char *parent;40 unsigned int reg;41 unsigned int shift;42};43 44static const struct div4_clk div4_clks[] = {45 { "zg", "pll0", CPG_FRQCRA, 16 },46 { "m3", "pll1", CPG_FRQCRA, 12 },47 { "b", "pll1", CPG_FRQCRA, 8 },48 { "m1", "pll1", CPG_FRQCRA, 4 },49 { "m2", "pll1", CPG_FRQCRA, 0 },50 { "zx", "pll1", CPG_FRQCRB, 12 },51 { "hp", "pll1", CPG_FRQCRB, 4 },52 { NULL, NULL, 0, 0 },53};54 55static const struct clk_div_table div4_div_table[] = {56 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },57 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },58 { 12, 7 }, { 0, 0 }59};60 61static const struct clk_div_table z_div_table[] = {62 /* ZSEL == 0 */63 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },64 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },65 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },66 /* ZSEL == 1 */67 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },68 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }69};70 71static struct clk * __init72sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,73 void __iomem *base, const char *name)74{75 const struct clk_div_table *table = NULL;76 unsigned int shift, reg, width;77 const char *parent_name = NULL;78 unsigned int mult = 1;79 unsigned int div = 1;80 81 if (!strcmp(name, "main")) {82 /* extal1, extal1_div2, extal2, extal2_div2 */83 u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;84 85 parent_name = of_clk_get_parent_name(np, parent_idx >> 1);86 div = (parent_idx & 1) + 1;87 } else if (!strncmp(name, "pll", 3)) {88 void __iomem *enable_reg = base;89 u32 enable_bit = name[3] - '0';90 91 parent_name = "main";92 switch (enable_bit) {93 case 0:94 enable_reg += CPG_PLL0CR;95 break;96 case 1:97 enable_reg += CPG_PLL1CR;98 break;99 case 2:100 enable_reg += CPG_PLL2CR;101 break;102 case 3:103 enable_reg += CPG_PLL3CR;104 break;105 default:106 return ERR_PTR(-EINVAL);107 }108 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;110 /* handle CFG bit for PLL1 and PLL2 */111 if (enable_bit == 1 || enable_bit == 2)112 if (readl(enable_reg) & BIT(20))113 mult *= 2;114 }115 } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {116 u32 phy_no = name[3] - '0';117 void __iomem *dsi_reg = base +118 (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);119 120 parent_name = phy_no ? "dsi1pck" : "dsi0pck";121 mult = readl(dsi_reg);122 if (!(mult & 0x8000))123 mult = 1;124 else125 mult = (mult & 0x3f) + 1;126 } else if (!strcmp(name, "z")) {127 parent_name = "pll0";128 table = z_div_table;129 reg = CPG_FRQCRB;130 shift = 24;131 width = 5;132 } else {133 const struct div4_clk *c;134 135 for (c = div4_clks; c->name; c++) {136 if (!strcmp(name, c->name)) {137 parent_name = c->parent;138 table = div4_div_table;139 reg = c->reg;140 shift = c->shift;141 width = 4;142 break;143 }144 }145 if (!c->name)146 return ERR_PTR(-EINVAL);147 }148 149 if (!table) {150 return clk_register_fixed_factor(NULL, name, parent_name, 0,151 mult, div);152 } else {153 return clk_register_divider_table(NULL, name, parent_name, 0,154 base + reg, shift, width, 0,155 table, &cpg->lock);156 }157}158 159static void __init sh73a0_cpg_clocks_init(struct device_node *np)160{161 struct sh73a0_cpg *cpg;162 void __iomem *base;163 struct clk **clks;164 unsigned int i;165 int num_clks;166 167 num_clks = of_property_count_strings(np, "clock-output-names");168 if (num_clks < 0) {169 pr_err("%s: failed to count clocks\n", __func__);170 return;171 }172 173 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);174 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);175 if (cpg == NULL || clks == NULL) {176 /* We're leaking memory on purpose, there's no point in cleaning177 * up as the system won't boot anyway.178 */179 return;180 }181 182 spin_lock_init(&cpg->lock);183 184 cpg->data.clks = clks;185 cpg->data.clk_num = num_clks;186 187 base = of_iomap(np, 0);188 if (WARN_ON(base == NULL))189 return;190 191 /* Set SDHI clocks to a known state */192 writel(0x108, base + CPG_SD0CKCR);193 writel(0x108, base + CPG_SD1CKCR);194 writel(0x108, base + CPG_SD2CKCR);195 196 for (i = 0; i < num_clks; ++i) {197 const char *name;198 struct clk *clk;199 200 of_property_read_string_index(np, "clock-output-names", i,201 &name);202 203 clk = sh73a0_cpg_register_clock(np, cpg, base, name);204 if (IS_ERR(clk))205 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",206 __func__, np, name, PTR_ERR(clk));207 else208 cpg->data.clks[i] = clk;209 }210 211 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);212}213CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",214 sh73a0_cpg_clocks_init);215