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1// SPDX-License-Identifier: GPL-2.02/*3 * r8a7743 Clock Pulse Generator / Module Standby and Software Reset4 *5 * Copyright (C) 2016 Cogent Embedded Inc.6 */7 8#include <linux/device.h>9#include <linux/init.h>10#include <linux/kernel.h>11#include <linux/of.h>12#include <linux/soc/renesas/rcar-rst.h>13 14#include <dt-bindings/clock/r8a7743-cpg-mssr.h>15 16#include "renesas-cpg-mssr.h"17#include "rcar-gen2-cpg.h"18 19enum clk_ids {20 /* Core Clock Outputs exported to DT */21 LAST_DT_CORE_CLK = R8A7743_CLK_OSC,22 23 /* External Input Clocks */24 CLK_EXTAL,25 CLK_USB_EXTAL,26 27 /* Internal Core Clocks */28 CLK_MAIN,29 CLK_PLL0,30 CLK_PLL1,31 CLK_PLL3,32 CLK_PLL1_DIV2,33 34 /* Module Clocks */35 MOD_CLK_BASE36};37 38static struct cpg_core_clk r8a7743_core_clks[] __initdata = {39 /* External Clock Inputs */40 DEF_INPUT("extal", CLK_EXTAL),41 DEF_INPUT("usb_extal", CLK_USB_EXTAL),42 43 /* Internal Core Clocks */44 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),45 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),46 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),47 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),48 49 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),50 51 /* Core Clock Outputs */52 DEF_BASE("z", R8A7743_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),53 DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),54 DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),55 DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),56 DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),57 58 DEF_FIXED("zg", R8A7743_CLK_ZG, CLK_PLL1, 3, 1),59 DEF_FIXED("zx", R8A7743_CLK_ZX, CLK_PLL1, 3, 1),60 DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),61 DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),62 DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),63 DEF_FIXED("lb", R8A7743_CLK_LB, CLK_PLL1, 24, 1),64 DEF_FIXED("p", R8A7743_CLK_P, CLK_PLL1, 24, 1),65 DEF_FIXED("cl", R8A7743_CLK_CL, CLK_PLL1, 48, 1),66 DEF_FIXED("m2", R8A7743_CLK_M2, CLK_PLL1, 8, 1),67 DEF_FIXED("zb3", R8A7743_CLK_ZB3, CLK_PLL3, 4, 1),68 DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2, CLK_PLL3, 8, 1),69 DEF_FIXED("ddr", R8A7743_CLK_DDR, CLK_PLL3, 8, 1),70 DEF_FIXED("mp", R8A7743_CLK_MP, CLK_PLL1_DIV2, 15, 1),71 DEF_FIXED("cp", R8A7743_CLK_CP, CLK_EXTAL, 2, 1),72 DEF_FIXED("r", R8A7743_CLK_R, CLK_PLL1, 49152, 1),73 DEF_FIXED("osc", R8A7743_CLK_OSC, CLK_PLL1, 12288, 1),74 75 DEF_DIV6P1("sd2", R8A7743_CLK_SD2, CLK_PLL1_DIV2, 0x078),76 DEF_DIV6P1("sd3", R8A7743_CLK_SD3, CLK_PLL1_DIV2, 0x26c),77 DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0, CLK_PLL1_DIV2, 0x240),78};79 80static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {81 DEF_MOD("msiof0", 0, R8A7743_CLK_MP),82 DEF_MOD("vcp0", 101, R8A7743_CLK_ZS),83 DEF_MOD("vpc0", 103, R8A7743_CLK_ZS),84 DEF_MOD("tmu1", 111, R8A7743_CLK_P),85 DEF_MOD("3dg", 112, R8A7743_CLK_ZG),86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),89 DEF_MOD("tmu3", 121, R8A7743_CLK_P),90 DEF_MOD("tmu2", 122, R8A7743_CLK_P),91 DEF_MOD("cmt0", 124, R8A7743_CLK_R),92 DEF_MOD("tmu0", 125, R8A7743_CLK_CP),93 DEF_MOD("vsp1du1", 127, R8A7743_CLK_ZS),94 DEF_MOD("vsp1du0", 128, R8A7743_CLK_ZS),95 DEF_MOD("vsps", 131, R8A7743_CLK_ZS),96 DEF_MOD("scifa2", 202, R8A7743_CLK_MP),97 DEF_MOD("scifa1", 203, R8A7743_CLK_MP),98 DEF_MOD("scifa0", 204, R8A7743_CLK_MP),99 DEF_MOD("msiof2", 205, R8A7743_CLK_MP),100 DEF_MOD("scifb0", 206, R8A7743_CLK_MP),101 DEF_MOD("scifb1", 207, R8A7743_CLK_MP),102 DEF_MOD("msiof1", 208, R8A7743_CLK_MP),103 DEF_MOD("scifb2", 216, R8A7743_CLK_MP),104 DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),105 DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),106 DEF_MOD("tpu0", 304, R8A7743_CLK_CP),107 DEF_MOD("sdhi3", 311, R8A7743_CLK_SD3),108 DEF_MOD("sdhi2", 312, R8A7743_CLK_SD2),109 DEF_MOD("sdhi0", 314, R8A7743_CLK_SD0),110 DEF_MOD("mmcif0", 315, R8A7743_CLK_MMC0),111 DEF_MOD("iic0", 318, R8A7743_CLK_HP),112 DEF_MOD("pciec", 319, R8A7743_CLK_MP),113 DEF_MOD("iic1", 323, R8A7743_CLK_HP),114 DEF_MOD("usb3.0", 328, R8A7743_CLK_MP),115 DEF_MOD("cmt1", 329, R8A7743_CLK_R),116 DEF_MOD("usbhs-dmac0", 330, R8A7743_CLK_HP),117 DEF_MOD("usbhs-dmac1", 331, R8A7743_CLK_HP),118 DEF_MOD("rwdt", 402, R8A7743_CLK_R),119 DEF_MOD("irqc", 407, R8A7743_CLK_CP),120 DEF_MOD("intc-sys", 408, R8A7743_CLK_ZS),121 DEF_MOD("audio-dmac1", 501, R8A7743_CLK_HP),122 DEF_MOD("audio-dmac0", 502, R8A7743_CLK_HP),123 DEF_MOD("thermal", 522, CLK_EXTAL),124 DEF_MOD("pwm", 523, R8A7743_CLK_P),125 DEF_MOD("usb-ehci", 703, R8A7743_CLK_MP),126 DEF_MOD("usbhs", 704, R8A7743_CLK_HP),127 DEF_MOD("hscif2", 713, R8A7743_CLK_ZS),128 DEF_MOD("scif5", 714, R8A7743_CLK_P),129 DEF_MOD("scif4", 715, R8A7743_CLK_P),130 DEF_MOD("hscif1", 716, R8A7743_CLK_ZS),131 DEF_MOD("hscif0", 717, R8A7743_CLK_ZS),132 DEF_MOD("scif3", 718, R8A7743_CLK_P),133 DEF_MOD("scif2", 719, R8A7743_CLK_P),134 DEF_MOD("scif1", 720, R8A7743_CLK_P),135 DEF_MOD("scif0", 721, R8A7743_CLK_P),136 DEF_MOD("du1", 723, R8A7743_CLK_ZX),137 DEF_MOD("du0", 724, R8A7743_CLK_ZX),138 DEF_MOD("lvds0", 726, R8A7743_CLK_ZX),139 DEF_MOD("ipmmu-sgx", 800, R8A7743_CLK_ZX),140 DEF_MOD("vin2", 809, R8A7743_CLK_ZG),141 DEF_MOD("vin1", 810, R8A7743_CLK_ZG),142 DEF_MOD("vin0", 811, R8A7743_CLK_ZG),143 DEF_MOD("etheravb", 812, R8A7743_CLK_HP),144 DEF_MOD("ether", 813, R8A7743_CLK_P),145 DEF_MOD("sata1", 814, R8A7743_CLK_ZS),146 DEF_MOD("sata0", 815, R8A7743_CLK_ZS),147 DEF_MOD("gpio7", 904, R8A7743_CLK_CP),148 DEF_MOD("gpio6", 905, R8A7743_CLK_CP),149 DEF_MOD("gpio5", 907, R8A7743_CLK_CP),150 DEF_MOD("gpio4", 908, R8A7743_CLK_CP),151 DEF_MOD("gpio3", 909, R8A7743_CLK_CP),152 DEF_MOD("gpio2", 910, R8A7743_CLK_CP),153 DEF_MOD("gpio1", 911, R8A7743_CLK_CP),154 DEF_MOD("gpio0", 912, R8A7743_CLK_CP),155 DEF_MOD("can1", 915, R8A7743_CLK_P),156 DEF_MOD("can0", 916, R8A7743_CLK_P),157 DEF_MOD("qspi_mod", 917, R8A7743_CLK_QSPI),158 DEF_MOD("i2c5", 925, R8A7743_CLK_HP),159 DEF_MOD("iicdvfs", 926, R8A7743_CLK_CP),160 DEF_MOD("i2c4", 927, R8A7743_CLK_HP),161 DEF_MOD("i2c3", 928, R8A7743_CLK_HP),162 DEF_MOD("i2c2", 929, R8A7743_CLK_HP),163 DEF_MOD("i2c1", 930, R8A7743_CLK_HP),164 DEF_MOD("i2c0", 931, R8A7743_CLK_HP),165 DEF_MOD("ssi-all", 1005, R8A7743_CLK_P),166 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),167 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),168 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),169 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),170 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),171 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),172 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),173 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),174 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),175 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),176 DEF_MOD("scu-all", 1017, R8A7743_CLK_P),177 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),178 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),179 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),180 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),181 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),182 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),183 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),184 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),185 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),186 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),187 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),188 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),189 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),190 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),191 DEF_MOD("scifa3", 1106, R8A7743_CLK_MP),192 DEF_MOD("scifa4", 1107, R8A7743_CLK_MP),193 DEF_MOD("scifa5", 1108, R8A7743_CLK_MP),194};195 196static const unsigned int r8a7743_crit_mod_clks[] __initconst = {197 MOD_CLK_ID(402), /* RWDT */198 MOD_CLK_ID(408), /* INTC-SYS (GIC) */199};200 201/*202 * CPG Clock Data203 */204 205/*206 * MD EXTAL PLL0 PLL1 PLL3207 * 14 13 19 (MHz) *1 *1208 *---------------------------------------------------209 * 0 0 0 15 x172/2 x208/2 x106210 * 0 0 1 15 x172/2 x208/2 x88211 * 0 1 0 20 x130/2 x156/2 x80212 * 0 1 1 20 x130/2 x156/2 x66213 * 1 0 0 26 / 2 x200/2 x240/2 x122214 * 1 0 1 26 / 2 x200/2 x240/2 x102215 * 1 1 0 30 / 2 x172/2 x208/2 x106216 * 1 1 1 30 / 2 x172/2 x208/2 x88217 *218 * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)219 */220#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \221 (((md) & BIT(13)) >> 12) | \222 (((md) & BIT(19)) >> 19))223 224static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {225 /* EXTAL div PLL1 mult PLL3 mult */226 { 1, 208, 106, },227 { 1, 208, 88, },228 { 1, 156, 80, },229 { 1, 156, 66, },230 { 2, 240, 122, },231 { 2, 240, 102, },232 { 2, 208, 106, },233 { 2, 208, 88, },234};235 236static int __init r8a7743_cpg_mssr_init(struct device *dev)237{238 const struct rcar_gen2_cpg_pll_config *cpg_pll_config;239 struct device_node *np = dev->of_node;240 unsigned int i;241 u32 cpg_mode;242 int error;243 244 error = rcar_rst_read_mode_pins(&cpg_mode);245 if (error)246 return error;247 248 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];249 250 if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {251 /* RZ/G1N uses a 1/5 divider for ZG */252 for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)253 if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {254 r8a7743_core_clks[i].div = 5;255 break;256 }257 }258 return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);259}260 261const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {262 /* Core Clocks */263 .core_clks = r8a7743_core_clks,264 .num_core_clks = ARRAY_SIZE(r8a7743_core_clks),265 .last_dt_core_clk = LAST_DT_CORE_CLK,266 .num_total_core_clks = MOD_CLK_BASE,267 268 /* Module Clocks */269 .mod_clks = r8a7743_mod_clks,270 .num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),271 .num_hw_mod_clks = 12 * 32,272 273 /* Critical Module Clocks */274 .crit_mod_clks = r8a7743_crit_mod_clks,275 .num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),276 277 /* Callbacks */278 .init = r8a7743_cpg_mssr_init,279 .cpg_clk_register = rcar_gen2_cpg_clk_register,280};281