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1// SPDX-License-Identifier: GPL-2.02/*3 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset4 *5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>6 * Copyright (C) 2019 Renesas Electronics Corp.7 *8 * Based on r8a7795-cpg-mssr.c9 *10 * Copyright (C) 2015 Glider bvba11 * Copyright (C) 2015 Renesas Electronics Corp.12 */13 14#include <linux/device.h>15#include <linux/init.h>16#include <linux/kernel.h>17#include <linux/soc/renesas/rcar-rst.h>18 19#include <dt-bindings/clock/r8a77965-cpg-mssr.h>20 21#include "renesas-cpg-mssr.h"22#include "rcar-gen3-cpg.h"23 24enum clk_ids {25 /* Core Clock Outputs exported to DT */26 LAST_DT_CORE_CLK = R8A77965_CLK_OSC,27 28 /* External Input Clocks */29 CLK_EXTAL,30 CLK_EXTALR,31 32 /* Internal Core Clocks */33 CLK_MAIN,34 CLK_PLL0,35 CLK_PLL1,36 CLK_PLL3,37 CLK_PLL4,38 CLK_PLL1_DIV2,39 CLK_PLL1_DIV4,40 CLK_S0,41 CLK_S1,42 CLK_S2,43 CLK_S3,44 CLK_SDSRC,45 CLK_SSPSRC,46 CLK_RPCSRC,47 CLK_RINT,48 49 /* Module Clocks */50 MOD_CLK_BASE51};52 53static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {54 /* External Clock Inputs */55 DEF_INPUT("extal", CLK_EXTAL),56 DEF_INPUT("extalr", CLK_EXTALR),57 58 /* Internal Core Clocks */59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),64 65 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),66 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),67 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),68 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),69 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),70 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),71 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),72 73 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),74 75 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),76 77 /* Core Clock Outputs */78 DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),79 DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),80 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),81 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),82 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),83 DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),84 DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),85 DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),86 DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),87 DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),88 DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),89 DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),90 DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),91 DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),92 DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),93 DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),94 DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),95 DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),96 DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),97 DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),98 DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),99 DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),100 101 DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074),102 DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078),103 DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268),104 DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c),105 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074),106 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078),107 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),108 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),109 110 DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),111 DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),112 113 DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),114 DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),115 DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),116 DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),117 118 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),119 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),120 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),121 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),122 123 DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),124 125 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),126};127 128static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {129 DEF_MOD("3dge", 112, R8A77965_CLK_ZG),130 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),131 DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),132 DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),133 DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),134 DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),135 DEF_MOD("tmu0", 125, R8A77965_CLK_CP),136 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),137 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),138 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),139 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),140 DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),141 DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),142 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),143 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),144 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),145 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),146 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),147 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),148 DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),149 150 DEF_MOD("cmt3", 300, R8A77965_CLK_R),151 DEF_MOD("cmt2", 301, R8A77965_CLK_R),152 DEF_MOD("cmt1", 302, R8A77965_CLK_R),153 DEF_MOD("cmt0", 303, R8A77965_CLK_R),154 DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),155 DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),156 DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),157 DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),158 DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),159 DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),160 DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),161 DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),162 DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),163 DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),164 DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),165 166 DEF_MOD("rwdt", 402, R8A77965_CLK_R),167 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),168 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),169 170 DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),171 DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),172 DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),173 DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),174 DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),175 DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),176 DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),177 DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),178 DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),179 DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),180 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),181 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),182 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),183 DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),184 DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),185 DEF_MOD("thermal", 522, R8A77965_CLK_CP),186 DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),187 188 DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),189 DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),190 DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),191 DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),192 DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),193 DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),194 DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),195 DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),196 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),197 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),198 199 DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),200 DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),201 DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),202 DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),203 DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),204 DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),205 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),206 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),207 DEF_MOD("du3", 721, R8A77965_CLK_S2D1),208 DEF_MOD("du1", 723, R8A77965_CLK_S2D1),209 DEF_MOD("du0", 724, R8A77965_CLK_S2D1),210 DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),211 DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),212 213 DEF_MOD("mlp", 802, R8A77965_CLK_S2D1),214 DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),215 DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),216 DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),217 DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),218 DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),219 DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),220 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),221 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),222 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),223 DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),224 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),225 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),226 227 DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),228 DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),229 DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),230 DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),231 DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),232 DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),233 DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),234 DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),235 DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),236 DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),237 DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),238 DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),239 DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),240 DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),241 DEF_MOD("adg", 922, R8A77965_CLK_S0D4),242 DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),243 DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),244 DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),245 DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),246 DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),247 DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),248 249 DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),250 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),251 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),252 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),253 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),254 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),255 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),256 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),257 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),258 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),259 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),260 DEF_MOD("dab", 1016, R8A77965_CLK_S0D6),261 DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),262 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),263 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),264 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),265 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),266 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),267 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),268 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),269 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),270 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),271 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),272 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),273 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),274 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),275 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),276};277 278static const unsigned int r8a77965_crit_mod_clks[] __initconst = {279 MOD_CLK_ID(402), /* RWDT */280 MOD_CLK_ID(408), /* INTC-AP (GIC) */281};282 283/*284 * CPG Clock Data285 */286 287/*288 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC289 * 14 13 19 17 (MHz)290 *-----------------------------------------------------------------291 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16292 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16293 * 0 0 1 0 Prohibited setting294 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16295 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19296 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19297 * 0 1 1 0 Prohibited setting298 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19299 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24300 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24301 * 1 0 1 0 Prohibited setting302 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24303 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32304 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32305 * 1 1 1 0 Prohibited setting306 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32307 */308#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \309 (((md) & BIT(13)) >> 11) | \310 (((md) & BIT(19)) >> 18) | \311 (((md) & BIT(17)) >> 17))312 313static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {314 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */315 { 1, 192, 1, 192, 1, 16, },316 { 1, 192, 1, 128, 1, 16, },317 { 0, /* Prohibited setting */ },318 { 1, 192, 1, 192, 1, 16, },319 { 1, 160, 1, 160, 1, 19, },320 { 1, 160, 1, 106, 1, 19, },321 { 0, /* Prohibited setting */ },322 { 1, 160, 1, 160, 1, 19, },323 { 1, 128, 1, 128, 1, 24, },324 { 1, 128, 1, 84, 1, 24, },325 { 0, /* Prohibited setting */ },326 { 1, 128, 1, 128, 1, 24, },327 { 2, 192, 1, 192, 1, 32, },328 { 2, 192, 1, 128, 1, 32, },329 { 0, /* Prohibited setting */ },330 { 2, 192, 1, 192, 1, 32, },331};332 333static int __init r8a77965_cpg_mssr_init(struct device *dev)334{335 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;336 u32 cpg_mode;337 int error;338 339 error = rcar_rst_read_mode_pins(&cpg_mode);340 if (error)341 return error;342 343 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];344 if (!cpg_pll_config->extal_div) {345 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);346 return -EINVAL;347 }348 349 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);350}351 352const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {353 /* Core Clocks */354 .core_clks = r8a77965_core_clks,355 .num_core_clks = ARRAY_SIZE(r8a77965_core_clks),356 .last_dt_core_clk = LAST_DT_CORE_CLK,357 .num_total_core_clks = MOD_CLK_BASE,358 359 /* Module Clocks */360 .mod_clks = r8a77965_mod_clks,361 .num_mod_clks = ARRAY_SIZE(r8a77965_mod_clks),362 .num_hw_mod_clks = 12 * 32,363 364 /* Critical Module Clocks */365 .crit_mod_clks = r8a77965_crit_mod_clks,366 .num_crit_mod_clks = ARRAY_SIZE(r8a77965_crit_mod_clks),367 368 /* Callbacks */369 .init = r8a77965_cpg_mssr_init,370 .cpg_clk_register = rcar_gen3_cpg_clk_register,371};372