418 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * RZ/G2UL CPG driver4 *5 * Copyright (C) 2022 Renesas Electronics Corp.6 */7 8#include <linux/clk-provider.h>9#include <linux/device.h>10#include <linux/init.h>11#include <linux/kernel.h>12 13#include <dt-bindings/clock/r9a07g043-cpg.h>14 15#include "rzg2l-cpg.h"16 17/* Specific registers. */18#define CPG_PL2SDHI_DSEL (0x218)19 20/* Clock select configuration. */21#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)22#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)23 24/* Clock status configuration. */25#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)26#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)27 28enum clk_ids {29 /* Core Clock Outputs exported to DT */30 LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,31 32 /* External Input Clocks */33 CLK_EXTAL,34 35 /* Internal Core Clocks */36 CLK_OSC_DIV1000,37 CLK_PLL1,38 CLK_PLL2,39 CLK_PLL2_DIV2,40 CLK_PLL2_DIV2_8,41 CLK_PLL2_DIV2_10,42 CLK_PLL3,43 CLK_PLL3_400,44 CLK_PLL3_533,45 CLK_PLL3_DIV2,46 CLK_PLL3_DIV2_4,47 CLK_PLL3_DIV2_4_2,48 CLK_SEL_PLL3_3,49 CLK_DIV_PLL3_C,50#ifdef CONFIG_ARM6451 CLK_M2_DIV2,52 CLK_PLL5,53 CLK_PLL5_500,54 CLK_PLL5_250,55 CLK_PLL5_FOUTPOSTDIV,56 CLK_DSI_DIV,57#endif58 CLK_PLL6,59 CLK_PLL6_250,60 CLK_P1_DIV2,61 CLK_PLL2_800,62 CLK_PLL2_SDHI_533,63 CLK_PLL2_SDHI_400,64 CLK_PLL2_SDHI_266,65 CLK_SD0_DIV4,66 CLK_SD1_DIV4,67 68 /* Module Clocks */69 MOD_CLK_BASE,70};71 72/* Divider tables */73static const struct clk_div_table dtable_1_8[] = {74 {0, 1},75 {1, 2},76 {2, 4},77 {3, 8},78 {0, 0},79};80 81static const struct clk_div_table dtable_1_32[] = {82 {0, 1},83 {1, 2},84 {2, 4},85 {3, 8},86 {4, 32},87 {0, 0},88};89 90/* Mux clock tables */91static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };92static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };93static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };94 95static const u32 mtable_sdhi[] = { 1, 2, 3 };96 97static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {98 /* External Clock Inputs */99 DEF_INPUT("extal", CLK_EXTAL),100 101 /* Internal Core Clocks */102 DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),103 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),104 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),105 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),106 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),107 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),108 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),109 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),110 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),111 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),112 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),113 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),114 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),115 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),116 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),117 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),118 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),119 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),120 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),121#ifdef CONFIG_ARM64122 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),123 DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),124 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),125 DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),126#endif127 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),128 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),129 130 /* Core output clk */131 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),132 DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),133 DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),134 DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),135 DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),136 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),137 DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),138 DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),139 DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),140 DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),141 DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),142 DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),143 DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,144 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),145 DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,146 mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),147 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),148 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),149#ifdef CONFIG_ARM64150 DEF_FIXED("M2", R9A07G043_CLK_M2, CLK_PLL3_533, 1, 2),151 DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G043_CLK_M2, 1, 2),152 DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_PLL5_FOUTPOSTDIV, CLK_SET_RATE_PARENT),153 DEF_FIXED("M3", R9A07G043_CLK_M3, CLK_DSI_DIV, 1, 1),154#endif155};156 157static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {158#ifdef CONFIG_ARM64159 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,160 0x514, 0),161 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,162 0x518, 0),163 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,164 0x518, 1),165#endif166#ifdef CONFIG_RISCV167 DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,168 0x518, 0),169 DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,170 0x518, 1),171#endif172 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,173 0x52c, 0),174 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,175 0x52c, 1),176 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,177 0x534, 0),178 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,179 0x534, 1),180 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,181 0x534, 2),182 DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0,183 0x538, 0),184 DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,185 0x548, 0),186 DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,187 0x548, 1),188 DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,189 0x550, 0),190 DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,191 0x550, 1),192 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,193 0x554, 0),194 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,195 0x554, 1),196 DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,197 0x554, 2),198 DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,199 0x554, 3),200 DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,201 0x554, 4),202 DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,203 0x554, 5),204 DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,205 0x554, 6),206 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,207 0x554, 7),208#ifdef CONFIG_ARM64209 DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,210 0x564, 0),211 DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,212 0x564, 1),213 DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,214 0x564, 2),215 DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,216 0x564, 3),217 DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,218 0x56c, 0),219 DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT,220 0x56c, 0),221 DEF_MOD("lcdc_clk_d", R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3,222 0x56c, 1),223#endif224 DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,225 0x570, 0),226 DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,227 0x570, 1),228 DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,229 0x570, 2),230 DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,231 0x570, 3),232 DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,233 0x570, 4),234 DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,235 0x570, 5),236 DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,237 0x570, 6),238 DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,239 0x570, 7),240 DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,241 0x578, 0),242 DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,243 0x578, 1),244 DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,245 0x578, 2),246 DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,247 0x578, 3),248 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,249 0x57c, 0),250 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,251 0x57c, 0),252 DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,253 0x57c, 1),254 DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,255 0x57c, 1),256 DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,257 0x580, 0),258 DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,259 0x580, 1),260 DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,261 0x580, 2),262 DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,263 0x580, 3),264 DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,265 0x584, 0),266 DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,267 0x584, 1),268 DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,269 0x584, 2),270 DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,271 0x584, 3),272 DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,273 0x584, 4),274 DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,275 0x588, 0),276 DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,277 0x588, 1),278 DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,279 0x590, 0),280 DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,281 0x590, 1),282 DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,283 0x590, 2),284 DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,285 0x594, 0),286 DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,287 0x598, 0),288 DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,289 0x5a8, 0),290 DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,291 0x5a8, 1),292 DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,293 0x5ac, 0),294#ifdef CONFIG_RISCV295 DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,296 0x608, 0),297#endif298};299 300static const struct rzg2l_reset r9a07g043_resets[] = {301#ifdef CONFIG_ARM64302 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),303 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),304 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),305#endif306#ifdef CONFIG_RISCV307 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),308#endif309 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),310 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),311 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),312 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),313 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),314 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),315 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),316 DEF_RST(R9A07G043_SPI_RST, 0x850, 0),317 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),318 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),319#ifdef CONFIG_ARM64320 DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0),321 DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1),322 DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2),323 DEF_RST(R9A07G043_LCDC_RESET_N, 0x86c, 0),324#endif325 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),326 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),327 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),328 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),329 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),330 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),331 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),332 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),333 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),334 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),335 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),336 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),337 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),338 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),339 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),340 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),341 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),342 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),343 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),344 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),345 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),346 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),347 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),348 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),349 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),350 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),351 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),352 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),353 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),354 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),355 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),356 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),357#ifdef CONFIG_RISCV358 DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),359#endif360 361};362 363static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {364#ifdef CONFIG_ARM64365 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,366 MOD_CLK_BASE + R9A07G043_IA55_CLK,367#endif368#ifdef CONFIG_RISCV369 MOD_CLK_BASE + R9A07G043_IAX45_CLK,370 MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,371#endif372 MOD_CLK_BASE + R9A07G043_DMAC_ACLK,373};374 375#ifdef CONFIG_ARM64376static const unsigned int r9a07g043_no_pm_mod_clks[] = {377 MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,378 MOD_CLK_BASE + R9A07G043_CRU_VCLK,379};380#endif381 382const struct rzg2l_cpg_info r9a07g043_cpg_info = {383 /* Core Clocks */384 .core_clks = r9a07g043_core_clks,385 .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),386 .last_dt_core_clk = LAST_DT_CORE_CLK,387 .num_total_core_clks = MOD_CLK_BASE,388 389 /* Critical Module Clocks */390 .crit_mod_clks = r9a07g043_crit_mod_clks,391 .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),392 393 /* Module Clocks */394 .mod_clks = r9a07g043_mod_clks,395 .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),396#ifdef CONFIG_ARM64397 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,398 399 /* No PM Module Clocks */400 .no_pm_mod_clks = r9a07g043_no_pm_mod_clks,401 .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g043_no_pm_mod_clks),402#endif403#ifdef CONFIG_RISCV404 .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,405#endif406 407 /* Resets */408 .resets = r9a07g043_resets,409#ifdef CONFIG_ARM64410 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */411#endif412#ifdef CONFIG_RISCV413 .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */414#endif415 416 .has_clk_mon_regs = true,417};418